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Miller" , Jakub Kicinski , Paolo Abeni , Eric Dumazet , "Andrew Lunn" CC: Gal Pressman , Leon Romanovsky , "Yael Chemla" , Saeed Mahameed , "Leon Romanovsky" , Tariq Toukan , "Jonathan Corbet" , , , , , Kalesh Anakkur Purayil , Jacob Keller , Stanislav Fomichev Subject: [PATCH net-next V2 1/4] net/mlx5e: Ensure each counter group uses its PCAM bit Date: Sun, 16 Mar 2025 10:14:33 +0200 Message-ID: <1742112876-2890-2-git-send-email-tariqt@nvidia.com> X-Mailer: git-send-email 2.8.0 In-Reply-To: <1742112876-2890-1-git-send-email-tariqt@nvidia.com> References: <1742112876-2890-1-git-send-email-tariqt@nvidia.com> Precedence: bulk X-Mailing-List: netdev@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-NV-OnPremToCloud: AnonymousSubmission X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: CY4PEPF0000EE30:EE_|CYYPR12MB8869:EE_ X-MS-Office365-Filtering-Correlation-Id: 2fb0e9c5-c547-4250-2658-08dd6462a230 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|82310400026|1800799024|36860700013|376014|7416014; X-Microsoft-Antispam-Message-Info: JsF3m+SPr92qD9X5HkQUbUbWb94CADGJ+0TWEHHgMUY2cjvrQyWjFWkRnMiWVVLvQLNVRHOaxK/JW1lOshow0KMrKOrmEaDetYwjqp3asFgntgBSPKOY/Kqv9RyhIGzA2iLl/jodwZWi5fmnYOvdBixtHgvobD4c2Bvg5m6X7B3JsdbLjvyjSwz43HWVj7xX8ArR0OAigDpwrlEyrWGJ1EVVYCas4vTsJvrp8wn3mtDVICQkMhp75uhINN3w3BEMPtNB8j098AO+ofc6R9sHHyPOjnLrpM4/MMTCF56umyu6sVd3Ao3CmTuo9cUOv+ySCj0VokN0ST2d5plOpBLZueMlBSKscEui87yVct0yZFdU/mhY9IXAxWsS3SFM/5HklHMepYsrWP1HfqZF3bI3JOG8/CMwtW/tyZF9I/DWp/FpbwKp/ogNOxzHETHsJN+PpbPt958mwGzKz+cosk4WL1kEMXRJGxTLMQDFGmAe7Yh2SNm4n/39UujwHKLA9dgHG0mVtaTicZUF5ENjeaL0uK0e+3g3DAaDVmGmK1voj7EJl4xyPTJDb+Xg5t0U0bfv4EnRiufuhSU80kUrynCgNK2kMVo68E6EAVnq5gmUn/zpUdyyC52YH3FFqqIRrac15mrTpGGDTi8yJ1koNb7j3Nly05UF1kNMZarc0YCll/7JX8pG7Y6qUDEkB0hZ4xx7qd8Tm4GGw2FN7smy+YRzhRNagXGM/E1lnVACLHYgdvI+ETH6sL6Hi9IAg8hmjYW9+Nc/vEcMlPrNH4IH9esx05ukKoXLyrplaI6j2HY7uAxHhO+Buq+SAuywdVqX8ZqlqRirqm/wBYHEirh1L/DjQ7+4T58x6O6W36EZIn7ZjtzWZ6Gcbo+p4jLVmKXq8d9wWp6Df8hQckly3bGHCXY2uqC28XXg1T/AqrZdHGxGFTAkQ2LlzlL4BeA5duwMYE9Yr61T3Wpg12STCc5MqmC2pg0+pg/9cmhzQkdOxlBrsZPq74zEzQc1wKr39X0AWwoilmcLWJ9kuOEilmAzlAOLsdEemzj1KUf5lJrK0ukP/tKpsRFyF45eC7iTLz8OlxfONYkGoORVB8X/nhTorjxeDfpvrTlum9ixEM8YIrl+IAKB9/k+V0RcEOq++ZHWe827vRb/SwPQ164hz9AsqenTmpoSgXZg0Nq4GBdJUqEj8zQDRgXD5t/MDtMOYYLI8yiMCrOQVesDZ15ljILP6n5Drdl5fzU9z7UVUTdkuMALAlAXFzCS22rYtY8qcMcuFdSGNt4koIcojMmXofwRLrKPCBJIcYkN8rdV+dF1p0EmIHC7ZM4fU/V+OzIFeLL/NgraHTVT5MTKjam9YsRq+1sPZHsLytukX+omvXegohJKedBZMf8rHGz372j9CiiepGoLqyFXIrO9wbpiEdf2rwIzQaKluZE9KRc3uZ2QBIsq8ex9enZDbYsX9df6/rNsLGAZwdcC5zd32fpWzsQW1yIWqfaFuZccVO4kKOGZ+KYS2Fk= X-Forefront-Antispam-Report: CIP:216.228.118.232;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:dc7edge1.nvidia.com;CAT:NONE;SFS:(13230040)(82310400026)(1800799024)(36860700013)(376014)(7416014);DIR:OUT;SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 16 Mar 2025 08:14:54.6334 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 2fb0e9c5-c547-4250-2658-08dd6462a230 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.118.232];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: CY4PEPF0000EE30.namprd05.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: CYYPR12MB8869 X-Patchwork-Delegate: kuba@kernel.org From: Yael Chemla The code was incorrectly relying on PCAM bit of ppcnt_statistical_group for accessing per_lane_error_counters. If ppcnt_statistical_group PCAM bit was not set, we would not read per_lane_error_counters, even when its PCAM bit is set. Given the existing device capabilities, it seems to cause no harm, so this change primarily serves as cleanup. Signed-off-by: Yael Chemla Reviewed-by: Cosmin Ratiu Signed-off-by: Tariq Toukan Reviewed-by: Jacob Keller Reviewed-by: Kalesh AP --- .../ethernet/mellanox/mlx5/core/en_stats.c | 24 ++++++++----------- 1 file changed, 10 insertions(+), 14 deletions(-) diff --git a/drivers/net/ethernet/mellanox/mlx5/core/en_stats.c b/drivers/net/ethernet/mellanox/mlx5/core/en_stats.c index 611ec4b6f370..77d34037b92b 100644 --- a/drivers/net/ethernet/mellanox/mlx5/core/en_stats.c +++ b/drivers/net/ethernet/mellanox/mlx5/core/en_stats.c @@ -1272,11 +1272,9 @@ static MLX5E_DECLARE_STATS_GRP_OP_FILL_STRS(phy) ethtool_puts(data, "link_down_events_phy"); - if (!MLX5_CAP_PCAM_FEATURE(mdev, ppcnt_statistical_group)) - return; - - for (i = 0; i < NUM_PPORT_PHY_STATISTICAL_COUNTERS; i++) - ethtool_puts(data, pport_phy_statistical_stats_desc[i].format); + if (MLX5_CAP_PCAM_FEATURE(mdev, ppcnt_statistical_group)) + for (i = 0; i < NUM_PPORT_PHY_STATISTICAL_COUNTERS; i++) + ethtool_puts(data, pport_phy_statistical_stats_desc[i].format); if (MLX5_CAP_PCAM_FEATURE(mdev, per_lane_error_counters)) for (i = 0; i < NUM_PPORT_PHY_STATISTICAL_PER_LANE_COUNTERS; i++) @@ -1294,15 +1292,13 @@ static MLX5E_DECLARE_STATS_GRP_OP_FILL_STATS(phy) data, MLX5_GET(ppcnt_reg, priv->stats.pport.phy_counters, counter_set.phys_layer_cntrs.link_down_events)); - if (!MLX5_CAP_PCAM_FEATURE(mdev, ppcnt_statistical_group)) - return; - - for (i = 0; i < NUM_PPORT_PHY_STATISTICAL_COUNTERS; i++) - mlx5e_ethtool_put_stat( - data, - MLX5E_READ_CTR64_BE( - &priv->stats.pport.phy_statistical_counters, - pport_phy_statistical_stats_desc, i)); + if (MLX5_CAP_PCAM_FEATURE(mdev, ppcnt_statistical_group)) + for (i = 0; i < NUM_PPORT_PHY_STATISTICAL_COUNTERS; i++) + mlx5e_ethtool_put_stat( + data, + MLX5E_READ_CTR64_BE( + &priv->stats.pport.phy_statistical_counters, + pport_phy_statistical_stats_desc, i)); if (MLX5_CAP_PCAM_FEATURE(mdev, per_lane_error_counters)) for (i = 0; i < NUM_PPORT_PHY_STATISTICAL_PER_LANE_COUNTERS; i++) From patchwork Sun Mar 16 08:14:34 2025 Content-Type: text/plain; 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Sun, 16 Mar 2025 01:14:52 -0700 From: Tariq Toukan To: "David S. Miller" , Jakub Kicinski , Paolo Abeni , Eric Dumazet , "Andrew Lunn" CC: Gal Pressman , Leon Romanovsky , "Yael Chemla" , Saeed Mahameed , "Leon Romanovsky" , Tariq Toukan , "Jonathan Corbet" , , , , , Kalesh Anakkur Purayil , Jacob Keller , Stanislav Fomichev Subject: [PATCH net-next V2 2/4] net/mlx5e: Access PHY layer counter group as other counter groups Date: Sun, 16 Mar 2025 10:14:34 +0200 Message-ID: <1742112876-2890-3-git-send-email-tariqt@nvidia.com> X-Mailer: git-send-email 2.8.0 In-Reply-To: <1742112876-2890-1-git-send-email-tariqt@nvidia.com> References: <1742112876-2890-1-git-send-email-tariqt@nvidia.com> Precedence: bulk X-Mailing-List: netdev@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-NV-OnPremToCloud: AnonymousSubmission X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: BN1PEPF00004683:EE_|SJ0PR12MB6928:EE_ X-MS-Office365-Filtering-Correlation-Id: c3857f24-58a1-4251-79d7-08dd6462a922 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|1800799024|36860700013|82310400026|7416014|376014; X-Microsoft-Antispam-Message-Info: +xeX3WtSYJCOe3or0HVMXf0eS1C8bLo1VICvtwZWDcDdp6aam1qnd/2mxgghNbcQ2vjRY026lEodWLRzbsDprMGGKvkryX0YqqSnnNzNMoKHr3wC+FHWlfxaFb+h1sX9w0BeSAK+IfaHIMIL8AQZre5LzLJkwie7LgzvvBPIiOON8P0JjQ91LK5JlZniZRaGr42J7PRYZT9PWGZuaMX58Y7P5FzMSMrpqFim1vptHz6/lEA8yq3yQBx/rqObjj/gvJxyeadM/skTpaEsphtCjj8T74VH+BzSBqoctn8SXLEQE3yWQZ7ohVmNgcLnOJc9ux37StrXv86T0XCKHSDAjRsMP1Mt55IuEhMsReELMU7Vq/lR5ZVned3tzJVhydWzjh1R6s8oiBucnQfjFrLlHVn/VSuqWK+Ts0jrNXu/8SzfFancTlNwU8CEPvg9THAn1mp21huRbMsPJbcTuIBO2ZMG4n8wRzMNuAb8wKaehMljBplEszUEmyMfgwFQpSCTaxoq0YATkLTwTFX7Hya8104bmlL9GUQ9e8ey2Sh6dOAgve5xv9vrj5ZwIjTd/w/yoYsHqpc3O7As8ILozXGidV1QRA+rhq+fqHGOlsyyfKrT/1+6vEwhvjtqYApJq79h2qc1YxjBdm4qcOFZSEbc4k7CWpX6XLFhDzbotEapUme7Cthj6I7J54aJmusYOw6Ep3Js0eByQxzpUae5xk5e7mYztZ2xxUGd8fGZYpbNN8kyjFpwwo4RKjiKvrS/R0pwnFvQuaD94W1O2JiBGRVOYUUq0wTD15OvJ9gqjUlQKKbbWxbI+ghBkrMTNADGfK1DbQwzJY+BbcaldeeDNnIUsCmD/NgZFCToV1ZeQMK41JcFh+yVBlfy6aQy1A+XlZ+RxR607/Njn3Go1CMaeSYdCcaCWK+FvFzKHsDK0O6LGACUfqY3gKCTjVKNssfcrWgud3TsqLp7YDRgJVVrRoYXlqay7CSGajC0Oyc3Iq1P+Yn/Zidi8KFtcgDgKdVMA7er3ZUg0LgBqwmxNQ5IswJdhOy7dpwVsiQpBW1OabED4+PTnjWT2AxxJ8U55CMV97EpHZYl4CKxN/BvGv2ISgyFAKchuCkHc1FvZLRTr9Hx2FgZVAc3cHGyV4TN9KzufAf9WmDINOUNUIYdASYY89/FQ+1cYXeh3kKTYVyal+jLmIKzCAg9l/+CM5q9SArBytpEFVJyOUBTa0L5zsggrqpI8RrbH8LXuJFljzncKnPKU+Go6FATJ7m/oQ+HfMQVEYWH1vdqKNoTGPMGDLMpXsxRr/YAsgrMSawZ65WsCy4urSxcDC1mjUwgDALiNss9uzWz4MVJzRg8lVCWrWQdZF7gA+OtzDN4FpEf6Jb+EH03nPyeLTaMb57kEU4PnUEKeQajX7nk2KvfDPR8lpmt2CS6jhO6QRO8YSLD6vjSw1ArGnUwjoAm1dvXvEhvU4JQpUxsr58r3yDHfMoZMm6EbK0n7YsZVnTJsS24D41mwjkvRoU= X-Forefront-Antispam-Report: CIP:216.228.118.233;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:dc7edge2.nvidia.com;CAT:NONE;SFS:(13230040)(1800799024)(36860700013)(82310400026)(7416014)(376014);DIR:OUT;SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 16 Mar 2025 08:15:06.1628 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: c3857f24-58a1-4251-79d7-08dd6462a922 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.118.233];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: BN1PEPF00004683.namprd03.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: SJ0PR12MB6928 X-Patchwork-Delegate: kuba@kernel.org From: Yael Chemla Adjust the way physical layer counters group is accessed to match the generic method used for accessing other PPCNT counter groups. Signed-off-by: Yael Chemla Reviewed-by: Cosmin Ratiu Signed-off-by: Tariq Toukan Reviewed-by: Jacob Keller --- .../ethernet/mellanox/mlx5/core/en_stats.c | 25 +++++++++++++------ 1 file changed, 18 insertions(+), 7 deletions(-) diff --git a/drivers/net/ethernet/mellanox/mlx5/core/en_stats.c b/drivers/net/ethernet/mellanox/mlx5/core/en_stats.c index 77d34037b92b..0cf0c920532f 100644 --- a/drivers/net/ethernet/mellanox/mlx5/core/en_stats.c +++ b/drivers/net/ethernet/mellanox/mlx5/core/en_stats.c @@ -1227,6 +1227,13 @@ void mlx5e_stats_ts_get(struct mlx5e_priv *priv, mutex_unlock(&priv->state_lock); } +#define PPORT_PHY_LAYER_OFF(c) \ + MLX5_BYTE_OFF(ppcnt_reg, \ + counter_set.phys_layer_cntrs.c) +static const struct counter_desc pport_phy_layer_cntrs_stats_desc[] = { + { "link_down_events_phy", PPORT_PHY_LAYER_OFF(link_down_events) } +}; + #define PPORT_PHY_STATISTICAL_OFF(c) \ MLX5_BYTE_OFF(ppcnt_reg, \ counter_set.phys_layer_statistical_cntrs.c##_high) @@ -1243,6 +1250,8 @@ pport_phy_statistical_err_lanes_stats_desc[] = { { "rx_err_lane_3_phy", PPORT_PHY_STATISTICAL_OFF(phy_corrected_bits_lane3) }, }; +#define NUM_PPORT_PHY_LAYER_COUNTERS \ + ARRAY_SIZE(pport_phy_layer_cntrs_stats_desc) #define NUM_PPORT_PHY_STATISTICAL_COUNTERS \ ARRAY_SIZE(pport_phy_statistical_stats_desc) #define NUM_PPORT_PHY_STATISTICAL_PER_LANE_COUNTERS \ @@ -1253,8 +1262,7 @@ static MLX5E_DECLARE_STATS_GRP_OP_NUM_STATS(phy) struct mlx5_core_dev *mdev = priv->mdev; int num_stats; - /* "1" for link_down_events special counter */ - num_stats = 1; + num_stats = NUM_PPORT_PHY_LAYER_COUNTERS; num_stats += MLX5_CAP_PCAM_FEATURE(mdev, ppcnt_statistical_group) ? NUM_PPORT_PHY_STATISTICAL_COUNTERS : 0; @@ -1270,7 +1278,8 @@ static MLX5E_DECLARE_STATS_GRP_OP_FILL_STRS(phy) struct mlx5_core_dev *mdev = priv->mdev; int i; - ethtool_puts(data, "link_down_events_phy"); + for (i = 0; i < NUM_PPORT_PHY_LAYER_COUNTERS; i++) + ethtool_puts(data, pport_phy_layer_cntrs_stats_desc[i].format); if (MLX5_CAP_PCAM_FEATURE(mdev, ppcnt_statistical_group)) for (i = 0; i < NUM_PPORT_PHY_STATISTICAL_COUNTERS; i++) @@ -1287,10 +1296,12 @@ static MLX5E_DECLARE_STATS_GRP_OP_FILL_STATS(phy) struct mlx5_core_dev *mdev = priv->mdev; int i; - /* link_down_events_phy has special handling since it is not stored in __be64 format */ - mlx5e_ethtool_put_stat( - data, MLX5_GET(ppcnt_reg, priv->stats.pport.phy_counters, - counter_set.phys_layer_cntrs.link_down_events)); + for (i = 0; i < NUM_PPORT_PHY_LAYER_COUNTERS; i++) + mlx5e_ethtool_put_stat( + data, + MLX5E_READ_CTR32_BE(&priv->stats.pport + .phy_counters, + pport_phy_layer_cntrs_stats_desc, i)); if (MLX5_CAP_PCAM_FEATURE(mdev, ppcnt_statistical_group)) for (i = 0; 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Miller" , Jakub Kicinski , Paolo Abeni , Eric Dumazet , "Andrew Lunn" CC: Gal Pressman , Leon Romanovsky , "Yael Chemla" , Saeed Mahameed , "Leon Romanovsky" , Tariq Toukan , "Jonathan Corbet" , , , , , Kalesh Anakkur Purayil , Jacob Keller , Stanislav Fomichev Subject: [PATCH net-next V2 3/4] net/mlx5e: Get counter group size by FW capability Date: Sun, 16 Mar 2025 10:14:35 +0200 Message-ID: <1742112876-2890-4-git-send-email-tariqt@nvidia.com> X-Mailer: git-send-email 2.8.0 In-Reply-To: <1742112876-2890-1-git-send-email-tariqt@nvidia.com> References: <1742112876-2890-1-git-send-email-tariqt@nvidia.com> Precedence: bulk X-Mailing-List: netdev@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-NV-OnPremToCloud: AnonymousSubmission X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: CY4PEPF0000EE33:EE_|MW3PR12MB4490:EE_ X-MS-Office365-Filtering-Correlation-Id: e88ec0c5-ef2a-4f91-ec24-08dd6462a7b5 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|36860700013|82310400026|1800799024|7416014|376014; X-Microsoft-Antispam-Message-Info: dsbmcAVF/OkYm5JOprB/3Xi/Pzg1e9PGUOTYZM1BCkTkCVG+4RAVgEBPe4xytrwFunVDg92ByyVlHeiccfDipPS9e61bteicRRqmGs4nTVCC0gvSKe+ElZy6BB6aAGZ4Yj7+Z5qo4TRQs4L880p/6ZV7zJZj60fZfiG1lOnUMy4hzAaXjIknr849srj/ZfcKxl/qCYDFm0UA8JFlvzz9pLWi2kxDBmDQO7Qoubn+udTc6Q7NPptBPVfrYM5Seg9OTqQg/0CCEML/pxYP7ivz9KgsJmq6TmXVaOBEsUO3bEf++kwhhpJUnXiNpMItWmmdjhOnQ35AbkBddBv4iRebILwalsIPnfQePWM861HLykxf09san8FDwDwYhc85ePuz+zj3mhj/2s1eGJ895gx8DHifkcaaJCI+AOGkmI+jj9lAyyjiHvLo+2trl03nbPq7Z8dE0FEV44My/Ix4FWgW55fSOOenngNOZlBup2xlfyVGpd1X+wTh5RrkX7kzOXg8JenvxfbIdc3uj70YLfwDZAlCyl4nuLUuOn3Z5lpXRWDHRqmQZ2Cu7Qla0uYtfFO2RirZwexrA2T+jy7V/4jLmMNVuOB33+ln+xzS9GIsbF0OMM+BuV3LMISGA+oEC9iRpgbOwCiLDH6L2we3JDVXxwudMRzdpEiNHuVZ9eHbmqkRR7c2YCOKs7poSO5jvqJrDP1ZbSuLKsh+JKU6n9RLPDhZ7XcCBC0ZpVWqmz8y5z4F3i1RyH+6BshCcptBS/dGI8UREGsOqZbAr3cIrP+wbH6Xdq26w1n6mbdDxCLGHRvv+Tpjkn12g5+/+oDynzf9PSXPGTxcEoUxVSgt6PR81AxNOlEuUflEgjB8/rgdVnCR2z5n6ennzdI4M7zW8RSM5wqqPP1lEeEwW+FPiWCnYyBkhvtf3YRQWq9kaXATYWx60DEbTjGjpBNHDin346VGY4cCVfG4+ycXvjSf+9lv+k5AT/AHZyVQzbrudiIIFSb1IPlQhAIB9h7t1CdRj9vNyyOaUE5n+3qfhnMfcXCeGugtyul7RO1qVK6psQO5kroUP5NJDw3mL1LtIq+iJsUcBnkvcessHJ3QwvV0sjbQQyKPeQypAbMiRvXcMbSnSLKH3Nhn5Y6Hp8LJSpniV7DuUJbNBfjzboa3eC8uk22gqMaZGzxhqKMvrnbC0SWPlO7cgSUEzxZhcUxUxf1JNtoICDYP1QvlPQrYwh6fKFFZcvy9TICiSHgzjWmXoKd09MhHvm8OnAFhREVdsUJKz4PoRKItWQ+eqbWbnmf3CTfcsaWn7FYNL9nR5lGYPv03Jxe/lULBRka9YCYSxyMo+fBYCGhjX7FHWSt+2EQmwucngMOEgqLH8Vc2KGwQaEuUizfh0SQ2Ueh6qrAtZb26j9ITumX2U6WBwsXU/fzyEXDQSCVi+JBqg4g7ja411+BhJy7b5t6v8cda1cuTYTMrw7N4ZgpViwX5VPcY77I6zB1Jvkm1l09yChn08ylnmozKRCg= X-Forefront-Antispam-Report: CIP:216.228.118.232;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:dc7edge1.nvidia.com;CAT:NONE;SFS:(13230040)(36860700013)(82310400026)(1800799024)(7416014)(376014);DIR:OUT;SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 16 Mar 2025 08:15:03.8831 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: e88ec0c5-ef2a-4f91-ec24-08dd6462a7b5 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.118.232];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: CY4PEPF0000EE33.namprd05.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: MW3PR12MB4490 X-Patchwork-Delegate: kuba@kernel.org From: Yael Chemla Retrieve the number of fields supported by each PPCNT counter group based on the FW capability for this group. Signed-off-by: Yael Chemla Signed-off-by: Tariq Toukan Reviewed-by: Jacob Keller Reviewed-by: Kalesh AP --- .../ethernet/mellanox/mlx5/core/en_stats.c | 58 ++++++++++--------- 1 file changed, 31 insertions(+), 27 deletions(-) diff --git a/drivers/net/ethernet/mellanox/mlx5/core/en_stats.c b/drivers/net/ethernet/mellanox/mlx5/core/en_stats.c index 0cf0c920532f..a417962acfa9 100644 --- a/drivers/net/ethernet/mellanox/mlx5/core/en_stats.c +++ b/drivers/net/ethernet/mellanox/mlx5/core/en_stats.c @@ -1257,6 +1257,13 @@ pport_phy_statistical_err_lanes_stats_desc[] = { #define NUM_PPORT_PHY_STATISTICAL_PER_LANE_COUNTERS \ ARRAY_SIZE(pport_phy_statistical_err_lanes_stats_desc) +#define NUM_PPORT_PHY_STATISTICAL_LOOPBACK_COUNTERS(dev) \ + (MLX5_CAP_PCAM_FEATURE(dev, ppcnt_statistical_group) ? \ + NUM_PPORT_PHY_STATISTICAL_COUNTERS : 0) +#define NUM_PPORT_PHY_STATISTICAL_PER_LANE_LOOPBACK_COUNTERS(dev) \ + (MLX5_CAP_PCAM_FEATURE(dev, per_lane_error_counters) ? \ + NUM_PPORT_PHY_STATISTICAL_PER_LANE_COUNTERS : 0) + static MLX5E_DECLARE_STATS_GRP_OP_NUM_STATS(phy) { struct mlx5_core_dev *mdev = priv->mdev; @@ -1264,11 +1271,9 @@ static MLX5E_DECLARE_STATS_GRP_OP_NUM_STATS(phy) num_stats = NUM_PPORT_PHY_LAYER_COUNTERS; - num_stats += MLX5_CAP_PCAM_FEATURE(mdev, ppcnt_statistical_group) ? - NUM_PPORT_PHY_STATISTICAL_COUNTERS : 0; + num_stats += NUM_PPORT_PHY_STATISTICAL_LOOPBACK_COUNTERS(mdev); - num_stats += MLX5_CAP_PCAM_FEATURE(mdev, per_lane_error_counters) ? - NUM_PPORT_PHY_STATISTICAL_PER_LANE_COUNTERS : 0; + num_stats += NUM_PPORT_PHY_STATISTICAL_PER_LANE_LOOPBACK_COUNTERS(mdev); return num_stats; } @@ -1281,14 +1286,15 @@ static MLX5E_DECLARE_STATS_GRP_OP_FILL_STRS(phy) for (i = 0; i < NUM_PPORT_PHY_LAYER_COUNTERS; i++) ethtool_puts(data, pport_phy_layer_cntrs_stats_desc[i].format); - if (MLX5_CAP_PCAM_FEATURE(mdev, ppcnt_statistical_group)) - for (i = 0; i < NUM_PPORT_PHY_STATISTICAL_COUNTERS; i++) - ethtool_puts(data, pport_phy_statistical_stats_desc[i].format); + for (i = 0; i < NUM_PPORT_PHY_STATISTICAL_LOOPBACK_COUNTERS(mdev); i++) + ethtool_puts(data, pport_phy_statistical_stats_desc[i].format); - if (MLX5_CAP_PCAM_FEATURE(mdev, per_lane_error_counters)) - for (i = 0; i < NUM_PPORT_PHY_STATISTICAL_PER_LANE_COUNTERS; i++) - ethtool_puts(data, - pport_phy_statistical_err_lanes_stats_desc[i].format); + for (i = 0; + i < NUM_PPORT_PHY_STATISTICAL_PER_LANE_LOOPBACK_COUNTERS(mdev); + i++) + ethtool_puts(data, + pport_phy_statistical_err_lanes_stats_desc[i] + .format); } static MLX5E_DECLARE_STATS_GRP_OP_FILL_STATS(phy) @@ -1303,23 +1309,21 @@ static MLX5E_DECLARE_STATS_GRP_OP_FILL_STATS(phy) .phy_counters, pport_phy_layer_cntrs_stats_desc, i)); - if (MLX5_CAP_PCAM_FEATURE(mdev, ppcnt_statistical_group)) - for (i = 0; i < NUM_PPORT_PHY_STATISTICAL_COUNTERS; i++) - mlx5e_ethtool_put_stat( - data, - MLX5E_READ_CTR64_BE( - &priv->stats.pport.phy_statistical_counters, - pport_phy_statistical_stats_desc, i)); + for (i = 0; i < NUM_PPORT_PHY_STATISTICAL_LOOPBACK_COUNTERS(mdev); i++) + mlx5e_ethtool_put_stat( + data, + MLX5E_READ_CTR64_BE( + &priv->stats.pport.phy_statistical_counters, + pport_phy_statistical_stats_desc, i)); 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Miller" , Jakub Kicinski , Paolo Abeni , Eric Dumazet , "Andrew Lunn" CC: Gal Pressman , Leon Romanovsky , "Yael Chemla" , Saeed Mahameed , "Leon Romanovsky" , Tariq Toukan , "Jonathan Corbet" , , , , , Kalesh Anakkur Purayil , Jacob Keller , Stanislav Fomichev Subject: [PATCH net-next V2 4/4] net/mlx5e: Expose port reset cycle recovery counter via ethtool Date: Sun, 16 Mar 2025 10:14:36 +0200 Message-ID: <1742112876-2890-5-git-send-email-tariqt@nvidia.com> X-Mailer: git-send-email 2.8.0 In-Reply-To: <1742112876-2890-1-git-send-email-tariqt@nvidia.com> References: <1742112876-2890-1-git-send-email-tariqt@nvidia.com> Precedence: bulk X-Mailing-List: netdev@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-NV-OnPremToCloud: AnonymousSubmission X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: BN1PEPF00004685:EE_|SA3PR12MB7974:EE_ X-MS-Office365-Filtering-Correlation-Id: 7d53355e-b07d-49b3-f47e-08dd6462b10a X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|82310400026|36860700013|1800799024|7416014|376014; X-Microsoft-Antispam-Message-Info: xVmNA51KZfBIPyl99NdsyjN7/M/fNCzQ8iZFtgUXQbGLg17wOy79q3pd9EVCWsNoCuuODx44zibabyAXE1PZ1d2YYywpYRfpvVr6N+KpkU9XouJ1ZR8t/uv6wzxH+NFbnckvoqbSqBq99zP3gJpA5lgkvzZmaxy9J6lTmt38pMzCyfXhRzYeNaq4gitwXfiXyU1aDHNZpO6zFpcXqPqc4NPNKRwnntyrICydCZMKLRO1dItl0pgt9FRjQXMGnM/4XGJhVRxdL85aBWheqtbYO3IGjdxtMe3Gl9Cty6tCpb84mA3J4esMmLHX+jN6H+IpjkFaHBEPQ3zetAaCY4Q9EeA3e86sYH0ScRCxOSoq58ymsD1kB0BEuoPZmSzYdx87KNu5ygJrSd/Tg4qSwukpkareXZRYf3j2/sgFa83JNpiLtpRs0IV/QgCEyCM7Ce02c0X4ZZ9Ujs/QCDiKo8aedrbDAkk1l7AUCXmXMuZfGfVFU0NxBqGAlbZ62F+QWVFHQqHww5qLXMsC7ImPqO78fAHTVoshC1FBDfizQMpPA1sBIS+x2vdkzri2gUPHKuJGVlvunJ6TvROypUwFtM2BlpTobnePjgquU2s4Fjc8IvDrXBDnyM2DYMa0ZWRWw11W+1sJIeoMcPtsskyV+kzELDw/GDPkwpLr1p1VyAV3HLgSNu6ou33vLrjnp3YAcBHh4XYE935yXR1ZkRd+YFRcDjENIjxNMa60imXsri/+t9fDnzhwAl4KlNmlE++Zg0KDeoxiiDqXZGtPdJqM1AmENxDmOqgit56wrHbYLQmRe8znGT7lXRLfyuBlHNj/9q9NeTo03zwGP/Od6yFvr6/GM5MrVgVH6KNr35dPXs4/Brjo6YL7ZNrfhF0KQf/b1DCWfRYNkEz9aH8oFrRwRNCrUUdRxgCzJ/2nU5guPEhYezTzrTyylZ4UDMu3RflMIcd19P7X54B+Ln+3igi8TuIlEkcZlRECP+6CUtRe1/ypOiMylKLirAykkh5fk9khe8h963NVVImIEp0WJgJGnPZBp3bM/PYpJPpdD4oXN/qPvIhQ/oAMRa3XVAi8Tx1mJdpSdKMQk4FlGAaxB9f07wvC/5vu2TVHlLeev6B5sKC+1TCFo6J5QxS/4T7DD5E/+JL+XuayUHUjBUqEEBJwYLiqHJp9CEvOFNnV1M6finzo+I/DDiU75GOaHctarE8xl9mPkNIpeLtBny1CpAd1rDKli1lHaXswmbGaJ/tQdEtrhpUNRGxXo8xXkBdV/BsdwmG32h9ehLQqFDmtdCpSQC7SP98TgIs5NQi9Uc0l5HtYRlXtHLwmVdh4ntKwCMIn3teB21/IUj4K8kN7OHuxHRo651z7ky6RYuF79VsK8CGQA364AvsCtiXozp4z5jaij0CUbcsGQNpNmKGsogdmbp1n8tXg6vv3cCYUFABefGVS7tSUtkxkv+hKenYf7cnCUrqNiVTJLnJ5XisarZl5ZN8uyNUdogY5DNEXkclwhanthVY= X-Forefront-Antispam-Report: CIP:216.228.118.233;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:dc7edge2.nvidia.com;CAT:NONE;SFS:(13230040)(82310400026)(36860700013)(1800799024)(7416014)(376014);DIR:OUT;SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 16 Mar 2025 08:15:19.4304 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 7d53355e-b07d-49b3-f47e-08dd6462b10a X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.118.233];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: BN1PEPF00004685.namprd03.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: SA3PR12MB7974 X-Patchwork-Delegate: kuba@kernel.org From: Yael Chemla Display recovery event of PPCNT recovery counters group. Counts (per link) the number of total successful recovery events of any recovery types during port reset cycle. Signed-off-by: Yael Chemla Reviewed-by: Cosmin Ratiu Signed-off-by: Tariq Toukan Reviewed-by: Jacob Keller --- .../ethernet/mellanox/mlx5/counters.rst | 5 +++ .../ethernet/mellanox/mlx5/core/en_stats.c | 44 ++++++++++++++++--- .../ethernet/mellanox/mlx5/core/en_stats.h | 4 ++ 3 files changed, 48 insertions(+), 5 deletions(-) diff --git a/Documentation/networking/device_drivers/ethernet/mellanox/mlx5/counters.rst b/Documentation/networking/device_drivers/ethernet/mellanox/mlx5/counters.rst index 99d95be4d159..43d72c8b713b 100644 --- a/Documentation/networking/device_drivers/ethernet/mellanox/mlx5/counters.rst +++ b/Documentation/networking/device_drivers/ethernet/mellanox/mlx5/counters.rst @@ -1082,6 +1082,11 @@ like flow control, FEC and more. need to replace the cable/transceiver. - Error + * - `total_success_recovery_phy` + - The number of total successful recovery events of any type during + ports reset cycle. + - Error + * - `rx_out_of_buffer` - Number of times receive queue had no software buffers allocated for the adapter's incoming traffic. diff --git a/drivers/net/ethernet/mellanox/mlx5/core/en_stats.c b/drivers/net/ethernet/mellanox/mlx5/core/en_stats.c index a417962acfa9..acb00fd7efa4 100644 --- a/drivers/net/ethernet/mellanox/mlx5/core/en_stats.c +++ b/drivers/net/ethernet/mellanox/mlx5/core/en_stats.c @@ -1250,12 +1250,22 @@ pport_phy_statistical_err_lanes_stats_desc[] = { { "rx_err_lane_3_phy", PPORT_PHY_STATISTICAL_OFF(phy_corrected_bits_lane3) }, }; +#define PPORT_PHY_RECOVERY_OFF(c) \ + MLX5_BYTE_OFF(ppcnt_reg, counter_set.phys_layer_recovery_cntrs.c) +static const struct counter_desc +pport_phy_recovery_cntrs_stats_desc[] = { + { "total_success_recovery_phy", + PPORT_PHY_RECOVERY_OFF(total_successful_recovery_events) } +}; + #define NUM_PPORT_PHY_LAYER_COUNTERS \ ARRAY_SIZE(pport_phy_layer_cntrs_stats_desc) #define NUM_PPORT_PHY_STATISTICAL_COUNTERS \ ARRAY_SIZE(pport_phy_statistical_stats_desc) #define NUM_PPORT_PHY_STATISTICAL_PER_LANE_COUNTERS \ ARRAY_SIZE(pport_phy_statistical_err_lanes_stats_desc) +#define NUM_PPORT_PHY_RECOVERY_COUNTERS \ + ARRAY_SIZE(pport_phy_recovery_cntrs_stats_desc) #define NUM_PPORT_PHY_STATISTICAL_LOOPBACK_COUNTERS(dev) \ (MLX5_CAP_PCAM_FEATURE(dev, ppcnt_statistical_group) ? \ @@ -1263,6 +1273,9 @@ pport_phy_statistical_err_lanes_stats_desc[] = { #define NUM_PPORT_PHY_STATISTICAL_PER_LANE_LOOPBACK_COUNTERS(dev) \ (MLX5_CAP_PCAM_FEATURE(dev, per_lane_error_counters) ? \ NUM_PPORT_PHY_STATISTICAL_PER_LANE_COUNTERS : 0) +#define NUM_PPORT_PHY_RECOVERY_LOOPBACK_COUNTERS(dev) \ + (MLX5_CAP_PCAM_FEATURE(dev, ppcnt_recovery_counters) ? \ + NUM_PPORT_PHY_RECOVERY_COUNTERS : 0) static MLX5E_DECLARE_STATS_GRP_OP_NUM_STATS(phy) { @@ -1275,6 +1288,7 @@ static MLX5E_DECLARE_STATS_GRP_OP_NUM_STATS(phy) num_stats += NUM_PPORT_PHY_STATISTICAL_PER_LANE_LOOPBACK_COUNTERS(mdev); + num_stats += NUM_PPORT_PHY_RECOVERY_LOOPBACK_COUNTERS(mdev); return num_stats; } @@ -1295,6 +1309,10 @@ static MLX5E_DECLARE_STATS_GRP_OP_FILL_STRS(phy) ethtool_puts(data, pport_phy_statistical_err_lanes_stats_desc[i] .format); + + for (i = 0; i < NUM_PPORT_PHY_RECOVERY_LOOPBACK_COUNTERS(mdev); i++) + ethtool_puts(data, + pport_phy_recovery_cntrs_stats_desc[i].format); } static MLX5E_DECLARE_STATS_GRP_OP_FILL_STATS(phy) @@ -1324,6 +1342,13 @@ static MLX5E_DECLARE_STATS_GRP_OP_FILL_STATS(phy) MLX5E_READ_CTR64_BE( &priv->stats.pport.phy_statistical_counters, pport_phy_statistical_err_lanes_stats_desc, i)); + + for (i = 0; i < NUM_PPORT_PHY_RECOVERY_LOOPBACK_COUNTERS(mdev); i++) + mlx5e_ethtool_put_stat( + data, + MLX5E_READ_CTR32_BE( + &priv->stats.pport.phy_recovery_counters, + pport_phy_recovery_cntrs_stats_desc, i)); } static MLX5E_DECLARE_STATS_GRP_OP_UPDATE_STATS(phy) @@ -1339,12 +1364,21 @@ static MLX5E_DECLARE_STATS_GRP_OP_UPDATE_STATS(phy) MLX5_SET(ppcnt_reg, in, grp, MLX5_PHYSICAL_LAYER_COUNTERS_GROUP); mlx5_core_access_reg(mdev, in, sz, out, sz, MLX5_REG_PPCNT, 0, 0); - if (!MLX5_CAP_PCAM_FEATURE(mdev, ppcnt_statistical_group)) - return; + if (MLX5_CAP_PCAM_FEATURE(mdev, ppcnt_statistical_group)) { + out = pstats->phy_statistical_counters; + MLX5_SET(ppcnt_reg, in, grp, + MLX5_PHYSICAL_LAYER_STATISTICAL_GROUP); + mlx5_core_access_reg(mdev, in, sz, out, sz, MLX5_REG_PPCNT, 0, + 0); + } - out = pstats->phy_statistical_counters; - MLX5_SET(ppcnt_reg, in, grp, MLX5_PHYSICAL_LAYER_STATISTICAL_GROUP); - mlx5_core_access_reg(mdev, in, sz, out, sz, MLX5_REG_PPCNT, 0, 0); + if (MLX5_CAP_PCAM_FEATURE(mdev, ppcnt_recovery_counters)) { + out = pstats->phy_recovery_counters; + MLX5_SET(ppcnt_reg, in, grp, + MLX5_PHYSICAL_LAYER_RECOVERY_GROUP); + mlx5_core_access_reg(mdev, in, sz, out, sz, MLX5_REG_PPCNT, 0, + 0); + } } void mlx5e_get_link_ext_stats(struct net_device *dev, diff --git a/drivers/net/ethernet/mellanox/mlx5/core/en_stats.h b/drivers/net/ethernet/mellanox/mlx5/core/en_stats.h index 5961c569cfe0..0d87947e348d 100644 --- a/drivers/net/ethernet/mellanox/mlx5/core/en_stats.h +++ b/drivers/net/ethernet/mellanox/mlx5/core/en_stats.h @@ -309,6 +309,9 @@ struct mlx5e_vport_stats { #define PPORT_PHY_STATISTICAL_GET(pstats, c) \ MLX5_GET64(ppcnt_reg, (pstats)->phy_statistical_counters, \ counter_set.phys_layer_statistical_cntrs.c##_high) +#define PPORT_PHY_RECOVERY_GET(pstats, c) \ + MLX5_GET64(ppcnt_reg, (pstats)->phy_recovery_counters, \ + counter_set.phys_layer_recovery_cntrs.c) #define PPORT_PER_PRIO_GET(pstats, prio, c) \ MLX5_GET64(ppcnt_reg, pstats->per_prio_counters[prio], \ counter_set.eth_per_prio_grp_data_layout.c##_high) @@ -324,6 +327,7 @@ struct mlx5e_pport_stats { __be64 per_prio_counters[NUM_PPORT_PRIO][MLX5_ST_SZ_QW(ppcnt_reg)]; __be64 phy_counters[MLX5_ST_SZ_QW(ppcnt_reg)]; __be64 phy_statistical_counters[MLX5_ST_SZ_QW(ppcnt_reg)]; + __be64 phy_recovery_counters[MLX5_ST_SZ_QW(ppcnt_reg)]; __be64 eth_ext_counters[MLX5_ST_SZ_QW(ppcnt_reg)]; __be64 per_tc_prio_counters[NUM_PPORT_PRIO][MLX5_ST_SZ_QW(ppcnt_reg)]; __be64 per_tc_congest_prio_counters[NUM_PPORT_PRIO][MLX5_ST_SZ_QW(ppcnt_reg)];