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Signed-off-by: Akihiko Odaki --- hw/intc/arm_gicv3_cpuif.c | 100 +++++++++--------- hw/intc/arm_gicv3_kvm.c | 2 +- target/arm/debug_helper.c | 2 +- target/arm/helper.c | 219 +++++++++++++++++++++----------------- target/arm/tcg/tlb-insns.c | 256 +++++++++++++++++++++++++-------------------- 5 files changed, 321 insertions(+), 258 deletions(-) diff --git a/hw/intc/arm_gicv3_cpuif.c b/hw/intc/arm_gicv3_cpuif.c index 7f1d071c198b..e02854204d25 100644 --- a/hw/intc/arm_gicv3_cpuif.c +++ b/hw/intc/arm_gicv3_cpuif.c @@ -2432,7 +2432,7 @@ static void icc_reset(CPUARMState *env, const ARMCPRegInfo *ri) static const ARMCPRegInfo gicv3_cpuif_reginfo[] = { { .name = "ICC_PMR_EL1", .state = ARM_CP_STATE_BOTH, .opc0 = 3, .opc1 = 0, .crn = 4, .crm = 6, .opc2 = 0, - .type = ARM_CP_IO | ARM_CP_NO_RAW, + .type = ARM_CP_IO | ARM_CP_NO_RAW | ARM_CP_NO_GDB, .access = PL1_RW, .accessfn = gicv3_irqfiq_access, .readfn = icc_pmr_read, .writefn = icc_pmr_write, @@ -2444,32 +2444,32 @@ static const ARMCPRegInfo gicv3_cpuif_reginfo[] = { }, { .name = "ICC_IAR0_EL1", .state = ARM_CP_STATE_BOTH, .opc0 = 3, .opc1 = 0, .crn = 12, .crm = 8, .opc2 = 0, - .type = ARM_CP_IO | ARM_CP_NO_RAW, + .type = ARM_CP_IO | ARM_CP_NO_RAW | ARM_CP_NO_GDB, .access = PL1_R, .accessfn = gicv3_fiq_access, .readfn = icc_iar0_read, }, { .name = "ICC_EOIR0_EL1", .state = ARM_CP_STATE_BOTH, .opc0 = 3, .opc1 = 0, .crn = 12, .crm = 8, .opc2 = 1, - .type = ARM_CP_IO | ARM_CP_NO_RAW, + .type = ARM_CP_IO | ARM_CP_NO_RAW | ARM_CP_NO_GDB, .access = PL1_W, .accessfn = gicv3_fiq_access, .writefn = icc_eoir_write, }, { .name = "ICC_HPPIR0_EL1", .state = ARM_CP_STATE_BOTH, .opc0 = 3, .opc1 = 0, .crn = 12, .crm = 8, .opc2 = 2, - .type = ARM_CP_IO | ARM_CP_NO_RAW, + .type = ARM_CP_IO | ARM_CP_NO_RAW | ARM_CP_NO_GDB, .access = PL1_R, .accessfn = gicv3_fiq_access, .readfn = icc_hppir0_read, }, { .name = "ICC_BPR0_EL1", .state = ARM_CP_STATE_BOTH, .opc0 = 3, .opc1 = 0, .crn = 12, .crm = 8, .opc2 = 3, - .type = ARM_CP_IO | ARM_CP_NO_RAW, + .type = ARM_CP_IO | ARM_CP_NO_RAW | ARM_CP_NO_GDB, .access = PL1_RW, .accessfn = gicv3_fiq_access, .readfn = icc_bpr_read, .writefn = icc_bpr_write, }, { .name = "ICC_AP0R0_EL1", .state = ARM_CP_STATE_BOTH, .opc0 = 3, .opc1 = 0, .crn = 12, .crm = 8, .opc2 = 4, - .type = ARM_CP_IO | ARM_CP_NO_RAW, + .type = ARM_CP_IO | ARM_CP_NO_RAW | ARM_CP_NO_GDB, .access = PL1_RW, .accessfn = gicv3_fiq_access, .readfn = icc_ap_read, .writefn = icc_ap_write, @@ -2477,81 +2477,81 @@ static const ARMCPRegInfo gicv3_cpuif_reginfo[] = { /* All the ICC_AP1R*_EL1 registers are banked */ { .name = "ICC_AP1R0_EL1", .state = ARM_CP_STATE_BOTH, .opc0 = 3, .opc1 = 0, .crn = 12, .crm = 9, .opc2 = 0, - .type = ARM_CP_IO | ARM_CP_NO_RAW, + .type = ARM_CP_IO | ARM_CP_NO_RAW | ARM_CP_NO_GDB, .access = PL1_RW, .accessfn = gicv3_irq_access, .readfn = icc_ap_read, .writefn = icc_ap_write, }, { .name = "ICC_DIR_EL1", .state = ARM_CP_STATE_BOTH, .opc0 = 3, .opc1 = 0, .crn = 12, .crm = 11, .opc2 = 1, - .type = ARM_CP_IO | ARM_CP_NO_RAW, + .type = ARM_CP_IO | ARM_CP_NO_RAW | ARM_CP_NO_GDB, .access = PL1_W, .accessfn = gicv3_dir_access, .writefn = icc_dir_write, }, { .name = "ICC_RPR_EL1", .state = ARM_CP_STATE_BOTH, .opc0 = 3, .opc1 = 0, .crn = 12, .crm = 11, .opc2 = 3, - .type = ARM_CP_IO | ARM_CP_NO_RAW, + .type = ARM_CP_IO | ARM_CP_NO_RAW | ARM_CP_NO_GDB, .access = PL1_R, .accessfn = gicv3_irqfiq_access, .readfn = icc_rpr_read, }, { .name = "ICC_SGI1R_EL1", .state = ARM_CP_STATE_AA64, .opc0 = 3, .opc1 = 0, .crn = 12, .crm = 11, .opc2 = 5, - .type = ARM_CP_IO | ARM_CP_NO_RAW, + .type = ARM_CP_IO | ARM_CP_NO_RAW | ARM_CP_NO_GDB, .access = PL1_W, .accessfn = gicv3_sgi_access, .writefn = icc_sgi1r_write, }, { .name = "ICC_SGI1R", .cp = 15, .opc1 = 0, .crm = 12, - .type = ARM_CP_64BIT | ARM_CP_IO | ARM_CP_NO_RAW, + .type = ARM_CP_64BIT | ARM_CP_IO | ARM_CP_NO_RAW | ARM_CP_NO_GDB, .access = PL1_W, .accessfn = gicv3_sgi_access, .writefn = icc_sgi1r_write, }, { .name = "ICC_ASGI1R_EL1", .state = ARM_CP_STATE_AA64, .opc0 = 3, .opc1 = 0, .crn = 12, .crm = 11, .opc2 = 6, - .type = ARM_CP_IO | ARM_CP_NO_RAW, + .type = ARM_CP_IO | ARM_CP_NO_RAW | ARM_CP_NO_GDB, .access = PL1_W, .accessfn = gicv3_sgi_access, .writefn = icc_asgi1r_write, }, { .name = "ICC_ASGI1R", .cp = 15, .opc1 = 1, .crm = 12, - .type = ARM_CP_64BIT | ARM_CP_IO | ARM_CP_NO_RAW, + .type = ARM_CP_64BIT | ARM_CP_IO | ARM_CP_NO_RAW | ARM_CP_NO_GDB, .access = PL1_W, .accessfn = gicv3_sgi_access, .writefn = icc_asgi1r_write, }, { .name = "ICC_SGI0R_EL1", .state = ARM_CP_STATE_AA64, .opc0 = 3, .opc1 = 0, .crn = 12, .crm = 11, .opc2 = 7, - .type = ARM_CP_IO | ARM_CP_NO_RAW, + .type = ARM_CP_IO | ARM_CP_NO_RAW | ARM_CP_NO_GDB, .access = PL1_W, .accessfn = gicv3_sgi_access, .writefn = icc_sgi0r_write, }, { .name = "ICC_SGI0R", .cp = 15, .opc1 = 2, .crm = 12, - .type = ARM_CP_64BIT | ARM_CP_IO | ARM_CP_NO_RAW, + .type = ARM_CP_64BIT | ARM_CP_IO | ARM_CP_NO_RAW | ARM_CP_NO_GDB, .access = PL1_W, .accessfn = gicv3_sgi_access, .writefn = icc_sgi0r_write, }, { .name = "ICC_IAR1_EL1", .state = ARM_CP_STATE_BOTH, .opc0 = 3, .opc1 = 0, .crn = 12, .crm = 12, .opc2 = 0, - .type = ARM_CP_IO | ARM_CP_NO_RAW, + .type = ARM_CP_IO | ARM_CP_NO_RAW | ARM_CP_NO_GDB, .access = PL1_R, .accessfn = gicv3_irq_access, .readfn = icc_iar1_read, }, { .name = "ICC_EOIR1_EL1", .state = ARM_CP_STATE_BOTH, .opc0 = 3, .opc1 = 0, .crn = 12, .crm = 12, .opc2 = 1, - .type = ARM_CP_IO | ARM_CP_NO_RAW, + .type = ARM_CP_IO | ARM_CP_NO_RAW | ARM_CP_NO_GDB, .access = PL1_W, .accessfn = gicv3_irq_access, .writefn = icc_eoir_write, }, { .name = "ICC_HPPIR1_EL1", .state = ARM_CP_STATE_BOTH, .opc0 = 3, .opc1 = 0, .crn = 12, .crm = 12, .opc2 = 2, - .type = ARM_CP_IO | ARM_CP_NO_RAW, + .type = ARM_CP_IO | ARM_CP_NO_RAW | ARM_CP_NO_GDB, .access = PL1_R, .accessfn = gicv3_irq_access, .readfn = icc_hppir1_read, }, /* This register is banked */ { .name = "ICC_BPR1_EL1", .state = ARM_CP_STATE_BOTH, .opc0 = 3, .opc1 = 0, .crn = 12, .crm = 12, .opc2 = 3, - .type = ARM_CP_IO | ARM_CP_NO_RAW, + .type = ARM_CP_IO | ARM_CP_NO_RAW | ARM_CP_NO_GDB, .access = PL1_RW, .accessfn = gicv3_irq_access, .readfn = icc_bpr_read, .writefn = icc_bpr_write, @@ -2559,14 +2559,14 @@ static const ARMCPRegInfo gicv3_cpuif_reginfo[] = { /* This register is banked */ { .name = "ICC_CTLR_EL1", .state = ARM_CP_STATE_BOTH, .opc0 = 3, .opc1 = 0, .crn = 12, .crm = 12, .opc2 = 4, - .type = ARM_CP_IO | ARM_CP_NO_RAW, + .type = ARM_CP_IO | ARM_CP_NO_RAW | ARM_CP_NO_GDB, .access = PL1_RW, .accessfn = gicv3_irqfiq_access, .readfn = icc_ctlr_el1_read, .writefn = icc_ctlr_el1_write, }, { .name = "ICC_SRE_EL1", .state = ARM_CP_STATE_BOTH, .opc0 = 3, .opc1 = 0, .crn = 12, .crm = 12, .opc2 = 5, - .type = ARM_CP_NO_RAW | ARM_CP_CONST, + .type = ARM_CP_NO_RAW | ARM_CP_NO_GDB | ARM_CP_CONST, .access = PL1_RW, /* We don't support IRQ/FIQ bypass and system registers are * always enabled, so all our bits are RAZ/WI or RAO/WI. @@ -2577,7 +2577,7 @@ static const ARMCPRegInfo gicv3_cpuif_reginfo[] = { }, { .name = "ICC_IGRPEN0_EL1", .state = ARM_CP_STATE_BOTH, .opc0 = 3, .opc1 = 0, .crn = 12, .crm = 12, .opc2 = 6, - .type = ARM_CP_IO | ARM_CP_NO_RAW, + .type = ARM_CP_IO | ARM_CP_NO_RAW | ARM_CP_NO_GDB, .access = PL1_RW, .accessfn = gicv3_fiq_access, .fgt = FGT_ICC_IGRPENN_EL1, .readfn = icc_igrpen_read, @@ -2586,7 +2586,7 @@ static const ARMCPRegInfo gicv3_cpuif_reginfo[] = { /* This register is banked */ { .name = "ICC_IGRPEN1_EL1", .state = ARM_CP_STATE_BOTH, .opc0 = 3, .opc1 = 0, .crn = 12, .crm = 12, .opc2 = 7, - .type = ARM_CP_IO | ARM_CP_NO_RAW, + .type = ARM_CP_IO | ARM_CP_NO_RAW | ARM_CP_NO_GDB, .access = PL1_RW, .accessfn = gicv3_irq_access, .fgt = FGT_ICC_IGRPENN_EL1, .readfn = icc_igrpen_read, @@ -2594,7 +2594,7 @@ static const ARMCPRegInfo gicv3_cpuif_reginfo[] = { }, { .name = "ICC_SRE_EL2", .state = ARM_CP_STATE_BOTH, .opc0 = 3, .opc1 = 4, .crn = 12, .crm = 9, .opc2 = 5, - .type = ARM_CP_NO_RAW | ARM_CP_CONST, + .type = ARM_CP_NO_RAW | ARM_CP_NO_GDB | ARM_CP_CONST, .access = PL2_RW, /* We don't support IRQ/FIQ bypass and system registers are * always enabled, so all our bits are RAZ/WI or RAO/WI. @@ -2603,14 +2603,14 @@ static const ARMCPRegInfo gicv3_cpuif_reginfo[] = { }, { .name = "ICC_CTLR_EL3", .state = ARM_CP_STATE_BOTH, .opc0 = 3, .opc1 = 6, .crn = 12, .crm = 12, .opc2 = 4, - .type = ARM_CP_IO | ARM_CP_NO_RAW, + .type = ARM_CP_IO | ARM_CP_NO_RAW | ARM_CP_NO_GDB, .access = PL3_RW, .readfn = icc_ctlr_el3_read, .writefn = icc_ctlr_el3_write, }, { .name = "ICC_SRE_EL3", .state = ARM_CP_STATE_BOTH, .opc0 = 3, .opc1 = 6, .crn = 12, .crm = 12, .opc2 = 5, - .type = ARM_CP_NO_RAW | ARM_CP_CONST, + .type = ARM_CP_NO_RAW | ARM_CP_NO_GDB | ARM_CP_CONST, .access = PL3_RW, /* We don't support IRQ/FIQ bypass and system registers are * always enabled, so all our bits are RAZ/WI or RAO/WI. @@ -2619,7 +2619,7 @@ static const ARMCPRegInfo gicv3_cpuif_reginfo[] = { }, { .name = "ICC_IGRPEN1_EL3", .state = ARM_CP_STATE_BOTH, .opc0 = 3, .opc1 = 6, .crn = 12, .crm = 12, .opc2 = 7, - .type = ARM_CP_IO | ARM_CP_NO_RAW, + .type = ARM_CP_IO | ARM_CP_NO_RAW | ARM_CP_NO_GDB, .access = PL3_RW, .readfn = icc_igrpen1_el3_read, .writefn = icc_igrpen1_el3_write, @@ -2629,14 +2629,14 @@ static const ARMCPRegInfo gicv3_cpuif_reginfo[] = { static const ARMCPRegInfo gicv3_cpuif_icc_apxr1_reginfo[] = { { .name = "ICC_AP0R1_EL1", .state = ARM_CP_STATE_BOTH, .opc0 = 3, .opc1 = 0, .crn = 12, .crm = 8, .opc2 = 5, - .type = ARM_CP_IO | ARM_CP_NO_RAW, + .type = ARM_CP_IO | ARM_CP_NO_RAW | ARM_CP_NO_GDB, .access = PL1_RW, .accessfn = gicv3_fiq_access, .readfn = icc_ap_read, .writefn = icc_ap_write, }, { .name = "ICC_AP1R1_EL1", .state = ARM_CP_STATE_BOTH, .opc0 = 3, .opc1 = 0, .crn = 12, .crm = 9, .opc2 = 1, - .type = ARM_CP_IO | ARM_CP_NO_RAW, + .type = ARM_CP_IO | ARM_CP_NO_RAW | ARM_CP_NO_GDB, .access = PL1_RW, .accessfn = gicv3_irq_access, .readfn = icc_ap_read, .writefn = icc_ap_write, @@ -2646,28 +2646,28 @@ static const ARMCPRegInfo gicv3_cpuif_icc_apxr1_reginfo[] = { static const ARMCPRegInfo gicv3_cpuif_icc_apxr23_reginfo[] = { { .name = "ICC_AP0R2_EL1", .state = ARM_CP_STATE_BOTH, .opc0 = 3, .opc1 = 0, .crn = 12, .crm = 8, .opc2 = 6, - .type = ARM_CP_IO | ARM_CP_NO_RAW, + .type = ARM_CP_IO | ARM_CP_NO_RAW | ARM_CP_NO_GDB, .access = PL1_RW, .accessfn = gicv3_fiq_access, .readfn = icc_ap_read, .writefn = icc_ap_write, }, { .name = "ICC_AP0R3_EL1", .state = ARM_CP_STATE_BOTH, .opc0 = 3, .opc1 = 0, .crn = 12, .crm = 8, .opc2 = 7, - .type = ARM_CP_IO | ARM_CP_NO_RAW, + .type = ARM_CP_IO | ARM_CP_NO_RAW | ARM_CP_NO_GDB, .access = PL1_RW, .accessfn = gicv3_fiq_access, .readfn = icc_ap_read, .writefn = icc_ap_write, }, { .name = "ICC_AP1R2_EL1", .state = ARM_CP_STATE_BOTH, .opc0 = 3, .opc1 = 0, .crn = 12, .crm = 9, .opc2 = 2, - .type = ARM_CP_IO | ARM_CP_NO_RAW, + .type = ARM_CP_IO | ARM_CP_NO_RAW | ARM_CP_NO_GDB, .access = PL1_RW, .accessfn = gicv3_irq_access, .readfn = icc_ap_read, .writefn = icc_ap_write, }, { .name = "ICC_AP1R3_EL1", .state = ARM_CP_STATE_BOTH, .opc0 = 3, .opc1 = 0, .crn = 12, .crm = 9, .opc2 = 3, - .type = ARM_CP_IO | ARM_CP_NO_RAW, + .type = ARM_CP_IO | ARM_CP_NO_RAW | ARM_CP_NO_GDB, .access = PL1_RW, .accessfn = gicv3_irq_access, .readfn = icc_ap_read, .writefn = icc_ap_write, @@ -2677,7 +2677,7 @@ static const ARMCPRegInfo gicv3_cpuif_icc_apxr23_reginfo[] = { static const ARMCPRegInfo gicv3_cpuif_gicv3_nmi_reginfo[] = { { .name = "ICC_NMIAR1_EL1", .state = ARM_CP_STATE_BOTH, .opc0 = 3, .opc1 = 0, .crn = 12, .crm = 9, .opc2 = 5, - .type = ARM_CP_IO | ARM_CP_NO_RAW, + .type = ARM_CP_IO | ARM_CP_NO_RAW | ARM_CP_NO_GDB, .access = PL1_R, .accessfn = gicv3_irq_access, .readfn = icc_nmiar1_read, }, @@ -2893,7 +2893,7 @@ static uint64_t ich_elrsr_read(CPUARMState *env, const ARMCPRegInfo *ri) static const ARMCPRegInfo gicv3_cpuif_hcr_reginfo[] = { { .name = "ICH_AP0R0_EL2", .state = ARM_CP_STATE_BOTH, .opc0 = 3, .opc1 = 4, .crn = 12, .crm = 8, .opc2 = 0, - .type = ARM_CP_IO | ARM_CP_NO_RAW, + .type = ARM_CP_IO | ARM_CP_NO_RAW | ARM_CP_NO_GDB, .nv2_redirect_offset = 0x480, .access = PL2_RW, .readfn = ich_ap_read, @@ -2901,7 +2901,7 @@ static const ARMCPRegInfo gicv3_cpuif_hcr_reginfo[] = { }, { .name = "ICH_AP1R0_EL2", .state = ARM_CP_STATE_BOTH, .opc0 = 3, .opc1 = 4, .crn = 12, .crm = 9, .opc2 = 0, - .type = ARM_CP_IO | ARM_CP_NO_RAW, + .type = ARM_CP_IO | ARM_CP_NO_RAW | ARM_CP_NO_GDB, .nv2_redirect_offset = 0x4a0, .access = PL2_RW, .readfn = ich_ap_read, @@ -2909,7 +2909,7 @@ static const ARMCPRegInfo gicv3_cpuif_hcr_reginfo[] = { }, { .name = "ICH_HCR_EL2", .state = ARM_CP_STATE_BOTH, .opc0 = 3, .opc1 = 4, .crn = 12, .crm = 11, .opc2 = 0, - .type = ARM_CP_IO | ARM_CP_NO_RAW, + .type = ARM_CP_IO | ARM_CP_NO_RAW | ARM_CP_NO_GDB, .nv2_redirect_offset = 0x4c0, .access = PL2_RW, .readfn = ich_hcr_read, @@ -2917,31 +2917,31 @@ static const ARMCPRegInfo gicv3_cpuif_hcr_reginfo[] = { }, { .name = "ICH_VTR_EL2", .state = ARM_CP_STATE_BOTH, .opc0 = 3, .opc1 = 4, .crn = 12, .crm = 11, .opc2 = 1, - .type = ARM_CP_IO | ARM_CP_NO_RAW, + .type = ARM_CP_IO | ARM_CP_NO_RAW | ARM_CP_NO_GDB, .access = PL2_R, .readfn = ich_vtr_read, }, { .name = "ICH_MISR_EL2", .state = ARM_CP_STATE_BOTH, .opc0 = 3, .opc1 = 4, .crn = 12, .crm = 11, .opc2 = 2, - .type = ARM_CP_IO | ARM_CP_NO_RAW, + .type = ARM_CP_IO | ARM_CP_NO_RAW | ARM_CP_NO_GDB, .access = PL2_R, .readfn = ich_misr_read, }, { .name = "ICH_EISR_EL2", .state = ARM_CP_STATE_BOTH, .opc0 = 3, .opc1 = 4, .crn = 12, .crm = 11, .opc2 = 3, - .type = ARM_CP_IO | ARM_CP_NO_RAW, + .type = ARM_CP_IO | ARM_CP_NO_RAW | ARM_CP_NO_GDB, .access = PL2_R, .readfn = ich_eisr_read, }, { .name = "ICH_ELRSR_EL2", .state = ARM_CP_STATE_BOTH, .opc0 = 3, .opc1 = 4, .crn = 12, .crm = 11, .opc2 = 5, - .type = ARM_CP_IO | ARM_CP_NO_RAW, + .type = ARM_CP_IO | ARM_CP_NO_RAW | ARM_CP_NO_GDB, .access = PL2_R, .readfn = ich_elrsr_read, }, { .name = "ICH_VMCR_EL2", .state = ARM_CP_STATE_BOTH, .opc0 = 3, .opc1 = 4, .crn = 12, .crm = 11, .opc2 = 7, - .type = ARM_CP_IO | ARM_CP_NO_RAW, + .type = ARM_CP_IO | ARM_CP_NO_RAW | ARM_CP_NO_GDB, .nv2_redirect_offset = 0x4c8, .access = PL2_RW, .readfn = ich_vmcr_read, @@ -2952,7 +2952,7 @@ static const ARMCPRegInfo gicv3_cpuif_hcr_reginfo[] = { static const ARMCPRegInfo gicv3_cpuif_ich_apxr1_reginfo[] = { { .name = "ICH_AP0R1_EL2", .state = ARM_CP_STATE_BOTH, .opc0 = 3, .opc1 = 4, .crn = 12, .crm = 8, .opc2 = 1, - .type = ARM_CP_IO | ARM_CP_NO_RAW, + .type = ARM_CP_IO | ARM_CP_NO_RAW | ARM_CP_NO_GDB, .nv2_redirect_offset = 0x488, .access = PL2_RW, .readfn = ich_ap_read, @@ -2960,7 +2960,7 @@ static const ARMCPRegInfo gicv3_cpuif_ich_apxr1_reginfo[] = { }, { .name = "ICH_AP1R1_EL2", .state = ARM_CP_STATE_BOTH, .opc0 = 3, .opc1 = 4, .crn = 12, .crm = 9, .opc2 = 1, - .type = ARM_CP_IO | ARM_CP_NO_RAW, + .type = ARM_CP_IO | ARM_CP_NO_RAW | ARM_CP_NO_GDB, .nv2_redirect_offset = 0x4a8, .access = PL2_RW, .readfn = ich_ap_read, @@ -2971,7 +2971,7 @@ static const ARMCPRegInfo gicv3_cpuif_ich_apxr1_reginfo[] = { static const ARMCPRegInfo gicv3_cpuif_ich_apxr23_reginfo[] = { { .name = "ICH_AP0R2_EL2", .state = ARM_CP_STATE_BOTH, .opc0 = 3, .opc1 = 4, .crn = 12, .crm = 8, .opc2 = 2, - .type = ARM_CP_IO | ARM_CP_NO_RAW, + .type = ARM_CP_IO | ARM_CP_NO_RAW | ARM_CP_NO_GDB, .nv2_redirect_offset = 0x490, .access = PL2_RW, .readfn = ich_ap_read, @@ -2979,7 +2979,7 @@ static const ARMCPRegInfo gicv3_cpuif_ich_apxr23_reginfo[] = { }, { .name = "ICH_AP0R3_EL2", .state = ARM_CP_STATE_BOTH, .opc0 = 3, .opc1 = 4, .crn = 12, .crm = 8, .opc2 = 3, - .type = ARM_CP_IO | ARM_CP_NO_RAW, + .type = ARM_CP_IO | ARM_CP_NO_RAW | ARM_CP_NO_GDB, .nv2_redirect_offset = 0x498, .access = PL2_RW, .readfn = ich_ap_read, @@ -2987,7 +2987,7 @@ static const ARMCPRegInfo gicv3_cpuif_ich_apxr23_reginfo[] = { }, { .name = "ICH_AP1R2_EL2", .state = ARM_CP_STATE_BOTH, .opc0 = 3, .opc1 = 4, .crn = 12, .crm = 9, .opc2 = 2, - .type = ARM_CP_IO | ARM_CP_NO_RAW, + .type = ARM_CP_IO | ARM_CP_NO_RAW | ARM_CP_NO_GDB, .nv2_redirect_offset = 0x4b0, .access = PL2_RW, .readfn = ich_ap_read, @@ -2995,7 +2995,7 @@ static const ARMCPRegInfo gicv3_cpuif_ich_apxr23_reginfo[] = { }, { .name = "ICH_AP1R3_EL2", .state = ARM_CP_STATE_BOTH, .opc0 = 3, .opc1 = 4, .crn = 12, .crm = 9, .opc2 = 3, - .type = ARM_CP_IO | ARM_CP_NO_RAW, + .type = ARM_CP_IO | ARM_CP_NO_RAW | ARM_CP_NO_GDB, .nv2_redirect_offset = 0x4b8, .access = PL2_RW, .readfn = ich_ap_read, @@ -3130,7 +3130,7 @@ void gicv3_init_cpuif(GICv3State *s) { .name = "ICH_LRn_EL2", .state = ARM_CP_STATE_BOTH, .opc0 = 3, .opc1 = 4, .crn = 12, .crm = 12 + (j >> 3), .opc2 = j & 7, - .type = ARM_CP_IO | ARM_CP_NO_RAW, + .type = ARM_CP_IO | ARM_CP_NO_RAW | ARM_CP_NO_GDB, .nv2_redirect_offset = 0x400 + 8 * j, .access = PL2_RW, .readfn = ich_lr_read, @@ -3139,7 +3139,7 @@ void gicv3_init_cpuif(GICv3State *s) { .name = "ICH_LRCn_EL2", .state = ARM_CP_STATE_AA32, .cp = 15, .opc1 = 4, .crn = 12, .crm = 14 + (j >> 3), .opc2 = j & 7, - .type = ARM_CP_IO | ARM_CP_NO_RAW, + .type = ARM_CP_IO | ARM_CP_NO_RAW | ARM_CP_NO_GDB, .access = PL2_RW, .readfn = ich_lr_read, .writefn = ich_lr_write, diff --git a/hw/intc/arm_gicv3_kvm.c b/hw/intc/arm_gicv3_kvm.c index 8e17cab2a0fe..910ffe7c2baa 100644 --- a/hw/intc/arm_gicv3_kvm.c +++ b/hw/intc/arm_gicv3_kvm.c @@ -736,7 +736,7 @@ static const ARMCPRegInfo gicv3_cpuif_reginfo[] = { * If ARM_CP_NOP is used, resetfn is not called, * So ARM_CP_NO_RAW is appropriate type. */ - .type = ARM_CP_NO_RAW, + .type = ARM_CP_NO_RAW | ARM_CP_NO_GDB, .access = PL1_RW, .readfn = arm_cp_read_zero, .writefn = arm_cp_write_ignore, diff --git a/target/arm/debug_helper.c b/target/arm/debug_helper.c index a9a619ba6b1b..1c0a633e0f09 100644 --- a/target/arm/debug_helper.c +++ b/target/arm/debug_helper.c @@ -1013,7 +1013,7 @@ static const ARMCPRegInfo debug_cp_reginfo[] = { .fieldoffset = offsetof(CPUARMState, cp15.mdscr_el1), }, { .name = "OSLAR_EL1", .state = ARM_CP_STATE_BOTH, .cp = 14, .opc0 = 2, .opc1 = 0, .crn = 1, .crm = 0, .opc2 = 4, - .access = PL1_W, .type = ARM_CP_NO_RAW, + .access = PL1_W, .type = ARM_CP_NO_RAW | ARM_CP_NO_GDB, .accessfn = access_tdosa, .fgt = FGT_OSLAR_EL1, .writefn = oslar_write }, diff --git a/target/arm/helper.c b/target/arm/helper.c index f0ead22937bf..5ce468ac2693 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -521,7 +521,7 @@ static const ARMCPRegInfo not_v7_cp_reginfo[] = { .resetvalue = 0 }, /* v6 doesn't have the cache ID registers but Linux reads them anyway */ { .name = "DUMMY", .cp = 15, .crn = 0, .crm = 0, .opc1 = 1, .opc2 = CP_ANY, - .access = PL1_R, .type = ARM_CP_CONST | ARM_CP_NO_RAW, + .access = PL1_R, .type = ARM_CP_CONST | ARM_CP_NO_RAW | ARM_CP_NO_GDB, .resetvalue = 0 }, /* * We don't implement pre-v7 debug but most CPUs had at least a DBGDIDR; @@ -652,7 +652,8 @@ static const ARMCPRegInfo v6_cp_reginfo[] = { * So use arm_cp_write_ignore() function instead of ARM_CP_NOP flag. */ { .name = "ISB", .cp = 15, .crn = 7, .crm = 5, .opc1 = 0, .opc2 = 4, - .access = PL0_W, .type = ARM_CP_NO_RAW, .writefn = arm_cp_write_ignore }, + .access = PL0_W, .type = ARM_CP_NO_RAW | ARM_CP_NO_GDB, + .writefn = arm_cp_write_ignore }, { .name = "DSB", .cp = 15, .crn = 7, .crm = 10, .opc1 = 0, .opc2 = 4, .access = PL0_W, .type = ARM_CP_NOP }, { .name = "DMB", .cp = 15, .crn = 7, .crm = 10, .opc1 = 0, .opc2 = 5, @@ -1926,13 +1927,13 @@ static const ARMCPRegInfo v7_cp_reginfo[] = { { .name = "PMSWINC", .cp = 15, .crn = 9, .crm = 12, .opc1 = 0, .opc2 = 4, .access = PL0_W, .accessfn = pmreg_access_swinc, .fgt = FGT_PMSWINC_EL0, - .type = ARM_CP_NO_RAW | ARM_CP_IO, + .type = ARM_CP_NO_RAW | ARM_CP_NO_GDB | ARM_CP_IO, .writefn = pmswinc_write }, { .name = "PMSWINC_EL0", .state = ARM_CP_STATE_AA64, .opc0 = 3, .opc1 = 3, .crn = 9, .crm = 12, .opc2 = 4, .access = PL0_W, .accessfn = pmreg_access_swinc, .fgt = FGT_PMSWINC_EL0, - .type = ARM_CP_NO_RAW | ARM_CP_IO, + .type = ARM_CP_NO_RAW | ARM_CP_NO_GDB | ARM_CP_IO, .writefn = pmswinc_write }, { .name = "PMSELR", .cp = 15, .crn = 9, .crm = 12, .opc1 = 0, .opc2 = 5, .access = PL0_RW, .type = ARM_CP_ALIAS, @@ -1974,24 +1975,24 @@ static const ARMCPRegInfo v7_cp_reginfo[] = { .fieldoffset = offsetof(CPUARMState, cp15.pmccfiltr_el0), .resetvalue = 0, }, { .name = "PMXEVTYPER", .cp = 15, .crn = 9, .crm = 13, .opc1 = 0, .opc2 = 1, - .access = PL0_RW, .type = ARM_CP_NO_RAW | ARM_CP_IO, + .access = PL0_RW, .type = ARM_CP_NO_RAW | ARM_CP_NO_GDB | ARM_CP_IO, .accessfn = pmreg_access, .fgt = FGT_PMEVTYPERN_EL0, .writefn = pmxevtyper_write, .readfn = pmxevtyper_read }, { .name = "PMXEVTYPER_EL0", .state = ARM_CP_STATE_AA64, .opc0 = 3, .opc1 = 3, .crn = 9, .crm = 13, .opc2 = 1, - .access = PL0_RW, .type = ARM_CP_NO_RAW | ARM_CP_IO, + .access = PL0_RW, .type = ARM_CP_NO_RAW | ARM_CP_NO_GDB | ARM_CP_IO, .accessfn = pmreg_access, .fgt = FGT_PMEVTYPERN_EL0, .writefn = pmxevtyper_write, .readfn = pmxevtyper_read }, { .name = "PMXEVCNTR", .cp = 15, .crn = 9, .crm = 13, .opc1 = 0, .opc2 = 2, - .access = PL0_RW, .type = ARM_CP_NO_RAW | ARM_CP_IO, + .access = PL0_RW, .type = ARM_CP_NO_RAW | ARM_CP_NO_GDB | ARM_CP_IO, .accessfn = pmreg_access_xevcntr, .fgt = FGT_PMEVCNTRN_EL0, .writefn = pmxevcntr_write, .readfn = pmxevcntr_read }, { .name = "PMXEVCNTR_EL0", .state = ARM_CP_STATE_AA64, .opc0 = 3, .opc1 = 3, .crn = 9, .crm = 13, .opc2 = 2, - .access = PL0_RW, .type = ARM_CP_NO_RAW | ARM_CP_IO, + .access = PL0_RW, .type = ARM_CP_NO_RAW | ARM_CP_NO_GDB | ARM_CP_IO, .accessfn = pmreg_access_xevcntr, .fgt = FGT_PMEVCNTRN_EL0, .writefn = pmxevcntr_write, .readfn = pmxevcntr_read }, @@ -2024,14 +2025,14 @@ static const ARMCPRegInfo v7_cp_reginfo[] = { { .name = "PMINTENCLR", .cp = 15, .crn = 9, .crm = 14, .opc1 = 0, .opc2 = 2, .access = PL1_RW, .accessfn = access_tpm, .fgt = FGT_PMINTEN, - .type = ARM_CP_ALIAS | ARM_CP_IO | ARM_CP_NO_RAW, + .type = ARM_CP_ALIAS | ARM_CP_IO | ARM_CP_NO_RAW | ARM_CP_NO_GDB, .fieldoffset = offsetof(CPUARMState, cp15.c9_pminten), .writefn = pmintenclr_write, }, { .name = "PMINTENCLR_EL1", .state = ARM_CP_STATE_AA64, .opc0 = 3, .opc1 = 0, .crn = 9, .crm = 14, .opc2 = 2, .access = PL1_RW, .accessfn = access_tpm, .fgt = FGT_PMINTEN, - .type = ARM_CP_ALIAS | ARM_CP_IO | ARM_CP_NO_RAW, + .type = ARM_CP_ALIAS | ARM_CP_IO | ARM_CP_NO_RAW | ARM_CP_NO_GDB, .fieldoffset = offsetof(CPUARMState, cp15.c9_pminten), .writefn = pmintenclr_write }, { .name = "CCSIDR", .state = ARM_CP_STATE_BOTH, @@ -2039,7 +2040,7 @@ static const ARMCPRegInfo v7_cp_reginfo[] = { .access = PL1_R, .accessfn = access_tid4, .fgt = FGT_CCSIDR_EL1, - .readfn = ccsidr_read, .type = ARM_CP_NO_RAW }, + .readfn = ccsidr_read, .type = ARM_CP_NO_RAW | ARM_CP_NO_GDB }, { .name = "CSSELR", .state = ARM_CP_STATE_BOTH, .opc0 = 3, .crn = 0, .crm = 0, .opc1 = 2, .opc2 = 0, .access = PL1_RW, @@ -2113,7 +2114,8 @@ static const ARMCPRegInfo v7_cp_reginfo[] = { { .name = "ISR_EL1", .state = ARM_CP_STATE_BOTH, .opc0 = 3, .opc1 = 0, .crn = 12, .crm = 1, .opc2 = 0, .fgt = FGT_ISR_EL1, - .type = ARM_CP_NO_RAW, .access = PL1_R, .readfn = isr_read }, + .type = ARM_CP_NO_RAW | ARM_CP_NO_GDB, + .access = PL1_R, .readfn = isr_read }, }; static const ARMCPRegInfo pmovsset_cp_reginfo[] = { @@ -3204,53 +3206,55 @@ static const ARMCPRegInfo generic_timer_cp_reginfo[] = { /* TimerValue views: a 32 bit downcounting view of the underlying state */ { .name = "CNTP_TVAL", .cp = 15, .crn = 14, .crm = 2, .opc1 = 0, .opc2 = 0, .secure = ARM_CP_SECSTATE_NS, - .type = ARM_CP_NO_RAW | ARM_CP_IO, .access = PL0_RW, + .type = ARM_CP_NO_RAW | ARM_CP_NO_GDB | ARM_CP_IO, .access = PL0_RW, .accessfn = gt_ptimer_access, .readfn = gt_phys_redir_tval_read, .writefn = gt_phys_redir_tval_write, }, { .name = "CNTP_TVAL_S", .cp = 15, .crn = 14, .crm = 2, .opc1 = 0, .opc2 = 0, .secure = ARM_CP_SECSTATE_S, - .type = ARM_CP_NO_RAW | ARM_CP_IO, .access = PL0_RW, + .type = ARM_CP_NO_RAW | ARM_CP_NO_GDB | ARM_CP_IO, .access = PL0_RW, .accessfn = gt_ptimer_access, .readfn = gt_sec_tval_read, .writefn = gt_sec_tval_write, }, { .name = "CNTP_TVAL_EL0", .state = ARM_CP_STATE_AA64, .opc0 = 3, .opc1 = 3, .crn = 14, .crm = 2, .opc2 = 0, - .type = ARM_CP_NO_RAW | ARM_CP_IO, .access = PL0_RW, + .type = ARM_CP_NO_RAW | ARM_CP_NO_GDB | ARM_CP_IO, .access = PL0_RW, .accessfn = gt_ptimer_access, .resetfn = gt_phys_timer_reset, .readfn = gt_phys_redir_tval_read, .writefn = gt_phys_redir_tval_write, }, { .name = "CNTV_TVAL", .cp = 15, .crn = 14, .crm = 3, .opc1 = 0, .opc2 = 0, - .type = ARM_CP_NO_RAW | ARM_CP_IO, .access = PL0_RW, + .type = ARM_CP_NO_RAW | ARM_CP_NO_GDB | ARM_CP_IO, .access = PL0_RW, .accessfn = gt_vtimer_access, .readfn = gt_virt_redir_tval_read, .writefn = gt_virt_redir_tval_write, }, { .name = "CNTV_TVAL_EL0", .state = ARM_CP_STATE_AA64, .opc0 = 3, .opc1 = 3, .crn = 14, .crm = 3, .opc2 = 0, - .type = ARM_CP_NO_RAW | ARM_CP_IO, .access = PL0_RW, + .type = ARM_CP_NO_RAW | ARM_CP_NO_GDB | ARM_CP_IO, .access = PL0_RW, .accessfn = gt_vtimer_access, .resetfn = gt_virt_timer_reset, .readfn = gt_virt_redir_tval_read, .writefn = gt_virt_redir_tval_write, }, /* The counter itself */ { .name = "CNTPCT", .cp = 15, .crm = 14, .opc1 = 0, - .access = PL0_R, .type = ARM_CP_64BIT | ARM_CP_NO_RAW | ARM_CP_IO, + .access = PL0_R, + .type = ARM_CP_64BIT | ARM_CP_NO_RAW | ARM_CP_NO_GDB | ARM_CP_IO, .accessfn = gt_pct_access, .readfn = gt_cnt_read, .resetfn = arm_cp_reset_ignore, }, { .name = "CNTPCT_EL0", .state = ARM_CP_STATE_AA64, .opc0 = 3, .opc1 = 3, .crn = 14, .crm = 0, .opc2 = 1, - .access = PL0_R, .type = ARM_CP_NO_RAW | ARM_CP_IO, + .access = PL0_R, .type = ARM_CP_NO_RAW | ARM_CP_NO_GDB | ARM_CP_IO, .accessfn = gt_pct_access, .readfn = gt_cnt_read, }, { .name = "CNTVCT", .cp = 15, .crm = 14, .opc1 = 1, - .access = PL0_R, .type = ARM_CP_64BIT | ARM_CP_NO_RAW | ARM_CP_IO, + .access = PL0_R, + .type = ARM_CP_64BIT | ARM_CP_NO_RAW | ARM_CP_NO_GDB | ARM_CP_IO, .accessfn = gt_vct_access, .readfn = gt_virt_cnt_read, .resetfn = arm_cp_reset_ignore, }, { .name = "CNTVCT_EL0", .state = ARM_CP_STATE_AA64, .opc0 = 3, .opc1 = 3, .crn = 14, .crm = 0, .opc2 = 2, - .access = PL0_R, .type = ARM_CP_NO_RAW | ARM_CP_IO, + .access = PL0_R, .type = ARM_CP_NO_RAW | ARM_CP_NO_GDB | ARM_CP_IO, .accessfn = gt_vct_access, .readfn = gt_virt_cnt_read, }, /* Comparison value, indicating when the timer goes off */ @@ -3305,7 +3309,7 @@ static const ARMCPRegInfo generic_timer_cp_reginfo[] = { */ { .name = "CNTPS_TVAL_EL1", .state = ARM_CP_STATE_AA64, .opc0 = 3, .opc1 = 7, .crn = 14, .crm = 2, .opc2 = 0, - .type = ARM_CP_NO_RAW | ARM_CP_IO, .access = PL1_RW, + .type = ARM_CP_NO_RAW | ARM_CP_NO_GDB | ARM_CP_IO, .access = PL1_RW, .accessfn = gt_stimer_access, .readfn = gt_sec_tval_read, .writefn = gt_sec_tval_write, @@ -3335,23 +3339,27 @@ static const ARMCPRegInfo generic_timer_cp_reginfo[] = { */ static const ARMCPRegInfo gen_timer_ecv_cp_reginfo[] = { { .name = "CNTVCTSS", .cp = 15, .crm = 14, .opc1 = 9, - .access = PL0_R, .type = ARM_CP_64BIT | ARM_CP_NO_RAW | ARM_CP_IO, + .access = PL0_R, + .type = ARM_CP_64BIT | ARM_CP_NO_RAW | ARM_CP_NO_GDB | ARM_CP_IO, .accessfn = gt_vct_access, .readfn = gt_virt_cnt_read, .resetfn = arm_cp_reset_ignore, }, { .name = "CNTVCTSS_EL0", .state = ARM_CP_STATE_AA64, .opc0 = 3, .opc1 = 3, .crn = 14, .crm = 0, .opc2 = 6, - .access = PL0_R, .type = ARM_CP_NO_RAW | ARM_CP_IO, + .access = PL0_R, + .type = ARM_CP_NO_RAW | ARM_CP_NO_GDB | ARM_CP_IO, .accessfn = gt_vct_access, .readfn = gt_virt_cnt_read, }, { .name = "CNTPCTSS", .cp = 15, .crm = 14, .opc1 = 8, - .access = PL0_R, .type = ARM_CP_64BIT | ARM_CP_NO_RAW | ARM_CP_IO, + .access = PL0_R, + .type = ARM_CP_64BIT | ARM_CP_NO_RAW | ARM_CP_NO_GDB | ARM_CP_IO, .accessfn = gt_pct_access, .readfn = gt_cnt_read, .resetfn = arm_cp_reset_ignore, }, { .name = "CNTPCTSS_EL0", .state = ARM_CP_STATE_AA64, .opc0 = 3, .opc1 = 3, .crn = 14, .crm = 0, .opc2 = 5, - .access = PL0_R, .type = ARM_CP_NO_RAW | ARM_CP_IO, + .access = PL0_R, + .type = ARM_CP_NO_RAW | ARM_CP_NO_GDB | ARM_CP_IO, .accessfn = gt_pct_access, .readfn = gt_cnt_read, }, }; @@ -3413,7 +3421,7 @@ static const ARMCPRegInfo generic_timer_cp_reginfo[] = { }, { .name = "CNTVCT_EL0", .state = ARM_CP_STATE_AA64, .opc0 = 3, .opc1 = 3, .crn = 14, .crm = 0, .opc2 = 2, - .access = PL0_R, .type = ARM_CP_NO_RAW | ARM_CP_IO, + .access = PL0_R, .type = ARM_CP_NO_RAW | ARM_CP_NO_GDB | ARM_CP_IO, .readfn = gt_virt_cnt_read, }, }; @@ -3425,7 +3433,7 @@ static const ARMCPRegInfo generic_timer_cp_reginfo[] = { static const ARMCPRegInfo gen_timer_ecv_cp_reginfo[] = { { .name = "CNTVCTSS_EL0", .state = ARM_CP_STATE_AA64, .opc0 = 3, .opc1 = 3, .crn = 14, .crm = 0, .opc2 = 6, - .access = PL0_R, .type = ARM_CP_NO_RAW | ARM_CP_IO, + .access = PL0_R, .type = ARM_CP_NO_RAW | ARM_CP_NO_GDB | ARM_CP_IO, .readfn = gt_virt_cnt_read, }, }; @@ -4118,12 +4126,12 @@ static uint64_t pmsav8r_regn_read(CPUARMState *env, const ARMCPRegInfo *ri) static const ARMCPRegInfo pmsav8r_cp_reginfo[] = { { .name = "PRBAR", .cp = 15, .opc1 = 0, .crn = 6, .crm = 3, .opc2 = 0, - .access = PL1_RW, .type = ARM_CP_NO_RAW, + .access = PL1_RW, .type = ARM_CP_NO_RAW | ARM_CP_NO_GDB, .accessfn = access_tvm_trvm, .readfn = prbar_read, .writefn = prbar_write }, { .name = "PRLAR", .cp = 15, .opc1 = 0, .crn = 6, .crm = 3, .opc2 = 1, - .access = PL1_RW, .type = ARM_CP_NO_RAW, + .access = PL1_RW, .type = ARM_CP_NO_RAW | ARM_CP_NO_GDB, .accessfn = access_tvm_trvm, .readfn = prlar_read, .writefn = prlar_write }, { .name = "PRSELR", .resetvalue = 0, @@ -4133,11 +4141,11 @@ static const ARMCPRegInfo pmsav8r_cp_reginfo[] = { .fieldoffset = offsetof(CPUARMState, pmsav7.rnr[M_REG_NS]) }, { .name = "HPRBAR", .resetvalue = 0, .cp = 15, .opc1 = 4, .crn = 6, .crm = 3, .opc2 = 0, - .access = PL2_RW, .type = ARM_CP_NO_RAW, + .access = PL2_RW, .type = ARM_CP_NO_RAW | ARM_CP_NO_GDB, .readfn = hprbar_read, .writefn = hprbar_write }, { .name = "HPRLAR", .cp = 15, .opc1 = 4, .crn = 6, .crm = 3, .opc2 = 1, - .access = PL2_RW, .type = ARM_CP_NO_RAW, + .access = PL2_RW, .type = ARM_CP_NO_RAW | ARM_CP_NO_GDB, .readfn = hprlar_read, .writefn = hprlar_write }, { .name = "HPRSELR", .resetvalue = 0, .cp = 15, .opc1 = 4, .crn = 6, .crm = 2, .opc2 = 1, @@ -4146,7 +4154,7 @@ static const ARMCPRegInfo pmsav8r_cp_reginfo[] = { .fieldoffset = offsetof(CPUARMState, pmsav8.hprselr) }, { .name = "HPRENR", .cp = 15, .opc1 = 4, .crn = 6, .crm = 1, .opc2 = 1, - .access = PL2_RW, .type = ARM_CP_NO_RAW, + .access = PL2_RW, .type = ARM_CP_NO_RAW | ARM_CP_NO_GDB, .readfn = hprenr_read, .writefn = hprenr_write }, }; @@ -4157,17 +4165,17 @@ static const ARMCPRegInfo pmsav7_cp_reginfo[] = { * not register cpregs but still need the state to be reset. */ { .name = "DRBAR", .cp = 15, .crn = 6, .opc1 = 0, .crm = 1, .opc2 = 0, - .access = PL1_RW, .type = ARM_CP_NO_RAW, + .access = PL1_RW, .type = ARM_CP_NO_RAW | ARM_CP_NO_GDB, .fieldoffset = offsetof(CPUARMState, pmsav7.drbar), .readfn = pmsav7_read, .writefn = pmsav7_write, .resetfn = arm_cp_reset_ignore }, { .name = "DRSR", .cp = 15, .crn = 6, .opc1 = 0, .crm = 1, .opc2 = 2, - .access = PL1_RW, .type = ARM_CP_NO_RAW, + .access = PL1_RW, .type = ARM_CP_NO_RAW | ARM_CP_NO_GDB, .fieldoffset = offsetof(CPUARMState, pmsav7.drsr), .readfn = pmsav7_read, .writefn = pmsav7_write, .resetfn = arm_cp_reset_ignore }, { .name = "DRACR", .cp = 15, .crn = 6, .opc1 = 0, .crm = 1, .opc2 = 4, - .access = PL1_RW, .type = ARM_CP_NO_RAW, + .access = PL1_RW, .type = ARM_CP_NO_RAW | ARM_CP_NO_GDB, .fieldoffset = offsetof(CPUARMState, pmsav7.dracr), .readfn = pmsav7_read, .writefn = pmsav7_write, .resetfn = arm_cp_reset_ignore }, @@ -4451,7 +4459,7 @@ static const ARMCPRegInfo omap_cp_reginfo[] = { .writefn = omap_threadid_write }, { .name = "TI925T_STATUS", .cp = 15, .crn = 15, .crm = 8, .opc1 = 0, .opc2 = 0, .access = PL1_RW, - .type = ARM_CP_NO_RAW, + .type = ARM_CP_NO_RAW | ARM_CP_NO_GDB, .readfn = arm_cp_read_zero, .writefn = omap_wfi_write, }, /* * TODO: Peripheral port remap register: @@ -4461,7 +4469,7 @@ static const ARMCPRegInfo omap_cp_reginfo[] = { */ { .name = "OMAP_CACHEMAINT", .cp = 15, .crn = 7, .crm = CP_ANY, .opc1 = 0, .opc2 = CP_ANY, .access = PL1_W, - .type = ARM_CP_OVERRIDE | ARM_CP_NO_RAW, + .type = ARM_CP_OVERRIDE | ARM_CP_NO_RAW | ARM_CP_NO_GDB, .writefn = omap_cachemaint_write }, { .name = "C9", .cp = 15, .crn = 9, .crm = CP_ANY, .opc1 = CP_ANY, .opc2 = CP_ANY, .access = PL1_RW, @@ -4511,21 +4519,21 @@ static const ARMCPRegInfo dummy_c15_cp_reginfo[] = { { .name = "C15_IMPDEF", .cp = 15, .crn = 15, .crm = CP_ANY, .opc1 = CP_ANY, .opc2 = CP_ANY, .access = PL1_RW, - .type = ARM_CP_CONST | ARM_CP_NO_RAW | ARM_CP_OVERRIDE, + .type = ARM_CP_CONST | ARM_CP_NO_RAW | ARM_CP_NO_GDB | ARM_CP_OVERRIDE, .resetvalue = 0 }, }; static const ARMCPRegInfo cache_dirty_status_cp_reginfo[] = { /* Cache status: RAZ because we have no cache so it's always clean */ { .name = "CDSR", .cp = 15, .crn = 7, .crm = 10, .opc1 = 0, .opc2 = 6, - .access = PL1_R, .type = ARM_CP_CONST | ARM_CP_NO_RAW, + .access = PL1_R, .type = ARM_CP_CONST | ARM_CP_NO_RAW | ARM_CP_NO_GDB, .resetvalue = 0 }, }; static const ARMCPRegInfo cache_block_ops_cp_reginfo[] = { /* We never have a block transfer operation in progress */ { .name = "BXSR", .cp = 15, .crn = 7, .crm = 12, .opc1 = 0, .opc2 = 4, - .access = PL0_R, .type = ARM_CP_CONST | ARM_CP_NO_RAW, + .access = PL0_R, .type = ARM_CP_CONST | ARM_CP_NO_RAW | ARM_CP_NO_GDB, .resetvalue = 0 }, /* The cache ops themselves: these all NOP for QEMU */ { .name = "IICR", .cp = 15, .crm = 5, .opc1 = 0, @@ -4548,10 +4556,10 @@ static const ARMCPRegInfo cache_test_clean_cp_reginfo[] = { * to indicate that there are no dirty cache lines. */ { .name = "TC_DCACHE", .cp = 15, .crn = 7, .crm = 10, .opc1 = 0, .opc2 = 3, - .access = PL0_R, .type = ARM_CP_CONST | ARM_CP_NO_RAW, + .access = PL0_R, .type = ARM_CP_CONST | ARM_CP_NO_RAW | ARM_CP_NO_GDB, .resetvalue = (1 << 30) }, { .name = "TCI_DCACHE", .cp = 15, .crn = 7, .crm = 14, .opc1 = 0, .opc2 = 3, - .access = PL0_R, .type = ARM_CP_CONST | ARM_CP_NO_RAW, + .access = PL0_R, .type = ARM_CP_CONST | ARM_CP_NO_RAW | ARM_CP_NO_GDB, .resetvalue = (1 << 30) }, }; @@ -4560,7 +4568,7 @@ static const ARMCPRegInfo strongarm_cp_reginfo[] = { { .name = "C9_READBUFFER", .cp = 15, .crn = 9, .crm = CP_ANY, .opc1 = CP_ANY, .opc2 = CP_ANY, .access = PL1_RW, .resetvalue = 0, - .type = ARM_CP_CONST | ARM_CP_OVERRIDE | ARM_CP_NO_RAW }, + .type = ARM_CP_CONST | ARM_CP_OVERRIDE | ARM_CP_NO_RAW | ARM_CP_NO_GDB }, }; static uint64_t midr_read(CPUARMState *env, const ARMCPRegInfo *ri) @@ -4683,7 +4691,7 @@ static void aa64_pan_write(CPUARMState *env, const ARMCPRegInfo *ri, static const ARMCPRegInfo pan_reginfo = { .name = "PAN", .state = ARM_CP_STATE_AA64, .opc0 = 3, .opc1 = 0, .crn = 4, .crm = 2, .opc2 = 3, - .type = ARM_CP_NO_RAW, .access = PL1_RW, + .type = ARM_CP_NO_RAW | ARM_CP_NO_GDB, .access = PL1_RW, .readfn = aa64_pan_read, .writefn = aa64_pan_write }; @@ -4701,7 +4709,7 @@ static void aa64_uao_write(CPUARMState *env, const ARMCPRegInfo *ri, static const ARMCPRegInfo uao_reginfo = { .name = "UAO", .state = ARM_CP_STATE_AA64, .opc0 = 3, .opc1 = 0, .crn = 4, .crm = 2, .opc2 = 4, - .type = ARM_CP_NO_RAW, .access = PL1_RW, + .type = ARM_CP_NO_RAW | ARM_CP_NO_GDB, .access = PL1_RW, .readfn = aa64_uao_read, .writefn = aa64_uao_write }; @@ -4719,7 +4727,7 @@ static void aa64_dit_write(CPUARMState *env, const ARMCPRegInfo *ri, static const ARMCPRegInfo dit_reginfo = { .name = "DIT", .state = ARM_CP_STATE_AA64, .opc0 = 3, .opc1 = 3, .crn = 4, .crm = 2, .opc2 = 5, - .type = ARM_CP_NO_RAW, .access = PL0_RW, + .type = ARM_CP_NO_RAW | ARM_CP_NO_GDB, .access = PL0_RW, .readfn = aa64_dit_read, .writefn = aa64_dit_write }; @@ -4737,7 +4745,7 @@ static void aa64_ssbs_write(CPUARMState *env, const ARMCPRegInfo *ri, static const ARMCPRegInfo ssbs_reginfo = { .name = "SSBS", .state = ARM_CP_STATE_AA64, .opc0 = 3, .opc1 = 3, .crn = 4, .crm = 2, .opc2 = 6, - .type = ARM_CP_NO_RAW, .access = PL0_RW, + .type = ARM_CP_NO_RAW | ARM_CP_NO_GDB, .access = PL0_RW, .readfn = aa64_ssbs_read, .writefn = aa64_ssbs_write }; @@ -5001,7 +5009,7 @@ static const ARMCPRegInfo v8_cp_reginfo[] = { .access = PL0_RW, .type = ARM_CP_NZCV }, { .name = "DAIF", .state = ARM_CP_STATE_AA64, .opc0 = 3, .opc1 = 3, .opc2 = 1, .crn = 4, .crm = 2, - .type = ARM_CP_NO_RAW, + .type = ARM_CP_NO_RAW | ARM_CP_NO_GDB, .access = PL0_RW, .accessfn = aa64_daif_access, .fieldoffset = offsetof(CPUARMState, daif), .writefn = aa64_daif_write, .resetfn = arm_cp_reset_ignore }, @@ -5015,7 +5023,7 @@ static const ARMCPRegInfo v8_cp_reginfo[] = { .readfn = aa64_fpsr_read, .writefn = aa64_fpsr_write }, { .name = "DCZID_EL0", .state = ARM_CP_STATE_AA64, .opc0 = 3, .opc1 = 3, .opc2 = 7, .crn = 0, .crm = 0, - .access = PL0_R, .type = ARM_CP_NO_RAW, + .access = PL0_R, .type = ARM_CP_NO_RAW | ARM_CP_NO_GDB, .fgt = FGT_DCZID_EL0, .readfn = aa64_dczid_read }, { .name = "DC_ZVA", .state = ARM_CP_STATE_AA64, @@ -5050,7 +5058,7 @@ static const ARMCPRegInfo v8_cp_reginfo[] = { .fgt = FGT_ICIVAU, .accessfn = access_tocu, #ifdef CONFIG_USER_ONLY - .type = ARM_CP_NO_RAW, + .type = ARM_CP_NO_RAW | ARM_CP_NO_GDB, .writefn = ic_ivau_write #else .type = ARM_CP_NOP @@ -5093,48 +5101,58 @@ static const ARMCPRegInfo v8_cp_reginfo[] = { /* 64 bit address translation operations */ { .name = "AT_S1E1R", .state = ARM_CP_STATE_AA64, .opc0 = 1, .opc1 = 0, .crn = 7, .crm = 8, .opc2 = 0, - .access = PL1_W, .type = ARM_CP_NO_RAW | ARM_CP_RAISES_EXC, + .access = PL1_W, + .type = ARM_CP_NO_RAW | ARM_CP_NO_GDB | ARM_CP_RAISES_EXC, .fgt = FGT_ATS1E1R, .accessfn = at_s1e01_access, .writefn = ats_write64 }, { .name = "AT_S1E1W", .state = ARM_CP_STATE_AA64, .opc0 = 1, .opc1 = 0, .crn = 7, .crm = 8, .opc2 = 1, - .access = PL1_W, .type = ARM_CP_NO_RAW | ARM_CP_RAISES_EXC, + .access = PL1_W, + .type = ARM_CP_NO_RAW | ARM_CP_NO_GDB | ARM_CP_RAISES_EXC, .fgt = FGT_ATS1E1W, .accessfn = at_s1e01_access, .writefn = ats_write64 }, { .name = "AT_S1E0R", .state = ARM_CP_STATE_AA64, .opc0 = 1, .opc1 = 0, .crn = 7, .crm = 8, .opc2 = 2, - .access = PL1_W, .type = ARM_CP_NO_RAW | ARM_CP_RAISES_EXC, + .access = PL1_W, + .type = ARM_CP_NO_RAW | ARM_CP_NO_GDB | ARM_CP_RAISES_EXC, .fgt = FGT_ATS1E0R, .accessfn = at_s1e01_access, .writefn = ats_write64 }, { .name = "AT_S1E0W", .state = ARM_CP_STATE_AA64, .opc0 = 1, .opc1 = 0, .crn = 7, .crm = 8, .opc2 = 3, - .access = PL1_W, .type = ARM_CP_NO_RAW | ARM_CP_RAISES_EXC, + .access = PL1_W, + .type = ARM_CP_NO_RAW | ARM_CP_NO_GDB | ARM_CP_RAISES_EXC, .fgt = FGT_ATS1E0W, .accessfn = at_s1e01_access, .writefn = ats_write64 }, { .name = "AT_S12E1R", .state = ARM_CP_STATE_AA64, .opc0 = 1, .opc1 = 4, .crn = 7, .crm = 8, .opc2 = 4, - .access = PL2_W, .type = ARM_CP_NO_RAW | ARM_CP_RAISES_EXC, + .access = PL2_W, + .type = ARM_CP_NO_RAW | ARM_CP_NO_GDB | ARM_CP_RAISES_EXC, .accessfn = at_e012_access, .writefn = ats_write64 }, { .name = "AT_S12E1W", .state = ARM_CP_STATE_AA64, .opc0 = 1, .opc1 = 4, .crn = 7, .crm = 8, .opc2 = 5, - .access = PL2_W, .type = ARM_CP_NO_RAW | ARM_CP_RAISES_EXC, + .access = PL2_W, + .type = ARM_CP_NO_RAW | ARM_CP_NO_GDB | ARM_CP_RAISES_EXC, .accessfn = at_e012_access, .writefn = ats_write64 }, { .name = "AT_S12E0R", .state = ARM_CP_STATE_AA64, .opc0 = 1, .opc1 = 4, .crn = 7, .crm = 8, .opc2 = 6, - .access = PL2_W, .type = ARM_CP_NO_RAW | ARM_CP_RAISES_EXC, + .access = PL2_W, + .type = ARM_CP_NO_RAW | ARM_CP_NO_GDB | ARM_CP_RAISES_EXC, .accessfn = at_e012_access, .writefn = ats_write64 }, { .name = "AT_S12E0W", .state = ARM_CP_STATE_AA64, .opc0 = 1, .opc1 = 4, .crn = 7, .crm = 8, .opc2 = 7, - .access = PL2_W, .type = ARM_CP_NO_RAW | ARM_CP_RAISES_EXC, + .access = PL2_W, + .type = ARM_CP_NO_RAW | ARM_CP_NO_GDB | ARM_CP_RAISES_EXC, .accessfn = at_e012_access, .writefn = ats_write64 }, /* AT S1E2* are elsewhere as they UNDEF from EL3 if EL2 is not present */ { .name = "AT_S1E3R", .state = ARM_CP_STATE_AA64, .opc0 = 1, .opc1 = 6, .crn = 7, .crm = 8, .opc2 = 0, - .access = PL3_W, .type = ARM_CP_NO_RAW | ARM_CP_RAISES_EXC, + .access = PL3_W, + .type = ARM_CP_NO_RAW | ARM_CP_NO_GDB | ARM_CP_RAISES_EXC, .writefn = ats_write64 }, { .name = "AT_S1E3W", .state = ARM_CP_STATE_AA64, .opc0 = 1, .opc1 = 6, .crn = 7, .crm = 8, .opc2 = 1, - .access = PL3_W, .type = ARM_CP_NO_RAW | ARM_CP_RAISES_EXC, + .access = PL3_W, + .type = ARM_CP_NO_RAW | ARM_CP_NO_GDB | ARM_CP_RAISES_EXC, .writefn = ats_write64 }, { .name = "PAR_EL1", .state = ARM_CP_STATE_AA64, .type = ARM_CP_ALIAS, @@ -5206,7 +5224,7 @@ static const ARMCPRegInfo v8_cp_reginfo[] = { .fieldoffset = offsetof(CPUARMState, sp_el[1]) }, { .name = "SPSel", .state = ARM_CP_STATE_AA64, .opc0 = 3, .opc1 = 0, .crn = 4, .crm = 2, .opc2 = 0, - .type = ARM_CP_NO_RAW, + .type = ARM_CP_NO_RAW | ARM_CP_NO_GDB, .access = PL1_RW, .readfn = spsel_read, .writefn = spsel_write }, { .name = "SPSR_IRQ", .state = ARM_CP_STATE_AA64, .type = ARM_CP_ALIAS, @@ -5742,12 +5760,12 @@ static const ARMCPRegInfo el2_cp_reginfo[] = { { .name = "AT_S1E2R", .state = ARM_CP_STATE_AA64, .opc0 = 1, .opc1 = 4, .crn = 7, .crm = 8, .opc2 = 0, .access = PL2_W, .accessfn = at_s1e2_access, - .type = ARM_CP_NO_RAW | ARM_CP_RAISES_EXC | ARM_CP_EL3_NO_EL2_UNDEF, + .type = ARM_CP_NO_RAW | ARM_CP_NO_GDB | ARM_CP_RAISES_EXC | ARM_CP_EL3_NO_EL2_UNDEF, .writefn = ats_write64 }, { .name = "AT_S1E2W", .state = ARM_CP_STATE_AA64, .opc0 = 1, .opc1 = 4, .crn = 7, .crm = 8, .opc2 = 1, .access = PL2_W, .accessfn = at_s1e2_access, - .type = ARM_CP_NO_RAW | ARM_CP_RAISES_EXC | ARM_CP_EL3_NO_EL2_UNDEF, + .type = ARM_CP_NO_RAW | ARM_CP_NO_GDB | ARM_CP_RAISES_EXC | ARM_CP_EL3_NO_EL2_UNDEF, .writefn = ats_write64 }, /* * The AArch32 ATS1H* operations are CONSTRAINED UNPREDICTABLE @@ -5757,10 +5775,12 @@ static const ARMCPRegInfo el2_cp_reginfo[] = { */ { .name = "ATS1HR", .cp = 15, .opc1 = 4, .crn = 7, .crm = 8, .opc2 = 0, .access = PL2_W, - .writefn = ats1h_write, .type = ARM_CP_NO_RAW | ARM_CP_RAISES_EXC }, + .writefn = ats1h_write, + .type = ARM_CP_NO_RAW | ARM_CP_NO_GDB | ARM_CP_RAISES_EXC }, { .name = "ATS1HW", .cp = 15, .opc1 = 4, .crn = 7, .crm = 8, .opc2 = 1, .access = PL2_W, - .writefn = ats1h_write, .type = ARM_CP_NO_RAW | ARM_CP_RAISES_EXC }, + .writefn = ats1h_write, + .type = ARM_CP_NO_RAW | ARM_CP_NO_GDB | ARM_CP_RAISES_EXC }, { .name = "CNTHCTL_EL2", .state = ARM_CP_STATE_BOTH, .opc0 = 3, .opc1 = 4, .crn = 14, .crm = 1, .opc2 = 0, /* @@ -5792,7 +5812,7 @@ static const ARMCPRegInfo el2_cp_reginfo[] = { .writefn = gt_hyp_cval_write, .raw_writefn = raw_write }, { .name = "CNTHP_TVAL_EL2", .state = ARM_CP_STATE_BOTH, .opc0 = 3, .opc1 = 4, .crn = 14, .crm = 2, .opc2 = 0, - .type = ARM_CP_NO_RAW | ARM_CP_IO, .access = PL2_RW, + .type = ARM_CP_NO_RAW | ARM_CP_NO_GDB | ARM_CP_IO, .access = PL2_RW, .resetfn = gt_hyp_timer_reset, .readfn = gt_hyp_tval_read, .writefn = gt_hyp_tval_write }, { .name = "CNTHP_CTL_EL2", .state = ARM_CP_STATE_BOTH, @@ -5851,7 +5871,7 @@ static const ARMCPRegInfo el2_sec_cp_reginfo[] = { /* Secure EL2 Physical Timer */ { .name = "CNTHPS_TVAL_EL2", .state = ARM_CP_STATE_AA64, .opc0 = 3, .opc1 = 4, .crn = 14, .crm = 5, .opc2 = 0, - .type = ARM_CP_NO_RAW | ARM_CP_IO, .access = PL2_RW, + .type = ARM_CP_NO_RAW | ARM_CP_NO_GDB | ARM_CP_IO, .access = PL2_RW, .accessfn = gt_sel2timer_access, .readfn = gt_sec_pel2_tval_read, .writefn = gt_sec_pel2_tval_write, @@ -5875,7 +5895,7 @@ static const ARMCPRegInfo el2_sec_cp_reginfo[] = { /* Secure EL2 Virtual Timer */ { .name = "CNTHVS_TVAL_EL2", .state = ARM_CP_STATE_AA64, .opc0 = 3, .opc1 = 4, .crn = 14, .crm = 4, .opc2 = 0, - .type = ARM_CP_NO_RAW | ARM_CP_IO, .access = PL2_RW, + .type = ARM_CP_NO_RAW | ARM_CP_NO_GDB | ARM_CP_IO, .access = PL2_RW, .accessfn = gt_sel2timer_access, .readfn = gt_sec_vel2_tval_read, .writefn = gt_sec_vel2_tval_write, @@ -6800,7 +6820,7 @@ static CPAccessResult aa64_allint_access(CPUARMState *env, static const ARMCPRegInfo nmi_reginfo[] = { { .name = "ALLINT", .state = ARM_CP_STATE_AA64, .opc0 = 3, .opc1 = 0, .opc2 = 0, .crn = 4, .crm = 3, - .type = ARM_CP_NO_RAW, + .type = ARM_CP_NO_RAW | ARM_CP_NO_GDB, .access = PL1_RW, .accessfn = aa64_allint_access, .fieldoffset = offsetof(CPUARMState, pstate), .writefn = aa64_allint_write, .readfn = aa64_allint_read, @@ -7099,11 +7119,11 @@ static uint64_t rndr_readfn(CPUARMState *env, const ARMCPRegInfo *ri) /* We do not support re-seeding, so the two registers operate the same. */ static const ARMCPRegInfo rndr_reginfo[] = { { .name = "RNDR", .state = ARM_CP_STATE_AA64, - .type = ARM_CP_NO_RAW | ARM_CP_SUPPRESS_TB_END | ARM_CP_IO, + .type = ARM_CP_NO_RAW | ARM_CP_NO_GDB | ARM_CP_SUPPRESS_TB_END | ARM_CP_IO, .opc0 = 3, .opc1 = 3, .crn = 2, .crm = 4, .opc2 = 0, .access = PL0_R, .readfn = rndr_readfn }, { .name = "RNDRRS", .state = ARM_CP_STATE_AA64, - .type = ARM_CP_NO_RAW | ARM_CP_SUPPRESS_TB_END | ARM_CP_IO, + .type = ARM_CP_NO_RAW | ARM_CP_NO_GDB | ARM_CP_SUPPRESS_TB_END | ARM_CP_IO, .opc0 = 3, .opc1 = 3, .crn = 2, .crm = 4, .opc2 = 1, .access = PL0_R, .readfn = rndr_readfn }, }; @@ -7145,7 +7165,8 @@ static void dccvap_writefn(CPUARMState *env, const ARMCPRegInfo *opaque, static const ARMCPRegInfo dcpop_reg[] = { { .name = "DC_CVAP", .state = ARM_CP_STATE_AA64, .opc0 = 1, .opc1 = 3, .crn = 7, .crm = 12, .opc2 = 1, - .access = PL0_W, .type = ARM_CP_NO_RAW | ARM_CP_SUPPRESS_TB_END, + .access = PL0_W, + .type = ARM_CP_NO_RAW | ARM_CP_NO_GDB | ARM_CP_SUPPRESS_TB_END, .fgt = FGT_DCCVAP, .accessfn = aa64_cacheop_poc_access, .writefn = dccvap_writefn }, }; @@ -7153,7 +7174,8 @@ static const ARMCPRegInfo dcpop_reg[] = { static const ARMCPRegInfo dcpodp_reg[] = { { .name = "DC_CVADP", .state = ARM_CP_STATE_AA64, .opc0 = 1, .opc1 = 3, .crn = 7, .crm = 13, .opc2 = 1, - .access = PL0_W, .type = ARM_CP_NO_RAW | ARM_CP_SUPPRESS_TB_END, + .access = PL0_W, + .type = ARM_CP_NO_RAW | ARM_CP_NO_GDB | ARM_CP_SUPPRESS_TB_END, .fgt = FGT_DCCVADP, .accessfn = aa64_cacheop_poc_access, .writefn = dccvap_writefn }, }; @@ -7265,7 +7287,7 @@ static const ARMCPRegInfo mte_reginfo[] = { .fieldoffset = offsetof(CPUARMState, cp15.gcr_el1) }, { .name = "TCO", .state = ARM_CP_STATE_AA64, .opc0 = 3, .opc1 = 3, .crn = 4, .crm = 2, .opc2 = 7, - .type = ARM_CP_NO_RAW, + .type = ARM_CP_NO_RAW | ARM_CP_NO_GDB, .access = PL0_RW, .readfn = tco_read, .writefn = tco_write }, { .name = "DC_IGVAC", .state = ARM_CP_STATE_AA64, .opc0 = 1, .opc1 = 0, .crn = 7, .crm = 6, .opc2 = 3, @@ -7553,7 +7575,7 @@ static const ARMCPRegInfo ccsidr2_reginfo[] = { .opc0 = 3, .opc1 = 1, .crn = 0, .crm = 0, .opc2 = 2, .access = PL1_R, .accessfn = access_tid4, - .readfn = ccsidr2_read, .type = ARM_CP_NO_RAW }, + .readfn = ccsidr2_read, .type = ARM_CP_NO_RAW | ARM_CP_NO_GDB }, }; static CPAccessResult access_aa64_tid3(CPUARMState *env, const ARMCPRegInfo *ri, @@ -7638,7 +7660,7 @@ static const ARMCPRegInfo vhe_reginfo[] = { .writefn = gt_hv_cval_write, .raw_writefn = raw_write }, { .name = "CNTHV_TVAL_EL2", .state = ARM_CP_STATE_BOTH, .opc0 = 3, .opc1 = 4, .crn = 14, .crm = 3, .opc2 = 0, - .type = ARM_CP_NO_RAW | ARM_CP_IO, .access = PL2_RW, + .type = ARM_CP_NO_RAW | ARM_CP_NO_GDB | ARM_CP_IO, .access = PL2_RW, .resetfn = gt_hv_timer_reset, .readfn = gt_hv_tval_read, .writefn = gt_hv_tval_write }, { .name = "CNTHV_CTL_EL2", .state = ARM_CP_STATE_BOTH, @@ -7663,12 +7685,12 @@ static const ARMCPRegInfo vhe_reginfo[] = { .writefn = gt_virt_ctl_write, .raw_writefn = raw_write }, { .name = "CNTP_TVAL_EL02", .state = ARM_CP_STATE_AA64, .opc0 = 3, .opc1 = 5, .crn = 14, .crm = 2, .opc2 = 0, - .type = ARM_CP_NO_RAW | ARM_CP_IO | ARM_CP_ALIAS, + .type = ARM_CP_NO_RAW | ARM_CP_NO_GDB | ARM_CP_IO | ARM_CP_ALIAS, .access = PL2_RW, .accessfn = e2h_access, .readfn = gt_phys_tval_read, .writefn = gt_phys_tval_write }, { .name = "CNTV_TVAL_EL02", .state = ARM_CP_STATE_AA64, .opc0 = 3, .opc1 = 5, .crn = 14, .crm = 3, .opc2 = 0, - .type = ARM_CP_NO_RAW | ARM_CP_IO | ARM_CP_ALIAS, + .type = ARM_CP_NO_RAW | ARM_CP_NO_GDB | ARM_CP_IO | ARM_CP_ALIAS, .access = PL2_RW, .accessfn = e2h_access, .readfn = gt_virt_tval_read, .writefn = gt_virt_tval_write }, { .name = "CNTP_CVAL_EL02", .state = ARM_CP_STATE_AA64, @@ -7692,12 +7714,14 @@ static const ARMCPRegInfo vhe_reginfo[] = { static const ARMCPRegInfo ats1e1_reginfo[] = { { .name = "AT_S1E1RP", .state = ARM_CP_STATE_AA64, .opc0 = 1, .opc1 = 0, .crn = 7, .crm = 9, .opc2 = 0, - .access = PL1_W, .type = ARM_CP_NO_RAW | ARM_CP_RAISES_EXC, + .access = PL1_W, + .type = ARM_CP_NO_RAW | ARM_CP_NO_GDB | ARM_CP_RAISES_EXC, .fgt = FGT_ATS1E1RP, .accessfn = at_s1e01_access, .writefn = ats_write64 }, { .name = "AT_S1E1WP", .state = ARM_CP_STATE_AA64, .opc0 = 1, .opc1 = 0, .crn = 7, .crm = 9, .opc2 = 1, - .access = PL1_W, .type = ARM_CP_NO_RAW | ARM_CP_RAISES_EXC, + .access = PL1_W, + .type = ARM_CP_NO_RAW | ARM_CP_NO_GDB | ARM_CP_RAISES_EXC, .fgt = FGT_ATS1E1WP, .accessfn = at_s1e01_access, .writefn = ats_write64 }, }; @@ -7705,11 +7729,13 @@ static const ARMCPRegInfo ats1e1_reginfo[] = { static const ARMCPRegInfo ats1cp_reginfo[] = { { .name = "ATS1CPRP", .cp = 15, .opc1 = 0, .crn = 7, .crm = 9, .opc2 = 0, - .access = PL1_W, .type = ARM_CP_NO_RAW | ARM_CP_RAISES_EXC, + .access = PL1_W, + .type = ARM_CP_NO_RAW | ARM_CP_NO_GDB | ARM_CP_RAISES_EXC, .writefn = ats_write }, { .name = "ATS1CPWP", .cp = 15, .opc1 = 0, .crn = 7, .crm = 9, .opc2 = 1, - .access = PL1_W, .type = ARM_CP_NO_RAW | ARM_CP_RAISES_EXC, + .access = PL1_W, + .type = ARM_CP_NO_RAW | ARM_CP_NO_GDB | ARM_CP_RAISES_EXC, .writefn = ats_write }, }; #endif @@ -7768,13 +7794,13 @@ void register_cp_regs_for_features(ARMCPU *cpu) */ { .name = "ID_PFR1", .state = ARM_CP_STATE_BOTH, .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 1, .opc2 = 1, - .access = PL1_R, .type = ARM_CP_NO_RAW, + .access = PL1_R, .type = ARM_CP_NO_RAW | ARM_CP_NO_GDB, .accessfn = access_aa32_tid3, #ifdef CONFIG_USER_ONLY .type = ARM_CP_CONST, .resetvalue = cpu->isar.id_pfr1, #else - .type = ARM_CP_NO_RAW, + .type = ARM_CP_NO_RAW | ARM_CP_NO_GDB, .accessfn = access_aa32_tid3, .readfn = id_pfr1_read, .writefn = arm_cp_write_ignore @@ -7902,7 +7928,7 @@ void register_cp_regs_for_features(ARMCPU *cpu) .type = ARM_CP_CONST, .resetvalue = cpu->isar.id_aa64pfr0 #else - .type = ARM_CP_NO_RAW, + .type = ARM_CP_NO_RAW | ARM_CP_NO_GDB, .accessfn = access_aa64_tid3, .readfn = id_aa64pfr0_read, .writefn = arm_cp_write_ignore @@ -8488,7 +8514,8 @@ void register_cp_regs_for_features(ARMCPU *cpu) /* This underdecoding is safe because the reginfo is NO_RAW. */ { .name = "ATS", .cp = 15, .crn = 7, .crm = 8, .opc1 = 0, .opc2 = CP_ANY, .access = PL1_W, .accessfn = ats_access, - .writefn = ats_write, .type = ARM_CP_NO_RAW | ARM_CP_RAISES_EXC }, + .writefn = ats_write, + .type = ARM_CP_NO_RAW | ARM_CP_NO_GDB | ARM_CP_RAISES_EXC }, #endif }; @@ -8572,7 +8599,8 @@ void register_cp_regs_for_features(ARMCPU *cpu) ARMCPRegInfo id_v8_midr_cp_reginfo[] = { { .name = "MIDR_EL1", .state = ARM_CP_STATE_BOTH, .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 0, .opc2 = 0, - .access = PL1_R, .type = ARM_CP_NO_RAW, .resetvalue = cpu->midr, + .access = PL1_R, .type = ARM_CP_NO_RAW | ARM_CP_NO_GDB, + .resetvalue = cpu->midr, .fgt = FGT_MIDR_EL1, .fieldoffset = offsetof(CPUARMState, cp15.c0_cpuid), .readfn = midr_read }, @@ -8696,7 +8724,8 @@ void register_cp_regs_for_features(ARMCPU *cpu) tmp_string = g_strdup_printf("PRBAR%u", i); ARMCPRegInfo tmp_prbarn_reginfo = { - .name = tmp_string, .type = ARM_CP_ALIAS | ARM_CP_NO_RAW, + .name = tmp_string, + .type = ARM_CP_ALIAS | ARM_CP_NO_RAW | ARM_CP_NO_GDB, .cp = 15, .opc1 = opc1, .crn = 6, .crm = crm, .opc2 = opc2, .access = PL1_RW, .resetvalue = 0, .accessfn = access_tvm_trvm, @@ -8708,7 +8737,8 @@ void register_cp_regs_for_features(ARMCPU *cpu) opc2 = extract32(i, 0, 1) << 2 | 0x1; tmp_string = g_strdup_printf("PRLAR%u", i); ARMCPRegInfo tmp_prlarn_reginfo = { - .name = tmp_string, .type = ARM_CP_ALIAS | ARM_CP_NO_RAW, + .name = tmp_string, + .type = ARM_CP_ALIAS | ARM_CP_NO_RAW | ARM_CP_NO_GDB, .cp = 15, .opc1 = opc1, .crn = 6, .crm = crm, .opc2 = opc2, .access = PL1_RW, .resetvalue = 0, .accessfn = access_tvm_trvm, @@ -8727,7 +8757,7 @@ void register_cp_regs_for_features(ARMCPU *cpu) tmp_string = g_strdup_printf("HPRBAR%u", i); ARMCPRegInfo tmp_hprbarn_reginfo = { .name = tmp_string, - .type = ARM_CP_NO_RAW, + .type = ARM_CP_NO_RAW | ARM_CP_NO_GDB, .cp = 15, .opc1 = opc1, .crn = 6, .crm = crm, .opc2 = opc2, .access = PL2_RW, .resetvalue = 0, .writefn = pmsav8r_regn_write, .readfn = pmsav8r_regn_read @@ -8739,7 +8769,7 @@ void register_cp_regs_for_features(ARMCPU *cpu) tmp_string = g_strdup_printf("HPRLAR%u", i); ARMCPRegInfo tmp_hprlarn_reginfo = { .name = tmp_string, - .type = ARM_CP_NO_RAW, + .type = ARM_CP_NO_RAW | ARM_CP_NO_GDB, .cp = 15, .opc1 = opc1, .crn = 6, .crm = crm, .opc2 = opc2, .access = PL2_RW, .resetvalue = 0, .writefn = pmsav8r_regn_write, .readfn = pmsav8r_regn_read @@ -8757,7 +8787,8 @@ void register_cp_regs_for_features(ARMCPU *cpu) { .name = "MPIDR_EL1", .state = ARM_CP_STATE_BOTH, .opc0 = 3, .crn = 0, .crm = 0, .opc1 = 0, .opc2 = 5, .fgt = FGT_MPIDR_EL1, - .access = PL1_R, .readfn = mpidr_read, .type = ARM_CP_NO_RAW }, + .access = PL1_R, .readfn = mpidr_read, + .type = ARM_CP_NO_RAW | ARM_CP_NO_GDB }, }; #ifdef CONFIG_USER_ONLY static const ARMCPRegUserSpaceInfo mpidr_user_cp_reginfo[] = { @@ -9195,7 +9226,7 @@ static void add_cpreg_to_hashtable(ARMCPU *cpu, const ARMCPRegInfo *r, * never migratable and not even raw-accessible. */ if (r2->type & ARM_CP_SPECIAL_MASK) { - r2->type |= ARM_CP_NO_RAW; + r2->type |= ARM_CP_NO_RAW | ARM_CP_NO_GDB; } if (((r->crm == CP_ANY) && crm != 0) || ((r->opc1 == CP_ANY) && opc1 != 0) || diff --git a/target/arm/tcg/tlb-insns.c b/target/arm/tcg/tlb-insns.c index 630a481f0f81..8508b253e97d 100644 --- a/target/arm/tcg/tlb-insns.c +++ b/target/arm/tcg/tlb-insns.c @@ -513,291 +513,323 @@ static const ARMCPRegInfo tlbi_not_v7_cp_reginfo[] = { */ { .name = "TLBIALL", .cp = 15, .crn = 8, .crm = CP_ANY, .opc1 = CP_ANY, .opc2 = 0, .access = PL1_W, .writefn = tlbiall_write, - .type = ARM_CP_NO_RAW }, + .type = ARM_CP_NO_RAW | ARM_CP_NO_GDB }, { .name = "TLBIMVA", .cp = 15, .crn = 8, .crm = CP_ANY, .opc1 = CP_ANY, .opc2 = 1, .access = PL1_W, .writefn = tlbimva_write, - .type = ARM_CP_NO_RAW }, + .type = ARM_CP_NO_RAW | ARM_CP_NO_GDB }, { .name = "TLBIASID", .cp = 15, .crn = 8, .crm = CP_ANY, .opc1 = CP_ANY, .opc2 = 2, .access = PL1_W, .writefn = tlbiasid_write, - .type = ARM_CP_NO_RAW }, + .type = ARM_CP_NO_RAW | ARM_CP_NO_GDB }, { .name = "TLBIMVAA", .cp = 15, .crn = 8, .crm = CP_ANY, .opc1 = CP_ANY, .opc2 = 3, .access = PL1_W, .writefn = tlbimvaa_write, - .type = ARM_CP_NO_RAW }, + .type = ARM_CP_NO_RAW | ARM_CP_NO_GDB }, }; static const ARMCPRegInfo tlbi_v7_cp_reginfo[] = { /* 32 bit ITLB invalidates */ { .name = "ITLBIALL", .cp = 15, .opc1 = 0, .crn = 8, .crm = 5, .opc2 = 0, - .type = ARM_CP_NO_RAW, .access = PL1_W, .accessfn = access_ttlb, + .type = ARM_CP_NO_RAW | ARM_CP_NO_GDB, + .access = PL1_W, .accessfn = access_ttlb, .writefn = tlbiall_write }, { .name = "ITLBIMVA", .cp = 15, .opc1 = 0, .crn = 8, .crm = 5, .opc2 = 1, - .type = ARM_CP_NO_RAW, .access = PL1_W, .accessfn = access_ttlb, + .type = ARM_CP_NO_RAW | ARM_CP_NO_GDB, + .access = PL1_W, .accessfn = access_ttlb, .writefn = tlbimva_write }, { .name = "ITLBIASID", .cp = 15, .opc1 = 0, .crn = 8, .crm = 5, .opc2 = 2, - .type = ARM_CP_NO_RAW, .access = PL1_W, .accessfn = access_ttlb, + .type = ARM_CP_NO_RAW | ARM_CP_NO_GDB, + .access = PL1_W, .accessfn = access_ttlb, .writefn = tlbiasid_write }, /* 32 bit DTLB invalidates */ { .name = "DTLBIALL", .cp = 15, .opc1 = 0, .crn = 8, .crm = 6, .opc2 = 0, - .type = ARM_CP_NO_RAW, .access = PL1_W, .accessfn = access_ttlb, + .type = ARM_CP_NO_RAW | ARM_CP_NO_GDB, + .access = PL1_W, .accessfn = access_ttlb, .writefn = tlbiall_write }, { .name = "DTLBIMVA", .cp = 15, .opc1 = 0, .crn = 8, .crm = 6, .opc2 = 1, - .type = ARM_CP_NO_RAW, .access = PL1_W, .accessfn = access_ttlb, + .type = ARM_CP_NO_RAW | ARM_CP_NO_GDB, + .access = PL1_W, .accessfn = access_ttlb, .writefn = tlbimva_write }, { .name = "DTLBIASID", .cp = 15, .opc1 = 0, .crn = 8, .crm = 6, .opc2 = 2, - .type = ARM_CP_NO_RAW, .access = PL1_W, .accessfn = access_ttlb, + .type = ARM_CP_NO_RAW | ARM_CP_NO_GDB, + .access = PL1_W, .accessfn = access_ttlb, .writefn = tlbiasid_write }, /* 32 bit TLB invalidates */ { .name = "TLBIALL", .cp = 15, .opc1 = 0, .crn = 8, .crm = 7, .opc2 = 0, - .type = ARM_CP_NO_RAW, .access = PL1_W, .accessfn = access_ttlb, + .type = ARM_CP_NO_RAW | ARM_CP_NO_GDB, + .access = PL1_W, .accessfn = access_ttlb, .writefn = tlbiall_write }, { .name = "TLBIMVA", .cp = 15, .opc1 = 0, .crn = 8, .crm = 7, .opc2 = 1, - .type = ARM_CP_NO_RAW, .access = PL1_W, .accessfn = access_ttlb, + .type = ARM_CP_NO_RAW | ARM_CP_NO_GDB, + .access = PL1_W, .accessfn = access_ttlb, .writefn = tlbimva_write }, { .name = "TLBIASID", .cp = 15, .opc1 = 0, .crn = 8, .crm = 7, .opc2 = 2, - .type = ARM_CP_NO_RAW, .access = PL1_W, .accessfn = access_ttlb, + .type = ARM_CP_NO_RAW | ARM_CP_NO_GDB, + .access = PL1_W, .accessfn = access_ttlb, .writefn = tlbiasid_write }, { .name = "TLBIMVAA", .cp = 15, .opc1 = 0, .crn = 8, .crm = 7, .opc2 = 3, - .type = ARM_CP_NO_RAW, .access = PL1_W, .accessfn = access_ttlb, + .type = ARM_CP_NO_RAW | ARM_CP_NO_GDB, + .access = PL1_W, .accessfn = access_ttlb, .writefn = tlbimvaa_write }, }; static const ARMCPRegInfo tlbi_v7mp_cp_reginfo[] = { /* 32 bit TLB invalidates, Inner Shareable */ { .name = "TLBIALLIS", .cp = 15, .opc1 = 0, .crn = 8, .crm = 3, .opc2 = 0, - .type = ARM_CP_NO_RAW, .access = PL1_W, .accessfn = access_ttlbis, + .type = ARM_CP_NO_RAW | ARM_CP_NO_GDB, + .access = PL1_W, .accessfn = access_ttlbis, .writefn = tlbiall_is_write }, { .name = "TLBIMVAIS", .cp = 15, .opc1 = 0, .crn = 8, .crm = 3, .opc2 = 1, - .type = ARM_CP_NO_RAW, .access = PL1_W, .accessfn = access_ttlbis, + .type = ARM_CP_NO_RAW | ARM_CP_NO_GDB, + .access = PL1_W, .accessfn = access_ttlbis, .writefn = tlbimva_is_write }, { .name = "TLBIASIDIS", .cp = 15, .opc1 = 0, .crn = 8, .crm = 3, .opc2 = 2, - .type = ARM_CP_NO_RAW, .access = PL1_W, .accessfn = access_ttlbis, + .type = ARM_CP_NO_RAW | ARM_CP_NO_GDB, + .access = PL1_W, .accessfn = access_ttlbis, .writefn = tlbiasid_is_write }, { .name = "TLBIMVAAIS", .cp = 15, .opc1 = 0, .crn = 8, .crm = 3, .opc2 = 3, - .type = ARM_CP_NO_RAW, .access = PL1_W, .accessfn = access_ttlbis, + .type = ARM_CP_NO_RAW | ARM_CP_NO_GDB, + .access = PL1_W, .accessfn = access_ttlbis, .writefn = tlbimvaa_is_write }, }; static const ARMCPRegInfo tlbi_v8_cp_reginfo[] = { /* AArch32 TLB invalidate last level of translation table walk */ { .name = "TLBIMVALIS", .cp = 15, .opc1 = 0, .crn = 8, .crm = 3, .opc2 = 5, - .type = ARM_CP_NO_RAW, .access = PL1_W, .accessfn = access_ttlbis, + .type = ARM_CP_NO_RAW | ARM_CP_NO_GDB, + .access = PL1_W, .accessfn = access_ttlbis, .writefn = tlbimva_is_write }, { .name = "TLBIMVAALIS", .cp = 15, .opc1 = 0, .crn = 8, .crm = 3, .opc2 = 7, - .type = ARM_CP_NO_RAW, .access = PL1_W, .accessfn = access_ttlbis, + .type = ARM_CP_NO_RAW | ARM_CP_NO_GDB, + .access = PL1_W, .accessfn = access_ttlbis, .writefn = tlbimvaa_is_write }, { .name = "TLBIMVAL", .cp = 15, .opc1 = 0, .crn = 8, .crm = 7, .opc2 = 5, - .type = ARM_CP_NO_RAW, .access = PL1_W, .accessfn = access_ttlb, + .type = ARM_CP_NO_RAW | ARM_CP_NO_GDB, + .access = PL1_W, .accessfn = access_ttlb, .writefn = tlbimva_write }, { .name = "TLBIMVAAL", .cp = 15, .opc1 = 0, .crn = 8, .crm = 7, .opc2 = 7, - .type = ARM_CP_NO_RAW, .access = PL1_W, .accessfn = access_ttlb, + .type = ARM_CP_NO_RAW | ARM_CP_NO_GDB, + .access = PL1_W, .accessfn = access_ttlb, .writefn = tlbimvaa_write }, { .name = "TLBIMVALH", .cp = 15, .opc1 = 4, .crn = 8, .crm = 7, .opc2 = 5, - .type = ARM_CP_NO_RAW, .access = PL2_W, + .type = ARM_CP_NO_RAW | ARM_CP_NO_GDB, .access = PL2_W, .writefn = tlbimva_hyp_write }, { .name = "TLBIMVALHIS", .cp = 15, .opc1 = 4, .crn = 8, .crm = 3, .opc2 = 5, - .type = ARM_CP_NO_RAW, .access = PL2_W, + .type = ARM_CP_NO_RAW | ARM_CP_NO_GDB, .access = PL2_W, .writefn = tlbimva_hyp_is_write }, { .name = "TLBIIPAS2", .cp = 15, .opc1 = 4, .crn = 8, .crm = 4, .opc2 = 1, - .type = ARM_CP_NO_RAW, .access = PL2_W, + .type = ARM_CP_NO_RAW | ARM_CP_NO_GDB, .access = PL2_W, .writefn = tlbiipas2_hyp_write }, { .name = "TLBIIPAS2IS", .cp = 15, .opc1 = 4, .crn = 8, .crm = 0, .opc2 = 1, - .type = ARM_CP_NO_RAW, .access = PL2_W, + .type = ARM_CP_NO_RAW | ARM_CP_NO_GDB, .access = PL2_W, .writefn = tlbiipas2is_hyp_write }, { .name = "TLBIIPAS2L", .cp = 15, .opc1 = 4, .crn = 8, .crm = 4, .opc2 = 5, - .type = ARM_CP_NO_RAW, .access = PL2_W, + .type = ARM_CP_NO_RAW | ARM_CP_NO_GDB, .access = PL2_W, .writefn = tlbiipas2_hyp_write }, { .name = "TLBIIPAS2LIS", .cp = 15, .opc1 = 4, .crn = 8, .crm = 0, .opc2 = 5, - .type = ARM_CP_NO_RAW, .access = PL2_W, + .type = ARM_CP_NO_RAW | ARM_CP_NO_GDB, .access = PL2_W, .writefn = tlbiipas2is_hyp_write }, /* AArch64 TLBI operations */ { .name = "TLBI_VMALLE1IS", .state = ARM_CP_STATE_AA64, .opc0 = 1, .opc1 = 0, .crn = 8, .crm = 3, .opc2 = 0, .access = PL1_W, .accessfn = access_ttlbis, - .type = ARM_CP_NO_RAW | ARM_CP_ADD_TLBI_NXS, + .type = ARM_CP_NO_RAW | ARM_CP_NO_GDB | ARM_CP_ADD_TLBI_NXS, .fgt = FGT_TLBIVMALLE1IS, .writefn = tlbi_aa64_vmalle1is_write }, { .name = "TLBI_VAE1IS", .state = ARM_CP_STATE_AA64, .opc0 = 1, .opc1 = 0, .crn = 8, .crm = 3, .opc2 = 1, .access = PL1_W, .accessfn = access_ttlbis, - .type = ARM_CP_NO_RAW | ARM_CP_ADD_TLBI_NXS, + .type = ARM_CP_NO_RAW | ARM_CP_NO_GDB | ARM_CP_ADD_TLBI_NXS, .fgt = FGT_TLBIVAE1IS, .writefn = tlbi_aa64_vae1is_write }, { .name = "TLBI_ASIDE1IS", .state = ARM_CP_STATE_AA64, .opc0 = 1, .opc1 = 0, .crn = 8, .crm = 3, .opc2 = 2, .access = PL1_W, .accessfn = access_ttlbis, - .type = ARM_CP_NO_RAW | ARM_CP_ADD_TLBI_NXS, + .type = ARM_CP_NO_RAW | ARM_CP_NO_GDB | ARM_CP_ADD_TLBI_NXS, .fgt = FGT_TLBIASIDE1IS, .writefn = tlbi_aa64_vmalle1is_write }, { .name = "TLBI_VAAE1IS", .state = ARM_CP_STATE_AA64, .opc0 = 1, .opc1 = 0, .crn = 8, .crm = 3, .opc2 = 3, .access = PL1_W, .accessfn = access_ttlbis, - .type = ARM_CP_NO_RAW | ARM_CP_ADD_TLBI_NXS, + .type = ARM_CP_NO_RAW | ARM_CP_NO_GDB | ARM_CP_ADD_TLBI_NXS, .fgt = FGT_TLBIVAAE1IS, .writefn = tlbi_aa64_vae1is_write }, { .name = "TLBI_VALE1IS", .state = ARM_CP_STATE_AA64, .opc0 = 1, .opc1 = 0, .crn = 8, .crm = 3, .opc2 = 5, .access = PL1_W, .accessfn = access_ttlbis, - .type = ARM_CP_NO_RAW | ARM_CP_ADD_TLBI_NXS, + .type = ARM_CP_NO_RAW | ARM_CP_NO_GDB | ARM_CP_ADD_TLBI_NXS, .fgt = FGT_TLBIVALE1IS, .writefn = tlbi_aa64_vae1is_write }, { .name = "TLBI_VAALE1IS", .state = ARM_CP_STATE_AA64, .opc0 = 1, .opc1 = 0, .crn = 8, .crm = 3, .opc2 = 7, .access = PL1_W, .accessfn = access_ttlbis, - .type = ARM_CP_NO_RAW | ARM_CP_ADD_TLBI_NXS, + .type = ARM_CP_NO_RAW | ARM_CP_NO_GDB | ARM_CP_ADD_TLBI_NXS, .fgt = FGT_TLBIVAALE1IS, .writefn = tlbi_aa64_vae1is_write }, { .name = "TLBI_VMALLE1", .state = ARM_CP_STATE_AA64, .opc0 = 1, .opc1 = 0, .crn = 8, .crm = 7, .opc2 = 0, .access = PL1_W, .accessfn = access_ttlb, - .type = ARM_CP_NO_RAW | ARM_CP_ADD_TLBI_NXS, + .type = ARM_CP_NO_RAW | ARM_CP_NO_GDB | ARM_CP_ADD_TLBI_NXS, .fgt = FGT_TLBIVMALLE1, .writefn = tlbi_aa64_vmalle1_write }, { .name = "TLBI_VAE1", .state = ARM_CP_STATE_AA64, .opc0 = 1, .opc1 = 0, .crn = 8, .crm = 7, .opc2 = 1, .access = PL1_W, .accessfn = access_ttlb, - .type = ARM_CP_NO_RAW | ARM_CP_ADD_TLBI_NXS, + .type = ARM_CP_NO_RAW | ARM_CP_NO_GDB | ARM_CP_ADD_TLBI_NXS, .fgt = FGT_TLBIVAE1, .writefn = tlbi_aa64_vae1_write }, { .name = "TLBI_ASIDE1", .state = ARM_CP_STATE_AA64, .opc0 = 1, .opc1 = 0, .crn = 8, .crm = 7, .opc2 = 2, .access = PL1_W, .accessfn = access_ttlb, - .type = ARM_CP_NO_RAW | ARM_CP_ADD_TLBI_NXS, + .type = ARM_CP_NO_RAW | ARM_CP_NO_GDB | ARM_CP_ADD_TLBI_NXS, .fgt = FGT_TLBIASIDE1, .writefn = tlbi_aa64_vmalle1_write }, { .name = "TLBI_VAAE1", .state = ARM_CP_STATE_AA64, .opc0 = 1, .opc1 = 0, .crn = 8, .crm = 7, .opc2 = 3, .access = PL1_W, .accessfn = access_ttlb, - .type = ARM_CP_NO_RAW | ARM_CP_ADD_TLBI_NXS, + .type = ARM_CP_NO_RAW | ARM_CP_NO_GDB | ARM_CP_ADD_TLBI_NXS, .fgt = FGT_TLBIVAAE1, .writefn = tlbi_aa64_vae1_write }, { .name = "TLBI_VALE1", .state = ARM_CP_STATE_AA64, .opc0 = 1, .opc1 = 0, .crn = 8, .crm = 7, .opc2 = 5, .access = PL1_W, .accessfn = access_ttlb, - .type = ARM_CP_NO_RAW | ARM_CP_ADD_TLBI_NXS, + .type = ARM_CP_NO_RAW | ARM_CP_NO_GDB | ARM_CP_ADD_TLBI_NXS, .fgt = FGT_TLBIVALE1, .writefn = tlbi_aa64_vae1_write }, { .name = "TLBI_VAALE1", .state = ARM_CP_STATE_AA64, .opc0 = 1, .opc1 = 0, .crn = 8, .crm = 7, .opc2 = 7, .access = PL1_W, .accessfn = access_ttlb, - .type = ARM_CP_NO_RAW | ARM_CP_ADD_TLBI_NXS, + .type = ARM_CP_NO_RAW | ARM_CP_NO_GDB | ARM_CP_ADD_TLBI_NXS, .fgt = FGT_TLBIVAALE1, .writefn = tlbi_aa64_vae1_write }, { .name = "TLBI_IPAS2E1IS", .state = ARM_CP_STATE_AA64, .opc0 = 1, .opc1 = 4, .crn = 8, .crm = 0, .opc2 = 1, - .access = PL2_W, .type = ARM_CP_NO_RAW | ARM_CP_ADD_TLBI_NXS, + .access = PL2_W, + .type = ARM_CP_NO_RAW | ARM_CP_NO_GDB | ARM_CP_ADD_TLBI_NXS, .writefn = tlbi_aa64_ipas2e1is_write }, { .name = "TLBI_IPAS2LE1IS", .state = ARM_CP_STATE_AA64, .opc0 = 1, .opc1 = 4, .crn = 8, .crm = 0, .opc2 = 5, - .access = PL2_W, .type = ARM_CP_NO_RAW | ARM_CP_ADD_TLBI_NXS, + .access = PL2_W, + .type = ARM_CP_NO_RAW | ARM_CP_NO_GDB | ARM_CP_ADD_TLBI_NXS, .writefn = tlbi_aa64_ipas2e1is_write }, { .name = "TLBI_ALLE1IS", .state = ARM_CP_STATE_AA64, .opc0 = 1, .opc1 = 4, .crn = 8, .crm = 3, .opc2 = 4, - .access = PL2_W, .type = ARM_CP_NO_RAW | ARM_CP_ADD_TLBI_NXS, + .access = PL2_W, + .type = ARM_CP_NO_RAW | ARM_CP_NO_GDB | ARM_CP_ADD_TLBI_NXS, .writefn = tlbi_aa64_alle1is_write }, { .name = "TLBI_VMALLS12E1IS", .state = ARM_CP_STATE_AA64, .opc0 = 1, .opc1 = 4, .crn = 8, .crm = 3, .opc2 = 6, - .access = PL2_W, .type = ARM_CP_NO_RAW | ARM_CP_ADD_TLBI_NXS, + .access = PL2_W, + .type = ARM_CP_NO_RAW | ARM_CP_NO_GDB | ARM_CP_ADD_TLBI_NXS, .writefn = tlbi_aa64_alle1is_write }, { .name = "TLBI_IPAS2E1", .state = ARM_CP_STATE_AA64, .opc0 = 1, .opc1 = 4, .crn = 8, .crm = 4, .opc2 = 1, - .access = PL2_W, .type = ARM_CP_NO_RAW | ARM_CP_ADD_TLBI_NXS, + .access = PL2_W, + .type = ARM_CP_NO_RAW | ARM_CP_NO_GDB | ARM_CP_ADD_TLBI_NXS, .writefn = tlbi_aa64_ipas2e1_write }, { .name = "TLBI_IPAS2LE1", .state = ARM_CP_STATE_AA64, .opc0 = 1, .opc1 = 4, .crn = 8, .crm = 4, .opc2 = 5, - .access = PL2_W, .type = ARM_CP_NO_RAW | ARM_CP_ADD_TLBI_NXS, + .access = PL2_W, + .type = ARM_CP_NO_RAW | ARM_CP_NO_GDB | ARM_CP_ADD_TLBI_NXS, .writefn = tlbi_aa64_ipas2e1_write }, { .name = "TLBI_ALLE1", .state = ARM_CP_STATE_AA64, .opc0 = 1, .opc1 = 4, .crn = 8, .crm = 7, .opc2 = 4, - .access = PL2_W, .type = ARM_CP_NO_RAW | ARM_CP_ADD_TLBI_NXS, + .access = PL2_W, + .type = ARM_CP_NO_RAW | ARM_CP_NO_GDB | ARM_CP_ADD_TLBI_NXS, .writefn = tlbi_aa64_alle1_write }, { .name = "TLBI_VMALLS12E1", .state = ARM_CP_STATE_AA64, .opc0 = 1, .opc1 = 4, .crn = 8, .crm = 7, .opc2 = 6, - .access = PL2_W, .type = ARM_CP_NO_RAW | ARM_CP_ADD_TLBI_NXS, + .access = PL2_W, + .type = ARM_CP_NO_RAW | ARM_CP_NO_GDB | ARM_CP_ADD_TLBI_NXS, .writefn = tlbi_aa64_alle1is_write }, }; static const ARMCPRegInfo tlbi_el2_cp_reginfo[] = { { .name = "TLBIALLNSNH", .cp = 15, .opc1 = 4, .crn = 8, .crm = 7, .opc2 = 4, - .type = ARM_CP_NO_RAW, .access = PL2_W, + .type = ARM_CP_NO_RAW | ARM_CP_NO_GDB, .access = PL2_W, .writefn = tlbiall_nsnh_write }, { .name = "TLBIALLNSNHIS", .cp = 15, .opc1 = 4, .crn = 8, .crm = 3, .opc2 = 4, - .type = ARM_CP_NO_RAW, .access = PL2_W, + .type = ARM_CP_NO_RAW | ARM_CP_NO_GDB, .access = PL2_W, .writefn = tlbiall_nsnh_is_write }, { .name = "TLBIALLH", .cp = 15, .opc1 = 4, .crn = 8, .crm = 7, .opc2 = 0, - .type = ARM_CP_NO_RAW, .access = PL2_W, + .type = ARM_CP_NO_RAW | ARM_CP_NO_GDB, .access = PL2_W, .writefn = tlbiall_hyp_write }, { .name = "TLBIALLHIS", .cp = 15, .opc1 = 4, .crn = 8, .crm = 3, .opc2 = 0, - .type = ARM_CP_NO_RAW, .access = PL2_W, + .type = ARM_CP_NO_RAW | ARM_CP_NO_GDB, .access = PL2_W, .writefn = tlbiall_hyp_is_write }, { .name = "TLBIMVAH", .cp = 15, .opc1 = 4, .crn = 8, .crm = 7, .opc2 = 1, - .type = ARM_CP_NO_RAW, .access = PL2_W, + .type = ARM_CP_NO_RAW | ARM_CP_NO_GDB, .access = PL2_W, .writefn = tlbimva_hyp_write }, { .name = "TLBIMVAHIS", .cp = 15, .opc1 = 4, .crn = 8, .crm = 3, .opc2 = 1, - .type = ARM_CP_NO_RAW, .access = PL2_W, + .type = ARM_CP_NO_RAW | ARM_CP_NO_GDB, .access = PL2_W, .writefn = tlbimva_hyp_is_write }, { .name = "TLBI_ALLE2", .state = ARM_CP_STATE_AA64, .opc0 = 1, .opc1 = 4, .crn = 8, .crm = 7, .opc2 = 0, .access = PL2_W, - .type = ARM_CP_NO_RAW | ARM_CP_ADD_TLBI_NXS | ARM_CP_EL3_NO_EL2_UNDEF, + .type = ARM_CP_NO_RAW | ARM_CP_NO_GDB | ARM_CP_ADD_TLBI_NXS | ARM_CP_EL3_NO_EL2_UNDEF, .writefn = tlbi_aa64_alle2_write }, { .name = "TLBI_VAE2", .state = ARM_CP_STATE_AA64, .opc0 = 1, .opc1 = 4, .crn = 8, .crm = 7, .opc2 = 1, .access = PL2_W, - .type = ARM_CP_NO_RAW | ARM_CP_ADD_TLBI_NXS | ARM_CP_EL3_NO_EL2_UNDEF, + .type = ARM_CP_NO_RAW | ARM_CP_NO_GDB | ARM_CP_ADD_TLBI_NXS | ARM_CP_EL3_NO_EL2_UNDEF, .writefn = tlbi_aa64_vae2_write }, { .name = "TLBI_VALE2", .state = ARM_CP_STATE_AA64, .opc0 = 1, .opc1 = 4, .crn = 8, .crm = 7, .opc2 = 5, .access = PL2_W, - .type = ARM_CP_NO_RAW | ARM_CP_ADD_TLBI_NXS | ARM_CP_EL3_NO_EL2_UNDEF, + .type = ARM_CP_NO_RAW | ARM_CP_NO_GDB | ARM_CP_ADD_TLBI_NXS | ARM_CP_EL3_NO_EL2_UNDEF, .writefn = tlbi_aa64_vae2_write }, { .name = "TLBI_ALLE2IS", .state = ARM_CP_STATE_AA64, .opc0 = 1, .opc1 = 4, .crn = 8, .crm = 3, .opc2 = 0, .access = PL2_W, - .type = ARM_CP_NO_RAW | ARM_CP_ADD_TLBI_NXS | ARM_CP_EL3_NO_EL2_UNDEF, + .type = ARM_CP_NO_RAW | ARM_CP_NO_GDB | ARM_CP_ADD_TLBI_NXS | ARM_CP_EL3_NO_EL2_UNDEF, .writefn = tlbi_aa64_alle2is_write }, { .name = "TLBI_VAE2IS", .state = ARM_CP_STATE_AA64, .opc0 = 1, .opc1 = 4, .crn = 8, .crm = 3, .opc2 = 1, .access = PL2_W, - .type = ARM_CP_NO_RAW | ARM_CP_ADD_TLBI_NXS | ARM_CP_EL3_NO_EL2_UNDEF, + .type = ARM_CP_NO_RAW | ARM_CP_NO_GDB | ARM_CP_ADD_TLBI_NXS | ARM_CP_EL3_NO_EL2_UNDEF, .writefn = tlbi_aa64_vae2is_write }, { .name = "TLBI_VALE2IS", .state = ARM_CP_STATE_AA64, .opc0 = 1, .opc1 = 4, .crn = 8, .crm = 3, .opc2 = 5, .access = PL2_W, - .type = ARM_CP_NO_RAW | ARM_CP_ADD_TLBI_NXS | ARM_CP_EL3_NO_EL2_UNDEF, + .type = ARM_CP_NO_RAW | ARM_CP_NO_GDB | ARM_CP_ADD_TLBI_NXS | ARM_CP_EL3_NO_EL2_UNDEF, .writefn = tlbi_aa64_vae2is_write }, }; static const ARMCPRegInfo tlbi_el3_cp_reginfo[] = { { .name = "TLBI_ALLE3IS", .state = ARM_CP_STATE_AA64, .opc0 = 1, .opc1 = 6, .crn = 8, .crm = 3, .opc2 = 0, - .access = PL3_W, .type = ARM_CP_NO_RAW | ARM_CP_ADD_TLBI_NXS, + .access = PL3_W, + .type = ARM_CP_NO_RAW | ARM_CP_NO_GDB | ARM_CP_ADD_TLBI_NXS, .writefn = tlbi_aa64_alle3is_write }, { .name = "TLBI_VAE3IS", .state = ARM_CP_STATE_AA64, .opc0 = 1, .opc1 = 6, .crn = 8, .crm = 3, .opc2 = 1, - .access = PL3_W, .type = ARM_CP_NO_RAW | ARM_CP_ADD_TLBI_NXS, + .access = PL3_W, + .type = ARM_CP_NO_RAW | ARM_CP_NO_GDB | ARM_CP_ADD_TLBI_NXS, .writefn = tlbi_aa64_vae3is_write }, { .name = "TLBI_VALE3IS", .state = ARM_CP_STATE_AA64, .opc0 = 1, .opc1 = 6, .crn = 8, .crm = 3, .opc2 = 5, - .access = PL3_W, .type = ARM_CP_NO_RAW | ARM_CP_ADD_TLBI_NXS, + .access = PL3_W, + .type = ARM_CP_NO_RAW | ARM_CP_NO_GDB | ARM_CP_ADD_TLBI_NXS, .writefn = tlbi_aa64_vae3is_write }, { .name = "TLBI_ALLE3", .state = ARM_CP_STATE_AA64, .opc0 = 1, .opc1 = 6, .crn = 8, .crm = 7, .opc2 = 0, - .access = PL3_W, .type = ARM_CP_NO_RAW | ARM_CP_ADD_TLBI_NXS, + .access = PL3_W, + .type = ARM_CP_NO_RAW | ARM_CP_NO_GDB | ARM_CP_ADD_TLBI_NXS, .writefn = tlbi_aa64_alle3_write }, { .name = "TLBI_VAE3", .state = ARM_CP_STATE_AA64, .opc0 = 1, .opc1 = 6, .crn = 8, .crm = 7, .opc2 = 1, - .access = PL3_W, .type = ARM_CP_NO_RAW | ARM_CP_ADD_TLBI_NXS, + .access = PL3_W, + .type = ARM_CP_NO_RAW | ARM_CP_NO_GDB | ARM_CP_ADD_TLBI_NXS, .writefn = tlbi_aa64_vae3_write }, { .name = "TLBI_VALE3", .state = ARM_CP_STATE_AA64, .opc0 = 1, .opc1 = 6, .crn = 8, .crm = 7, .opc2 = 5, - .access = PL3_W, .type = ARM_CP_NO_RAW | ARM_CP_ADD_TLBI_NXS, + .access = PL3_W, + .type = ARM_CP_NO_RAW | ARM_CP_NO_GDB | ARM_CP_ADD_TLBI_NXS, .writefn = tlbi_aa64_vae3_write }, }; @@ -1000,144 +1032,144 @@ static const ARMCPRegInfo tlbirange_reginfo[] = { { .name = "TLBI_RVAE1IS", .state = ARM_CP_STATE_AA64, .opc0 = 1, .opc1 = 0, .crn = 8, .crm = 2, .opc2 = 1, .access = PL1_W, .accessfn = access_ttlbis, - .type = ARM_CP_NO_RAW | ARM_CP_ADD_TLBI_NXS, + .type = ARM_CP_NO_RAW | ARM_CP_NO_GDB | ARM_CP_ADD_TLBI_NXS, .fgt = FGT_TLBIRVAE1IS, .writefn = tlbi_aa64_rvae1is_write }, { .name = "TLBI_RVAAE1IS", .state = ARM_CP_STATE_AA64, .opc0 = 1, .opc1 = 0, .crn = 8, .crm = 2, .opc2 = 3, .access = PL1_W, .accessfn = access_ttlbis, - .type = ARM_CP_NO_RAW | ARM_CP_ADD_TLBI_NXS, + .type = ARM_CP_NO_RAW | ARM_CP_NO_GDB | ARM_CP_ADD_TLBI_NXS, .fgt = FGT_TLBIRVAAE1IS, .writefn = tlbi_aa64_rvae1is_write }, { .name = "TLBI_RVALE1IS", .state = ARM_CP_STATE_AA64, .opc0 = 1, .opc1 = 0, .crn = 8, .crm = 2, .opc2 = 5, .access = PL1_W, .accessfn = access_ttlbis, - .type = ARM_CP_NO_RAW | ARM_CP_ADD_TLBI_NXS, + .type = ARM_CP_NO_RAW | ARM_CP_NO_GDB | ARM_CP_ADD_TLBI_NXS, .fgt = FGT_TLBIRVALE1IS, .writefn = tlbi_aa64_rvae1is_write }, { .name = "TLBI_RVAALE1IS", .state = ARM_CP_STATE_AA64, .opc0 = 1, .opc1 = 0, .crn = 8, .crm = 2, .opc2 = 7, .access = PL1_W, .accessfn = access_ttlbis, - .type = ARM_CP_NO_RAW | ARM_CP_ADD_TLBI_NXS, + .type = ARM_CP_NO_RAW | ARM_CP_NO_GDB | ARM_CP_ADD_TLBI_NXS, .fgt = FGT_TLBIRVAALE1IS, .writefn = tlbi_aa64_rvae1is_write }, { .name = "TLBI_RVAE1OS", .state = ARM_CP_STATE_AA64, .opc0 = 1, .opc1 = 0, .crn = 8, .crm = 5, .opc2 = 1, .access = PL1_W, .accessfn = access_ttlbos, - .type = ARM_CP_NO_RAW | ARM_CP_ADD_TLBI_NXS, + .type = ARM_CP_NO_RAW | ARM_CP_NO_GDB | ARM_CP_ADD_TLBI_NXS, .fgt = FGT_TLBIRVAE1OS, .writefn = tlbi_aa64_rvae1is_write }, { .name = "TLBI_RVAAE1OS", .state = ARM_CP_STATE_AA64, .opc0 = 1, .opc1 = 0, .crn = 8, .crm = 5, .opc2 = 3, .access = PL1_W, .accessfn = access_ttlbos, - .type = ARM_CP_NO_RAW | ARM_CP_ADD_TLBI_NXS, + .type = ARM_CP_NO_RAW | ARM_CP_NO_GDB | ARM_CP_ADD_TLBI_NXS, .fgt = FGT_TLBIRVAAE1OS, .writefn = tlbi_aa64_rvae1is_write }, { .name = "TLBI_RVALE1OS", .state = ARM_CP_STATE_AA64, .opc0 = 1, .opc1 = 0, .crn = 8, .crm = 5, .opc2 = 5, .access = PL1_W, .accessfn = access_ttlbos, - .type = ARM_CP_NO_RAW | ARM_CP_ADD_TLBI_NXS, + .type = ARM_CP_NO_RAW | ARM_CP_NO_GDB | ARM_CP_ADD_TLBI_NXS, .fgt = FGT_TLBIRVALE1OS, .writefn = tlbi_aa64_rvae1is_write }, { .name = "TLBI_RVAALE1OS", .state = ARM_CP_STATE_AA64, .opc0 = 1, .opc1 = 0, .crn = 8, .crm = 5, .opc2 = 7, .access = PL1_W, .accessfn = access_ttlbos, - .type = ARM_CP_NO_RAW | ARM_CP_ADD_TLBI_NXS, + .type = ARM_CP_NO_RAW | ARM_CP_NO_GDB | ARM_CP_ADD_TLBI_NXS, .fgt = FGT_TLBIRVAALE1OS, .writefn = tlbi_aa64_rvae1is_write }, { .name = "TLBI_RVAE1", .state = ARM_CP_STATE_AA64, .opc0 = 1, .opc1 = 0, .crn = 8, .crm = 6, .opc2 = 1, .access = PL1_W, .accessfn = access_ttlb, - .type = ARM_CP_NO_RAW | ARM_CP_ADD_TLBI_NXS, + .type = ARM_CP_NO_RAW | ARM_CP_NO_GDB | ARM_CP_ADD_TLBI_NXS, .fgt = FGT_TLBIRVAE1, .writefn = tlbi_aa64_rvae1_write }, { .name = "TLBI_RVAAE1", .state = ARM_CP_STATE_AA64, .opc0 = 1, .opc1 = 0, .crn = 8, .crm = 6, .opc2 = 3, .access = PL1_W, .accessfn = access_ttlb, - .type = ARM_CP_NO_RAW | ARM_CP_ADD_TLBI_NXS, + .type = ARM_CP_NO_RAW | ARM_CP_NO_GDB | ARM_CP_ADD_TLBI_NXS, .fgt = FGT_TLBIRVAAE1, .writefn = tlbi_aa64_rvae1_write }, { .name = "TLBI_RVALE1", .state = ARM_CP_STATE_AA64, .opc0 = 1, .opc1 = 0, .crn = 8, .crm = 6, .opc2 = 5, .access = PL1_W, .accessfn = access_ttlb, - .type = ARM_CP_NO_RAW | ARM_CP_ADD_TLBI_NXS, + .type = ARM_CP_NO_RAW | ARM_CP_NO_GDB | ARM_CP_ADD_TLBI_NXS, .fgt = FGT_TLBIRVALE1, .writefn = tlbi_aa64_rvae1_write }, { .name = "TLBI_RVAALE1", .state = ARM_CP_STATE_AA64, .opc0 = 1, .opc1 = 0, .crn = 8, .crm = 6, .opc2 = 7, .access = PL1_W, .accessfn = access_ttlb, - .type = ARM_CP_NO_RAW | ARM_CP_ADD_TLBI_NXS, + .type = ARM_CP_NO_RAW | ARM_CP_NO_GDB | ARM_CP_ADD_TLBI_NXS, .fgt = FGT_TLBIRVAALE1, .writefn = tlbi_aa64_rvae1_write }, { .name = "TLBI_RIPAS2E1IS", .state = ARM_CP_STATE_AA64, .opc0 = 1, .opc1 = 4, .crn = 8, .crm = 0, .opc2 = 2, - .access = PL2_W, .type = ARM_CP_NO_RAW | ARM_CP_ADD_TLBI_NXS, + .access = PL2_W, .type = ARM_CP_NO_RAW | ARM_CP_NO_GDB | ARM_CP_ADD_TLBI_NXS, .writefn = tlbi_aa64_ripas2e1is_write }, { .name = "TLBI_RIPAS2LE1IS", .state = ARM_CP_STATE_AA64, .opc0 = 1, .opc1 = 4, .crn = 8, .crm = 0, .opc2 = 6, - .access = PL2_W, .type = ARM_CP_NO_RAW | ARM_CP_ADD_TLBI_NXS, + .access = PL2_W, .type = ARM_CP_NO_RAW | ARM_CP_NO_GDB | ARM_CP_ADD_TLBI_NXS, .writefn = tlbi_aa64_ripas2e1is_write }, { .name = "TLBI_RVAE2IS", .state = ARM_CP_STATE_AA64, .opc0 = 1, .opc1 = 4, .crn = 8, .crm = 2, .opc2 = 1, .access = PL2_W, - .type = ARM_CP_NO_RAW | ARM_CP_ADD_TLBI_NXS | ARM_CP_EL3_NO_EL2_UNDEF, + .type = ARM_CP_NO_RAW | ARM_CP_NO_GDB | ARM_CP_ADD_TLBI_NXS | ARM_CP_EL3_NO_EL2_UNDEF, .writefn = tlbi_aa64_rvae2is_write }, { .name = "TLBI_RVALE2IS", .state = ARM_CP_STATE_AA64, .opc0 = 1, .opc1 = 4, .crn = 8, .crm = 2, .opc2 = 5, .access = PL2_W, - .type = ARM_CP_NO_RAW | ARM_CP_ADD_TLBI_NXS | ARM_CP_EL3_NO_EL2_UNDEF, + .type = ARM_CP_NO_RAW | ARM_CP_NO_GDB | ARM_CP_ADD_TLBI_NXS | ARM_CP_EL3_NO_EL2_UNDEF, .writefn = tlbi_aa64_rvae2is_write }, { .name = "TLBI_RIPAS2E1", .state = ARM_CP_STATE_AA64, .opc0 = 1, .opc1 = 4, .crn = 8, .crm = 4, .opc2 = 2, - .access = PL2_W, .type = ARM_CP_NO_RAW | ARM_CP_ADD_TLBI_NXS, + .access = PL2_W, .type = ARM_CP_NO_RAW | ARM_CP_NO_GDB | ARM_CP_ADD_TLBI_NXS, .writefn = tlbi_aa64_ripas2e1_write }, { .name = "TLBI_RIPAS2LE1", .state = ARM_CP_STATE_AA64, .opc0 = 1, .opc1 = 4, .crn = 8, .crm = 4, .opc2 = 6, - .access = PL2_W, .type = ARM_CP_NO_RAW | ARM_CP_ADD_TLBI_NXS, + .access = PL2_W, .type = ARM_CP_NO_RAW | ARM_CP_NO_GDB | ARM_CP_ADD_TLBI_NXS, .writefn = tlbi_aa64_ripas2e1_write }, { .name = "TLBI_RVAE2OS", .state = ARM_CP_STATE_AA64, .opc0 = 1, .opc1 = 4, .crn = 8, .crm = 5, .opc2 = 1, .access = PL2_W, - .type = ARM_CP_NO_RAW | ARM_CP_ADD_TLBI_NXS | ARM_CP_EL3_NO_EL2_UNDEF, + .type = ARM_CP_NO_RAW | ARM_CP_NO_GDB | ARM_CP_ADD_TLBI_NXS | ARM_CP_EL3_NO_EL2_UNDEF, .writefn = tlbi_aa64_rvae2is_write }, { .name = "TLBI_RVALE2OS", .state = ARM_CP_STATE_AA64, .opc0 = 1, .opc1 = 4, .crn = 8, .crm = 5, .opc2 = 5, .access = PL2_W, - .type = ARM_CP_NO_RAW | ARM_CP_ADD_TLBI_NXS | ARM_CP_EL3_NO_EL2_UNDEF, + .type = ARM_CP_NO_RAW | ARM_CP_NO_GDB | ARM_CP_ADD_TLBI_NXS | ARM_CP_EL3_NO_EL2_UNDEF, .writefn = tlbi_aa64_rvae2is_write }, { .name = "TLBI_RVAE2", .state = ARM_CP_STATE_AA64, .opc0 = 1, .opc1 = 4, .crn = 8, .crm = 6, .opc2 = 1, .access = PL2_W, - .type = ARM_CP_NO_RAW | ARM_CP_ADD_TLBI_NXS | ARM_CP_EL3_NO_EL2_UNDEF, + .type = ARM_CP_NO_RAW | ARM_CP_NO_GDB | ARM_CP_ADD_TLBI_NXS | ARM_CP_EL3_NO_EL2_UNDEF, .writefn = tlbi_aa64_rvae2_write }, { .name = "TLBI_RVALE2", .state = ARM_CP_STATE_AA64, .opc0 = 1, .opc1 = 4, .crn = 8, .crm = 6, .opc2 = 5, .access = PL2_W, - .type = ARM_CP_NO_RAW | ARM_CP_ADD_TLBI_NXS | ARM_CP_EL3_NO_EL2_UNDEF, + .type = ARM_CP_NO_RAW | ARM_CP_NO_GDB | ARM_CP_ADD_TLBI_NXS | ARM_CP_EL3_NO_EL2_UNDEF, .writefn = tlbi_aa64_rvae2_write }, { .name = "TLBI_RVAE3IS", .state = ARM_CP_STATE_AA64, .opc0 = 1, .opc1 = 6, .crn = 8, .crm = 2, .opc2 = 1, - .access = PL3_W, .type = ARM_CP_NO_RAW | ARM_CP_ADD_TLBI_NXS, + .access = PL3_W, .type = ARM_CP_NO_RAW | ARM_CP_NO_GDB | ARM_CP_ADD_TLBI_NXS, .writefn = tlbi_aa64_rvae3is_write }, { .name = "TLBI_RVALE3IS", .state = ARM_CP_STATE_AA64, .opc0 = 1, .opc1 = 6, .crn = 8, .crm = 2, .opc2 = 5, - .access = PL3_W, .type = ARM_CP_NO_RAW | ARM_CP_ADD_TLBI_NXS, + .access = PL3_W, .type = ARM_CP_NO_RAW | ARM_CP_NO_GDB | ARM_CP_ADD_TLBI_NXS, .writefn = tlbi_aa64_rvae3is_write }, { .name = "TLBI_RVAE3OS", .state = ARM_CP_STATE_AA64, .opc0 = 1, .opc1 = 6, .crn = 8, .crm = 5, .opc2 = 1, - .access = PL3_W, .type = ARM_CP_NO_RAW | ARM_CP_ADD_TLBI_NXS, + .access = PL3_W, .type = ARM_CP_NO_RAW | ARM_CP_NO_GDB | ARM_CP_ADD_TLBI_NXS, .writefn = tlbi_aa64_rvae3is_write }, { .name = "TLBI_RVALE3OS", .state = ARM_CP_STATE_AA64, .opc0 = 1, .opc1 = 6, .crn = 8, .crm = 5, .opc2 = 5, - .access = PL3_W, .type = ARM_CP_NO_RAW | ARM_CP_ADD_TLBI_NXS, + .access = PL3_W, .type = ARM_CP_NO_RAW | ARM_CP_NO_GDB | ARM_CP_ADD_TLBI_NXS, .writefn = tlbi_aa64_rvae3is_write }, { .name = "TLBI_RVAE3", .state = ARM_CP_STATE_AA64, .opc0 = 1, .opc1 = 6, .crn = 8, .crm = 6, .opc2 = 1, - .access = PL3_W, .type = ARM_CP_NO_RAW | ARM_CP_ADD_TLBI_NXS, + .access = PL3_W, .type = ARM_CP_NO_RAW | ARM_CP_NO_GDB | ARM_CP_ADD_TLBI_NXS, .writefn = tlbi_aa64_rvae3_write }, { .name = "TLBI_RVALE3", .state = ARM_CP_STATE_AA64, .opc0 = 1, .opc1 = 6, .crn = 8, .crm = 6, .opc2 = 5, - .access = PL3_W, .type = ARM_CP_NO_RAW | ARM_CP_ADD_TLBI_NXS, + .access = PL3_W, .type = ARM_CP_NO_RAW | ARM_CP_NO_GDB | ARM_CP_ADD_TLBI_NXS, .writefn = tlbi_aa64_rvae3_write }, }; @@ -1145,62 +1177,62 @@ static const ARMCPRegInfo tlbios_reginfo[] = { { .name = "TLBI_VMALLE1OS", .state = ARM_CP_STATE_AA64, .opc0 = 1, .opc1 = 0, .crn = 8, .crm = 1, .opc2 = 0, .access = PL1_W, .accessfn = access_ttlbos, - .type = ARM_CP_NO_RAW | ARM_CP_ADD_TLBI_NXS, + .type = ARM_CP_NO_RAW | ARM_CP_NO_GDB | ARM_CP_ADD_TLBI_NXS, .fgt = FGT_TLBIVMALLE1OS, .writefn = tlbi_aa64_vmalle1is_write }, { .name = "TLBI_VAE1OS", .state = ARM_CP_STATE_AA64, .opc0 = 1, .opc1 = 0, .crn = 8, .crm = 1, .opc2 = 1, .fgt = FGT_TLBIVAE1OS, .access = PL1_W, .accessfn = access_ttlbos, - .type = ARM_CP_NO_RAW | ARM_CP_ADD_TLBI_NXS, + .type = ARM_CP_NO_RAW | ARM_CP_NO_GDB | ARM_CP_ADD_TLBI_NXS, .writefn = tlbi_aa64_vae1is_write }, { .name = "TLBI_ASIDE1OS", .state = ARM_CP_STATE_AA64, .opc0 = 1, .opc1 = 0, .crn = 8, .crm = 1, .opc2 = 2, .access = PL1_W, .accessfn = access_ttlbos, - .type = ARM_CP_NO_RAW | ARM_CP_ADD_TLBI_NXS, + .type = ARM_CP_NO_RAW | ARM_CP_NO_GDB | ARM_CP_ADD_TLBI_NXS, .fgt = FGT_TLBIASIDE1OS, .writefn = tlbi_aa64_vmalle1is_write }, { .name = "TLBI_VAAE1OS", .state = ARM_CP_STATE_AA64, .opc0 = 1, .opc1 = 0, .crn = 8, .crm = 1, .opc2 = 3, .access = PL1_W, .accessfn = access_ttlbos, - .type = ARM_CP_NO_RAW | ARM_CP_ADD_TLBI_NXS, + .type = ARM_CP_NO_RAW | ARM_CP_NO_GDB | ARM_CP_ADD_TLBI_NXS, .fgt = FGT_TLBIVAAE1OS, .writefn = tlbi_aa64_vae1is_write }, { .name = "TLBI_VALE1OS", .state = ARM_CP_STATE_AA64, .opc0 = 1, .opc1 = 0, .crn = 8, .crm = 1, .opc2 = 5, .access = PL1_W, .accessfn = access_ttlbos, - .type = ARM_CP_NO_RAW | ARM_CP_ADD_TLBI_NXS, + .type = ARM_CP_NO_RAW | ARM_CP_NO_GDB | ARM_CP_ADD_TLBI_NXS, .fgt = FGT_TLBIVALE1OS, .writefn = tlbi_aa64_vae1is_write }, { .name = "TLBI_VAALE1OS", .state = ARM_CP_STATE_AA64, .opc0 = 1, .opc1 = 0, .crn = 8, .crm = 1, .opc2 = 7, .access = PL1_W, .accessfn = access_ttlbos, - .type = ARM_CP_NO_RAW | ARM_CP_ADD_TLBI_NXS, + .type = ARM_CP_NO_RAW | ARM_CP_NO_GDB | ARM_CP_ADD_TLBI_NXS, .fgt = FGT_TLBIVAALE1OS, .writefn = tlbi_aa64_vae1is_write }, { .name = "TLBI_ALLE2OS", .state = ARM_CP_STATE_AA64, .opc0 = 1, .opc1 = 4, .crn = 8, .crm = 1, .opc2 = 0, .access = PL2_W, - .type = ARM_CP_NO_RAW | ARM_CP_ADD_TLBI_NXS | ARM_CP_EL3_NO_EL2_UNDEF, + .type = ARM_CP_NO_RAW | ARM_CP_NO_GDB | ARM_CP_ADD_TLBI_NXS | ARM_CP_EL3_NO_EL2_UNDEF, .writefn = tlbi_aa64_alle2is_write }, { .name = "TLBI_VAE2OS", .state = ARM_CP_STATE_AA64, .opc0 = 1, .opc1 = 4, .crn = 8, .crm = 1, .opc2 = 1, .access = PL2_W, - .type = ARM_CP_NO_RAW | ARM_CP_ADD_TLBI_NXS | ARM_CP_EL3_NO_EL2_UNDEF, + .type = ARM_CP_NO_RAW | ARM_CP_NO_GDB | ARM_CP_ADD_TLBI_NXS | ARM_CP_EL3_NO_EL2_UNDEF, .writefn = tlbi_aa64_vae2is_write }, { .name = "TLBI_ALLE1OS", .state = ARM_CP_STATE_AA64, .opc0 = 1, .opc1 = 4, .crn = 8, .crm = 1, .opc2 = 4, .access = PL2_W, - .type = ARM_CP_NO_RAW | ARM_CP_ADD_TLBI_NXS, + .type = ARM_CP_NO_RAW | ARM_CP_NO_GDB | ARM_CP_ADD_TLBI_NXS, .writefn = tlbi_aa64_alle1is_write }, { .name = "TLBI_VALE2OS", .state = ARM_CP_STATE_AA64, .opc0 = 1, .opc1 = 4, .crn = 8, .crm = 1, .opc2 = 5, .access = PL2_W, - .type = ARM_CP_NO_RAW | ARM_CP_ADD_TLBI_NXS | ARM_CP_EL3_NO_EL2_UNDEF, + .type = ARM_CP_NO_RAW | ARM_CP_NO_GDB | ARM_CP_ADD_TLBI_NXS | ARM_CP_EL3_NO_EL2_UNDEF, .writefn = tlbi_aa64_vae2is_write }, { .name = "TLBI_VMALLS12E1OS", .state = ARM_CP_STATE_AA64, .opc0 = 1, .opc1 = 4, .crn = 8, .crm = 1, .opc2 = 6, - .access = PL2_W, .type = ARM_CP_NO_RAW | ARM_CP_ADD_TLBI_NXS, + .access = PL2_W, .type = ARM_CP_NO_RAW | ARM_CP_NO_GDB | ARM_CP_ADD_TLBI_NXS, .writefn = tlbi_aa64_alle1is_write }, { .name = "TLBI_IPAS2E1OS", .state = ARM_CP_STATE_AA64, .opc0 = 1, .opc1 = 4, .crn = 8, .crm = 4, .opc2 = 0, @@ -1216,15 +1248,15 @@ static const ARMCPRegInfo tlbios_reginfo[] = { .access = PL2_W, .type = ARM_CP_NOP | ARM_CP_ADD_TLBI_NXS }, { .name = "TLBI_ALLE3OS", .state = ARM_CP_STATE_AA64, .opc0 = 1, .opc1 = 6, .crn = 8, .crm = 1, .opc2 = 0, - .access = PL3_W, .type = ARM_CP_NO_RAW | ARM_CP_ADD_TLBI_NXS, + .access = PL3_W, .type = ARM_CP_NO_RAW | ARM_CP_NO_GDB | ARM_CP_ADD_TLBI_NXS, .writefn = tlbi_aa64_alle3is_write }, { .name = "TLBI_VAE3OS", .state = ARM_CP_STATE_AA64, .opc0 = 1, .opc1 = 6, .crn = 8, .crm = 1, .opc2 = 1, - .access = PL3_W, .type = ARM_CP_NO_RAW | ARM_CP_ADD_TLBI_NXS, + .access = PL3_W, .type = ARM_CP_NO_RAW | ARM_CP_NO_GDB | ARM_CP_ADD_TLBI_NXS, .writefn = tlbi_aa64_vae3is_write }, { .name = "TLBI_VALE3OS", .state = ARM_CP_STATE_AA64, .opc0 = 1, .opc1 = 6, .crn = 8, .crm = 1, .opc2 = 5, - .access = PL3_W, .type = ARM_CP_NO_RAW | ARM_CP_ADD_TLBI_NXS, + .access = PL3_W, .type = ARM_CP_NO_RAW | ARM_CP_NO_GDB | ARM_CP_ADD_TLBI_NXS, .writefn = tlbi_aa64_vae3is_write }, }; @@ -1247,11 +1279,11 @@ static void tlbi_aa64_paallos_write(CPUARMState *env, const ARMCPRegInfo *ri, static const ARMCPRegInfo tlbi_rme_reginfo[] = { { .name = "TLBI_PAALL", .state = ARM_CP_STATE_AA64, .opc0 = 1, .opc1 = 6, .crn = 8, .crm = 7, .opc2 = 4, - .access = PL3_W, .type = ARM_CP_NO_RAW, + .access = PL3_W, .type = ARM_CP_NO_RAW | ARM_CP_NO_GDB, .writefn = tlbi_aa64_paall_write }, { .name = "TLBI_PAALLOS", .state = ARM_CP_STATE_AA64, .opc0 = 1, .opc1 = 6, .crn = 8, .crm = 1, .opc2 = 4, - .access = PL3_W, .type = ARM_CP_NO_RAW, + .access = PL3_W, .type = ARM_CP_NO_RAW | ARM_CP_NO_GDB, .writefn = tlbi_aa64_paallos_write }, /* * QEMU does not have a way to invalidate by physical address, thus @@ -1261,11 +1293,11 @@ static const ARMCPRegInfo tlbi_rme_reginfo[] = { */ { .name = "TLBI_RPALOS", .state = ARM_CP_STATE_AA64, .opc0 = 1, .opc1 = 6, .crn = 8, .crm = 4, .opc2 = 7, - .access = PL3_W, .type = ARM_CP_NO_RAW, + .access = PL3_W, .type = ARM_CP_NO_RAW | ARM_CP_NO_GDB, .writefn = tlbi_aa64_paallos_write }, { .name = "TLBI_RPAOS", .state = ARM_CP_STATE_AA64, .opc0 = 1, .opc1 = 6, .crn = 8, .crm = 4, .opc2 = 3, - .access = PL3_W, .type = ARM_CP_NO_RAW, + .access = PL3_W, .type = ARM_CP_NO_RAW | ARM_CP_NO_GDB, .writefn = tlbi_aa64_paallos_write }, }; From patchwork Mon Mar 17 11:16:23 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Akihiko Odaki X-Patchwork-Id: 14018983 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 0CC93C28B28 for ; Mon, 17 Mar 2025 11:18:31 +0000 (UTC) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1tu8Si-0003H9-N7; Mon, 17 Mar 2025 07:16:52 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1tu8SZ-0003Dj-OB for qemu-devel@nongnu.org; Mon, 17 Mar 2025 07:16:43 -0400 Received: from mail-pl1-x629.google.com ([2607:f8b0:4864:20::629]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1tu8SV-0003lA-JE for qemu-devel@nongnu.org; Mon, 17 Mar 2025 07:16:43 -0400 Received: by mail-pl1-x629.google.com with SMTP id d9443c01a7336-223a7065ff8so33441085ad.0 for ; Mon, 17 Mar 2025 04:16:38 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=daynix-com.20230601.gappssmtp.com; s=20230601; t=1742210198; x=1742814998; darn=nongnu.org; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:from:to:cc:subject:date:message-id :reply-to; bh=nvZxXJ1GvFvx4INbCk9ERB4VBpXlB9W+lCDR6eWj6sU=; b=H+T2cYL7X13cQy/ILr0gZ4ommCJzEMgEryES6tKL7Dn+OizwwbEv8Ms6JolnzPF5O/ 6oIBNlydBU2i9RtDRyrs1DVEOp4nXa/kqiFk0MnvvrEXNl+YuwWmSpF66mIbsl2FD+af G5SRolE4add1EYVN8Z8kZhXW3Ebvi8hYY+lmm8gvS5IIhcr2axdZt5M1j09ZqSU7BEby FXY/1dLT4CVcE9lUVfZ6Ea0mT6sABXQkqRu/ugf7qEkn96kF1qEy7v7zqj0GpACY79I5 FGjswFqhYyqPBPiZG1AJYPwdwVb1JtrybxJgB9SaDF7mDJglWSz/xdhXPC7CQZIaZM7o 7/rA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1742210198; x=1742814998; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=nvZxXJ1GvFvx4INbCk9ERB4VBpXlB9W+lCDR6eWj6sU=; b=j9+fEhFHTBIGmSmZXfwlsNHeO9i5Rega+eYhkONzdL5aPFX97wK69au+QLNHxu4U8D f67OJsKCh9bru7xye76sxhnbAqHQ3w9iOZZxTmhbYW0Ti00s5LqEFhy+VL7WuHsfnGe5 c6/IYBavt71FnPH2Lar+WLUWV2qFuprHO+bI+u1ABJM2o0G9mj/Y8/yKrXJTy2oIJ5C8 SvSmH9KNvC5pY/o3/6j7Jzo6Lm6bPw1bh9XAJ7Or+hUj67fhpX78PuabEXTuz1TedXr6 z5/lnFYtDSvaMAuczvatt199b+iOBwujL3PcUsWka/IP1PqG1lrxMTkb+PnWJsxGKySc RQ0A== X-Gm-Message-State: AOJu0YxIxfi8WGNcojQoxF3vefxSM56oLWowCYjcDq8Wdrr7kToHs1Hc gi1M+UUeBMDs2xD7YKNDehTfxu/CHmLkJgadzB3Qt+/IHHKu5LWhJHgxD906rC0= X-Gm-Gg: ASbGncsbYHAZUeHYd/gvYJYkokxid5AW5yIR4mtPDpHq0J6YaXAGmeLEYT0wbD7YQ4K Vua3g1cw7MBPJ45GCoB0hP8G91anIKQh5kuwZCA37ENiod+Rz8gyHLWXNb/osSXfoOKoLm+Mhz9 FguK85W/rQj3BRBM4GBBGQeUtPzgD2PdgEcV6Nhj4VxEIH/UbOlb0lL3qSQZEU37SIUxxad+R70 SFaU1eXX6t5Mf28Z5FtyCahTt+Ax5i8EYoK2rdT8OGaJr1CA7gaPLzVmVQb9kQ+Zy5o8Hz4b1Xg r9dbnObE07xOQ114zF4Uj6WrrX1EYti0u/Ae2o3y2bBCePfE X-Google-Smtp-Source: AGHT+IEVqDXHHFE6x727TS/DtRWBMYY1HDZ/XgkQyqYFQrWK4neiNqcXxXDVqi8EhX3DeUmi9s6WUQ== X-Received: by 2002:a05:6a00:4f82:b0:736:3d7c:236c with SMTP id d2e1a72fcca58-737223b9711mr13501161b3a.14.1742210197806; Mon, 17 Mar 2025 04:16:37 -0700 (PDT) Received: from localhost ([157.82.207.107]) by smtp.gmail.com with UTF8SMTPSA id d2e1a72fcca58-73711694430sm7254565b3a.122.2025.03.17.04.16.36 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Mon, 17 Mar 2025 04:16:37 -0700 (PDT) From: Akihiko Odaki Date: Mon, 17 Mar 2025 20:16:23 +0900 Subject: [PATCH 2/4] target/arm: Do not imply ARM_CP_NO_GDB MIME-Version: 1.0 Message-Id: <20250317-raw-v1-2-09e2dfff0e90@daynix.com> References: <20250317-raw-v1-0-09e2dfff0e90@daynix.com> In-Reply-To: <20250317-raw-v1-0-09e2dfff0e90@daynix.com> To: qemu-devel@nongnu.org Cc: Peter Maydell , qemu-arm@nongnu.org, devel@daynix.com, Akihiko Odaki X-Mailer: b4 0.15-dev-edae6 Received-SPF: pass client-ip=2607:f8b0:4864:20::629; envelope-from=akihiko.odaki@daynix.com; helo=mail-pl1-x629.google.com X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Do not imply ARM_CP_NO_GDB when ARM_CP_NO_RAW. A register without raw access support may still expose some state to GDB that is managed by something else. A register may its state with another register but may not be used for either migration or KVM state synchronization. For example, a multiplexing register cannot support raw access. KVM may also have a problem when synchronizing a register. Such a register can be flagged with ARM_CP_ALIAS | ARM_CP_NO_RAW, but its value can be still exposed to GDB as it's usually the case for registers flagged with ARM_CP_ALIAS. ARM_CP_NO_GDB should not be implied in this case. Signed-off-by: Akihiko Odaki --- target/arm/cpregs.h | 8 ++++---- target/arm/gdbstub.c | 2 +- 2 files changed, 5 insertions(+), 5 deletions(-) diff --git a/target/arm/cpregs.h b/target/arm/cpregs.h index 52377c6eb50f..99e2afc84250 100644 --- a/target/arm/cpregs.h +++ b/target/arm/cpregs.h @@ -75,10 +75,10 @@ enum { */ ARM_CP_IO = 1 << 9, /* - * Flag: Register has no underlying state and does not support raw access - * for state saving/loading; it will not be used for either migration or - * KVM state synchronization. Typically this is for "registers" which are - * actually used as instructions for cache maintenance and so on. + * Flag: Register does not support raw access for state saving/loading; it + * will not be used for either migration or KVM state synchronization. + * Typically this is for "registers" which are actually used as instructions + * for cache maintenance and so on. */ ARM_CP_NO_RAW = 1 << 10, /* diff --git a/target/arm/gdbstub.c b/target/arm/gdbstub.c index 30068c226273..4459e90811b8 100644 --- a/target/arm/gdbstub.c +++ b/target/arm/gdbstub.c @@ -270,7 +270,7 @@ static void arm_register_sysreg_for_feature(gpointer key, gpointer value, CPUARMState *env = &cpu->env; DynamicGDBFeatureInfo *dyn_feature = &cpu->dyn_sysreg_feature; - if (!(ri->type & (ARM_CP_NO_RAW | ARM_CP_NO_GDB))) { + if (!(ri->type & ARM_CP_NO_GDB)) { if (arm_feature(env, ARM_FEATURE_AARCH64)) { if (ri->state == ARM_CP_STATE_AA64) { arm_gen_one_feature_sysreg(¶m->builder, dyn_feature, From patchwork Mon Mar 17 11:16:24 2025 Content-Type: text/plain; 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Expose them as we do for other alias registers. Signed-off-by: Akihiko Odaki --- target/arm/helper.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/target/arm/helper.c b/target/arm/helper.c index 5ce468ac2693..2dd8f4d56a1e 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -2025,14 +2025,14 @@ static const ARMCPRegInfo v7_cp_reginfo[] = { { .name = "PMINTENCLR", .cp = 15, .crn = 9, .crm = 14, .opc1 = 0, .opc2 = 2, .access = PL1_RW, .accessfn = access_tpm, .fgt = FGT_PMINTEN, - .type = ARM_CP_ALIAS | ARM_CP_IO | ARM_CP_NO_RAW | ARM_CP_NO_GDB, + .type = ARM_CP_ALIAS | ARM_CP_IO | ARM_CP_NO_RAW, .fieldoffset = offsetof(CPUARMState, cp15.c9_pminten), .writefn = pmintenclr_write, }, { .name = "PMINTENCLR_EL1", .state = ARM_CP_STATE_AA64, .opc0 = 3, .opc1 = 0, .crn = 9, .crm = 14, .opc2 = 2, .access = PL1_RW, .accessfn = access_tpm, .fgt = FGT_PMINTEN, - .type = ARM_CP_ALIAS | ARM_CP_IO | ARM_CP_NO_RAW | ARM_CP_NO_GDB, + .type = ARM_CP_ALIAS | ARM_CP_IO | ARM_CP_NO_RAW, .fieldoffset = offsetof(CPUARMState, cp15.c9_pminten), .writefn = pmintenclr_write }, { .name = "CCSIDR", .state = ARM_CP_STATE_BOTH, From patchwork Mon Mar 17 11:16:25 2025 Content-Type: text/plain; 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Mon, 17 Mar 2025 04:16:44 -0700 (PDT) Received: from localhost ([157.82.207.107]) by smtp.gmail.com with UTF8SMTPSA id d9443c01a7336-225c6bd4d6csm72288065ad.238.2025.03.17.04.16.43 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Mon, 17 Mar 2025 04:16:44 -0700 (PDT) From: Akihiko Odaki Date: Mon, 17 Mar 2025 20:16:25 +0900 Subject: [PATCH 4/4] target/arm: Flag PMCNTENCLR with ARM_CP_NO_RAW MIME-Version: 1.0 Message-Id: <20250317-raw-v1-4-09e2dfff0e90@daynix.com> References: <20250317-raw-v1-0-09e2dfff0e90@daynix.com> In-Reply-To: <20250317-raw-v1-0-09e2dfff0e90@daynix.com> To: qemu-devel@nongnu.org Cc: Peter Maydell , qemu-arm@nongnu.org, devel@daynix.com, Akihiko Odaki X-Mailer: b4 0.15-dev-edae6 Received-SPF: pass client-ip=2607:f8b0:4864:20::62d; envelope-from=akihiko.odaki@daynix.com; helo=mail-pl1-x62d.google.com X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org A normal write to PMCNTENCLR clears written bits so it is not appropriate for writing a raw value. This kind of situation is usually handled by setting a raw write function, but flag the register with ARM_CP_NO_RAW instead to workaround a problem with KVM. KVM also has the same problem with PMINTENSET so add a comment to note that. This register is already flagged with ARM_CP_NO_RAW. Signed-off-by: Akihiko Odaki --- target/arm/helper.c | 14 ++++++++++++-- 1 file changed, 12 insertions(+), 2 deletions(-) diff --git a/target/arm/helper.c b/target/arm/helper.c index 2dd8f4d56a1e..ee15132aadea 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -1901,12 +1901,21 @@ static const ARMCPRegInfo v7_cp_reginfo[] = { .accessfn = pmreg_access, .fgt = FGT_PMCNTEN, .writefn = pmcntenclr_write, - .type = ARM_CP_ALIAS | ARM_CP_IO }, + /* + * Flag PMCNTENCLR with ARM_CP_NO_RAW instead of implementing raw + * access to workaround a problem with KVM; KVM applies bit operations + * that prevents writing back raw values since Linux 6.7: + * https://web.git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/commit/?id=a45f41d754e0b37de4b7dc1fb3c6b7a1285882fc + * + * It is fine to lack raw access with PMCNTENCLR because KVM still + * exposes PMCNTENSET, which shares the underlying state. + */ + .type = ARM_CP_ALIAS | ARM_CP_IO | ARM_CP_NO_RAW }, { .name = "PMCNTENCLR_EL0", .state = ARM_CP_STATE_AA64, .opc0 = 3, .opc1 = 3, .crn = 9, .crm = 12, .opc2 = 2, .access = PL0_RW, .accessfn = pmreg_access, .fgt = FGT_PMCNTEN, - .type = ARM_CP_ALIAS | ARM_CP_IO, + .type = ARM_CP_ALIAS | ARM_CP_IO | ARM_CP_NO_RAW, .fieldoffset = offsetof(CPUARMState, cp15.c9_pmcnten), .writefn = pmcntenclr_write }, { .name = "PMOVSR", .cp = 15, .crn = 9, .crm = 12, .opc1 = 0, .opc2 = 3, @@ -2025,6 +2034,7 @@ static const ARMCPRegInfo v7_cp_reginfo[] = { { .name = "PMINTENCLR", .cp = 15, .crn = 9, .crm = 14, .opc1 = 0, .opc2 = 2, .access = PL1_RW, .accessfn = access_tpm, .fgt = FGT_PMINTEN, + /* Flag PMINTENCLR with ARM_CP_NO_RAW, as with PMCNTENCLR. */ .type = ARM_CP_ALIAS | ARM_CP_IO | ARM_CP_NO_RAW, .fieldoffset = offsetof(CPUARMState, cp15.c9_pminten), .writefn = pmintenclr_write, },