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[2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-43d1fe60ad4sm107914985e9.29.2025.03.17.07.28.21 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 17 Mar 2025 07:28:21 -0700 (PDT) From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Subject: [PATCH for-10.1 1/9] core/cpu.h: gdb_arch_name string should not be freed Date: Mon, 17 Mar 2025 14:28:11 +0000 Message-ID: <20250317142819.900029-2-peter.maydell@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250317142819.900029-1-peter.maydell@linaro.org> References: <20250317142819.900029-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::329; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x329.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org The documentation for the CPUClass::gdb_arch_name method claims that the returned string should be freed with g_free(). This is not correct: in commit a650683871ba728 we changed this method to instead return a simple constant string, but forgot to update the documentation. Make the documentation match the new semantics. Fixes: a650683871ba728 ("hw/core/cpu: Return static value with gdb_arch_name()") Signed-off-by: Peter Maydell Reviewed-by: Alex Bennée Reviewed-by: Philippe Mathieu-Daudé --- include/hw/core/cpu.h | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/include/hw/core/cpu.h b/include/hw/core/cpu.h index 5d11d26556a..5873ee5998f 100644 --- a/include/hw/core/cpu.h +++ b/include/hw/core/cpu.h @@ -135,7 +135,8 @@ struct SysemuCPUOps; * @gdb_stop_before_watchpoint: Indicates whether GDB expects the CPU to stop * before the insn which triggers a watchpoint rather than after it. * @gdb_arch_name: Optional callback that returns the architecture name known - * to GDB. The caller must free the returned string with g_free. + * to GDB. The returned value is expected to be a simple constant string: + * the caller will not g_free() it. * @disas_set_info: Setup architecture specific components of disassembly info * @adjust_watchpoint_address: Perform a target-specific adjustment to an * address before attempting to match it against watchpoints. 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[2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-43d1fe60ad4sm107914985e9.29.2025.03.17.07.28.22 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 17 Mar 2025 07:28:22 -0700 (PDT) From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Subject: [PATCH for-10.1 2/9] gdbstub: Allow gdb_core_xml_file to be set at runtime Date: Mon, 17 Mar 2025 14:28:12 +0000 Message-ID: <20250317142819.900029-3-peter.maydell@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250317142819.900029-1-peter.maydell@linaro.org> References: <20250317142819.900029-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::32b; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x32b.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Currently the CPUClass:gdb_core_xml_file setting is a simple 'const char *' which the CPU class must set to a fixed string. Allow the CPU class to instead set a new method gdb_get_core_xml_file() which returns this string. This will allow Arm CPUs to use different XML files for AArch32 vs AArch64 without having to have an extra AArch64-specific class type purely to give somewhere to set cc->gdb_core_xml_file differently. Signed-off-by: Peter Maydell Acked-by: Alex Bennée --- include/hw/core/cpu.h | 5 +++++ gdbstub/gdbstub.c | 23 +++++++++++++++++++---- 2 files changed, 24 insertions(+), 4 deletions(-) diff --git a/include/hw/core/cpu.h b/include/hw/core/cpu.h index 5873ee5998f..140d8a0bd79 100644 --- a/include/hw/core/cpu.h +++ b/include/hw/core/cpu.h @@ -132,6 +132,10 @@ struct SysemuCPUOps; * @gdb_num_core_regs: Number of core registers accessible to GDB or 0 to infer * from @gdb_core_xml_file. * @gdb_core_xml_file: File name for core registers GDB XML description. + * @gdb_get_core_xml_file: Optional callback that returns the file name for + * the core registers GDB XML description. The returned value is expected to + * be a simple constant string: the caller will not g_free() it. If this + * is NULL then @gdb_core_xml_file will be used instead. * @gdb_stop_before_watchpoint: Indicates whether GDB expects the CPU to stop * before the insn which triggers a watchpoint rather than after it. * @gdb_arch_name: Optional callback that returns the architecture name known @@ -167,6 +171,7 @@ struct CPUClass { const char *gdb_core_xml_file; const gchar * (*gdb_arch_name)(CPUState *cpu); + const char * (*gdb_get_core_xml_file)(CPUState *cpu); void (*disas_set_info)(CPUState *cpu, disassemble_info *info); diff --git a/gdbstub/gdbstub.c b/gdbstub/gdbstub.c index 282e13e163f..565f6b33a90 100644 --- a/gdbstub/gdbstub.c +++ b/gdbstub/gdbstub.c @@ -565,15 +565,30 @@ static void gdb_register_feature(CPUState *cpu, int base_reg, g_array_append_val(cpu->gdb_regs, s); } +static const char *gdb_get_core_xml_file(CPUState *cpu) +{ + CPUClass *cc = cpu->cc; + + /* + * The CPU class can provide the XML filename via a method, + * or as a simple fixed string field. + */ + if (cc->gdb_get_core_xml_file) { + return cc->gdb_get_core_xml_file(cpu); + } + return cc->gdb_core_xml_file; +} + void gdb_init_cpu(CPUState *cpu) { CPUClass *cc = cpu->cc; const GDBFeature *feature; + const char *xmlfile = gdb_get_core_xml_file(cpu); cpu->gdb_regs = g_array_new(false, false, sizeof(GDBRegisterState)); - if (cc->gdb_core_xml_file) { - feature = gdb_find_static_feature(cc->gdb_core_xml_file); + if (xmlfile) { + feature = gdb_find_static_feature(xmlfile); gdb_register_feature(cpu, 0, cc->gdb_read_register, cc->gdb_write_register, feature); @@ -1644,7 +1659,7 @@ void gdb_extend_qsupported_features(char *qflags) static void handle_query_supported(GArray *params, void *user_ctx) { g_string_printf(gdbserver_state.str_buf, "PacketSize=%x", MAX_PACKET_LENGTH); - if (first_cpu->cc->gdb_core_xml_file) { + if (gdb_get_core_xml_file(first_cpu)) { g_string_append(gdbserver_state.str_buf, ";qXfer:features:read+"); } @@ -1701,7 +1716,7 @@ static void handle_query_xfer_features(GArray *params, void *user_ctx) } process = gdb_get_cpu_process(gdbserver_state.g_cpu); - if (!gdbserver_state.g_cpu->cc->gdb_core_xml_file) { + if (!gdb_get_core_xml_file(gdbserver_state.g_cpu)) { gdb_put_packet(""); return; } From patchwork Mon Mar 17 14:28:13 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 14019397 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 26F52C35FF3 for ; Mon, 17 Mar 2025 14:31:16 +0000 (UTC) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1tuBSK-0000hJ-1r; Mon, 17 Mar 2025 10:28:40 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1tuBS8-0000Zk-NV for qemu-devel@nongnu.org; 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[2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-43d1fe60ad4sm107914985e9.29.2025.03.17.07.28.23 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 17 Mar 2025 07:28:23 -0700 (PDT) From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Subject: [PATCH for-10.1 3/9] target/arm: Handle AArch64 in TYPE_ARM_CPU gdb_arch_name Date: Mon, 17 Mar 2025 14:28:13 +0000 Message-ID: <20250317142819.900029-4-peter.maydell@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250317142819.900029-1-peter.maydell@linaro.org> References: <20250317142819.900029-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::335; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x335.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Instead of having the TYPE_AARCH64_CPU subclass set CPUClass::gdb_arch_name to a different function, make the TYPE_ARM_CPU implementation of the method handle AArch64. For the moment we make the "is this AArch64?" function test "is the CPU of TYPE_AARCH64_CPU?", so that this produces no behavioural change. When we've moved all the gdbstub related methods across to the base class, we will be able to change this to be "does the CPU have the ARM_FEATURE_AARCH64 feature?". Signed-off-by: Peter Maydell Reviewed-by: Alex Bennée Reviewed-by: Philippe Mathieu-Daudé --- target/arm/internals.h | 6 ++++++ target/arm/cpu.c | 3 +++ target/arm/cpu64.c | 6 ------ 3 files changed, 9 insertions(+), 6 deletions(-) diff --git a/target/arm/internals.h b/target/arm/internals.h index bb962389192..a14c269fa5a 100644 --- a/target/arm/internals.h +++ b/target/arm/internals.h @@ -1691,6 +1691,12 @@ void aarch64_add_sve_properties(Object *obj); void aarch64_add_sme_properties(Object *obj); #endif +/* Return true if the gdbstub is presenting an AArch64 CPU */ +static inline bool arm_gdbstub_is_aarch64(ARMCPU *cpu) +{ + return object_dynamic_cast(OBJECT(cpu), TYPE_AARCH64_CPU); +} + /* Read the CONTROL register as the MRS instruction would. */ uint32_t arm_v7m_mrs_control(CPUARMState *env, uint32_t secure); diff --git a/target/arm/cpu.c b/target/arm/cpu.c index 01786ac7879..d69403fda90 100644 --- a/target/arm/cpu.c +++ b/target/arm/cpu.c @@ -2647,6 +2647,9 @@ static const gchar *arm_gdb_arch_name(CPUState *cs) ARMCPU *cpu = ARM_CPU(cs); CPUARMState *env = &cpu->env; + if (arm_gdbstub_is_aarch64(cpu)) { + return "aarch64"; + } if (arm_feature(env, ARM_FEATURE_IWMMXT)) { return "iwmmxt"; } diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c index 8188ede5cc8..020b32f21e9 100644 --- a/target/arm/cpu64.c +++ b/target/arm/cpu64.c @@ -813,11 +813,6 @@ static void aarch64_cpu_finalizefn(Object *obj) { } -static const gchar *aarch64_gdb_arch_name(CPUState *cs) -{ - return "aarch64"; -} - static void aarch64_cpu_class_init(ObjectClass *oc, void *data) { CPUClass *cc = CPU_CLASS(oc); @@ -825,7 +820,6 @@ static void aarch64_cpu_class_init(ObjectClass *oc, void *data) cc->gdb_read_register = aarch64_cpu_gdb_read_register; cc->gdb_write_register = aarch64_cpu_gdb_write_register; cc->gdb_core_xml_file = "aarch64-core.xml"; - cc->gdb_arch_name = aarch64_gdb_arch_name; object_class_property_add_bool(oc, "aarch64", aarch64_cpu_get_aarch64, aarch64_cpu_set_aarch64); From patchwork Mon Mar 17 14:28:14 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 14019388 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id B2CB2C35FF3 for ; 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[2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-43d1fe60ad4sm107914985e9.29.2025.03.17.07.28.24 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 17 Mar 2025 07:28:24 -0700 (PDT) From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Subject: [PATCH for-10.1 4/9] target/arm: Handle gdb_core_xml_file in TYPE_ARM_CPU Date: Mon, 17 Mar 2025 14:28:14 +0000 Message-ID: <20250317142819.900029-5-peter.maydell@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250317142819.900029-1-peter.maydell@linaro.org> References: <20250317142819.900029-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::336; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x336.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Instead of having the TYPE_AARCH64_CPU subclass set CPUClass:gdb_core_xml_file to a different value from that that TYPE_ARM_CPU uses, implement the gdb_get_core_xml_file method in the TYPE_ARM_CPU class to return either the AArch64 or AArch32 XML file name. Signed-off-by: Peter Maydell --- target/arm/cpu.c | 16 +++++++++++++++- target/arm/cpu64.c | 1 - target/arm/tcg/cpu-v7m.c | 1 - 3 files changed, 15 insertions(+), 3 deletions(-) diff --git a/target/arm/cpu.c b/target/arm/cpu.c index d69403fda90..75d5df4879b 100644 --- a/target/arm/cpu.c +++ b/target/arm/cpu.c @@ -2656,6 +2656,20 @@ static const gchar *arm_gdb_arch_name(CPUState *cs) return "arm"; } +static const char *arm_gdb_get_core_xml_file(CPUState *cs) +{ + ARMCPU *cpu = ARM_CPU(cs); + CPUARMState *env = &cpu->env; + + if (arm_gdbstub_is_aarch64(cpu)) { + return "aarch64-core.xml"; + } + if (arm_feature(env, ARM_FEATURE_M)) { + return "arm-m-profile.xml"; + } + return "arm-core.xml"; +} + #ifndef CONFIG_USER_ONLY #include "hw/core/sysemu-cpu-ops.h" @@ -2721,6 +2735,7 @@ static void arm_cpu_class_init(ObjectClass *oc, void *data) cc->sysemu_ops = &arm_sysemu_ops; #endif cc->gdb_arch_name = arm_gdb_arch_name; + cc->gdb_get_core_xml_file = arm_gdb_get_core_xml_file; cc->gdb_stop_before_watchpoint = true; cc->disas_set_info = arm_disas_set_info; @@ -2743,7 +2758,6 @@ static void cpu_register_class_init(ObjectClass *oc, void *data) CPUClass *cc = CPU_CLASS(acc); acc->info = data; - cc->gdb_core_xml_file = "arm-core.xml"; if (acc->info->deprecation_note) { cc->deprecation_note = acc->info->deprecation_note; } diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c index 020b32f21e9..3094df366ec 100644 --- a/target/arm/cpu64.c +++ b/target/arm/cpu64.c @@ -819,7 +819,6 @@ static void aarch64_cpu_class_init(ObjectClass *oc, void *data) cc->gdb_read_register = aarch64_cpu_gdb_read_register; cc->gdb_write_register = aarch64_cpu_gdb_write_register; - cc->gdb_core_xml_file = "aarch64-core.xml"; object_class_property_add_bool(oc, "aarch64", aarch64_cpu_get_aarch64, aarch64_cpu_set_aarch64); diff --git a/target/arm/tcg/cpu-v7m.c b/target/arm/tcg/cpu-v7m.c index c4dd3092726..8acaf860b68 100644 --- a/target/arm/tcg/cpu-v7m.c +++ b/target/arm/tcg/cpu-v7m.c @@ -261,7 +261,6 @@ static void arm_v7m_class_init(ObjectClass *oc, void *data) acc->info = data; cc->tcg_ops = &arm_v7m_tcg_ops; - cc->gdb_core_xml_file = "arm-m-profile.xml"; } static const ARMCPUInfo arm_v7m_cpus[] = { From patchwork Mon Mar 17 14:28:15 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 14019391 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 51803C282EC for ; Mon, 17 Mar 2025 14:29:42 +0000 (UTC) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1tuBSP-0000oU-FC; Mon, 17 Mar 2025 10:28:45 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1tuBSA-0000bP-KM for qemu-devel@nongnu.org; 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[2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-43d1fe60ad4sm107914985e9.29.2025.03.17.07.28.25 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 17 Mar 2025 07:28:25 -0700 (PDT) From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Subject: [PATCH for-10.1 5/9] target/arm: Handle AArch64 gdb read/write regs in TYPE_ARM_CPU Date: Mon, 17 Mar 2025 14:28:15 +0000 Message-ID: <20250317142819.900029-6-peter.maydell@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250317142819.900029-1-peter.maydell@linaro.org> References: <20250317142819.900029-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::32b; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x32b.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Instead of having the TYPE_AARCH64_CPU subclass set CPUClass::gdb_read_register and ::gdb_write_register to different methods from those of the TYPE_ARM_CPU parent class, have the TYPE_ARM_CPU methods handle either AArch32 or AArch64 at runtime. Signed-off-by: Peter Maydell Reviewed-by: Philippe Mathieu-Daudé --- target/arm/cpu64.c | 5 ----- target/arm/gdbstub.c | 12 ++++++++++++ 2 files changed, 12 insertions(+), 5 deletions(-) diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c index 3094df366ec..2f87df082cd 100644 --- a/target/arm/cpu64.c +++ b/target/arm/cpu64.c @@ -815,11 +815,6 @@ static void aarch64_cpu_finalizefn(Object *obj) static void aarch64_cpu_class_init(ObjectClass *oc, void *data) { - CPUClass *cc = CPU_CLASS(oc); - - cc->gdb_read_register = aarch64_cpu_gdb_read_register; - cc->gdb_write_register = aarch64_cpu_gdb_write_register; - object_class_property_add_bool(oc, "aarch64", aarch64_cpu_get_aarch64, aarch64_cpu_set_aarch64); object_class_property_set_description(oc, "aarch64", diff --git a/target/arm/gdbstub.c b/target/arm/gdbstub.c index 30068c22627..ce4497ad7c3 100644 --- a/target/arm/gdbstub.c +++ b/target/arm/gdbstub.c @@ -44,6 +44,12 @@ int arm_cpu_gdb_read_register(CPUState *cs, GByteArray *mem_buf, int n) ARMCPU *cpu = ARM_CPU(cs); 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[2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-43d1fe60ad4sm107914985e9.29.2025.03.17.07.28.26 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 17 Mar 2025 07:28:26 -0700 (PDT) From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Subject: [PATCH for-10.1 6/9] target/arm: Present AArch64 gdbstub based on ARM_FEATURE_AARCH64 Date: Mon, 17 Mar 2025 14:28:16 +0000 Message-ID: <20250317142819.900029-7-peter.maydell@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250317142819.900029-1-peter.maydell@linaro.org> References: <20250317142819.900029-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::330; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x330.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Currently we provide an AArch64 gdbstub for CPUs which are TYPE_AARCH64_CPU, and an AArch32 gdbstub for those which are only TYPE_ARM_CPU. This mostly does the right thing, except in the corner case of KVM with -cpu host,aarch64=off. That produces a CPU which is TYPE_AARCH64_CPU but which has ARM_FEATURE_AARCH64 removed and which to the guest is in AArch32 mode. Now we have moved all the handling of AArch64-vs-AArch32 gdbstub behaviour into TYPE_ARM_CPU we can change the condition we use for whether to select the AArch64 gdbstub to look at ARM_FEATURE_AARCH64. This will mean that we now correctly provide an AArch32 gdbstub for aarch64=off CPUs. Signed-off-by: Peter Maydell Reviewed-by: Philippe Mathieu-Daudé --- target/arm/internals.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/target/arm/internals.h b/target/arm/internals.h index a14c269fa5a..a18d87fa28b 100644 --- a/target/arm/internals.h +++ b/target/arm/internals.h @@ -1694,7 +1694,7 @@ void aarch64_add_sme_properties(Object *obj); /* Return true if the gdbstub is presenting an AArch64 CPU */ static inline bool arm_gdbstub_is_aarch64(ARMCPU *cpu) { - return object_dynamic_cast(OBJECT(cpu), TYPE_AARCH64_CPU); + return arm_feature(&cpu->env, ARM_FEATURE_AARCH64); } /* Read the CONTROL register as the MRS instruction would. */ From patchwork Mon Mar 17 14:28:17 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 14019393 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id D8012C28B30 for ; Mon, 17 Mar 2025 14:29:54 +0000 (UTC) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1tuBST-0000oa-4A; Mon, 17 Mar 2025 10:28:49 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1tuBSF-0000fI-UM for qemu-devel@nongnu.org; Mon, 17 Mar 2025 10:28:36 -0400 Received: from mail-wm1-x331.google.com ([2a00:1450:4864:20::331]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1tuBSA-0001C1-Cu for qemu-devel@nongnu.org; Mon, 17 Mar 2025 10:28:35 -0400 Received: by mail-wm1-x331.google.com with SMTP id 5b1f17b1804b1-43cfba466b2so22627285e9.3 for ; Mon, 17 Mar 2025 07:28:29 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1742221709; x=1742826509; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:from:to:cc:subject:date:message-id :reply-to; bh=12NoV+qUwolNTR/lyBhiD8xL6EvtlX/77nQHYFb4d7s=; b=kMVHGNouJDtVDHVEQLzlJo0h7I2E44kyk1DsXF+vVzlZJ4KQcWDAz0tokvoJ6Unm/M 4VGYmVMi/4SH1EQ2+6VCCb70Be6AH0N/My8qf8f7UnrV11pajbosbMXYLX8Bh25RRiCM fiopiWTXOp8ymedXghNH+I5YGwWN05xA95oDmOudqOFJcpNSucz3kOosm+kDaU8a1q8g alkdAgZ30e9Ti15V8uvplKSj2hk499s/bIR6A7ucaOCFaIHCWhZNdOBSV1Fan6Qz1Zd/ kZftuBD92e71/tRarpBrdlPd55eozSSXmWZEW+DAZnEy8mADrN3LXPDg/ygOcHy0eBrG Ko/A== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1742221709; x=1742826509; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=12NoV+qUwolNTR/lyBhiD8xL6EvtlX/77nQHYFb4d7s=; b=nGGwT7MjjCId6OONzV6eygTML5rG1lVpG9wm0Dx0eqOZgmIGTemgL787yqQOV+RTcj 80nJkVh5x7iPm25R4Afk2dBz91hd0NTJ6Q+rpfAw0cwrbPXS08RCMlWKBPk3THBBJaWx K/mAvT1S3Kwdq0NNm/Gd/4A6YwwYXah9ugvACzpLpXWlgr4wifPkGLOTd/wii60URG58 dHSTlaaSLj+BeMMMleM+ZnpM2MHndkidJpFhpJw1UXvqZugzpD5RVv5L8uji6Efhy+gK vGO4RWPai0kvKzK1eSaeKnC52vEvsq7A4OkkyelZZV7sRoFLT7CL4DWaLEQkyg6n0Xj6 vhzQ== X-Forwarded-Encrypted: i=1; AJvYcCWV6ujvSnN8uE4fUWWnagmhR8j47oh1oSE1sjg2MKzKzmk2Tg25F873HIH5FI6mxtLD/r8EaDpzGZs1@nongnu.org X-Gm-Message-State: AOJu0Ywvev5TMJ3olVoHCQHOFKQ1wbSgJXeZ0LWQyOgrWTeFzVUfh4uw GP7you4CzyyuS1/ZlmeHdbxJ8Vz6+86MCwIN69mjmWqGb25iPnb9H5faR0BNJ1ispUlipjAVF0R y X-Gm-Gg: ASbGncslgpyUK8KK9QfsrrRKP/AMPqmTbd+AZLP7Ul2+YNGISMJLArcKhMp1DkMs2D5 5zH0q6LG1N3p8eMR1hFu2xXLTUEt2tHvbk+DAmvsDcgtgSAW2To810svKj3AgDaLpbrJe4zOFCo gkfdR4m9ziRfly10wiAPwwDyi6ewJikSgj8eHP/MTAGkN6xXD6eXzw5U9yQ+0r/ILwwsJQ7Aiyg DHmlNdfdXCunzP9drv0nhVGhs02xFKQq+iuqhUwk34f043uT0hODOsFtqMepZEQSb8jdZK15pkh 1qLObGJvIGFcOxAMypcmZBehqI8jb2Zi9MEAYeeGnuyI+EDi/tM= X-Google-Smtp-Source: AGHT+IGpBHCzykbXxWcXhiu7h/aN6iP/PHg8IQjHJIIz9irlj1m3HfoLJsjVINPdWH6VTW9MCVhycA== X-Received: by 2002:a7b:c4c9:0:b0:43c:f969:13c0 with SMTP id 5b1f17b1804b1-43d23cb505fmr111623215e9.29.1742221708482; Mon, 17 Mar 2025 07:28:28 -0700 (PDT) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-43d1fe60ad4sm107914985e9.29.2025.03.17.07.28.27 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 17 Mar 2025 07:28:27 -0700 (PDT) From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Subject: [PATCH for-10.1 7/9] target/arm: Move aarch64 CPU property code to TYPE_ARM_CPU Date: Mon, 17 Mar 2025 14:28:17 +0000 Message-ID: <20250317142819.900029-8-peter.maydell@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250317142819.900029-1-peter.maydell@linaro.org> References: <20250317142819.900029-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::331; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x331.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org The only thing we have left in the TYPE_AARCH64_CPU class that makes it different to TYPE_ARM_CPU is that we register the handling of the "aarch64" property there. Move the handling of this property to the base class, where we make it a property of the object rather than of the class, and add it to the CPU if it has the ARM_FEATURE_AARCH64 property present at init. This is in line with how we handle other Arm CPU properties, and should not change which CPUs it's visible for. Signed-off-by: Peter Maydell Reviewed-by: Philippe Mathieu-Daudé --- target/arm/cpu.c | 36 ++++++++++++++++++++++++++++++++++++ target/arm/cpu64.c | 33 --------------------------------- 2 files changed, 36 insertions(+), 33 deletions(-) diff --git a/target/arm/cpu.c b/target/arm/cpu.c index 75d5df4879b..9c6e8f5a935 100644 --- a/target/arm/cpu.c +++ b/target/arm/cpu.c @@ -1608,6 +1608,35 @@ static void arm_set_pmu(Object *obj, bool value, Error **errp) cpu->has_pmu = value; } +static bool aarch64_cpu_get_aarch64(Object *obj, Error **errp) +{ + ARMCPU *cpu = ARM_CPU(obj); + + return arm_feature(&cpu->env, ARM_FEATURE_AARCH64); +} + +static void aarch64_cpu_set_aarch64(Object *obj, bool value, Error **errp) +{ + ARMCPU *cpu = ARM_CPU(obj); + + /* + * At this time, this property is only allowed if KVM is enabled. This + * restriction allows us to avoid fixing up functionality that assumes a + * uniform execution state like do_interrupt. + */ + if (value == false) { + if (!kvm_enabled() || !kvm_arm_aarch32_supported()) { + error_setg(errp, "'aarch64' feature cannot be disabled " + "unless KVM is enabled and 32-bit EL1 " + "is supported"); + return; + } + unset_feature(&cpu->env, ARM_FEATURE_AARCH64); + } else { + set_feature(&cpu->env, ARM_FEATURE_AARCH64); + } +} + unsigned int gt_cntfrq_period_ns(ARMCPU *cpu) { /* @@ -1735,6 +1764,13 @@ void arm_cpu_post_init(Object *obj) */ arm_cpu_propagate_feature_implications(cpu); + if (arm_feature(&cpu->env, ARM_FEATURE_AARCH64)) { + object_property_add_bool(obj, "aarch64", aarch64_cpu_get_aarch64, + aarch64_cpu_set_aarch64); + object_property_set_description(obj, "aarch64", + "Set on/off to enable/disable aarch64 " + "execution state "); + } if (arm_feature(&cpu->env, ARM_FEATURE_CBAR) || arm_feature(&cpu->env, ARM_FEATURE_CBAR_RO)) { qdev_property_add_static(DEVICE(obj), &arm_cpu_reset_cbar_property); diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c index 2f87df082cd..49cf06a7bdc 100644 --- a/target/arm/cpu64.c +++ b/target/arm/cpu64.c @@ -781,45 +781,12 @@ static const ARMCPUInfo aarch64_cpus[] = { #endif }; -static bool aarch64_cpu_get_aarch64(Object *obj, Error **errp) -{ - ARMCPU *cpu = ARM_CPU(obj); - - return arm_feature(&cpu->env, ARM_FEATURE_AARCH64); -} - -static void aarch64_cpu_set_aarch64(Object *obj, bool value, Error **errp) -{ - ARMCPU *cpu = ARM_CPU(obj); - - /* At this time, this property is only allowed if KVM is enabled. This - * restriction allows us to avoid fixing up functionality that assumes a - * uniform execution state like do_interrupt. - */ - if (value == false) { - if (!kvm_enabled() || !kvm_arm_aarch32_supported()) { - error_setg(errp, "'aarch64' feature cannot be disabled " - "unless KVM is enabled and 32-bit EL1 " - "is supported"); - return; - } - unset_feature(&cpu->env, ARM_FEATURE_AARCH64); - } else { - set_feature(&cpu->env, ARM_FEATURE_AARCH64); - } -} - static void aarch64_cpu_finalizefn(Object *obj) { } static void aarch64_cpu_class_init(ObjectClass *oc, void *data) { - object_class_property_add_bool(oc, "aarch64", aarch64_cpu_get_aarch64, - aarch64_cpu_set_aarch64); - object_class_property_set_description(oc, "aarch64", - "Set on/off to enable/disable aarch64 " - "execution state "); } static void aarch64_cpu_instance_init(Object *obj) From patchwork Mon Mar 17 14:28:18 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 14019390 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id C5AA1C3DA4A for ; Mon, 17 Mar 2025 14:29:26 +0000 (UTC) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1tuBSW-0000q2-Qw; Mon, 17 Mar 2025 10:28:52 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1tuBSF-0000es-FW for qemu-devel@nongnu.org; Mon, 17 Mar 2025 10:28:35 -0400 Received: from mail-wm1-x32c.google.com ([2a00:1450:4864:20::32c]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1tuBSB-0001Ck-6l for qemu-devel@nongnu.org; Mon, 17 Mar 2025 10:28:35 -0400 Received: by mail-wm1-x32c.google.com with SMTP id 5b1f17b1804b1-43cef035a3bso15639525e9.1 for ; Mon, 17 Mar 2025 07:28:30 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1742221709; x=1742826509; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:from:to:cc:subject:date:message-id :reply-to; bh=w7WKqYLy7NEpjkefHXnJSfu6zGOyWq7eC8uKJPQR8rk=; b=PezYq2v3+2uzC+l3+J7jMyxj4kb/fdEgmf75MIuQ+e11TMJVtOQ4QUdjQ1tC3tvRxY aXNN+mtLgqqviVhfsLt+yyiozLTTSeFojRPLKXtjHEX6nVAQmpT0rW0QzXLqB9Tyxs4q PYqgU+AjJaMBUwiLn2pW8ub6gzIh2Bv4xx2l1I4JCPrzYXvHxZChOKcIT/gVilBc7CMz ntFOuYbKgUfH8giBunbYoMLfmoG3Klz32dufecUk75JgK0koi5f/1QqMQKzOJK8KB3fw uJXH+zeZUb7xSKmUbmJFuDK9nWGGFunugDtPBiEGgqyduinBX1aSJX8qzq7mOHJhGIck wOcQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1742221709; x=1742826509; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=w7WKqYLy7NEpjkefHXnJSfu6zGOyWq7eC8uKJPQR8rk=; b=bl/sb3Sao9nOi87UliPDvPIqYlf/kdtc8XSTC7OR785Fo/tbJvcEcAFt1Bm4CtdBl1 tOu8wgJA0pxzStiFX1tHILn9R/V5q7m+rmTBhCcENcG4ML5p546n3+PomdCDky4e8aXd x9RvGLXXjtOuPurhy70PoOwhr1+l4xc5BXu3cjFvlDU/4KcSAgrcClZXzeR5ehINtFiR KujoON1gGeivHD/AyVk3jb8/+jXrTmg5WYO4D+9i461opk2w1fyQ8ex42mkl2H88iV5D EPaZhFAdgf+8xdEqPiLay7s9/LpWLRv0qj9IhIMTKudvX/hM92VjrqhFI1ta08Wp8fcv Rtog== X-Forwarded-Encrypted: i=1; AJvYcCVF2hHDOYRt3bq7ECGeBRsb5zli1bhHe6ImwT5DpJ1iw/GyziXx9RtqoHib5AXAMFS9TQzClJcikjMC@nongnu.org X-Gm-Message-State: AOJu0Yzee9YKNGmFm87RyxjQv0ozAG1rH/Ck7225RlLunej/GfiXvutQ rC/hbemO58rRWr8zxs5pMfeKUK51qAyNqSWliPWgGgqX5WxKzV7KJns+n3qkhtU= X-Gm-Gg: ASbGncsyLJQSezeA5K+y3e5315cts6oGe5FvRXh97pP2jb9GtvmWy16+NcIHFYhcVte Zg6V8uUwiF22tciRLcvT9qitcrgRJd383BIw6KYSSLAnWXCXLUIW4w+DZ+4Y0kouOPCwHtM4a4H 4uwyX6korqEoyzKt1h2jpaj0U5h+XJiK2svTQenY7H9VnHpjeHck/ifkN6HN5fySWhzbnE75QWf 4BsAK6ZZ7V7N6ONcHKShBd6nfjrrbs18/3KgjDWyOJ07JliBejSV9rHDA4YfC/YuhwtfSCO/80U 5o8Lj6MNbu3CvIiOpmMHPnohRNLcbeUN4W1Iiyjl/RHY7PjOWbk= X-Google-Smtp-Source: AGHT+IGteN4Bi1WBu6nBwMrKa4VYjQSO/0ELq2zu/dSlQ2PFYdag+Z9iJ4ZF/MX8mO5OUpYbpVWV/w== X-Received: by 2002:a05:600c:3c9e:b0:43d:ea:51d2 with SMTP id 5b1f17b1804b1-43d1ecc380dmr145325795e9.14.1742221709423; Mon, 17 Mar 2025 07:28:29 -0700 (PDT) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-43d1fe60ad4sm107914985e9.29.2025.03.17.07.28.28 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 17 Mar 2025 07:28:28 -0700 (PDT) From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Subject: [PATCH for-10.1 8/9] target/arm/kvm: don't check TYPE_AARCH64_CPU Date: Mon, 17 Mar 2025 14:28:18 +0000 Message-ID: <20250317142819.900029-9-peter.maydell@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250317142819.900029-1-peter.maydell@linaro.org> References: <20250317142819.900029-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::32c; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x32c.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org We want to merge TYPE_AARCH64_CPU with TYPE_ARM_CPU, so enforcing in kvm_arch_init_vcpu() that the CPU class is a subclass of TYPE_AARCH64_CPU will no longer be possible. It's safe to just remove this test, because any purely-AArch32 CPU will fail the "kvm_target isn't set" check, because we no longer support the old AArch32-host KVM setup and so CPUs like the Cortex-A7 no longer set cpu->kvm_target. Only the 'host', 'max', and the odd special cases 'cortex-a53' and 'cortex-a57' set kvm_target. Signed-off-by: Peter Maydell Reviewed-by: Philippe Mathieu-Daudé --- target/arm/kvm.c | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) diff --git a/target/arm/kvm.c b/target/arm/kvm.c index da30bdbb234..7418eb57537 100644 --- a/target/arm/kvm.c +++ b/target/arm/kvm.c @@ -1882,8 +1882,7 @@ int kvm_arch_init_vcpu(CPUState *cs) CPUARMState *env = &cpu->env; uint64_t psciver; - if (cpu->kvm_target == QEMU_KVM_ARM_TARGET_NONE || - !object_dynamic_cast(OBJECT(cpu), TYPE_AARCH64_CPU)) { + if (cpu->kvm_target == QEMU_KVM_ARM_TARGET_NONE) { error_report("KVM is not supported for this guest CPU type"); return -EINVAL; } From patchwork Mon Mar 17 14:28:19 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 14019396 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 1D931C282EC for ; Mon, 17 Mar 2025 14:31:16 +0000 (UTC) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1tuBSO-0000o0-KO; Mon, 17 Mar 2025 10:28:44 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1tuBSG-0000fs-GB for qemu-devel@nongnu.org; Mon, 17 Mar 2025 10:28:37 -0400 Received: from mail-wm1-x32f.google.com ([2a00:1450:4864:20::32f]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1tuBSC-0001DX-DB for qemu-devel@nongnu.org; Mon, 17 Mar 2025 10:28:35 -0400 Received: by mail-wm1-x32f.google.com with SMTP id 5b1f17b1804b1-43d2d952eb1so10336575e9.1 for ; Mon, 17 Mar 2025 07:28:31 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1742221710; x=1742826510; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:from:to:cc:subject:date:message-id :reply-to; bh=IGKVMeg4aDxvbEQfJftU83jMmdBHS/KLNHZo9WpIB6Q=; b=KgPl5X+vBGiWG4s0QK/MBma0/dJNievroG8yTAHVEzk3Zt5NYmkFyX1i9H20fgGTa3 2DCPfEN3tMKbQofs3wuuM2z7HUEOuld0l0JNs+xzL2u3s2XXgXEOUA9OEqK5TBV16mTZ dn4maArEOH2BcVQO9T0ywJAiL9K77e5gRGzkp9xiyeLKMXFbAHb7JuwO/mPUvxea3doB MInur6daRYUBA7axJm2mzUjd+WpbX5nJI38dXvS4s7cpZOwB6KxqmjZc8vfAhGzBgkgF TO6zzCj0pC3/GS4cca1FM/dP7/DjHGa+mKx3IJbAF8Dp8Ps1liUK2o4f9FWYJXqHxoeY BnLw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1742221710; x=1742826510; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=IGKVMeg4aDxvbEQfJftU83jMmdBHS/KLNHZo9WpIB6Q=; b=EgZRMA0d8bg/VrZeDCfO+Ttms5VehwLfAtlqEreO6Wv7Uty5j29oPx7QnVWkOPazSN Dsn07cvJPnbaSNpK5dWtI6luvcLhro23FkF/O+X04I2Bf1F1Df42KBZJWdfQ8eRq1+bz i157JVaGTgv12IzVAzUhE9JS5LUIyHVL2MiPYDJ85/pYdGK7FHoCNUbImcl28ocVfQDX 9jaDzxLxeFtTC77XLuVMf3vN++GYutSMjpBFs0S/h3iYcwB9x7PCjcCa5lXCXRSdzxRq v4THRDlB9i9PWoel8YKSw/I/zNZE52lr2g+ReGss4SK2wmvZL+1+j9+URGmbids/y9Vb RyHw== X-Forwarded-Encrypted: i=1; AJvYcCW9zBg6MIZZ0F4mq3cqKq42GxbFvxRxQVDOOGt5dBf3+LY+wKEMKgkj4wnQB/dsi13Wmc6bbHVOW/3F@nongnu.org X-Gm-Message-State: AOJu0Yx0ehbhQoseVqqkdhdYiPs/bDMOOsio3XCnj7ZBXNXebGDgRN28 CUEVme3XPnDo69B9kCHZ+pall4mWgbwDgwjfXM+VU1jqdjZ1FY1BiyaF50Mk/EnPWYugAfP4JeG 1 X-Gm-Gg: ASbGncu91MbLvMD5wmbbkVwdAt6l5cFzeZ7K7SIdv/A21H/Nhxl4EkCAtvSr9aD4eLh 7cWwRXijdM7ghQAyammZQYxgVfcy4csdx7XTQQVJ4OybVCb/DfWCICJjos80/ZgcWFKUl2sb5Vm 8FUEAnQSg5fbMkja+MosvafQrapc6NUvtvF+uX0vlKatEXkuXhKu8q8Rjhlrz2iBhZAVe/YQxBa alXgpnqvJnDfVi/11Npn5ISgG4XyPRnURmJlsmBo5vsKYc68SleODs5Z1gozJ5IuMS+A/ieQ4bH pbZn9b+FzR0UYbQZskOdvbIaGFLm83AvMZH/zpjRJqVnnQYuhJG2LOYj1eTaSQ== X-Google-Smtp-Source: AGHT+IHjQSceXaoTiB7jwNXtux+dMPc0ELOg/8WD+nn1wAZVcN96rMvzmT0XM0yTabxYV+MCitMQYg== X-Received: by 2002:a05:600c:3c99:b0:43c:f597:d565 with SMTP id 5b1f17b1804b1-43d3897499bmr577705e9.12.1742221710402; Mon, 17 Mar 2025 07:28:30 -0700 (PDT) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-43d1fe60ad4sm107914985e9.29.2025.03.17.07.28.29 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 17 Mar 2025 07:28:29 -0700 (PDT) From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Subject: [PATCH for-10.1 9/9] target/arm: Remove TYPE_AARCH64_CPU Date: Mon, 17 Mar 2025 14:28:19 +0000 Message-ID: <20250317142819.900029-10-peter.maydell@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250317142819.900029-1-peter.maydell@linaro.org> References: <20250317142819.900029-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::32f; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x32f.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org The TYPE_AARCH64_CPU class is an abstract type that is the parent of all the AArch64 CPUs. It now has no special behaviour of its own, so we can eliminate it and make the AArch64 CPUs directly inherit from TYPE_ARM_CPU. Signed-off-by: Peter Maydell Reviewed-by: Philippe Mathieu-Daudé --- target/arm/cpu-qom.h | 5 ----- target/arm/cpu.h | 4 ---- target/arm/internals.h | 1 - target/arm/cpu64.c | 49 +----------------------------------------- target/arm/tcg/cpu64.c | 2 +- 5 files changed, 2 insertions(+), 59 deletions(-) diff --git a/target/arm/cpu-qom.h b/target/arm/cpu-qom.h index b497667d61e..2fcb0e12525 100644 --- a/target/arm/cpu-qom.h +++ b/target/arm/cpu-qom.h @@ -28,11 +28,6 @@ OBJECT_DECLARE_CPU_TYPE(ARMCPU, ARMCPUClass, ARM_CPU) #define TYPE_ARM_MAX_CPU "max-" TYPE_ARM_CPU -#define TYPE_AARCH64_CPU "aarch64-cpu" -typedef struct AArch64CPUClass AArch64CPUClass; -DECLARE_CLASS_CHECKERS(AArch64CPUClass, AARCH64_CPU, - TYPE_AARCH64_CPU) - #define ARM_CPU_TYPE_SUFFIX "-" TYPE_ARM_CPU #define ARM_CPU_TYPE_NAME(name) (name ARM_CPU_TYPE_SUFFIX) diff --git a/target/arm/cpu.h b/target/arm/cpu.h index 8f52380c88c..c9c53a6294b 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -1161,10 +1161,6 @@ struct ARMCPUClass { ResettablePhases parent_phases; }; -struct AArch64CPUClass { - ARMCPUClass parent_class; -}; - /* Callback functions for the generic timer's timers. */ void arm_gt_ptimer_cb(void *opaque); void arm_gt_vtimer_cb(void *opaque); diff --git a/target/arm/internals.h b/target/arm/internals.h index a18d87fa28b..0c24208f183 100644 --- a/target/arm/internals.h +++ b/target/arm/internals.h @@ -350,7 +350,6 @@ static inline int r14_bank_number(int mode) } void arm_cpu_register(const ARMCPUInfo *info); -void aarch64_cpu_register(const ARMCPUInfo *info); void register_cp_regs_for_features(ARMCPU *cpu); void init_cpreg_list(ARMCPU *cpu); diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c index 49cf06a7bdc..200da1c489b 100644 --- a/target/arm/cpu64.c +++ b/target/arm/cpu64.c @@ -781,59 +781,12 @@ static const ARMCPUInfo aarch64_cpus[] = { #endif }; -static void aarch64_cpu_finalizefn(Object *obj) -{ -} - -static void aarch64_cpu_class_init(ObjectClass *oc, void *data) -{ -} - -static void aarch64_cpu_instance_init(Object *obj) -{ - ARMCPUClass *acc = ARM_CPU_GET_CLASS(obj); - - acc->info->initfn(obj); - arm_cpu_post_init(obj); -} - -static void cpu_register_class_init(ObjectClass *oc, void *data) -{ - ARMCPUClass *acc = ARM_CPU_CLASS(oc); - - acc->info = data; -} - -void aarch64_cpu_register(const ARMCPUInfo *info) -{ - TypeInfo type_info = { - .parent = TYPE_AARCH64_CPU, - .instance_init = aarch64_cpu_instance_init, - .class_init = info->class_init ?: cpu_register_class_init, - .class_data = (void *)info, - }; - - type_info.name = g_strdup_printf("%s-" TYPE_ARM_CPU, info->name); - type_register_static(&type_info); - g_free((void *)type_info.name); -} - -static const TypeInfo aarch64_cpu_type_info = { - .name = TYPE_AARCH64_CPU, - .parent = TYPE_ARM_CPU, - .instance_finalize = aarch64_cpu_finalizefn, - .abstract = true, - .class_init = aarch64_cpu_class_init, -}; - static void aarch64_cpu_register_types(void) { size_t i; - type_register_static(&aarch64_cpu_type_info); - for (i = 0; i < ARRAY_SIZE(aarch64_cpus); ++i) { - aarch64_cpu_register(&aarch64_cpus[i]); + arm_cpu_register(&aarch64_cpus[i]); } } diff --git a/target/arm/tcg/cpu64.c b/target/arm/tcg/cpu64.c index 29ab0ac79da..5d8ed2794d3 100644 --- a/target/arm/tcg/cpu64.c +++ b/target/arm/tcg/cpu64.c @@ -1316,7 +1316,7 @@ static void aarch64_cpu_register_types(void) size_t i; for (i = 0; i < ARRAY_SIZE(aarch64_cpus); ++i) { - aarch64_cpu_register(&aarch64_cpus[i]); + arm_cpu_register(&aarch64_cpus[i]); } }