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Tue, 18 Mar 2025 06:50:20 GMT Received: from hu-mmanikan-blr.qualcomm.com (10.80.80.8) by nalasex01a.na.qualcomm.com (10.47.209.196) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.9; Mon, 17 Mar 2025 23:50:16 -0700 From: Manikanta Mylavarapu To: , , , , , , , , CC: Subject: [PATCH v2] arm64: dts: qcom: ipq5424: fix and relocate uart1 gpio configurations Date: Tue, 18 Mar 2025 12:19:39 +0530 Message-ID: <20250318064939.3638381-1-quic_mmanikan@quicinc.com> X-Mailer: git-send-email 2.34.1 Precedence: bulk X-Mailing-List: linux-arm-msm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-ClientProxiedBy: nasanex01a.na.qualcomm.com (10.52.223.231) To nalasex01a.na.qualcomm.com (10.47.209.196) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-GUID: gW1C8LM_Hk8RNw4ekJeumjz8fZWFv5FJ X-Proofpoint-ORIG-GUID: gW1C8LM_Hk8RNw4ekJeumjz8fZWFv5FJ X-Authority-Analysis: v=2.4 cv=XKcwSRhE c=1 sm=1 tr=0 ts=67d917ad cx=c_pps a=ouPCqIW2jiPt+lZRy3xVPw==:117 a=ouPCqIW2jiPt+lZRy3xVPw==:17 a=GEpy-HfZoHoA:10 a=Vs1iUdzkB0EA:10 a=COk6AnOGAAAA:8 a=EwbgSTejZl1M597PQjwA:9 a=HVqvvCGUhjtjaAmPp66E:22 a=TjNXssC_j7lpFel5tvFf:22 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1093,Hydra:6.0.680,FMLib:17.12.68.34 definitions=2025-03-18_03,2025-03-17_03,2024-11-22_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 lowpriorityscore=0 mlxlogscore=561 priorityscore=1501 clxscore=1015 phishscore=0 impostorscore=0 adultscore=0 mlxscore=0 malwarescore=0 suspectscore=0 spamscore=0 bulkscore=0 classifier=spam authscore=0 authtc=n/a authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.19.0-2502280000 definitions=main-2503180046 Update the bias configuration for UART1 TX and RX pins to ensure correct settings for RDP466. Additionally, move the UART1 GPIO configurations from the common .dtsi file to the RDP-specific .dts files to account for differing bias configurations across RDPs of IPQ5424. Fixes: 1a91d2a6021e ("arm64: dts: qcom: add IPQ5424 SoC and rdp466 board support") Signed-off-by: Manikanta Mylavarapu Reviewed-by: Kathiravan Thirumoorthy --- Changes in V2: - Consolidated uart1_tx_state and uart1_rx_state nodes into a single qup_uart1_default_state node, which includes the configuration for both UART1 TX and RX pins. - Inserted a blank line before the status property in the UART1 node. - Fixed review comments from Kathiravan Thirumoorthy. arch/arm64/boot/dts/qcom/ipq5424-rdp466.dts | 19 ++++++++++++++++++- arch/arm64/boot/dts/qcom/ipq5424.dtsi | 7 ------- 2 files changed, 18 insertions(+), 8 deletions(-) base-commit: da920b7df701770e006928053672147075587fb2 diff --git a/arch/arm64/boot/dts/qcom/ipq5424-rdp466.dts b/arch/arm64/boot/dts/qcom/ipq5424-rdp466.dts index b9752e8d579e..f0cba6b2be70 100644 --- a/arch/arm64/boot/dts/qcom/ipq5424-rdp466.dts +++ b/arch/arm64/boot/dts/qcom/ipq5424-rdp466.dts @@ -102,6 +102,22 @@ &ssphy_0 { }; &tlmm { + qup_uart1_default_state: qup-uart1-default-state { + uart1-tx-pins { + pins = "gpio44"; + function = "uart1"; + drive-strength = <8>; + bias-pull-down; + }; + + uart1-rx-pins { + pins = "gpio43"; + function = "uart1"; + drive-strength = <8>; + bias-pull-up; + }; + }; + spi0_default_state: spi0-default-state { clk-pins { pins = "gpio6"; @@ -157,8 +173,9 @@ data-pins { }; &uart1 { - pinctrl-0 = <&uart1_pins>; + pinctrl-0 = <&qup_uart1_default_state>; pinctrl-names = "default"; + status = "okay"; }; diff --git a/arch/arm64/boot/dts/qcom/ipq5424.dtsi b/arch/arm64/boot/dts/qcom/ipq5424.dtsi index 402d0a2c7bcc..0117f6422347 100644 --- a/arch/arm64/boot/dts/qcom/ipq5424.dtsi +++ b/arch/arm64/boot/dts/qcom/ipq5424.dtsi @@ -262,13 +262,6 @@ tlmm: pinctrl@1000000 { gpio-ranges = <&tlmm 0 0 50>; interrupt-controller; #interrupt-cells = <2>; - - uart1_pins: uart1-state { - pins = "gpio43", "gpio44"; - function = "uart1"; - drive-strength = <8>; - bias-pull-up; - }; }; gcc: clock-controller@1800000 {