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Iglesias" , Peter Maydell , Alistair Francis , =?utf-8?q?Corvin_K=C3=B6hne?= , Paolo Bonzini , YannickV Subject: [PATCH 05/21] hw/dma/zynq: Notify devcfg on FPGA reset via SLCR control Date: Tue, 18 Mar 2025 14:07:56 +0100 Message-ID: <20250318130817.119636-6-corvin.koehne@gmail.com> X-Mailer: git-send-email 2.49.0 In-Reply-To: <20250318130817.119636-1-corvin.koehne@gmail.com> References: <20250318130817.119636-1-corvin.koehne@gmail.com> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::635; envelope-from=corvin.koehne@gmail.com; helo=mail-ej1-x635.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org From: YannickV When the FPGA_RST_CTRL register in the SLCR (System Level Control Register) is written to, the devcfg (Device Configuration) should indicate the finished reset. Problems occure when Loaders trigger a reset via SLCR and poll for the done flag in devcfg. Since the flag will never be set, this can result in an endless loop. A callback function `slcr_reset_handler` is added to the `XlnxZynqDevcfg` structure. The `slcr_reset` function sets the `PCFG_DONE` flag when triggered by an FPGA reset in the SLCR. The SLCR write handler calls the `slcr_reset` function when the FPGA reset control register (`R_FPGA_RST_CTRL`) is written with the reset value. Signed-off-by: Yannick Voßen --- hw/dma/xlnx-zynq-devcfg.c | 7 +++++++ hw/misc/zynq_slcr.c | 16 ++++++++++++++++ include/hw/dma/xlnx-zynq-devcfg.h | 1 + 3 files changed, 24 insertions(+) diff --git a/hw/dma/xlnx-zynq-devcfg.c b/hw/dma/xlnx-zynq-devcfg.c index 03b5280228..611a57b4d4 100644 --- a/hw/dma/xlnx-zynq-devcfg.c +++ b/hw/dma/xlnx-zynq-devcfg.c @@ -138,6 +138,11 @@ static void xlnx_zynq_devcfg_update_ixr(XlnxZynqDevcfg *s) qemu_set_irq(s->irq, ~s->regs[R_INT_MASK] & s->regs[R_INT_STS]); } +static void slcr_reset (DeviceState *dev) { + XlnxZynqDevcfg *s = XLNX_ZYNQ_DEVCFG(dev); + s->regs[R_INT_STS] |= R_INT_STS_PCFG_DONE_MASK; +} + static void xlnx_zynq_devcfg_reset(DeviceState *dev) { XlnxZynqDevcfg *s = XLNX_ZYNQ_DEVCFG(dev); @@ -374,6 +379,8 @@ static void xlnx_zynq_devcfg_init(Object *obj) XlnxZynqDevcfg *s = XLNX_ZYNQ_DEVCFG(obj); RegisterInfoArray *reg_array; + s->slcr_reset_handler = slcr_reset; + sysbus_init_irq(sbd, &s->irq); memory_region_init(&s->iomem, obj, "devcfg", XLNX_ZYNQ_DEVCFG_R_MAX * 4); diff --git a/hw/misc/zynq_slcr.c b/hw/misc/zynq_slcr.c index a766bab182..9b3220f354 100644 --- a/hw/misc/zynq_slcr.c +++ b/hw/misc/zynq_slcr.c @@ -26,6 +26,7 @@ #include "qom/object.h" #include "hw/qdev-properties.h" #include "qapi/error.h" +#include "hw/dma/xlnx-zynq-devcfg.h" #ifndef ZYNQ_SLCR_ERR_DEBUG #define ZYNQ_SLCR_ERR_DEBUG 0 @@ -576,6 +577,21 @@ static void zynq_slcr_write(void *opaque, hwaddr offset, zynq_slcr_compute_clocks(s); zynq_slcr_propagate_clocks(s); break; + case R_FPGA_RST_CTRL: + if (val == 0) { + Object *devcfgObject = + object_resolve_type_unambiguous("xlnx.ps7-dev-cfg", NULL); + if (!devcfgObject) { + break; + } + DeviceState *devcfg = OBJECT_CHECK(DeviceState, devcfgObject, + "xlnx.ps7-dev-cfg"); + XlnxZynqDevcfg *zynqdevcfg = XLNX_ZYNQ_DEVCFG(devcfg); + if (zynqdevcfg) { + zynqdevcfg->slcr_reset_handler(devcfg); + } + } + break; } } diff --git a/include/hw/dma/xlnx-zynq-devcfg.h b/include/hw/dma/xlnx-zynq-devcfg.h index 2ab054e598..f48a630c5a 100644 --- a/include/hw/dma/xlnx-zynq-devcfg.h +++ b/include/hw/dma/xlnx-zynq-devcfg.h @@ -56,6 +56,7 @@ struct XlnxZynqDevcfg { uint8_t dma_cmd_fifo_num; bool is_initialized; + void (*slcr_reset_handler) (DeviceState *dev); uint32_t regs[XLNX_ZYNQ_DEVCFG_R_MAX]; RegisterInfo regs_info[XLNX_ZYNQ_DEVCFG_R_MAX]; From patchwork Tue Mar 18 13:07:57 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Corvin_K=C3=B6hne?= X-Patchwork-Id: 14020994 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 2135BC28B2F for ; Tue, 18 Mar 2025 13:16:19 +0000 (UTC) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1tuWib-0000Oy-Tx; Tue, 18 Mar 2025 09:10:54 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1tuWiJ-00084M-Nh; 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Tue, 18 Mar 2025 06:10:19 -0700 (PDT) Received: from corvink-nb.beckhoff.com ([195.226.174.194]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-ac3147f3101sm850678066b.69.2025.03.18.06.10.18 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 18 Mar 2025 06:10:18 -0700 (PDT) From: =?utf-8?q?Corvin_K=C3=B6hne?= To: qemu-devel@nongnu.org, qemu-arm@nongnu.org Cc: =?utf-8?q?Yannick_Vo=C3=9Fen?= , "Edgar E. Iglesias" , Peter Maydell , Alistair Francis , =?utf-8?q?Corvin_K=C3=B6hne?= , Paolo Bonzini , YannickV Subject: [PATCH 06/21] hw/dma/zynq-devcfg: Simulate dummy PL reset Date: Tue, 18 Mar 2025 14:07:57 +0100 Message-ID: <20250318130817.119636-7-corvin.koehne@gmail.com> X-Mailer: git-send-email 2.49.0 In-Reply-To: <20250318130817.119636-1-corvin.koehne@gmail.com> References: <20250318130817.119636-1-corvin.koehne@gmail.com> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::630; envelope-from=corvin.koehne@gmail.com; helo=mail-ej1-x630.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org From: YannickV Setting PCFG_PROG_B should reset the PL. After a reset PCFG_INIT should indicate that the reset is finished successfully. In order to add a MMIO-Device as part of the PL in the Zynq, the reset logic must succeed. The PCFG_INIT flag is now set when the PL reset is triggered by PCFG_PROG_B. Indicating the reset was successful. Signed-off-by: Yannick Voßen --- hw/dma/xlnx-zynq-devcfg.c | 10 ++++++++++ 1 file changed, 10 insertions(+) diff --git a/hw/dma/xlnx-zynq-devcfg.c b/hw/dma/xlnx-zynq-devcfg.c index 611a57b4d4..c44b802b22 100644 --- a/hw/dma/xlnx-zynq-devcfg.c +++ b/hw/dma/xlnx-zynq-devcfg.c @@ -49,6 +49,7 @@ REG32(CTRL, 0x00) FIELD(CTRL, FORCE_RST, 31, 1) /* Not supported, wr ignored */ + FIELD(CTRL, PCFG_PROG_B, 30, 1) FIELD(CTRL, PCAP_PR, 27, 1) /* Forced to 0 on bad unlock */ FIELD(CTRL, PCAP_MODE, 26, 1) FIELD(CTRL, MULTIBOOT_EN, 24, 1) @@ -116,6 +117,7 @@ REG32(STATUS, 0x14) FIELD(STATUS, PSS_GTS_USR_B, 11, 1) FIELD(STATUS, PSS_FST_CFG_B, 10, 1) FIELD(STATUS, PSS_CFG_RESET_B, 5, 1) + FIELD(STATUS, PCFG_INIT, 4, 1) REG32(DMA_SRC_ADDR, 0x18) REG32(DMA_DST_ADDR, 0x1C) @@ -209,6 +211,14 @@ static uint64_t r_ctrl_pre_write(RegisterInfo *reg, uint64_t val) val |= lock_ctrl_map[i] & s->regs[R_CTRL]; } } + + uint32_t pcfg_prog_b = FIELD_EX32(val, CTRL, PCFG_PROG_B); + if (pcfg_prog_b) { + s->regs[R_STATUS] |= R_STATUS_PCFG_INIT_MASK; + } else { + s->regs[R_STATUS] &= ~R_STATUS_PCFG_INIT_MASK; + } + return val; } From patchwork Tue Mar 18 13:07:58 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Corvin_K=C3=B6hne?= X-Patchwork-Id: 14020988 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id BB7D6C282EC for ; Tue, 18 Mar 2025 13:14:23 +0000 (UTC) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1tuWil-0001Ns-98; Tue, 18 Mar 2025 09:11:03 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1tuWiY-0000Ar-D1; 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Tue, 18 Mar 2025 06:10:31 -0700 (PDT) Received: from corvink-nb.beckhoff.com ([195.226.174.194]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-ac3147f3101sm850678066b.69.2025.03.18.06.10.27 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 18 Mar 2025 06:10:27 -0700 (PDT) From: =?utf-8?q?Corvin_K=C3=B6hne?= To: qemu-devel@nongnu.org, qemu-arm@nongnu.org Cc: =?utf-8?q?Yannick_Vo=C3=9Fen?= , "Edgar E. Iglesias" , Peter Maydell , Alistair Francis , =?utf-8?q?Corvin_K=C3=B6hne?= , Paolo Bonzini , YannickV Subject: [PATCH 07/21] hw/dma/zynq-devcfg: Indicate power-up status of PL Date: Tue, 18 Mar 2025 14:07:58 +0100 Message-ID: <20250318130817.119636-8-corvin.koehne@gmail.com> X-Mailer: git-send-email 2.49.0 In-Reply-To: <20250318130817.119636-1-corvin.koehne@gmail.com> References: <20250318130817.119636-1-corvin.koehne@gmail.com> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::52d; envelope-from=corvin.koehne@gmail.com; helo=mail-ed1-x52d.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org From: YannickV It is assumed, that the programmable logic (PL) is always powered during emulation. Therefor the PCFG_POR_B bit in the MCTRL register is set. This commit is necessary for the Beckhoff CX7200 board emulation that has a FPGA implemented in the PL. Signed-off-by: Yannick Voßen --- hw/dma/xlnx-zynq-devcfg.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/hw/dma/xlnx-zynq-devcfg.c b/hw/dma/xlnx-zynq-devcfg.c index c44b802b22..c595d090fa 100644 --- a/hw/dma/xlnx-zynq-devcfg.c +++ b/hw/dma/xlnx-zynq-devcfg.c @@ -339,7 +339,7 @@ static const RegisterAccessInfo xlnx_zynq_devcfg_regs_info[] = { /* Silicon 3.0 for version field, the mysterious reserved bit 23 * and QEMU platform identifier. */ - .reset = 0x2 << R_MCTRL_PS_VERSION_SHIFT | 1 << 23 | R_MCTRL_QEMU_MASK, + .reset = 0x2 << R_MCTRL_PS_VERSION_SHIFT | 1 << 23 | 1 << R_MCTRL_PCFG_POR_B_SHIFT | R_MCTRL_QEMU_MASK, .ro = ~R_MCTRL_INT_PCAP_LPBK_MASK, .rsvd = 0x00f00303, }, From patchwork Tue Mar 18 13:07:59 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Corvin_K=C3=B6hne?= X-Patchwork-Id: 14020982 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 87CD8C28B2F for ; Tue, 18 Mar 2025 13:14:11 +0000 (UTC) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1tuWjo-0002Xk-Sf; Tue, 18 Mar 2025 09:12:09 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1tuWiq-0001ts-J1; Tue, 18 Mar 2025 09:11:09 -0400 Received: from mail-lj1-x229.google.com ([2a00:1450:4864:20::229]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1tuWio-0003la-Fc; Tue, 18 Mar 2025 09:11:08 -0400 Received: by mail-lj1-x229.google.com with SMTP id 38308e7fff4ca-30bae572157so56630771fa.3; Tue, 18 Mar 2025 06:11:04 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20230601; t=1742303463; x=1742908263; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=0cc1uZY19mfyr0bTj71wtNtnhiaEWQlAkAZt8nIkpWE=; b=jVIBAN+urq1B3opUxjK+RiS0Mw84yZSlhTkeH21Dt8JljuVUGDc8dtpnArGHhDg/xF hWQfpueJD1SBN2tdvwAiLZzHKFwEwTg4VV8v2wGWaH2brneLCnEJ5aSxq41s8Bgj11Hv DTgkbMG8tE+3pvNdnSHYGKM1PZze6woKeE0obMWGN2lRRkSxulrFcNs7ABOEq812vznE rX1QgZqZ3m94zY6KoJZyVNmKeAITfwRhTXNMD0Xq0rXN8bDi6jMF/84lS87NJ0mEvBqx j9cBB+JvY+3fI8/AjAR758w3uT6anW01VnB1ZFU1rzcPbhMkU8NN3qdhBqaSy6nnCjko bdJQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1742303463; x=1742908263; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=0cc1uZY19mfyr0bTj71wtNtnhiaEWQlAkAZt8nIkpWE=; b=rP0DLie17Q/nrlaF4Jg8Bod2uNEcnzUFUIt4GUebEaSEArkTiZ+CnzbzsSFnTlsgep AvLfQT2QlfFZYnTKGjFKSshfsVyVkSZ/PrPfQBibkJeIE06/4zH/hwXKkQUtac2l0YCb GNaggENddXOC+WQmrtnD66X6G4SJmjgtOq3hBtmSSU0Ms0svG6oBxPKU/ZLQC4ACNdnL IKLcSzTNbYB8Gn4s9WlOuBm4TFiCghYZWlC9PB4KcKZXT5QyNxkAuga48G4eH9KCKwxV VBuNDliakErM9BKL03EzywOIZL5usz3kCwT4bdtiut8ycVPgR8qwpDULI9jgj4VBaW7D 2fvA== X-Forwarded-Encrypted: i=1; AJvYcCWDgxnWT26+ppWU0iy0/kAalcuYnKZXnuz++sMPJ/fkKyiXtbRf8db6+ujBypUPrTuFQWFAEUtqtg==@nongnu.org X-Gm-Message-State: AOJu0Yxy9hjnmL6lVKqTGdxotiANjZQ2u9uGTuybCsNn83/Jo4RadX7a WAwoFfFMhaXVo5sPwLk0bDv3KsHI6zwl0orH7IDKJ4nk4DoZc5f8ArAeaCdL X-Gm-Gg: ASbGnctjCwuFLjPSpwWK7VRljXOLlb6+uy0BdeBoMByYfPWz+hronSfc8Nbj1OxRqvW +Ux6MupfcPloOMRkirlhzcJ9ShD3OBrdiAPDOJQelM4lrXFWQfn158eaBw7+4dPPNHSQLSZ47b9 oATZJfXfMQmRWzIWaJUR8i3/YxghJ1dKH5iCvCveR24QQUx7b4kO9ShW3e0EfX6WFW3nDLGk8zO e7FXhpREOjZ5IiZwecmUvtvRqZSUsoKnFzdCQ1vDGx1d+mYm40n2hveJU+iSir6Ikh7lQfQcjVy j+EMI9cGRMg3AZ3PcgvvEbX3zegzVg2/wXRmU6WB5mglKRnjEeB+NjgVpJ+0xPGXex0= X-Google-Smtp-Source: AGHT+IHwT1XLLORMDllqjLTe01RDYTLtyhmLqkNxCh58gk3HHiNRNQAqN7J99vv+LnWYu2+dINHGgw== X-Received: by 2002:a17:907:97d3:b0:ac3:cff:80f1 with SMTP id a640c23a62f3a-ac3303e70e3mr1680550766b.54.1742303442070; Tue, 18 Mar 2025 06:10:42 -0700 (PDT) Received: from corvink-nb.beckhoff.com ([195.226.174.194]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-ac3147f3101sm850678066b.69.2025.03.18.06.10.39 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 18 Mar 2025 06:10:39 -0700 (PDT) From: =?utf-8?q?Corvin_K=C3=B6hne?= To: qemu-devel@nongnu.org, qemu-arm@nongnu.org Cc: =?utf-8?q?Yannick_Vo=C3=9Fen?= , "Edgar E. Iglesias" , Peter Maydell , Alistair Francis , =?utf-8?q?Corvin_K=C3=B6hne?= , Paolo Bonzini , YannickV Subject: [PATCH 08/21] hw/dma/zynq-devcfg: Fix register memory Date: Tue, 18 Mar 2025 14:07:59 +0100 Message-ID: <20250318130817.119636-9-corvin.koehne@gmail.com> X-Mailer: git-send-email 2.49.0 In-Reply-To: <20250318130817.119636-1-corvin.koehne@gmail.com> References: <20250318130817.119636-1-corvin.koehne@gmail.com> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::229; envelope-from=corvin.koehne@gmail.com; helo=mail-lj1-x229.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org From: YannickV Registers are always 32 bit aligned. R_MAX is not the maximum register address, it is the maximum register number. The memory size can be determined by 4 * R_MAX. Currently every register with an offset bigger than 0x40 will be ignored, because the memory size is set wrong. This effects the MCTRL register and makes it useless. This commit restores the correct behaviour. Signed-off-by: Yannick Voßen --- hw/dma/xlnx-zynq-devcfg.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/hw/dma/xlnx-zynq-devcfg.c b/hw/dma/xlnx-zynq-devcfg.c index c595d090fa..24461677ef 100644 --- a/hw/dma/xlnx-zynq-devcfg.c +++ b/hw/dma/xlnx-zynq-devcfg.c @@ -400,7 +400,7 @@ static void xlnx_zynq_devcfg_init(Object *obj) s->regs_info, s->regs, &xlnx_zynq_devcfg_reg_ops, XLNX_ZYNQ_DEVCFG_ERR_DEBUG, - XLNX_ZYNQ_DEVCFG_R_MAX); + XLNX_ZYNQ_DEVCFG_R_MAX * 4); memory_region_add_subregion(&s->iomem, A_CTRL, ®_array->mem); From patchwork Tue Mar 18 13:08:00 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Corvin_K=C3=B6hne?= X-Patchwork-Id: 14021005 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 971E6C282EC for ; Tue, 18 Mar 2025 13:17:20 +0000 (UTC) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1tuWir-0001r4-Cx; Tue, 18 Mar 2025 09:11:09 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1tuWik-0001Lr-Ds; Tue, 18 Mar 2025 09:11:02 -0400 Received: from mail-ej1-x62a.google.com ([2a00:1450:4864:20::62a]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1tuWih-0003l4-DK; Tue, 18 Mar 2025 09:11:01 -0400 Received: by mail-ej1-x62a.google.com with SMTP id a640c23a62f3a-ac2ab99e16eso185092766b.0; Tue, 18 Mar 2025 06:10:58 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20230601; t=1742303457; x=1742908257; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=8z+PHMNfzA0XW1PBgVhogbq+RReNZeV3FJfN4W1yf98=; b=bJg2A4sebX/6VWcyZbFM9bfqE8BhQzCdwL2PI1HcfeoohJuk946xulXgUzf42xvsVE pb6V7ZH/JTRW4KEViLxItRjlwRD+seYjBMCASWdsD7HDHOnUnGLBEiFVwLmMdDY2Ho+H Sj34SYVnkB081FmH4OTDmhfb+j+7G2gAqYo4suPq7gU1kNTI1f2iXPuHkDBQACu7OhK5 41oyNrsIgjv41yxKXTN8ozObxeAjxoJ69u8dAiQ+Ust4pqIndXTxOr9XrpCNbigPIfuO haVuUcSCsV02kuSjP4D9kmDmywbKWoe8CVCpxwrgjtq4aM1F9cXEjkUuJsVU/HrETfqX za3A== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1742303457; x=1742908257; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=8z+PHMNfzA0XW1PBgVhogbq+RReNZeV3FJfN4W1yf98=; b=YGyeUr0Ti8+xvMugsZxBsAHKcgkGMAlpHom3m5PB3O6nCzZUg4kU4nDI0cxAI/Q6em jX4p5yI2pWOvK6gpUbPoGYmAeCHKKaIolISecXh8Pyy7BLDq1oaInvVUok/8Bq6O7xlG mqMhiF4WCSpg74rgZO5hm+btUaahLbo/xyL3/pgUDkhtiRb5o3DGx2uP/0E5Ir6TxLom DPP7BSMv1SOQcHgE/5KpDWhZ/Zdje9ZL57lvAIgehG55qE1sYVF5lMUl0OIWwy2VbKxm F9N/6YDC75yavEXaFq9OTFDMfM/VLqV6vZrOWHvjyjq829JF9ld1gVO1mdX8V2xJa+VU rn8w== X-Forwarded-Encrypted: i=1; AJvYcCUcaJhVdwWd+dHaA7+Vx8+MhH65Zg6b9DX0lNZ7wYYK0yhx5OzsXdtn4iIEPRjCuZqPYAC7XWYN4A==@nongnu.org X-Gm-Message-State: AOJu0Yzhr1+Y/ngCEtAsycNgyLMEzAyGtWsoj4eMqgCl8mN9RBWep2/P krP3tn2YrmYs89+P4q85+CGlZuJWG0jxTdrmy5Fkq8BTBUBPyU3sYGps56be X-Gm-Gg: ASbGncsAdmiHD3KqRt5WLAb7dgmISbxoZ1aiX8vpc9+6IQHL/9qRRppABy0tQdTqpIi xV3xLnlSnqQu0U17AFw8/INrt2Q0hzgZEi6q8I22DAVeHghA7OIZaklNlK8qOpT9BRePUEtlvmA q75PEo8N8ythcvrRZ+6kYCQU46ETstgpfQMy7cgjKl20bgCle+5ZkxDJZpH1/JD8MGSBDRLbPph NaysRHe6vht4OiK06gLIoX5NwemAbbe9Op0UysvBTi0zsywm1dkVOfhr0H7DROrhS5AaJhh947a XuGRkVA4Cgm3LLYgN+rS7rnBfEwelsEv8r+C9GtG2kxttq/T7pu71H7SmabRtdYZVJo= X-Google-Smtp-Source: AGHT+IGY9c4APGKBp+xm0KfRaH0oxOof2+Jwm8vsWPIt+arlYfsaJlLTDrl4RgF+nBwnbdOyenjTkA== X-Received: by 2002:a17:907:2ce3:b0:ac2:c397:2b36 with SMTP id a640c23a62f3a-ac3302c92cfmr1630146266b.22.1742303453859; Tue, 18 Mar 2025 06:10:53 -0700 (PDT) Received: from corvink-nb.beckhoff.com ([195.226.174.194]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-ac3147f3101sm850678066b.69.2025.03.18.06.10.52 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 18 Mar 2025 06:10:53 -0700 (PDT) From: =?utf-8?q?Corvin_K=C3=B6hne?= To: qemu-devel@nongnu.org Cc: =?utf-8?q?Yannick_Vo=C3=9Fen?= , "Edgar E. Iglesias" , qemu-arm@nongnu.org, Peter Maydell , Alistair Francis , =?utf-8?q?Corvin_K=C3=B6hne?= , Paolo Bonzini , YannickV Subject: [PATCH 09/21] hw/misc: Add dummy ZYNQ DDR controller Date: Tue, 18 Mar 2025 14:08:00 +0100 Message-ID: <20250318130817.119636-10-corvin.koehne@gmail.com> X-Mailer: git-send-email 2.49.0 In-Reply-To: <20250318130817.119636-1-corvin.koehne@gmail.com> References: <20250318130817.119636-1-corvin.koehne@gmail.com> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::62a; envelope-from=corvin.koehne@gmail.com; helo=mail-ej1-x62a.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org From: YannickV A dummy DDR controller for ZYNQ has been added. While all registers are present, not all are functional. Read and write access is validated, and the user mode can be set. This provides a basic DDR controller initialization, preventing system hangs due to endless polling or similar issues. Signed-off-by: Yannick Voßen --- hw/misc/Kconfig | 3 + hw/misc/meson.build | 1 + hw/misc/zynq_ddr-ctrl.c | 331 ++++++++++++++++++++++++++++++++++++++++ 3 files changed, 335 insertions(+) create mode 100644 hw/misc/zynq_ddr-ctrl.c diff --git a/hw/misc/Kconfig b/hw/misc/Kconfig index ec0fa5aa9f..1bc4228572 100644 --- a/hw/misc/Kconfig +++ b/hw/misc/Kconfig @@ -222,4 +222,7 @@ config IOSB config XLNX_VERSAL_TRNG bool +config DDR_CTRLR + bool + source macio/Kconfig diff --git a/hw/misc/meson.build b/hw/misc/meson.build index 6d47de482c..8d4c4279c4 100644 --- a/hw/misc/meson.build +++ b/hw/misc/meson.build @@ -91,6 +91,7 @@ system_ss.add(when: 'CONFIG_RASPI', if_true: files( )) system_ss.add(when: 'CONFIG_SLAVIO', if_true: files('slavio_misc.c')) system_ss.add(when: 'CONFIG_ZYNQ', if_true: files('zynq_slcr.c')) +system_ss.add(when: 'CONFIG_ZYNQ', if_true: files('zynq_ddr-ctrl.c')) system_ss.add(when: 'CONFIG_XLNX_ZYNQMP_ARM', if_true: files('xlnx-zynqmp-crf.c')) system_ss.add(when: 'CONFIG_XLNX_ZYNQMP_ARM', if_true: files('xlnx-zynqmp-apu-ctrl.c')) system_ss.add(when: 'CONFIG_XLNX_VERSAL', if_true: files( diff --git a/hw/misc/zynq_ddr-ctrl.c b/hw/misc/zynq_ddr-ctrl.c new file mode 100644 index 0000000000..8cdf8be743 --- /dev/null +++ b/hw/misc/zynq_ddr-ctrl.c @@ -0,0 +1,331 @@ +#include "qemu/osdep.h" +#include "hw/sysbus.h" +#include "hw/register.h" +#include "qemu/bitops.h" +#include "qemu/log.h" +#include "qapi/error.h" +#include "hw/registerfields.h" +#include "system/block-backend.h" +#include "exec/address-spaces.h" +#include "exec/memory.h" +#include "system/dma.h" + +#ifndef DDRCTRL_ERR_DEBUG +#define DDRCTRL_ERR_DEBUG 0 +#endif + +#define DB_PRINT_L(level, ...) do { \ + if (DDRCTRL_ERR_DEBUG > (level)) { \ + fprintf(stderr, ": %s: ", __func__); \ + fprintf(stderr, ## __VA_ARGS__); \ + } \ +} while (0) + +#define DB_PRINT(...) DB_PRINT_L(0, ## __VA_ARGS__) + +REG32(DDRC_CTRL, 0x00) +REG32(TWO_RANK_CFG, 0x04) +REG32(HPR_REG, 0x08) +REG32(LPR_REG, 0x0C) +REG32(WR_REG, 0x10) +REG32(DRAM_PARAM_REG0, 0x14) +REG32(DRAM_PARAM_REG1, 0x18) +REG32(DRAM_PARAM_REG2, 0x1C) +REG32(DRAM_PARAM_REG3, 0x20) +REG32(DRAM_PARAM_REG4, 0x24) +REG32(DRAM_INIT_PARAM, 0x28) +REG32(DRAM_EMR_REG, 0x2C) +REG32(DRAM_EMR_MR_REG, 0x30) +REG32(DRAM_BURST8_RDWR, 0x34) +REG32(DRAM_DISABLE_DQ, 0x38) +REG32(DRAM_ADDR_MAP_BANK, 0x3C) +REG32(DRAM_ADDR_MAP_COL, 0x40) +REG32(DRAM_ADDR_MAP_ROW, 0x44) +REG32(DRAM_ODT_REG, 0x48) +REG32(PHY_DBG_REG, 0x4C) +REG32(PHY_CMD_TIMEOUT_RDDA, 0x50) +REG32(TA_CPT, 0x50) +REG32(MODE_STS_REG, 0x54) + FIELD(MODE_STS_REG, DDR_REG_DBG_STALL, 3, 3) + FIELD(MODE_STS_REG, DDR_REG_OPERATING_MODE, 0, 2) +REG32(DLL_CALIB, 0x58) +REG32(ODT_DELAY_HOLD, 0x5C) +REG32(CTRL_REG1, 0x60) +REG32(CTRL_REG2, 0x64) +REG32(CTRL_REG3, 0x68) +REG32(CTRL_REG4, 0x6C) +REG32(CTRL_REG5, 0x78) +REG32(CTRL_REG6, 0x7C) +REG32(CHE_REFRESH_TIMER0, 0xA0) +REG32(CHE_T_ZQ, 0xA4) +REG32(CHE_T_ZQ_SHORT_INTERVAL_REG, 0xA8) +REG32(DEEP_PWRDWN_REG, 0xAC) +REG32(REG_2C, 0xB0) +REG32(REG_2D, 0xB4) +REG32(DFI_TIMING, 0xB8) +REG32(CHE_ECC_CONTROL_REG_OFFSET, 0xC4) +REG32(CHE_CORR_ECC_LOG_REG_OFFSET, 0xC8) +REG32(CHE_CORR_ECC_ADDR_REG_OFFSET, 0xCC) +REG32(CHE_CORR_ECC_DATA_31_0_REG_OFFSET, 0xD0) +REG32(CHE_CORR_ECC_DATA_63_32_REG_OFFSET, 0xD4) +REG32(CHE_CORR_ECC_DATA_71_64_REG_OFFSET, 0xD8) +REG32(CHE_UNCORR_ECC_LOG_REG_OFFSET, 0xDC) +REG32(CHE_UNCORR_ECC_ADDR_REG_OFFSET, 0xE0) +REG32(CHE_UNCORR_ECC_DATA_31_0_REG_OFFSET, 0xE4) +REG32(CHE_UNCORR_ECC_DATA_63_32_REG_OFFSET, 0xE8) +REG32(CHE_UNCORR_ECC_DATA_71_64_REG_OFFSET, 0xEC) +REG32(CHE_ECC_STATS_REG_OFFSET, 0xF0) +REG32(ECC_SCRUB, 0xF4) +REG32(CHE_ECC_CORR_BIT_MASK_31_0_REG_OFFSET, 0xF8) +REG32(CHE_ECC_CORR_BIT_MASK_63_32_REG_OFFSET, 0xFC) +REG32(PHY_RCVER_ENABLE, 0x114) +REG32(PHY_CONFIG0, 0x118) +REG32(PHY_CONFIG1, 0x11C) +REG32(PHY_CONFIG2, 0x120) +REG32(PHY_CONFIG3, 0x124) +REG32(PHY_INIT_RATIO0, 0x12C) +REG32(PHY_INIT_RATIO1, 0x130) +REG32(PHY_INIT_RATIO2, 0x134) +REG32(PHY_INIT_RATIO3, 0x138) +REG32(PHY_RD_DQS_CFG0, 0x140) +REG32(PHY_RD_DQS_CFG1, 0x144) +REG32(PHY_RD_DQS_CFG2, 0x148) +REG32(PHY_RD_DQS_CFG3, 0x14C) +REG32(PHY_WR_DQS_CFG0, 0x154) +REG32(PHY_WR_DQS_CFG1, 0x158) +REG32(PHY_WR_DQS_CFG2, 0x15C) +REG32(PHY_WR_DQS_CFG3, 0x160) +REG32(PHY_WE_CFG0, 0x168) +REG32(PHY_WE_CFG1, 0x16C) +REG32(PHY_WE_CFG2, 0x170) +REG32(PHY_WE_CFG3, 0x174) +REG32(WR_DATA_SLV0, 0x17C) +REG32(WR_DATA_SLV1, 0x180) +REG32(WR_DATA_SLV2, 0x184) +REG32(WR_DATA_SLV3, 0x188) +REG32(REG_64, 0x190) +REG32(REG_65, 0x194) +REG32(REG69_6A0, 0x1A4) +REG32(REG69_6A1, 0x1A8) +REG32(REG6C_6D2, 0x1B0) +REG32(REG6C_6D3, 0x1B4) +REG32(REG6E_710, 0x1B8) +REG32(REG6E_711, 0x1BC) +REG32(REG6E_712, 0x1C0) +REG32(REG6E_713, 0x1C4) +REG32(PHY_DLL_STS0, 0x1CC) +REG32(PHY_DLL_STS1, 0x1D0) +REG32(PHY_DLL_STS2, 0x1D4) +REG32(PHY_DLL_STS3, 0x1D8) +REG32(DLL_LOCK_STS, 0x1E0) +REG32(PHY_CTRL_STS, 0x1E4) +REG32(PHY_CTRL_STS_REG2, 0x1E8) +REG32(AXI_ID, 0x200) +REG32(PAGE_MASK, 0x204) +REG32(AXI_PRIORITY_WR_PORT0, 0x208) +REG32(AXI_PRIORITY_WR_PORT1, 0x20C) +REG32(AXI_PRIORITY_WR_PORT2, 0x210) +REG32(AXI_PRIORITY_WR_PORT3, 0x214) +REG32(AXI_PRIORITY_RD_PORT0, 0x218) +REG32(AXI_PRIORITY_RD_PORT1, 0x21C) +REG32(AXI_PRIORITY_RD_PORT2, 0x220) +REG32(AXI_PRIORITY_RD_PORT3, 0x224) +REG32(EXCL_ACCESS_CFG0, 0x294) +REG32(EXCL_ACCESS_CFG1, 0x298) +REG32(EXCL_ACCESS_CFG2, 0x29C) +REG32(EXCL_ACCESS_CFG3, 0x2A0) +REG32(MODE_REG_READ, 0x2A4) +REG32(LPDDR_CTRL0, 0x2A8) +REG32(LPDDR_CTRL1, 0x2AC) +REG32(LPDDR_CTRL2, 0x2B0) +REG32(LPDDR_CTRL3, 0x2B4) + + +#define ZYNQ_DDRCTRL_MMIO_SIZE 0x400 +#define ZYNQ_DDRCTRL_NUM_REG (ZYNQ_DDRCTRL_MMIO_SIZE / 4) + +#define TYPE_DDRCTRL "zynq.ddr-ctlr" +#define DDRCTRL(obj) \ + OBJECT_CHECK(DDRCTRLState, (obj), TYPE_DDRCTRL) + +typedef struct DDRCTRLState { + SysBusDevice parent_obj; + + MemoryRegion iomem; + + uint32_t reg[ZYNQ_DDRCTRL_NUM_REG]; +} DDRCTRLState; + + +static bool zynq_ddrctrl_check_addr(hwaddr addr, bool rnw) +{ + switch (addr) { + case R_PHY_DBG_REG: + case R_MODE_STS_REG: + case R_CHE_CORR_ECC_LOG_REG_OFFSET ... + R_CHE_CORR_ECC_DATA_71_64_REG_OFFSET: + case R_CHE_UNCORR_ECC_ADDR_REG_OFFSET ... + R_CHE_UNCORR_ECC_DATA_71_64_REG_OFFSET: + case R_CHE_ECC_CORR_BIT_MASK_31_0_REG_OFFSET: + case R_CHE_ECC_CORR_BIT_MASK_63_32_REG_OFFSET: + case R_REG69_6A0 ... R_AXI_ID: + case R_MODE_REG_READ: + return rnw; + default: + return true; + } +} + +static void zynq_ddrctrl_reset_init(Object *obj, ResetType type) +{ + DDRCTRLState *s = DDRCTRL(obj); + + DB_PRINT("RESET"); + + s->reg[R_DDRC_CTRL] = 0x00000200; + s->reg[R_TWO_RANK_CFG] = 0x000C1076; + s->reg[R_HPR_REG] = 0x03C0780F; + s->reg[R_LPR_REG] = 0x03C0780F; + s->reg[R_WR_REG] = 0x0007F80F; + s->reg[R_DRAM_PARAM_REG0] = 0x00041016; + s->reg[R_DRAM_PARAM_REG1] = 0x351B48D9; + s->reg[R_DRAM_PARAM_REG2] = 0x83015904; + s->reg[R_DRAM_PARAM_REG3] = 0x250882D0; + s->reg[R_DRAM_PARAM_REG4] = 0x0000003C; + s->reg[R_DRAM_INIT_PARAM] = 0x00002007; + s->reg[R_DRAM_EMR_REG] = 0x00000008; + s->reg[R_DRAM_EMR_MR_REG] = 0x00000940; + s->reg[R_DRAM_BURST8_RDWR] = 0x00020034; + s->reg[R_DRAM_ADDR_MAP_BANK] = 0x00000F77; + s->reg[R_DRAM_ADDR_MAP_COL] = 0xFFF00000; + s->reg[R_DRAM_ADDR_MAP_ROW] = 0x0FF55555; + s->reg[R_DRAM_ODT_REG] = 0x00000249; + s->reg[R_PHY_CMD_TIMEOUT_RDDA] = 0x00010200; + s->reg[R_DLL_CALIB] = 0x00000101; + s->reg[R_ODT_DELAY_HOLD] = 0x00000023; + s->reg[R_CTRL_REG1] = 0x0000003E; + s->reg[R_CTRL_REG2] = 0x00020000; + s->reg[R_CTRL_REG3] = 0x00284027; + s->reg[R_CTRL_REG4] = 0x00001610; + s->reg[R_CTRL_REG5] = 0x00455111; + s->reg[R_CTRL_REG6] = 0x00032222; + s->reg[R_CHE_REFRESH_TIMER0] = 0x00008000; + s->reg[R_CHE_T_ZQ] = 0x10300802; + s->reg[R_CHE_T_ZQ_SHORT_INTERVAL_REG] = 0x0020003A; + s->reg[R_REG_2D] = 0x00000200; + s->reg[R_DFI_TIMING] = 0x00200067; + s->reg[R_ECC_SCRUB] = 0x00000008; + s->reg[R_PHY_CONFIG0] = 0x40000001; + s->reg[R_PHY_CONFIG1] = 0x40000001; + s->reg[R_PHY_CONFIG2] = 0x40000001; + s->reg[R_PHY_CONFIG3] = 0x40000001; + s->reg[R_PHY_RD_DQS_CFG0] = 0x00000040; + s->reg[R_PHY_RD_DQS_CFG1] = 0x00000040; + s->reg[R_PHY_RD_DQS_CFG2] = 0x00000040; + s->reg[R_PHY_RD_DQS_CFG3] = 0x00000040; + s->reg[R_PHY_WE_CFG0] = 0x00000040; + s->reg[R_PHY_WE_CFG1] = 0x00000040; + s->reg[R_PHY_WE_CFG2] = 0x00000040; + s->reg[R_PHY_WE_CFG3] = 0x00000040; + s->reg[R_WR_DATA_SLV0] = 0x00000080; + s->reg[R_WR_DATA_SLV1] = 0x00000080; + s->reg[R_WR_DATA_SLV2] = 0x00000080; + s->reg[R_WR_DATA_SLV3] = 0x00000080; + s->reg[R_REG_64] = 0x10020000; + s->reg[R_AXI_PRIORITY_WR_PORT0] = 0x000803FF; + s->reg[R_AXI_PRIORITY_WR_PORT1] = 0x000803FF; + s->reg[R_AXI_PRIORITY_WR_PORT2] = 0x000803FF; + s->reg[R_AXI_PRIORITY_WR_PORT3] = 0x000803FF; + s->reg[R_AXI_PRIORITY_RD_PORT0] = 0x000003FF; + s->reg[R_AXI_PRIORITY_RD_PORT1] = 0x000003FF; + s->reg[R_AXI_PRIORITY_RD_PORT2] = 0x000003FF; + s->reg[R_AXI_PRIORITY_RD_PORT3] = 0x000003FF; + s->reg[R_LPDDR_CTRL2] = 0x003C0015; + s->reg[R_LPDDR_CTRL3] = 0x00000601; +} + +static uint64_t zynq_ddrctrl_read(void *opaque, hwaddr addr, unsigned size) +{ + DDRCTRLState *s = opaque; + addr /= 4; + uint32_t ret = s->reg[addr]; + + if (!zynq_ddrctrl_check_addr(addr, true)) { + qemu_log_mask(LOG_GUEST_ERROR, "zynq_slcr: Invalid read access to " + " addr %" HWADDR_PRIx "\n", addr * 4); + return 0; + } + + DB_PRINT("addr: %08" HWADDR_PRIx " data: %08" PRIx32 "\n", addr * 4, ret); + return ret; +} + +static void zynq_ddrctrl_write(void *opaque, hwaddr addr, uint64_t val, + unsigned size) +{ + DDRCTRLState *s = opaque; + addr /= 4; + + if (!zynq_ddrctrl_check_addr(addr, false)) { + qemu_log_mask(LOG_GUEST_ERROR, "zynq_slcr: Invalid read access to " + " addr %" HWADDR_PRIx "\n", addr * 4); + return; + } + + DB_PRINT("addr: %08" HWADDR_PRIx " data: %08" PRIx64 "\n", addr * 4, val); + + switch (addr) { + case R_DDRC_CTRL: + if (val & 0x1) { + s->reg[R_MODE_STS_REG] |= + (R_MODE_STS_REG_DDR_REG_OPERATING_MODE_MASK & 0x1); + } else { + s->reg[R_MODE_STS_REG] &= + ~R_MODE_STS_REG_DDR_REG_OPERATING_MODE_MASK; + } + break; + } + + s->reg[addr] = val; +} + +static const MemoryRegionOps ddrctrl_ops = { + .read = zynq_ddrctrl_read, + .write = zynq_ddrctrl_write, + .endianness = DEVICE_LITTLE_ENDIAN, +}; + +static void zynq_ddrctrl_init(Object *obj) +{ + DB_PRINT("Init\n"); + + DDRCTRLState *s = DDRCTRL(obj); + + memory_region_init_io(&s->iomem, obj, &ddrctrl_ops, s, "ddrctrl", + ZYNQ_DDRCTRL_MMIO_SIZE); + sysbus_init_mmio(SYS_BUS_DEVICE(obj), &s->iomem); +} + +static void zynq_ddrctrl_class_init(ObjectClass *klass, void *data) +{ + DB_PRINT("Class init\n"); + + ResettableClass *rc = RESETTABLE_CLASS(klass); + + rc->phases.enter = zynq_ddrctrl_reset_init; +} + +static const TypeInfo ddrctrl_info = { + .name = TYPE_DDRCTRL, + .parent = TYPE_SYS_BUS_DEVICE, + .instance_size = sizeof(DDRCTRLState), + .class_init = zynq_ddrctrl_class_init, + .instance_init = zynq_ddrctrl_init, +}; + +static void ddrctrl_register_types(void) +{ + type_register_static(&ddrctrl_info); +} + +type_init(ddrctrl_register_types) From patchwork Tue Mar 18 13:08:01 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Corvin_K=C3=B6hne?= X-Patchwork-Id: 14020991 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 25667C282EC for ; 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Tue, 18 Mar 2025 06:10:57 -0700 (PDT) From: =?utf-8?q?Corvin_K=C3=B6hne?= To: qemu-devel@nongnu.org, qemu-arm@nongnu.org Cc: =?utf-8?q?Yannick_Vo=C3=9Fen?= , "Edgar E. Iglesias" , Peter Maydell , Alistair Francis , =?utf-8?q?Corvin_K=C3=B6hne?= , Paolo Bonzini , YannickV Subject: [PATCH 10/21] hw/misc/zynq_slcr: Add logic for DCI configuration Date: Tue, 18 Mar 2025 14:08:01 +0100 Message-ID: <20250318130817.119636-11-corvin.koehne@gmail.com> X-Mailer: git-send-email 2.49.0 In-Reply-To: <20250318130817.119636-1-corvin.koehne@gmail.com> References: <20250318130817.119636-1-corvin.koehne@gmail.com> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::636; envelope-from=corvin.koehne@gmail.com; helo=mail-ej1-x636.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org From: YannickV The registers for the digitally controlled impedance (DCI) clock are part of the system level control registers (SLCR). The DONE bit in the status register indicates a successfull DCI calibration. An description of the calibration process can be found here: https://docs.amd.com/r/en-US/ug585-zynq-7000-SoC-TRM/DDR-IOB-Impedance-Calibration The DCI control register and status register have been added. As soon as the ENABLE and RESET bit are set, the RESET bit has also been toggled to 0 before and the UPDATE_CONTROL is not set, the DONE bit in the status register is set. If these bits change the DONE bit is reset. Note that the option bits are not taken into consideration. Signed-off-by: Yannick Voßen --- hw/misc/zynq_slcr.c | 31 +++++++++++++++++++++++++++++++ 1 file changed, 31 insertions(+) diff --git a/hw/misc/zynq_slcr.c b/hw/misc/zynq_slcr.c index 9b3220f354..10ef8ecee8 100644 --- a/hw/misc/zynq_slcr.c +++ b/hw/misc/zynq_slcr.c @@ -181,6 +181,12 @@ REG32(GPIOB_CFG_HSTL, 0xb14) REG32(GPIOB_DRVR_BIAS_CTRL, 0xb18) REG32(DDRIOB, 0xb40) +REG32(DDRIOB_DCI_CTRL, 0xb70) + FIELD(DDRIOB_DCI_CTRL, RESET, 0, 1) + FIELD(DDRIOB_DCI_CTRL, ENABLE, 1, 1) + FIELD(DDRIOB_DCI_CTRL, UPDATE_CONTROL, 20, 1) +REG32(DDRIOB_DCI_STATUS, 0xb74) + FIELD(DDRIOB_DCI_STATUS, DONE, 13, 1) #define DDRIOB_LENGTH 14 #define ZYNQ_SLCR_MMIO_SIZE 0x1000 @@ -194,6 +200,8 @@ struct ZynqSLCRState { MemoryRegion iomem; + bool ddriob_dci_ctrl_reset_toggled; + uint32_t regs[ZYNQ_SLCR_NUM_REGS]; Clock *ps_clk; @@ -332,6 +340,8 @@ static void zynq_slcr_reset_init(Object *obj, ResetType type) DB_PRINT("RESET\n"); + s->ddriob_dci_ctrl_reset_toggled = false; + s->regs[R_LOCKSTA] = 1; /* 0x100 - 0x11C */ s->regs[R_ARM_PLL_CTRL] = 0x0001A008; @@ -419,6 +429,8 @@ static void zynq_slcr_reset_init(Object *obj, ResetType type) s->regs[R_DDRIOB + 4] = s->regs[R_DDRIOB + 5] = s->regs[R_DDRIOB + 6] = 0x00000e00; s->regs[R_DDRIOB + 12] = 0x00000021; + + s->regs[R_DDRIOB_DCI_CTRL] = 0x00000020; } static void zynq_slcr_reset_hold(Object *obj, ResetType type) @@ -555,6 +567,25 @@ static void zynq_slcr_write(void *opaque, hwaddr offset, (int)offset, (unsigned)val & 0xFFFF); } return; + + case R_DDRIOB_DCI_CTRL: + if (!FIELD_EX32(val, DDRIOB_DCI_CTRL, RESET) && + FIELD_EX32(s->regs[R_DDRIOB_DCI_CTRL], DDRIOB_DCI_CTRL, RESET)) { + + s->ddriob_dci_ctrl_reset_toggled = true; + DB_PRINT("DDRIOB DCI CTRL RESET was toggled\n"); + } + + if (FIELD_EX32(val, DDRIOB_DCI_CTRL, ENABLE) && + FIELD_EX32(val, DDRIOB_DCI_CTRL, RESET) && + !FIELD_EX32(val, DDRIOB_DCI_CTRL, UPDATE_CONTROL) && + s->ddriob_dci_ctrl_reset_toggled) { + + s->regs[R_DDRIOB_DCI_STATUS] |= R_DDRIOB_DCI_STATUS_DONE_MASK; + } else { + s->regs[R_DDRIOB_DCI_STATUS] &= ~R_DDRIOB_DCI_STATUS_DONE_MASK; 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Tue, 18 Mar 2025 06:11:08 -0700 (PDT) Received: from corvink-nb.beckhoff.com ([195.226.174.194]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-ac3147f3101sm850678066b.69.2025.03.18.06.11.07 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 18 Mar 2025 06:11:07 -0700 (PDT) From: =?utf-8?q?Corvin_K=C3=B6hne?= To: qemu-devel@nongnu.org, =?utf-8?q?Corvin_K=C3=B6hne?= , qemu-arm@nongnu.org Cc: =?utf-8?q?Yannick_Vo=C3=9Fen?= , "Edgar E. Iglesias" , Peter Maydell , Alistair Francis , Paolo Bonzini , YannickV Subject: [PATCH 11/21] hw/misc: Add Beckhoff CCAT device Date: Tue, 18 Mar 2025 14:08:02 +0100 Message-ID: <20250318130817.119636-12-corvin.koehne@gmail.com> X-Mailer: git-send-email 2.49.0 In-Reply-To: <20250318130817.119636-1-corvin.koehne@gmail.com> References: <20250318130817.119636-1-corvin.koehne@gmail.com> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::632; envelope-from=corvin.koehne@gmail.com; helo=mail-ej1-x632.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org From: YannickV This adds the Beckhoff Communication Controller (CCAT). The information block, EEPROM interface and DMA controller are currently implemented. The EEPROM provides production information for Beckhoff Devices. An EEPORM binary must therefor be handed over. It should be aligned to a power of two. If no EEPROM binary is handed over an empty EEPROM of size 4096 is initialized. This device is needed for the Beckhoff CX7200 board emulation. Signed-off-by: Yannick Voßen --- hw/misc/Kconfig | 3 + hw/misc/beckhoff_ccat.c | 365 ++++++++++++++++++++++++++++++++++++++++ hw/misc/meson.build | 1 + 3 files changed, 369 insertions(+) create mode 100644 hw/misc/beckhoff_ccat.c diff --git a/hw/misc/Kconfig b/hw/misc/Kconfig index 1bc4228572..c264862046 100644 --- a/hw/misc/Kconfig +++ b/hw/misc/Kconfig @@ -225,4 +225,7 @@ config XLNX_VERSAL_TRNG config DDR_CTRLR bool +config BECKHOFF_CCAT + bool + source macio/Kconfig diff --git a/hw/misc/beckhoff_ccat.c b/hw/misc/beckhoff_ccat.c new file mode 100644 index 0000000000..3ab1259702 --- /dev/null +++ b/hw/misc/beckhoff_ccat.c @@ -0,0 +1,365 @@ +/* + * Beckhoff Communication Controller Emulation + * + * Copyright (c) Beckhoff Automation GmbH. & Co. KG + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the + * Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License + * for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, see . + */ + +#include "qemu/osdep.h" +#include "hw/sysbus.h" +#include "hw/register.h" +#include "qemu/bitops.h" +#include "qemu/log.h" +#include "qapi/error.h" +#include "system/block-backend.h" +#include "exec/address-spaces.h" +#include "exec/memory.h" +#include "system/dma.h" +#include "qemu/error-report.h" +#include "block/block.h" +#include "block/block_int.h" +#include "block/qdict.h" +#include "hw/block/block.h" + +#ifndef CCAT_ERR_DEBUG +#define CCAT_ERR_DEBUG 0 +#endif + +#define DB_PRINT_L(level, ...) do { \ + if (CCAT_ERR_DEBUG > (level)) { \ + fprintf(stderr, ": %s: ", __func__); \ + fprintf(stderr, ## __VA_ARGS__); \ + } \ +} while (0) + +#define DB_PRINT(...) DB_PRINT_L(0, ## __VA_ARGS__) + +#define TYPE_BECKHOFF_CCAT "beckhoff-ccat" +#define BECKHOFF_CCAT(obj) \ + OBJECT_CHECK(BeckhoffCcat, (obj), TYPE_BECKHOFF_CCAT) + +#define MAX_NUM_SLOTS 32 + +#define CCAT_EEPROM_OFFSET 0x100 +#define CCAT_DMA_OFFSET 0x8000 + +#define CCAT_MEM_SIZE 0xFFFF +#define CCAT_DMA_SIZE 0x800 +#define CCAT_EEPROM_SIZE 0x20 + +#define EEPROM_MEMORY_SIZE 0x1000 + +#define EEPROM_CMD_OFFSET (CCAT_EEPROM_OFFSET + 0x00) + #define EEPROM_CMD_WRITE_MASK 0x2 + #define EEPROM_CMD_READ_MASK 0x1 +#define EEPROM_ADR_OFFSET (CCAT_EEPROM_OFFSET + 0x04) +#define EEPROM_DATA_OFFSET (CCAT_EEPROM_OFFSET + 0x08) + +#define DMA_BUFFER_OFFSET (CCAT_DMA_OFFSET + 0x00) +#define DMA_DIRECTION_OFFSET (CCAT_DMA_OFFSET + 0x7c0) + #define DMA_DIRECTION_MASK 1 +#define DMA_TRANSFER_OFFSET (CCAT_DMA_OFFSET + 0x7c4) +#define DMA_HOST_ADR_OFFSET (CCAT_DMA_OFFSET + 0x7c8) +#define DMA_TRANSFER_LENGTH_OFFSET (CCAT_DMA_OFFSET + 0x7cc) + +/* + * The informationblock is always located at address 0x0. + * Address and size are therefor replaced by two identifiers. + * The Parameter give information about the maximal number of + * function slots and the creation date (in this case 01.01.2001) + */ +#define CCAT_ID_1 0x88a4 +#define CCAT_ID_2 0x54414343 +#define CCAT_INFO_BLOCK_PARAMS (MAX_NUM_SLOTS << 0) | (0x1 << 8) | \ + (0x1 << 16) | (0x1 << 24) + +#define CCAT_FUN_TYPE_ENTRY 0x0001 +#define CCAT_FUN_TYPE_EEPROM 0x0012 +#define CCAT_FUN_TYPE_DMA 0x0013 + +typedef struct BeckhoffCcat { + SysBusDevice parent_obj; + + MemoryRegion iomem; + + uint8_t mem[CCAT_MEM_SIZE]; + + BlockBackend *eeprom_blk; + uint8_t *eeprom_storage; + int64_t eeprom_size; +} BeckhoffCcat; + +typedef struct __attribute__((packed)) CcatFunctionBlock { + uint16_t type; + uint16_t revision; + uint32_t parameter; + uint32_t address_offset; + uint32_t size; +} CcatFunctionBlock; + +static void sync_eeprom(BeckhoffCcat *s) +{ + if (!s->eeprom_blk) { + return; + } + blk_pwrite(s->eeprom_blk, 0, s->eeprom_size, s->eeprom_storage, 0); +} + +static uint64_t beckhoff_ccat_eeprom_read(void *opaque, hwaddr addr, + unsigned size) +{ + BeckhoffCcat *s = opaque; + uint64_t val = 0; + memcpy(&val, &s->mem[addr], size); + return val; +} + +static void beckhoff_ccat_eeprom_write(void *opaque, hwaddr addr, uint64_t val, + unsigned size) +{ + BeckhoffCcat *s = opaque; + uint64_t eeprom_adr; + switch (addr) { + case EEPROM_CMD_OFFSET: + eeprom_adr = *(uint32_t *)&s->mem[EEPROM_ADR_OFFSET]; + eeprom_adr = (eeprom_adr * 2) % s->eeprom_size; + if (val & EEPROM_CMD_READ_MASK) { + uint64_t buf = 0; + uint32_t bytes_to_read = 8; + if (eeprom_adr > s->eeprom_size - 8) { + bytes_to_read = s->eeprom_size - eeprom_adr; + } + memcpy(&buf, s->eeprom_storage + eeprom_adr, bytes_to_read); + *(uint64_t *)&s->mem[EEPROM_DATA_OFFSET] = buf; + + } else if (val & EEPROM_CMD_WRITE_MASK) { + uint32_t buf = *(uint32_t *)&s->mem[EEPROM_DATA_OFFSET]; + memcpy(s->eeprom_storage + eeprom_adr, &buf, 2); + sync_eeprom(s); + } + break; + default: + memcpy(&s->mem[addr], &val, size); + } +} + +static uint64_t beckhoff_ccat_dma_read(void *opaque, hwaddr addr, unsigned size) +{ + BeckhoffCcat *s = opaque; + uint64_t val = 0; + + switch (addr) { + case DMA_TRANSFER_OFFSET: + if (s->mem[DMA_TRANSFER_OFFSET] & 0x1) { + DB_PRINT("DMA transfer finished\n"); + s->mem[DMA_TRANSFER_OFFSET] = 0; + } + break; + } + memcpy(&val, &s->mem[addr], size); + return val; +} + +static void beckhoff_ccat_dma_write(void *opaque, hwaddr addr, uint64_t val, + unsigned size) +{ + BeckhoffCcat *s = opaque; + switch (addr) { + case DMA_TRANSFER_OFFSET: + uint8_t len = s->mem[DMA_TRANSFER_LENGTH_OFFSET]; + uint8_t *mem_buf = &s->mem[DMA_BUFFER_OFFSET]; + + if (s->mem[DMA_DIRECTION_OFFSET] & DMA_DIRECTION_MASK) { + dma_addr_t dmaAddr = *(uint32_t *)&s->mem[DMA_HOST_ADR_OFFSET]; + dma_memory_read(&address_space_memory, dmaAddr, + mem_buf, len * 8, MEMTXATTRS_UNSPECIFIED); + } else { + dma_addr_t dmaAddr = *(uint32_t *)&s->mem[DMA_HOST_ADR_OFFSET]; + dma_memory_write(&address_space_memory, dmaAddr + 8, + mem_buf, len * 8, MEMTXATTRS_UNSPECIFIED); + } + break; + } + memcpy(&s->mem[addr], &val, size); +} +static uint64_t beckhoff_ccat_read(void *opaque, hwaddr addr, unsigned size) +{ + DB_PRINT("CCAT_READ addr=0x%lx size=%u\n", addr, size); + + BeckhoffCcat *s = opaque; + uint64_t val = 0; + + if (addr > CCAT_MEM_SIZE - size) { + error_report("Overflow. Address or size is too large.\n"); + exit(1); + } + + if (addr >= CCAT_EEPROM_OFFSET && + addr <= CCAT_EEPROM_OFFSET + s->eeprom_size) { + return beckhoff_ccat_eeprom_read(opaque, addr, size); + } else if (addr >= CCAT_DMA_OFFSET && + addr <= CCAT_DMA_OFFSET + CCAT_DMA_SIZE) { + return beckhoff_ccat_dma_read(opaque, addr, size); + } else { + memcpy(&val, &s->mem[addr], size); + } + + return val; +} + +static void beckhoff_ccat_write(void *opaque, hwaddr addr, uint64_t val, + unsigned size) +{ + DB_PRINT("CCAT_WRITE addr=0x%lx size=%u val=0x%lx\n", addr, size, val); + + BeckhoffCcat *s = opaque; + + if (addr > CCAT_MEM_SIZE - size) { + error_report("Overflow. Address or size is too large.\n"); + exit(1); + } + + if (addr >= CCAT_EEPROM_OFFSET && + addr <= CCAT_EEPROM_OFFSET + s->eeprom_size) { + beckhoff_ccat_eeprom_write(opaque, addr, val, size); + } else if (addr >= CCAT_DMA_OFFSET && + addr <= CCAT_DMA_OFFSET + CCAT_DMA_SIZE) { + beckhoff_ccat_dma_write(opaque, addr, val, size); + } else { + memcpy(&s->mem[addr], &val, size); + } +} + +static const MemoryRegionOps beckhoff_ccat_ops = { + .read = beckhoff_ccat_read, + .write = beckhoff_ccat_write, + .endianness = DEVICE_LITTLE_ENDIAN, + .valid = { + .min_access_size = 1, + .max_access_size = 8, + }, +}; + + +static void beckhoff_ccat_reset(DeviceState *dev) +{ + BeckhoffCcat *s = BECKHOFF_CCAT(dev); + + CcatFunctionBlock function_blocks[MAX_NUM_SLOTS] = {0}; + + CcatFunctionBlock info_block = { + .type = CCAT_FUN_TYPE_ENTRY, + .revision = 0x0001, + .parameter = CCAT_INFO_BLOCK_PARAMS, + .address_offset = CCAT_ID_1, + .size = CCAT_ID_2 + }; + CcatFunctionBlock eeprom_block = { + .type = CCAT_FUN_TYPE_EEPROM, + .revision = 0x0001, + .parameter = 0, + .address_offset = CCAT_EEPROM_OFFSET, + .size = CCAT_EEPROM_SIZE + }; + CcatFunctionBlock dma_block = { + .type = CCAT_FUN_TYPE_DMA, + .revision = 0x0000, + .parameter = 0, + .address_offset = CCAT_DMA_OFFSET, + .size = CCAT_DMA_SIZE + }; + + /* + * The EEPROM interface is usually at function slot 11. + * The DMA controller is usually at function slot 15. + */ + function_blocks[0] = info_block; + function_blocks[11] = eeprom_block; + function_blocks[15] = dma_block; + + memcpy(&s->mem[0], function_blocks, sizeof(function_blocks)); +} + +static void beckhoff_ccat_realize(DeviceState *dev, Error **errp) +{ + BeckhoffCcat *s = BECKHOFF_CCAT(dev); + BlockBackend *blk; + + blk = blk_by_name("ccat-eeprom"); + + if (blk) { + uint64_t blk_size = blk_getlength(blk); + if (!is_power_of_2(blk_size)) { + error_report("Blockend size is not a power of two."); + } + + if (blk_size < 512) { + error_report("Blockend size is too small. Using backup."); + s->eeprom_size = EEPROM_MEMORY_SIZE; + s->eeprom_storage = blk_blockalign(NULL, s->eeprom_size); + memset(s->eeprom_storage, 0x00, s->eeprom_size); + } else { + DB_PRINT("EEPROM block backend found\n"); + blk_set_perm(blk, BLK_PERM_WRITE, BLK_PERM_ALL, errp); + + s->eeprom_size = blk_size; + s->eeprom_blk = blk; + s->eeprom_storage = blk_blockalign(s->eeprom_blk, s->eeprom_size); + + if (!blk_check_size_and_read_all(s->eeprom_blk, DEVICE(s), + s->eeprom_storage, s->eeprom_size, + errp)) { + exit(1); + } + } + } else { + s->eeprom_size = EEPROM_MEMORY_SIZE; + s->eeprom_storage = blk_blockalign(NULL, s->eeprom_size); + memset(s->eeprom_storage, 0x00, s->eeprom_size); + } + + beckhoff_ccat_reset(dev); +} + +static void beckhoff_ccat_init(Object *obj) +{ + BeckhoffCcat *s = BECKHOFF_CCAT(obj); + SysBusDevice *sbd = SYS_BUS_DEVICE(obj); + + memory_region_init_io(&s->iomem, obj, &beckhoff_ccat_ops, s, + TYPE_BECKHOFF_CCAT, CCAT_MEM_SIZE); + sysbus_init_mmio(sbd, &s->iomem); +} + +static void beckhoff_ccat_class_init(ObjectClass *klass, void *data) +{ + DeviceClass *dc = DEVICE_CLASS(klass); + dc->realize = beckhoff_ccat_realize; +} + +static const TypeInfo beckhoff_ccat_info = { + .name = TYPE_BECKHOFF_CCAT, + .parent = TYPE_SYS_BUS_DEVICE, + .instance_size = sizeof(BeckhoffCcat), + .class_init = beckhoff_ccat_class_init, + .instance_init = beckhoff_ccat_init, +}; + +static void beckhoff_ccat_register_types(void) +{ + type_register_static(&beckhoff_ccat_info); +} + +type_init(beckhoff_ccat_register_types) diff --git a/hw/misc/meson.build b/hw/misc/meson.build index 8d4c4279c4..ca0b261715 100644 --- a/hw/misc/meson.build +++ b/hw/misc/meson.build @@ -14,6 +14,7 @@ system_ss.add(when: 'CONFIG_PL310', if_true: files('arm_l2x0.c')) system_ss.add(when: 'CONFIG_INTEGRATOR_DEBUG', if_true: files('arm_integrator_debug.c')) system_ss.add(when: 'CONFIG_A9SCU', if_true: files('a9scu.c')) system_ss.add(when: 'CONFIG_ARM11SCU', if_true: files('arm11scu.c')) +system_ss.add(when: 'CONFIG_BECKHOFF_CCAT', if_true: files('beckhoff_ccat.c')) system_ss.add(when: 'CONFIG_ARM_V7M', if_true: files('armv7m_ras.c')) From patchwork Tue Mar 18 13:08:03 2025 Content-Type: text/plain; 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Tue, 18 Mar 2025 06:11:10 -0700 (PDT) Received: from corvink-nb.beckhoff.com ([195.226.174.194]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-ac3147f3101sm850678066b.69.2025.03.18.06.11.09 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 18 Mar 2025 06:11:10 -0700 (PDT) From: =?utf-8?q?Corvin_K=C3=B6hne?= To: qemu-devel@nongnu.org, =?utf-8?q?Corvin_K=C3=B6hne?= , qemu-arm@nongnu.org Cc: =?utf-8?q?Yannick_Vo=C3=9Fen?= , "Edgar E. Iglesias" , Peter Maydell , Alistair Francis , Paolo Bonzini , YannickV Subject: [PATCH 12/21] hw/arm: Add new machine based on xilinx-zynq-a9 for Beckhoff CX7200 Date: Tue, 18 Mar 2025 14:08:03 +0100 Message-ID: <20250318130817.119636-13-corvin.koehne@gmail.com> X-Mailer: git-send-email 2.49.0 In-Reply-To: <20250318130817.119636-1-corvin.koehne@gmail.com> References: <20250318130817.119636-1-corvin.koehne@gmail.com> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::52d; envelope-from=corvin.koehne@gmail.com; helo=mail-ed1-x52d.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org From: YannickV This commit introduces a new machine, derived from xilinx-zynq-a9, as a starting point for the Beckhoff CX7200 integration. Functions and structs are renamed to delimit the CX7200 board emulation from the existing Zynq emulation. At this stage, the new machine is a direct copy of hw/arm/xilinx_zynq.c. Future commits will adapt it to match the CX7200 hardware requirements. Signed-off-by: Yannick Voßen --- hw/arm/Kconfig | 18 ++ hw/arm/beckhoff_CX7200.c | 496 +++++++++++++++++++++++++++++++++++++++ hw/arm/meson.build | 1 + 3 files changed, 515 insertions(+) create mode 100644 hw/arm/beckhoff_CX7200.c diff --git a/hw/arm/Kconfig b/hw/arm/Kconfig index 15200a2d7e..8727b3e837 100644 --- a/hw/arm/Kconfig +++ b/hw/arm/Kconfig @@ -311,6 +311,24 @@ config ZYNQ select XILINX_SPIPS select ZYNQ_DEVCFG +config BECK_CX7200 + bool + default y + depends on TCG && ARM + select A9MPCORE + select CADENCE # UART + select PFLASH_CFI02 + select PL310 # cache controller + select PL330 + select SDHCI + select SSI_M25P80 + select USB_EHCI_SYSBUS + select XILINX # UART + select XILINX_AXI + select XILINX_SPI + select XILINX_SPIPS + select ZYNQ_DEVCFG + config ARM_V7M bool # currently v7M must be included in a TCG build due to translate.c diff --git a/hw/arm/beckhoff_CX7200.c b/hw/arm/beckhoff_CX7200.c new file mode 100644 index 0000000000..89466cfdd8 --- /dev/null +++ b/hw/arm/beckhoff_CX7200.c @@ -0,0 +1,496 @@ +/* + * Modified Xilinx Zynq Baseboard System emulation for Beckhoff CX7200. + * + * Based on /hw/arm/xilinx_zynq.c: + * Copyright (c) 2010 Xilinx. + * Copyright (c) 2012 Peter A.G. Crosthwaite (peter.croshtwaite@petalogix.com) + * Copyright (c) 2012 Petalogix Pty Ltd. + * Original code by Haibing Ma. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the Free + * Software Foundation; either version 2 of the License, or (at your option) + * any later version. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, see . + */ + +#include "qemu/osdep.h" +#include "qemu/units.h" +#include "qapi/error.h" +#include "hw/sysbus.h" +#include "hw/arm/boot.h" +#include "net/net.h" +#include "system/system.h" +#include "hw/boards.h" +#include "hw/block/flash.h" +#include "hw/loader.h" +#include "hw/adc/zynq-xadc.h" +#include "hw/ssi/ssi.h" +#include "hw/usb/chipidea.h" +#include "qemu/error-report.h" +#include "hw/sd/sdhci.h" +#include "hw/char/cadence_uart.h" +#include "hw/net/cadence_gem.h" +#include "hw/cpu/a9mpcore.h" +#include "hw/qdev-clock.h" +#include "hw/misc/unimp.h" +#include "system/reset.h" +#include "qom/object.h" +#include "exec/tswap.h" +#include "target/arm/cpu-qom.h" +#include "qapi/visitor.h" + +#define TYPE_CX7200_MACHINE MACHINE_TYPE_NAME("beckhoff-cx7200") +OBJECT_DECLARE_SIMPLE_TYPE(CX7200MachineState, CX7200_MACHINE) + +/* board base frequency: 33.333333 MHz */ +#define PS_CLK_FREQUENCY (100 * 1000 * 1000 / 3) + +#define NUM_SPI_FLASHES 4 +#define NUM_QSPI_FLASHES 2 +#define NUM_QSPI_BUSSES 2 + +#define FLASH_SIZE (64 * 1024 * 1024) +#define FLASH_SECTOR_SIZE (128 * 1024) + +#define IRQ_OFFSET 32 /* pic interrupts start from index 32 */ + +#define MPCORE_PERIPHBASE 0xF8F00000 +#define ZYNQ_BOARD_MIDR 0x413FC090 + +static const int dma_irqs[8] = { + 46, 47, 48, 49, 72, 73, 74, 75 +}; + +#define BOARD_SETUP_ADDR 0x100 + +#define SLCR_LOCK_OFFSET 0x004 +#define SLCR_UNLOCK_OFFSET 0x008 +#define SLCR_ARM_PLL_OFFSET 0x100 + +#define SLCR_XILINX_UNLOCK_KEY 0xdf0d +#define SLCR_XILINX_LOCK_KEY 0x767b + +#define ZYNQ_SDHCI_CAPABILITIES 0x69ec0080 /* Datasheet: UG585 (v1.12.1) */ + +#define ARMV7_IMM16(x) (extract32((x), 0, 12) | \ + extract32((x), 12, 4) << 16) + +/* + * Write immediate val to address r0 + addr. r0 should contain base offset + * of the SLCR block. Clobbers r1. + */ + +#define SLCR_WRITE(addr, val) \ + 0xe3001000 + ARMV7_IMM16(extract32((val), 0, 16)), /* movw r1 ... */ \ + 0xe3401000 + ARMV7_IMM16(extract32((val), 16, 16)), /* movt r1 ... */ \ + 0xe5801000 + (addr) + +#define ZYNQ_MAX_CPUS 2 + +struct CX7200MachineState { + MachineState parent; + Clock *ps_clk; + ARMCPU *cpu[ZYNQ_MAX_CPUS]; + uint8_t boot_mode; +}; + +static void beckhoff_cx7200_write_board_setup(ARMCPU *cpu, + const struct arm_boot_info *info) +{ + int n; + uint32_t board_setup_blob[] = { + 0xe3a004f8, /* mov r0, #0xf8000000 */ + SLCR_WRITE(SLCR_UNLOCK_OFFSET, SLCR_XILINX_UNLOCK_KEY), + SLCR_WRITE(SLCR_ARM_PLL_OFFSET, 0x00014008), + SLCR_WRITE(SLCR_LOCK_OFFSET, SLCR_XILINX_LOCK_KEY), + 0xe12fff1e, /* bx lr */ + }; + for (n = 0; n < ARRAY_SIZE(board_setup_blob); n++) { + board_setup_blob[n] = tswap32(board_setup_blob[n]); + } + rom_add_blob_fixed("board-setup", board_setup_blob, + sizeof(board_setup_blob), BOARD_SETUP_ADDR); +} + +static struct arm_boot_info beckhoff_cx7200_binfo = {}; + +static void gem_init(uint32_t base, qemu_irq irq) +{ + DeviceState *dev; + SysBusDevice *s; + + dev = qdev_new(TYPE_CADENCE_GEM); + qemu_configure_nic_device(dev, true, NULL); + object_property_set_int(OBJECT(dev), "phy-addr", 7, &error_abort); + s = SYS_BUS_DEVICE(dev); + sysbus_realize_and_unref(s, &error_fatal); + sysbus_mmio_map(s, 0, base); + sysbus_connect_irq(s, 0, irq); +} + +static inline int beckhoff_cx7200_init_spi_flashes(uint32_t base_addr, + qemu_irq irq, bool is_qspi, int unit0) +{ + int unit = unit0; + DeviceState *dev; + SysBusDevice *busdev; + SSIBus *spi; + DeviceState *flash_dev; + int i, j; + int num_busses = is_qspi ? NUM_QSPI_BUSSES : 1; + int num_ss = is_qspi ? NUM_QSPI_FLASHES : NUM_SPI_FLASHES; + + dev = qdev_new(is_qspi ? "xlnx.ps7-qspi" : "xlnx.ps7-spi"); + qdev_prop_set_uint8(dev, "num-txrx-bytes", is_qspi ? 4 : 1); + qdev_prop_set_uint8(dev, "num-ss-bits", num_ss); + qdev_prop_set_uint8(dev, "num-busses", num_busses); + busdev = SYS_BUS_DEVICE(dev); + sysbus_realize_and_unref(busdev, &error_fatal); + sysbus_mmio_map(busdev, 0, base_addr); + if (is_qspi) { + sysbus_mmio_map(busdev, 1, 0xFC000000); + } + sysbus_connect_irq(busdev, 0, irq); + + for (i = 0; i < num_busses; ++i) { + char bus_name[16]; + qemu_irq cs_line; + + snprintf(bus_name, 16, "spi%d", i); + spi = (SSIBus *)qdev_get_child_bus(dev, bus_name); + + for (j = 0; j < num_ss; ++j) { + DriveInfo *dinfo = drive_get(IF_MTD, 0, unit++); + flash_dev = qdev_new("n25q128"); + if (dinfo) { + qdev_prop_set_drive_err(flash_dev, "drive", + blk_by_legacy_dinfo(dinfo), + &error_fatal); + } + qdev_prop_set_uint8(flash_dev, "cs", j); + qdev_realize_and_unref(flash_dev, BUS(spi), &error_fatal); + + cs_line = qdev_get_gpio_in_named(flash_dev, SSI_GPIO_CS, 0); + sysbus_connect_irq(busdev, i * num_ss + j + 1, cs_line); + } + } + + return unit; +} + +static void beckhoff_cx7200_set_boot_mode(Object *obj, const char *str, + Error **errp) +{ + CX7200MachineState *m = CX7200_MACHINE(obj); + uint8_t mode = 0; + + if (!strncasecmp(str, "qspi", 4)) { + mode = 1; + } else if (!strncasecmp(str, "sd", 2)) { + mode = 5; + } else if (!strncasecmp(str, "nor", 3)) { + mode = 2; + } else if (!strncasecmp(str, "jtag", 4)) { + mode = 0; + } else { + error_setg(errp, "%s boot mode not supported", str); + return; + } + m->boot_mode = mode; +} + +static void beckhoff_cx7200_init(MachineState *machine) +{ + CX7200MachineState *cx7200_machine = CX7200_MACHINE(machine); + MemoryRegion *address_space_mem = get_system_memory(); + MemoryRegion *ocm_ram = g_new(MemoryRegion, 1); + DeviceState *dev, *slcr; + SysBusDevice *busdev; + qemu_irq pic[64]; + int n; + unsigned int smp_cpus = machine->smp.cpus; + + /* max 2GB ram */ + if (machine->ram_size > 2 * GiB) { + error_report("RAM size more than 2 GiB is not supported"); + exit(EXIT_FAILURE); + } + + for (n = 0; n < smp_cpus; n++) { + Object *cpuobj = object_new(machine->cpu_type); + + object_property_set_int(cpuobj, "midr", ZYNQ_BOARD_MIDR, + &error_fatal); + object_property_set_int(cpuobj, "reset-cbar", MPCORE_PERIPHBASE, + &error_fatal); + + qdev_realize(DEVICE(cpuobj), NULL, &error_fatal); + + cx7200_machine->cpu[n] = ARM_CPU(cpuobj); + } + + /* DDR remapped to address zero. */ + memory_region_add_subregion(address_space_mem, 0, machine->ram); + + /* 256K of on-chip memory */ + memory_region_init_ram(ocm_ram, NULL, "zynq.ocm_ram", 256 * KiB, + &error_fatal); + memory_region_add_subregion(address_space_mem, 0xFFFC0000, ocm_ram); + + DriveInfo *dinfo = drive_get(IF_PFLASH, 0, 0); + + /* AMD */ + pflash_cfi02_register(0xe2000000, "zynq.pflash", FLASH_SIZE, + dinfo ? blk_by_legacy_dinfo(dinfo) : NULL, + FLASH_SECTOR_SIZE, 1, + 1, 0x0066, 0x0022, 0x0000, 0x0000, 0x0555, 0x2aa, + 0); + + /* Create the main clock source, and feed slcr with it */ + cx7200_machine->ps_clk = CLOCK(object_new(TYPE_CLOCK)); + object_property_add_child(OBJECT(cx7200_machine), "ps_clk", + OBJECT(cx7200_machine->ps_clk)); + object_unref(OBJECT(cx7200_machine->ps_clk)); + clock_set_hz(cx7200_machine->ps_clk, PS_CLK_FREQUENCY); + + /* Create slcr, keep a pointer to connect clocks */ + slcr = qdev_new("xilinx-zynq_slcr"); + qdev_connect_clock_in(slcr, "ps_clk", cx7200_machine->ps_clk); + qdev_prop_set_uint8(slcr, "boot-mode", cx7200_machine->boot_mode); + sysbus_realize_and_unref(SYS_BUS_DEVICE(slcr), &error_fatal); + sysbus_mmio_map(SYS_BUS_DEVICE(slcr), 0, 0xF8000000); + + dev = qdev_new(TYPE_A9MPCORE_PRIV); + qdev_prop_set_uint32(dev, "num-cpu", smp_cpus); + busdev = SYS_BUS_DEVICE(dev); + sysbus_realize_and_unref(busdev, &error_fatal); + sysbus_mmio_map(busdev, 0, MPCORE_PERIPHBASE); + beckhoff_cx7200_binfo.gic_cpu_if_addr = MPCORE_PERIPHBASE + 0x100; + sysbus_create_varargs("l2x0", MPCORE_PERIPHBASE + 0x2000, NULL); + for (n = 0; n < smp_cpus; n++) { + /* See "hw/intc/arm_gic.h" for the IRQ line association */ + DeviceState *cpudev = DEVICE(cx7200_machine->cpu[n]); + sysbus_connect_irq(busdev, n, + qdev_get_gpio_in(cpudev, ARM_CPU_IRQ)); + sysbus_connect_irq(busdev, smp_cpus + n, + qdev_get_gpio_in(cpudev, ARM_CPU_FIQ)); + } + + for (n = 0; n < 64; n++) { + pic[n] = qdev_get_gpio_in(dev, n); + } + + n = beckhoff_cx7200_init_spi_flashes(0xE0006000, pic[58 - IRQ_OFFSET], + false, 0); + n = beckhoff_cx7200_init_spi_flashes(0xE0007000, pic[81 - IRQ_OFFSET], + false, n); + n = beckhoff_cx7200_init_spi_flashes(0xE000D000, pic[51 - IRQ_OFFSET], + true, n); + + sysbus_create_simple(TYPE_CHIPIDEA, 0xE0002000, pic[53 - IRQ_OFFSET]); + sysbus_create_simple(TYPE_CHIPIDEA, 0xE0003000, pic[76 - IRQ_OFFSET]); + + dev = qdev_new(TYPE_CADENCE_UART); + busdev = SYS_BUS_DEVICE(dev); + qdev_prop_set_chr(dev, "chardev", serial_hd(0)); + qdev_connect_clock_in(dev, "refclk", + qdev_get_clock_out(slcr, "uart0_ref_clk")); + sysbus_realize_and_unref(busdev, &error_fatal); + sysbus_mmio_map(busdev, 0, 0xE0000000); + sysbus_connect_irq(busdev, 0, pic[59 - IRQ_OFFSET]); + dev = qdev_new(TYPE_CADENCE_UART); + busdev = SYS_BUS_DEVICE(dev); + qdev_prop_set_chr(dev, "chardev", serial_hd(1)); + qdev_connect_clock_in(dev, "refclk", + qdev_get_clock_out(slcr, "uart1_ref_clk")); + sysbus_realize_and_unref(busdev, &error_fatal); + sysbus_mmio_map(busdev, 0, 0xE0001000); + sysbus_connect_irq(busdev, 0, pic[82 - IRQ_OFFSET]); + + sysbus_create_varargs("cadence_ttc", 0xF8001000, pic[42 - IRQ_OFFSET], + pic[43 - IRQ_OFFSET], pic[44 - IRQ_OFFSET], NULL); + sysbus_create_varargs("cadence_ttc", 0xF8002000, pic[69 - IRQ_OFFSET], + pic[70 - IRQ_OFFSET], pic[71 - IRQ_OFFSET], NULL); + + gem_init(0xE000B000, pic[54 - IRQ_OFFSET]); + gem_init(0xE000C000, pic[77 - IRQ_OFFSET]); + + for (n = 0; n < 2; n++) { + int hci_irq = n ? 79 : 56; + hwaddr hci_addr = n ? 0xE0101000 : 0xE0100000; + DriveInfo *di; + BlockBackend *blk; + DeviceState *carddev; + + /* + * Compatible with: + * - SD Host Controller Specification Version 2.0 Part A2 + * - SDIO Specification Version 2.0 + * - MMC Specification Version 3.31 + */ + dev = qdev_new(TYPE_SYSBUS_SDHCI); + qdev_prop_set_uint8(dev, "sd-spec-version", 2); + qdev_prop_set_uint64(dev, "capareg", ZYNQ_SDHCI_CAPABILITIES); + sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal); + sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, hci_addr); + sysbus_connect_irq(SYS_BUS_DEVICE(dev), 0, pic[hci_irq - IRQ_OFFSET]); + + di = drive_get(IF_SD, 0, n); + blk = di ? blk_by_legacy_dinfo(di) : NULL; + carddev = qdev_new(TYPE_SD_CARD); + qdev_prop_set_drive_err(carddev, "drive", blk, &error_fatal); + qdev_realize_and_unref(carddev, qdev_get_child_bus(dev, "sd-bus"), + &error_fatal); + } + + dev = qdev_new(TYPE_ZYNQ_XADC); + sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal); + sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, 0xF8007100); + sysbus_connect_irq(SYS_BUS_DEVICE(dev), 0, pic[39 - IRQ_OFFSET]); + + dev = qdev_new("pl330"); + object_property_set_link(OBJECT(dev), "memory", + OBJECT(address_space_mem), + &error_fatal); + qdev_prop_set_uint8(dev, "num_chnls", 8); + qdev_prop_set_uint8(dev, "num_periph_req", 4); + qdev_prop_set_uint8(dev, "num_events", 16); + + qdev_prop_set_uint8(dev, "data_width", 64); + qdev_prop_set_uint8(dev, "wr_cap", 8); + qdev_prop_set_uint8(dev, "wr_q_dep", 16); + qdev_prop_set_uint8(dev, "rd_cap", 8); + qdev_prop_set_uint8(dev, "rd_q_dep", 16); + qdev_prop_set_uint16(dev, "data_buffer_dep", 256); + + busdev = SYS_BUS_DEVICE(dev); + sysbus_realize_and_unref(busdev, &error_fatal); + sysbus_mmio_map(busdev, 0, 0xF8003000); + sysbus_connect_irq(busdev, 0, pic[45 - IRQ_OFFSET]); /* abort irq line */ + for (n = 0; n < ARRAY_SIZE(dma_irqs); ++n) { /* event irqs */ + sysbus_connect_irq(busdev, n + 1, pic[dma_irqs[n] - IRQ_OFFSET]); + } + + dev = qdev_new("xlnx.ps7-dev-cfg"); + busdev = SYS_BUS_DEVICE(dev); + sysbus_realize_and_unref(busdev, &error_fatal); + sysbus_connect_irq(busdev, 0, pic[40 - IRQ_OFFSET]); + sysbus_mmio_map(busdev, 0, 0xF8007000); + + /* + * Refer to the ug585-Zynq-7000-TRM manual B.3 (Module Summary) and + * the zynq-7000.dtsi. Add placeholders for unimplemented devices. + */ + create_unimplemented_device("zynq.i2c0", 0xE0004000, 4 * KiB); + create_unimplemented_device("zynq.i2c1", 0xE0005000, 4 * KiB); + create_unimplemented_device("zynq.can0", 0xE0008000, 4 * KiB); + create_unimplemented_device("zynq.can1", 0xE0009000, 4 * KiB); + create_unimplemented_device("zynq.gpio", 0xE000A000, 4 * KiB); + create_unimplemented_device("zynq.smcc", 0xE000E000, 4 * KiB); + + /* Direct Memory Access Controller, PL330, Non-Secure Mode */ + create_unimplemented_device("zynq.dma_ns", 0xF8004000, 4 * KiB); + + /* System Watchdog Timer Registers */ + create_unimplemented_device("zynq.swdt", 0xF8005000, 4 * KiB); + + /* DDR memory controller */ + create_unimplemented_device("zynq.ddrc", 0xF8006000, 4 * KiB); + + /* AXI_HP Interface (AFI) */ + create_unimplemented_device("zynq.axi_hp0", 0xF8008000, 0x28); + create_unimplemented_device("zynq.axi_hp1", 0xF8009000, 0x28); + create_unimplemented_device("zynq.axi_hp2", 0xF800A000, 0x28); + create_unimplemented_device("zynq.axi_hp3", 0xF800B000, 0x28); + + create_unimplemented_device("zynq.efuse", 0xF800d000, 0x20); + + /* Embedded Trace Buffer */ + create_unimplemented_device("zynq.etb", 0xF8801000, 4 * KiB); + + /* Cross Trigger Interface, ETB and TPIU */ + create_unimplemented_device("zynq.cti_etb_tpiu", 0xF8802000, 4 * KiB); + + /* Trace Port Interface Unit */ + create_unimplemented_device("zynq.tpiu", 0xF8803000, 4 * KiB); + + /* CoreSight Trace Funnel */ + create_unimplemented_device("zynq.funnel", 0xF8804000, 4 * KiB); + + /* Instrumentation Trace Macrocell */ + create_unimplemented_device("zynq.itm", 0xF8805000, 4 * KiB); + + /* Cross Trigger Interface, FTM */ + create_unimplemented_device("zynq.cti_ftm", 0xF8809000, 4 * KiB); + + /* Fabric Trace Macrocell */ + create_unimplemented_device("zynq.ftm", 0xF880B000, 4 * KiB); + + /* Cortex A9 Performance Monitoring Unit, CPU */ + create_unimplemented_device("cortex-a9.pmu0", 0xF8891000, 4 * KiB); + create_unimplemented_device("cortex-a9.pmu1", 0xF8893000, 4 * KiB); + + /* Cross Trigger Interface, CPU */ + create_unimplemented_device("zynq.cpu_cti0", 0xF8898000, 4 * KiB); + create_unimplemented_device("zynq.cpu_cti1", 0xF8899000, 4 * KiB); + + /* CoreSight PTM-A9, CPU */ + create_unimplemented_device("cortex-a9.ptm0", 0xF889c000, 4 * KiB); + create_unimplemented_device("cortex-a9.ptm1", 0xF889d000, 4 * KiB); + + /* AMBA NIC301 TrustZone */ + create_unimplemented_device("zynq.trustZone", 0xF8900000, 0x20); + + /* AMBA Network Interconnect Advanced Quality of Service (QoS-301) */ + create_unimplemented_device("zynq.qos301_cpu", 0xF8946000, 0x130); + create_unimplemented_device("zynq.qos301_dmac", 0xF8947000, 0x130); + create_unimplemented_device("zynq.qos301_iou", 0xF8948000, 0x130); + + beckhoff_cx7200_binfo.ram_size = machine->ram_size; + beckhoff_cx7200_binfo.board_id = 0xd32; + beckhoff_cx7200_binfo.loader_start = 0; + beckhoff_cx7200_binfo.board_setup_addr = BOARD_SETUP_ADDR; + beckhoff_cx7200_binfo.write_board_setup = beckhoff_cx7200_write_board_setup; + + arm_load_kernel(cx7200_machine->cpu[0], machine, &beckhoff_cx7200_binfo); +} + +static void beckhoff_cx7200_machine_class_init(ObjectClass *oc, void *data) +{ + static const char * const valid_cpu_types[] = { + ARM_CPU_TYPE_NAME("cortex-a9"), + NULL + }; + MachineClass *mc = MACHINE_CLASS(oc); + ObjectProperty *prop; + mc->desc = "Xilinx Zynq Platform Baseboard for Cortex-A9"; + mc->init = beckhoff_cx7200_init; + mc->max_cpus = ZYNQ_MAX_CPUS; + mc->no_sdcard = 1; + mc->ignore_memory_transaction_failures = true; + mc->valid_cpu_types = valid_cpu_types; + mc->default_ram_id = "zynq.ext_ram"; + prop = object_class_property_add_str(oc, "boot-mode", NULL, + beckhoff_cx7200_set_boot_mode); + object_class_property_set_description(oc, "boot-mode", + "Supported boot modes:" + " jtag qspi sd nor"); + object_property_set_default_str(prop, "qspi"); +} + +static const TypeInfo beckhoff_cx7200_machine_type = { + .name = TYPE_CX7200_MACHINE, + .parent = TYPE_MACHINE, + .class_init = beckhoff_cx7200_machine_class_init, + .instance_size = sizeof(CX7200MachineState), +}; + +static void beckhoff_cx7200_machine_register_types(void) +{ + type_register_static(&beckhoff_cx7200_machine_type); +} + +type_init(beckhoff_cx7200_machine_register_types) diff --git a/hw/arm/meson.build b/hw/arm/meson.build index ac473ce7cd..c862e9c88e 100644 --- a/hw/arm/meson.build +++ b/hw/arm/meson.build @@ -18,6 +18,7 @@ arm_ss.add(when: 'CONFIG_SBSA_REF', if_true: files('sbsa-ref.c')) arm_ss.add(when: 'CONFIG_STELLARIS', if_true: files('stellaris.c')) arm_ss.add(when: 'CONFIG_STM32VLDISCOVERY', if_true: files('stm32vldiscovery.c')) arm_ss.add(when: 'CONFIG_ZYNQ', if_true: files('xilinx_zynq.c')) +arm_ss.add(when: 'CONFIG_BECK_CX7200', if_true: files('beckhoff_CX7200.c')) arm_ss.add(when: 'CONFIG_SABRELITE', if_true: files('sabrelite.c')) arm_ss.add(when: 'CONFIG_ARM_V7M', if_true: files('armv7m.c')) From patchwork Tue Mar 18 13:08:04 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Corvin_K=C3=B6hne?= X-Patchwork-Id: 14020995 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 745C7C282EC for ; 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Tue, 18 Mar 2025 06:11:11 -0700 (PDT) From: =?utf-8?q?Corvin_K=C3=B6hne?= To: qemu-devel@nongnu.org, =?utf-8?q?Corvin_K=C3=B6hne?= , qemu-arm@nongnu.org Cc: =?utf-8?q?Yannick_Vo=C3=9Fen?= , "Edgar E. Iglesias" , Peter Maydell , Alistair Francis , Paolo Bonzini , YannickV Subject: [PATCH 13/21] hw/arm/beckhoff_CX7200: Remove second SD controller Date: Tue, 18 Mar 2025 14:08:04 +0100 Message-ID: <20250318130817.119636-14-corvin.koehne@gmail.com> X-Mailer: git-send-email 2.49.0 In-Reply-To: <20250318130817.119636-1-corvin.koehne@gmail.com> References: <20250318130817.119636-1-corvin.koehne@gmail.com> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::62b; envelope-from=corvin.koehne@gmail.com; helo=mail-ej1-x62b.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org From: YannickV The CX7200 has one SD controller connected to address 0xE0101000. The controller connected to address 0xE0100000 can be removed. Signed-off-by: Yannick Voßen --- hw/arm/beckhoff_CX7200.c | 48 ++++++++++++++++++---------------------- 1 file changed, 21 insertions(+), 27 deletions(-) diff --git a/hw/arm/beckhoff_CX7200.c b/hw/arm/beckhoff_CX7200.c index 89466cfdd8..bf3c66e5a4 100644 --- a/hw/arm/beckhoff_CX7200.c +++ b/hw/arm/beckhoff_CX7200.c @@ -207,11 +207,13 @@ static void beckhoff_cx7200_init(MachineState *machine) CX7200MachineState *cx7200_machine = CX7200_MACHINE(machine); MemoryRegion *address_space_mem = get_system_memory(); MemoryRegion *ocm_ram = g_new(MemoryRegion, 1); - DeviceState *dev, *slcr; + DeviceState *carddev, *dev, *slcr; SysBusDevice *busdev; qemu_irq pic[64]; int n; unsigned int smp_cpus = machine->smp.cpus; + DriveInfo *di; + BlockBackend *blk; /* max 2GB ram */ if (machine->ram_size > 2 * GiB) { @@ -318,33 +320,25 @@ static void beckhoff_cx7200_init(MachineState *machine) gem_init(0xE000B000, pic[54 - IRQ_OFFSET]); gem_init(0xE000C000, pic[77 - IRQ_OFFSET]); - for (n = 0; n < 2; n++) { - int hci_irq = n ? 79 : 56; - hwaddr hci_addr = n ? 0xE0101000 : 0xE0100000; - DriveInfo *di; - BlockBackend *blk; - DeviceState *carddev; + /* + * Compatible with: + * - SD Host Controller Specification Version 2.0 Part A2 + * - SDIO Specification Version 2.0 + * - MMC Specification Version 3.31 + */ + dev = qdev_new(TYPE_SYSBUS_SDHCI); + qdev_prop_set_uint8(dev, "sd-spec-version", 2); + qdev_prop_set_uint64(dev, "capareg", ZYNQ_SDHCI_CAPABILITIES); + sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal); + sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, 0xE0101000); + sysbus_connect_irq(SYS_BUS_DEVICE(dev), 0, pic[79 - IRQ_OFFSET]); - /* - * Compatible with: - * - SD Host Controller Specification Version 2.0 Part A2 - * - SDIO Specification Version 2.0 - * - MMC Specification Version 3.31 - */ - dev = qdev_new(TYPE_SYSBUS_SDHCI); - qdev_prop_set_uint8(dev, "sd-spec-version", 2); - qdev_prop_set_uint64(dev, "capareg", ZYNQ_SDHCI_CAPABILITIES); - sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal); - sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, hci_addr); - sysbus_connect_irq(SYS_BUS_DEVICE(dev), 0, pic[hci_irq - IRQ_OFFSET]); - - di = drive_get(IF_SD, 0, n); - blk = di ? blk_by_legacy_dinfo(di) : NULL; - carddev = qdev_new(TYPE_SD_CARD); - qdev_prop_set_drive_err(carddev, "drive", blk, &error_fatal); - qdev_realize_and_unref(carddev, qdev_get_child_bus(dev, "sd-bus"), - &error_fatal); - } + di = drive_get(IF_SD, 0, 0); + blk = di ? blk_by_legacy_dinfo(di) : NULL; + carddev = qdev_new(TYPE_SD_CARD); + qdev_prop_set_drive_err(carddev, "drive", blk, &error_fatal); + qdev_realize_and_unref(carddev, qdev_get_child_bus(dev, "sd-bus"), + &error_fatal); dev = qdev_new(TYPE_ZYNQ_XADC); sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal); From patchwork Tue Mar 18 13:08:05 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Corvin_K=C3=B6hne?= X-Patchwork-Id: 14020989 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id DF201C282EC for ; Tue, 18 Mar 2025 13:14:54 +0000 (UTC) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1tuWkq-0003b0-PK; Tue, 18 Mar 2025 09:13:12 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1tuWjR-0002Q6-U5; Tue, 18 Mar 2025 09:11:52 -0400 Received: from mail-ed1-x534.google.com ([2a00:1450:4864:20::534]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1tuWjI-0003rf-4S; Tue, 18 Mar 2025 09:11:41 -0400 Received: by mail-ed1-x534.google.com with SMTP id 4fb4d7f45d1cf-5dccaaca646so9911224a12.0; Tue, 18 Mar 2025 06:11:34 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20230601; t=1742303493; x=1742908293; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=dLy6aE/EeuI5uid3VlN7jU07cW6eNahLR7Xv7H+Vk24=; b=FDzFZywHonNvFweKH/Fv/YuaLT1ujiZlttpSjAFtLf6hHc2QxgosbjYKimjUGl4wzf FH49JA5mCZkjR+3L4JRfG/uWU+1ehLdxVlgGH3me+8jKrYaD2Qoc0dE6nErFcwODuR49 PCE91EkcUBXYdSq38RFPiZ4URd3TeYipo9h6i/1RvqPcBUL5plbM+B2/CBrA9N688cK+ jKmu3HJ76017dbsSM04Uz4c5DWOLxmtq1MMrGHzOD9LpNFQMxleKN4buC65LMKjmSrJD uWyzhL1HOmDkaMHtNmHRjV9D4w4bzzjzZLNMdTrIe0uv2Z44j3z4JvQctsmKQAGRLU6C Zkaw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1742303493; x=1742908293; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=dLy6aE/EeuI5uid3VlN7jU07cW6eNahLR7Xv7H+Vk24=; b=Aoa4HI7gG/HZcb2SChgTJdwGE3lLOuLtMwMtbHM6WguaJVOtGFkqPdYfRFB/zdY1Of /umucnBA9HCB6mwpn0OtpTuRIBdlNRHN/ugzccRlHfQDxcQ5kwkvU0KKeNLUeOInMhD8 rJwfHUF8gt2ZU0+Lwm0moS1/hNjAO9cJ+7yLy2OdqRdErny8Trh/UH+yaerY9LyaczhH 3YK11VexfAZsb4DLMMX3YCyie5y7+W6sdkyjAggIfD2d5ELX8hNROn1uHXrPisTfnM4Y nV7j9ht4wCWSBefgMVIcBC3fi6mnvSNLZMNaDB3jgZQqbe4wfEoF5vJi/eZwovelNQu2 7utg== X-Forwarded-Encrypted: i=1; AJvYcCXLOb3R+d/pE8NzDRoUJSxe8SFJ38glJl0LkD3qx2bSWM0APJSJ6saNBLtmVNphMCYXVUDUMKX0xw==@nongnu.org X-Gm-Message-State: AOJu0YyRJCfXKxOtRLi25XOcyjh2jZBK2iKRkuN+76371cbK+DKsB/br FZiQ1Y9IYTDKTSWTXcmNawGz7bF2wY0mw/tf0mxg/QFPWiF3qMoFZejrIU0w X-Gm-Gg: ASbGncu7fn7Z1gEq1/O/j9gKwIBTyKv5edQIAQFDSaSp1rxQSSUP95KkEYgYbifrtUU d7eBhZrjwb/UGtHdfJaWGbP9C20c0aKlNETQqZRdEDD1jojfK2VIiZY86KiFjOKD0Vp8/ypL6wE qnLTwezcTEqjVUx4/0kOVcbMRZOrquac0KQQ8Jr5v7PoDtiMmX5Arb7C8eqAyx5xdW6drCZh++3 JD9kesWgfbpzSlXOHpJCjigKgxyS7JfrP0XK1Czk79YFmlC4E4IyJlNNhT+Tahh5lp1fB/30YRN z3eMug2up/C9BjvjaXuUBBXnOwnprhnvE7413TzVz7fGghgDDkP21VNJ2oN8o5bUyX8= X-Google-Smtp-Source: AGHT+IHihL/Cq7L9zV5OfwuOJhib7AxVnNMS6ebIe+UaM5k0LsmMuiZJaCfpgQKR2TAzlqzZ/1zlvQ== X-Received: by 2002:a05:6402:3491:b0:5e6:102a:c30 with SMTP id 4fb4d7f45d1cf-5eb1efcbee0mr3955471a12.2.1742303482100; Tue, 18 Mar 2025 06:11:22 -0700 (PDT) Received: from corvink-nb.beckhoff.com ([195.226.174.194]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-ac3147f3101sm850678066b.69.2025.03.18.06.11.12 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 18 Mar 2025 06:11:12 -0700 (PDT) From: =?utf-8?q?Corvin_K=C3=B6hne?= To: qemu-devel@nongnu.org, =?utf-8?q?Corvin_K=C3=B6hne?= , qemu-arm@nongnu.org Cc: =?utf-8?q?Yannick_Vo=C3=9Fen?= , "Edgar E. Iglesias" , Peter Maydell , Alistair Francis , Paolo Bonzini , YannickV Subject: [PATCH 14/21] hw/arm/beckhoff_CX7200: Remove second GEM Date: Tue, 18 Mar 2025 14:08:05 +0100 Message-ID: <20250318130817.119636-15-corvin.koehne@gmail.com> X-Mailer: git-send-email 2.49.0 In-Reply-To: <20250318130817.119636-1-corvin.koehne@gmail.com> References: <20250318130817.119636-1-corvin.koehne@gmail.com> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::534; envelope-from=corvin.koehne@gmail.com; helo=mail-ed1-x534.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org From: YannickV The CX7200 has one Gigabit Ethernet MAC connected to address 0xE000C000. The one connected to address 0xE000B000 can be removed. Signed-off-by: Yannick Voßen --- hw/arm/beckhoff_CX7200.c | 1 - 1 file changed, 1 deletion(-) diff --git a/hw/arm/beckhoff_CX7200.c b/hw/arm/beckhoff_CX7200.c index bf3c66e5a4..3ceccaa9e6 100644 --- a/hw/arm/beckhoff_CX7200.c +++ b/hw/arm/beckhoff_CX7200.c @@ -317,7 +317,6 @@ static void beckhoff_cx7200_init(MachineState *machine) sysbus_create_varargs("cadence_ttc", 0xF8002000, pic[69 - IRQ_OFFSET], pic[70 - IRQ_OFFSET], pic[71 - IRQ_OFFSET], NULL); - gem_init(0xE000B000, pic[54 - IRQ_OFFSET]); gem_init(0xE000C000, pic[77 - IRQ_OFFSET]); /* From patchwork Tue Mar 18 13:08:06 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Corvin_K=C3=B6hne?= X-Patchwork-Id: 14021006 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 9E5ECC35FF3 for ; Tue, 18 Mar 2025 13:18:45 +0000 (UTC) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1tuWlo-0005KU-Ez; Tue, 18 Mar 2025 09:14:12 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1tuWjY-0002Qp-Bw; Tue, 18 Mar 2025 09:12:02 -0400 Received: from mail-ej1-x629.google.com ([2a00:1450:4864:20::629]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1tuWjT-0003tr-4D; Tue, 18 Mar 2025 09:11:48 -0400 Received: by mail-ej1-x629.google.com with SMTP id a640c23a62f3a-ac2dfdf3c38so1037392666b.3; Tue, 18 Mar 2025 06:11:45 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20230601; t=1742303504; x=1742908304; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=+EVxpnQ8AEBa+S4Znun5esfO9UMpfrf7hVR1yYjzFCA=; b=ZaNYSc/Gs4+gIVGoF/QVMsJ+AKUH0kyDaJcU5w1tyCixvto78znvhWZUIxJG+hFGRm Y+5FavMRFTjT1SRqfcvVMatUzu1YDiT2HqStIBCuXFcfcHH6e6rzNUv6hmOs3gQ1wiyy DBAyzuqcioP/brsR5W0+94B3ivZlBTakktQmyy0OBkr3Dsvcq9hasMdBoBAy+WHLGr3+ YxvLy9m6kg7fnGHSJsD6snCSiXB2Yz/VakTfYO9bF5yHEicE5vYGFEG8ilxtk8ry8wsK Xim/V9Vcw7uei0uAc2iRAis1XaXRmCKnP/705j/IMuhatTVYhNd4l6xcRchhyi3GvSaw m/AA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1742303504; x=1742908304; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=+EVxpnQ8AEBa+S4Znun5esfO9UMpfrf7hVR1yYjzFCA=; b=qw1Y7KqobI94kDPaa+kk9DZEJ3Bstzpwny9igvJd6mG1zzXRxZ+wfALwpbkrHXZgX5 3zClFQSVTTx4wjWqSlnpZzb9foyh7+rzXe61jqa0Edgf/2/gJzgYhu6BsfHe52atSmRp CqR7VN3DSfjFkTfvauXzeauKr3yRd19SP82vCxW9g5Jdbfjd6TZArmLWUZ3TYJiMB5SU V9zGgeGGs8YnuLvDgNZKQM8nTf3ABIBa5zE+bHjSI/rlvlBtTQOkOnegU+m0rsX5Sd3p T4vkJWE/c7VFi0ns535XaP8o1dDOushRl3ue70PpAuGxwII7ADAJraPIQFYZrTktnK1P NQwA== X-Forwarded-Encrypted: i=1; AJvYcCVnqs/eVlKZZdVj3zYEJ/11HpuenpGjLTu8d+5FVxJmAnzFdXcyPt5EHyWhqdFKEgTkx5qdGyBLWQ==@nongnu.org X-Gm-Message-State: AOJu0Yz5EDnSA4ZvqUh0iC8j7m3nGrSwjm6ultlr5MeIzPl+khpbOKbh sCVKNYb06UMJxE1GXSufHK00/m6XFTt+G2U/Y9Z9ZZ6U9BwP0GiiH5isJDhf X-Gm-Gg: ASbGncs6XPEHEXjIisRrceLrcRQ+wlsDV/zpBYwQJlEwiVUPTs5IKop+2yaZXvggUsb VIF4x5Tw8OAMRTcDB2sq9IAgbDcHFOCVT860XECrcHe4HAlzWqcHnJiNvAsCF/pm+o6ZJdsXQik B3uSIRjS5fqd7QJEHo9bBLiFbCEyEB4qXJjtDK/QKjiXfzBL57C6taZAlLdDKPLKRey/bqG69Wi zREXlzHnCsuyc61d8GOp8MoMY5NJD5BoIPigY898LXGXylGloGnnYk+VfMfgma+qVl8SwVAyNZ1 rv4cuGtM00J1oMaGVNzSBXKt8QoCQglcdC0348caXDVWpWXKFWmJGLpokAcsPLUc3ZU= X-Google-Smtp-Source: AGHT+IGFhtkm/+/tOjIpZakKVZobpqBEwhKeG6Z3oV3g9BYhBDX9dQQpDK42p0TrasQIF6j69a1y2g== X-Received: by 2002:a17:906:1117:b0:ac3:3f11:b49d with SMTP id a640c23a62f3a-ac33f1203dbmr1302062666b.0.1742303493022; Tue, 18 Mar 2025 06:11:33 -0700 (PDT) Received: from corvink-nb.beckhoff.com ([195.226.174.194]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-ac3147f3101sm850678066b.69.2025.03.18.06.11.32 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 18 Mar 2025 06:11:32 -0700 (PDT) From: =?utf-8?q?Corvin_K=C3=B6hne?= To: qemu-devel@nongnu.org, =?utf-8?q?Corvin_K=C3=B6hne?= , qemu-arm@nongnu.org Cc: =?utf-8?q?Yannick_Vo=C3=9Fen?= , "Edgar E. Iglesias" , Peter Maydell , Alistair Francis , Paolo Bonzini , YannickV Subject: [PATCH 15/21] hw/arm/beckhoff_CX7200: Adjust Flashes and Busses Date: Tue, 18 Mar 2025 14:08:06 +0100 Message-ID: <20250318130817.119636-16-corvin.koehne@gmail.com> X-Mailer: git-send-email 2.49.0 In-Reply-To: <20250318130817.119636-1-corvin.koehne@gmail.com> References: <20250318130817.119636-1-corvin.koehne@gmail.com> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::629; envelope-from=corvin.koehne@gmail.com; helo=mail-ej1-x629.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org From: YannickV The CX7200 has one QSPI flash connected to the QSPI bus. The defines are adjusted accordingly. The QSPI flash is a is25lp016d. There is no parallel flash. Signed-off-by: Yannick Voßen --- hw/arm/beckhoff_CX7200.c | 20 ++++---------------- 1 file changed, 4 insertions(+), 16 deletions(-) diff --git a/hw/arm/beckhoff_CX7200.c b/hw/arm/beckhoff_CX7200.c index 3ceccaa9e6..1e7152e871 100644 --- a/hw/arm/beckhoff_CX7200.c +++ b/hw/arm/beckhoff_CX7200.c @@ -48,12 +48,9 @@ OBJECT_DECLARE_SIMPLE_TYPE(CX7200MachineState, CX7200_MACHINE) /* board base frequency: 33.333333 MHz */ #define PS_CLK_FREQUENCY (100 * 1000 * 1000 / 3) -#define NUM_SPI_FLASHES 4 -#define NUM_QSPI_FLASHES 2 -#define NUM_QSPI_BUSSES 2 - -#define FLASH_SIZE (64 * 1024 * 1024) -#define FLASH_SECTOR_SIZE (128 * 1024) +#define NUM_SPI_FLASHES 0 +#define NUM_QSPI_FLASHES 1 +#define NUM_QSPI_BUSSES 1 #define IRQ_OFFSET 32 /* pic interrupts start from index 32 */ @@ -164,7 +161,7 @@ static inline int beckhoff_cx7200_init_spi_flashes(uint32_t base_addr, for (j = 0; j < num_ss; ++j) { DriveInfo *dinfo = drive_get(IF_MTD, 0, unit++); - flash_dev = qdev_new("n25q128"); + flash_dev = qdev_new("is25lp016d"); if (dinfo) { qdev_prop_set_drive_err(flash_dev, "drive", blk_by_legacy_dinfo(dinfo), @@ -242,15 +239,6 @@ static void beckhoff_cx7200_init(MachineState *machine) &error_fatal); memory_region_add_subregion(address_space_mem, 0xFFFC0000, ocm_ram); - DriveInfo *dinfo = drive_get(IF_PFLASH, 0, 0); - - /* AMD */ - pflash_cfi02_register(0xe2000000, "zynq.pflash", FLASH_SIZE, - dinfo ? blk_by_legacy_dinfo(dinfo) : NULL, - FLASH_SECTOR_SIZE, 1, - 1, 0x0066, 0x0022, 0x0000, 0x0000, 0x0555, 0x2aa, - 0); - /* Create the main clock source, and feed slcr with it */ cx7200_machine->ps_clk = CLOCK(object_new(TYPE_CLOCK)); object_property_add_child(OBJECT(cx7200_machine), "ps_clk", From patchwork Tue Mar 18 13:08:07 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Corvin_K=C3=B6hne?= X-Patchwork-Id: 14020990 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id C2554C282EC for ; Tue, 18 Mar 2025 13:15:16 +0000 (UTC) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1tuWkk-00034y-Vp; Tue, 18 Mar 2025 09:13:07 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1tuWji-0002Rw-NZ; Tue, 18 Mar 2025 09:12:04 -0400 Received: from mail-ej1-x62a.google.com ([2a00:1450:4864:20::62a]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1tuWje-0003wE-SC; Tue, 18 Mar 2025 09:12:00 -0400 Received: by mail-ej1-x62a.google.com with SMTP id a640c23a62f3a-ac2b10bea16so488193166b.0; Tue, 18 Mar 2025 06:11:57 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20230601; t=1742303516; x=1742908316; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=j23N8vOYcpKi67Cqo7/zZHv4kG2whHLTAlH6+ZbQMt4=; b=OHyI+t1Z1z6qmjTOVhElGWF1DdNhKsWTYn55QGpZ8wWCnXr+0i8wfKdrdJo5uPPBHW eowWM2MgP3l0fiLEDS91cI0Bo1F7spSdyGUCnRv4z53S3TE3/yTTOYGdX9/IMoLJQYCT mcn+GROXhSka3NVc4+W15adFcSmJLu8MdPmSPSS+OvN0VfeN6PqEI9RXDBkRXUtUYRqO QQIon+2kmOI3h7+JgeeDVN+RltcTIseNL+97ji1PpXkZS/AuZjvvbvOUEdvgqL0ypatB pqxs0ASFcc8t3wPtGVSwMeEzdVFo8Kqpt1N4S8dY+HYzFI/AZ5y03Esl7UXNn+rmoBMY nktA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1742303516; x=1742908316; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=j23N8vOYcpKi67Cqo7/zZHv4kG2whHLTAlH6+ZbQMt4=; b=hOsTXYOOG1N4tWU0oyZ8728Qg/XsVEvWgp7fuqBR302GTvcwr9mlWuKvQxYMTGGU4G qWcjPGzIHTSrtRc/cn2FDQl9GOb8p4Xio06h4yNzHFdcZBF+uzAatfHyC/UVF1CMeRtm vqaUzuC5P1SYH0pzMnjHGTaKZFI5c2GsSv+gBdjTB168rFnbVMTB76WyHmN7N70z5W0k 4j1wPrLZfGjLEFzNP1pJbAh3Sk69dbkKUG6nCvNCa258KEoTfDmYr/FdFpmdcmKOivCL qk0WVXJT0CzpCQSl64bFfjpu74Ii13OvBVYOcYmRUqjh7p4C/EWRVOw/zFE1VZYF9Psj dyEw== X-Forwarded-Encrypted: i=1; AJvYcCU2Yt/c7a8r0nk+9McJgx0Bp2AjJz2vA92xnsKXYN5j6i35cI7JBIFYJ1gp7OtZolm0eppct2Efgg==@nongnu.org X-Gm-Message-State: AOJu0Yw/nlYkAU1l6dTglQtKgIhY0TIQStUHpBABbBF2zYtbQMuLzFXw 8x7cD+4fSjr4sMCRe9cu7oCKL/S+zoCrt0zYTJbU/JQGcHbd1daRj0/7qKDT X-Gm-Gg: ASbGncv6dfX0icDAfTanyr05/T8tWaYLj4hp2iNJ59s4BQP7hfyJfghkYYuw/D/PHCS QxJAjlpW0GDQr0DZ6bnZHKeQwddeZyvqE8Og9EE2qmOBD9ynAqrbKEifahNHcBmI4Q4gTgc7AuX t9zB6frdV01W3G76v/H68VK0DIy/VCIWjSX0bCIaLAUIFORVBpNFErgJXG/tCbhzufPE1m6lStQ t7DO+TmVkZFc/lTNQiUYUT4XsabOJXZotBWnPjTZibu3Vbck9lsQ3dtBCtBFkALzU2zk4TgDLCS f1Bhn9gTgGEXh5Y6YDLj3arwnHKOxVIg38Pd93lHAj6mEq1UBO3XAuSp4QUOFQxpZxQ= X-Google-Smtp-Source: AGHT+IGGPWxnh0QlL4IU2qsLSPRZbfU8RQ7chA6yMQvIMv4KyCTLXafg6SP2b5xW3TltQ86sf0DFLg== X-Received: by 2002:a17:906:d554:b0:ac1:def4:ce20 with SMTP id a640c23a62f3a-ac330188c47mr1531992666b.18.1742303505310; Tue, 18 Mar 2025 06:11:45 -0700 (PDT) Received: from corvink-nb.beckhoff.com ([195.226.174.194]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-ac3147f3101sm850678066b.69.2025.03.18.06.11.44 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 18 Mar 2025 06:11:44 -0700 (PDT) From: =?utf-8?q?Corvin_K=C3=B6hne?= To: qemu-devel@nongnu.org, =?utf-8?q?Corvin_K=C3=B6hne?= , qemu-arm@nongnu.org Cc: =?utf-8?q?Yannick_Vo=C3=9Fen?= , "Edgar E. Iglesias" , Peter Maydell , Alistair Francis , Paolo Bonzini , YannickV Subject: [PATCH 16/21] hw/arm/beckhoff_CX7200: Remove usb interfaces Date: Tue, 18 Mar 2025 14:08:07 +0100 Message-ID: <20250318130817.119636-17-corvin.koehne@gmail.com> X-Mailer: git-send-email 2.49.0 In-Reply-To: <20250318130817.119636-1-corvin.koehne@gmail.com> References: <20250318130817.119636-1-corvin.koehne@gmail.com> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::62a; envelope-from=corvin.koehne@gmail.com; helo=mail-ej1-x62a.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org From: YannickV The CX7200 does not support usb interfaces. That is why they are removed. Signed-off-by: Yannick Voßen --- hw/arm/Kconfig | 1 - hw/arm/beckhoff_CX7200.c | 4 ---- 2 files changed, 5 deletions(-) diff --git a/hw/arm/Kconfig b/hw/arm/Kconfig index 8727b3e837..a8648b9edf 100644 --- a/hw/arm/Kconfig +++ b/hw/arm/Kconfig @@ -322,7 +322,6 @@ config BECK_CX7200 select PL330 select SDHCI select SSI_M25P80 - select USB_EHCI_SYSBUS select XILINX # UART select XILINX_AXI select XILINX_SPI diff --git a/hw/arm/beckhoff_CX7200.c b/hw/arm/beckhoff_CX7200.c index 1e7152e871..efce3be395 100644 --- a/hw/arm/beckhoff_CX7200.c +++ b/hw/arm/beckhoff_CX7200.c @@ -28,7 +28,6 @@ #include "hw/loader.h" #include "hw/adc/zynq-xadc.h" #include "hw/ssi/ssi.h" -#include "hw/usb/chipidea.h" #include "qemu/error-report.h" #include "hw/sd/sdhci.h" #include "hw/char/cadence_uart.h" @@ -280,9 +279,6 @@ static void beckhoff_cx7200_init(MachineState *machine) n = beckhoff_cx7200_init_spi_flashes(0xE000D000, pic[51 - IRQ_OFFSET], true, n); - sysbus_create_simple(TYPE_CHIPIDEA, 0xE0002000, pic[53 - IRQ_OFFSET]); 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Tue, 18 Mar 2025 06:11:57 -0700 (PDT) Received: from corvink-nb.beckhoff.com ([195.226.174.194]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-ac3147f3101sm850678066b.69.2025.03.18.06.11.56 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 18 Mar 2025 06:11:56 -0700 (PDT) From: =?utf-8?q?Corvin_K=C3=B6hne?= To: qemu-devel@nongnu.org, =?utf-8?q?Corvin_K=C3=B6hne?= , qemu-arm@nongnu.org Cc: =?utf-8?q?Yannick_Vo=C3=9Fen?= , "Edgar E. Iglesias" , Peter Maydell , Alistair Francis , Paolo Bonzini , YannickV Subject: [PATCH 17/21] hw/arm/beckhoff_CX7200: Remove unimplemented devices Date: Tue, 18 Mar 2025 14:08:08 +0100 Message-ID: <20250318130817.119636-18-corvin.koehne@gmail.com> X-Mailer: git-send-email 2.49.0 In-Reply-To: <20250318130817.119636-1-corvin.koehne@gmail.com> References: <20250318130817.119636-1-corvin.koehne@gmail.com> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::633; envelope-from=corvin.koehne@gmail.com; helo=mail-ej1-x633.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org From: YannickV Some unimplemented devices do not exist for the CX7200. All unimplemented devices have been removed for better overview and the fact that they are not necessary for a CX7200 emulation. Signed-off-by: Yannick Voßen --- hw/arm/beckhoff_CX7200.c | 69 ---------------------------------------- 1 file changed, 69 deletions(-) diff --git a/hw/arm/beckhoff_CX7200.c b/hw/arm/beckhoff_CX7200.c index efce3be395..a3f4045560 100644 --- a/hw/arm/beckhoff_CX7200.c +++ b/hw/arm/beckhoff_CX7200.c @@ -357,75 +357,6 @@ static void beckhoff_cx7200_init(MachineState *machine) sysbus_connect_irq(busdev, 0, pic[40 - IRQ_OFFSET]); sysbus_mmio_map(busdev, 0, 0xF8007000); - /* - * Refer to the ug585-Zynq-7000-TRM manual B.3 (Module Summary) and - * the zynq-7000.dtsi. Add placeholders for unimplemented devices. - */ - create_unimplemented_device("zynq.i2c0", 0xE0004000, 4 * KiB); - create_unimplemented_device("zynq.i2c1", 0xE0005000, 4 * KiB); - create_unimplemented_device("zynq.can0", 0xE0008000, 4 * KiB); - create_unimplemented_device("zynq.can1", 0xE0009000, 4 * KiB); - create_unimplemented_device("zynq.gpio", 0xE000A000, 4 * KiB); - create_unimplemented_device("zynq.smcc", 0xE000E000, 4 * KiB); - - /* Direct Memory Access Controller, PL330, Non-Secure Mode */ - create_unimplemented_device("zynq.dma_ns", 0xF8004000, 4 * KiB); - - /* System Watchdog Timer Registers */ - create_unimplemented_device("zynq.swdt", 0xF8005000, 4 * KiB); - - /* DDR memory controller */ - create_unimplemented_device("zynq.ddrc", 0xF8006000, 4 * KiB); - - /* AXI_HP Interface (AFI) */ - create_unimplemented_device("zynq.axi_hp0", 0xF8008000, 0x28); - create_unimplemented_device("zynq.axi_hp1", 0xF8009000, 0x28); - create_unimplemented_device("zynq.axi_hp2", 0xF800A000, 0x28); - create_unimplemented_device("zynq.axi_hp3", 0xF800B000, 0x28); - - create_unimplemented_device("zynq.efuse", 0xF800d000, 0x20); - - /* Embedded Trace Buffer */ - create_unimplemented_device("zynq.etb", 0xF8801000, 4 * KiB); - - /* Cross Trigger Interface, ETB and TPIU */ - create_unimplemented_device("zynq.cti_etb_tpiu", 0xF8802000, 4 * KiB); - - /* Trace Port Interface Unit */ - create_unimplemented_device("zynq.tpiu", 0xF8803000, 4 * KiB); - - /* CoreSight Trace Funnel */ - create_unimplemented_device("zynq.funnel", 0xF8804000, 4 * KiB); - - /* Instrumentation Trace Macrocell */ - create_unimplemented_device("zynq.itm", 0xF8805000, 4 * KiB); - - /* Cross Trigger Interface, FTM */ - create_unimplemented_device("zynq.cti_ftm", 0xF8809000, 4 * KiB); - - /* Fabric Trace Macrocell */ - create_unimplemented_device("zynq.ftm", 0xF880B000, 4 * KiB); - - /* Cortex A9 Performance Monitoring Unit, CPU */ - create_unimplemented_device("cortex-a9.pmu0", 0xF8891000, 4 * KiB); - create_unimplemented_device("cortex-a9.pmu1", 0xF8893000, 4 * KiB); - - /* Cross Trigger Interface, CPU */ - create_unimplemented_device("zynq.cpu_cti0", 0xF8898000, 4 * KiB); - create_unimplemented_device("zynq.cpu_cti1", 0xF8899000, 4 * KiB); - - /* CoreSight PTM-A9, CPU */ - create_unimplemented_device("cortex-a9.ptm0", 0xF889c000, 4 * KiB); - create_unimplemented_device("cortex-a9.ptm1", 0xF889d000, 4 * KiB); - - /* AMBA NIC301 TrustZone */ - create_unimplemented_device("zynq.trustZone", 0xF8900000, 0x20); - - /* AMBA Network Interconnect Advanced Quality of Service (QoS-301) */ - create_unimplemented_device("zynq.qos301_cpu", 0xF8946000, 0x130); - create_unimplemented_device("zynq.qos301_dmac", 0xF8947000, 0x130); - create_unimplemented_device("zynq.qos301_iou", 0xF8948000, 0x130); - beckhoff_cx7200_binfo.ram_size = machine->ram_size; beckhoff_cx7200_binfo.board_id = 0xd32; beckhoff_cx7200_binfo.loader_start = 0; From patchwork Tue Mar 18 13:08:09 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Corvin_K=C3=B6hne?= X-Patchwork-Id: 14020986 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 64865C28B2F for ; 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Tue, 18 Mar 2025 06:11:59 -0700 (PDT) From: =?utf-8?q?Corvin_K=C3=B6hne?= To: qemu-devel@nongnu.org, =?utf-8?q?Corvin_K=C3=B6hne?= , qemu-arm@nongnu.org Cc: =?utf-8?q?Yannick_Vo=C3=9Fen?= , "Edgar E. Iglesias" , Peter Maydell , Alistair Francis , Paolo Bonzini , YannickV Subject: [PATCH 18/21] hw/arm/beckhoff_CX7200: Set CPU frequency and PERIPHCLK period Date: Tue, 18 Mar 2025 14:08:09 +0100 Message-ID: <20250318130817.119636-19-corvin.koehne@gmail.com> X-Mailer: git-send-email 2.49.0 In-Reply-To: <20250318130817.119636-1-corvin.koehne@gmail.com> References: <20250318130817.119636-1-corvin.koehne@gmail.com> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::636; envelope-from=corvin.koehne@gmail.com; helo=mail-ej1-x636.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org From: YannickV The CPU frequency for the CX7200 is set to 720 MHz, with the peripheral clock running at half of the CPU frequency. That is why the PERIPHCLK_PERIOD is set to two. These values are forwarded to the A9 global timer, watchdog timer and MP Timer. Signed-off-by: Yannick Voßen --- hw/arm/beckhoff_CX7200.c | 10 ++++++++++ 1 file changed, 10 insertions(+) diff --git a/hw/arm/beckhoff_CX7200.c b/hw/arm/beckhoff_CX7200.c index a3f4045560..0f99cbf554 100644 --- a/hw/arm/beckhoff_CX7200.c +++ b/hw/arm/beckhoff_CX7200.c @@ -47,6 +47,9 @@ OBJECT_DECLARE_SIMPLE_TYPE(CX7200MachineState, CX7200_MACHINE) /* board base frequency: 33.333333 MHz */ #define PS_CLK_FREQUENCY (100 * 1000 * 1000 / 3) +#define PERIPHCLK_PERIOD 2 +#define PS7_CPU_CLK_FREQUENCY 720000000 + #define NUM_SPI_FLASHES 0 #define NUM_QSPI_FLASHES 1 #define NUM_QSPI_BUSSES 1 @@ -254,6 +257,13 @@ static void beckhoff_cx7200_init(MachineState *machine) dev = qdev_new(TYPE_A9MPCORE_PRIV); qdev_prop_set_uint32(dev, "num-cpu", smp_cpus); + A9MPPrivState *a9mp_priv_state = A9MPCORE_PRIV(dev); + a9mp_priv_state->gtimer.cpu_clk_freq_hz = PS7_CPU_CLK_FREQUENCY; + a9mp_priv_state->gtimer.periphclk_period = PERIPHCLK_PERIOD; + a9mp_priv_state->mptimer.clk_freq_hz = PS7_CPU_CLK_FREQUENCY; + a9mp_priv_state->mptimer.periphclk_period = PERIPHCLK_PERIOD; + a9mp_priv_state->wdt.clk_freq_hz = PS7_CPU_CLK_FREQUENCY; + a9mp_priv_state->wdt.periphclk_period = PERIPHCLK_PERIOD; busdev = SYS_BUS_DEVICE(dev); sysbus_realize_and_unref(busdev, &error_fatal); sysbus_mmio_map(busdev, 0, MPCORE_PERIPHBASE); From patchwork Tue Mar 18 13:08:10 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Corvin_K=C3=B6hne?= X-Patchwork-Id: 14020993 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id BF0E0C282EC for ; Tue, 18 Mar 2025 13:16:10 +0000 (UTC) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1tuWlk-0004yl-Ay; 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Tue, 18 Mar 2025 06:12:01 -0700 (PDT) Received: from corvink-nb.beckhoff.com ([195.226.174.194]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-ac3147f3101sm850678066b.69.2025.03.18.06.12.00 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 18 Mar 2025 06:12:01 -0700 (PDT) From: =?utf-8?q?Corvin_K=C3=B6hne?= To: qemu-devel@nongnu.org, =?utf-8?q?Corvin_K=C3=B6hne?= , qemu-arm@nongnu.org Cc: =?utf-8?q?Yannick_Vo=C3=9Fen?= , "Edgar E. Iglesias" , Peter Maydell , Alistair Francis , Paolo Bonzini , YannickV Subject: [PATCH 19/21] hw/arm/beckhoff_CX7200: Add CCAT to CX7200 Date: Tue, 18 Mar 2025 14:08:10 +0100 Message-ID: <20250318130817.119636-20-corvin.koehne@gmail.com> X-Mailer: git-send-email 2.49.0 In-Reply-To: <20250318130817.119636-1-corvin.koehne@gmail.com> References: <20250318130817.119636-1-corvin.koehne@gmail.com> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::62e; envelope-from=corvin.koehne@gmail.com; helo=mail-ej1-x62e.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org From: YannickV The Beckhoff CX7200 is based on the Xilinx Zynq-7000 SoC. It integrates the Beckhoff Communication Controller (CCAT), which is implemented as an FPGA within the Zynq's programmable logic (PL). This commit adds the CCAT as an MMIO device to the CX7200 machine in QEMU, enabling its emulation and interaction with the system. Signed-off-by: Yannick Voßen --- hw/arm/Kconfig | 1 + hw/arm/beckhoff_CX7200.c | 13 +++++++++++++ 2 files changed, 14 insertions(+) diff --git a/hw/arm/Kconfig b/hw/arm/Kconfig index a8648b9edf..782da4c22a 100644 --- a/hw/arm/Kconfig +++ b/hw/arm/Kconfig @@ -327,6 +327,7 @@ config BECK_CX7200 select XILINX_SPI select XILINX_SPIPS select ZYNQ_DEVCFG + select BECKHOFF_CCAT config ARM_V7M bool diff --git a/hw/arm/beckhoff_CX7200.c b/hw/arm/beckhoff_CX7200.c index 0f99cbf554..0fe03f570f 100644 --- a/hw/arm/beckhoff_CX7200.c +++ b/hw/arm/beckhoff_CX7200.c @@ -130,6 +130,17 @@ static void gem_init(uint32_t base, qemu_irq irq) sysbus_connect_irq(s, 0, irq); } +static void ccat_init(uint32_t base) +{ + DeviceState *dev; + SysBusDevice *busdev; + + dev = qdev_new("beckhoff-ccat"); + busdev = SYS_BUS_DEVICE(dev); + sysbus_realize_and_unref(busdev, &error_fatal); + sysbus_mmio_map(busdev, 0, base); +} + static inline int beckhoff_cx7200_init_spi_flashes(uint32_t base_addr, qemu_irq irq, bool is_qspi, int unit0) { @@ -313,6 +324,8 @@ static void beckhoff_cx7200_init(MachineState *machine) gem_init(0xE000C000, pic[77 - IRQ_OFFSET]); + ccat_init(0x40000000); + /* * Compatible with: * - SD Host Controller Specification Version 2.0 Part A2 From patchwork Tue Mar 18 13:08:11 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Corvin_K=C3=B6hne?= X-Patchwork-Id: 14020992 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id EEACEC28B2F for ; Tue, 18 Mar 2025 13:16:01 +0000 (UTC) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1tuWm0-0006Mz-WA; Tue, 18 Mar 2025 09:14:25 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1tuWkK-0002oi-Hz; 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Tue, 18 Mar 2025 06:12:03 -0700 (PDT) Received: from corvink-nb.beckhoff.com ([195.226.174.194]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-ac3147f3101sm850678066b.69.2025.03.18.06.12.02 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 18 Mar 2025 06:12:02 -0700 (PDT) From: =?utf-8?q?Corvin_K=C3=B6hne?= To: qemu-devel@nongnu.org, =?utf-8?q?Corvin_K=C3=B6hne?= , qemu-arm@nongnu.org Cc: =?utf-8?q?Yannick_Vo=C3=9Fen?= , "Edgar E. Iglesias" , Peter Maydell , Alistair Francis , Paolo Bonzini , YannickV Subject: [PATCH 20/21] hw/arm/beckhoff_CX7200: Add dummy DDR CTRL to CX7200 Date: Tue, 18 Mar 2025 14:08:11 +0100 Message-ID: <20250318130817.119636-21-corvin.koehne@gmail.com> X-Mailer: git-send-email 2.49.0 In-Reply-To: <20250318130817.119636-1-corvin.koehne@gmail.com> References: <20250318130817.119636-1-corvin.koehne@gmail.com> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::62f; envelope-from=corvin.koehne@gmail.com; helo=mail-ej1-x62f.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org From: YannickV The CX7200 polls for statusregisters in the DDR Controller. To avaid endless polling loops, a dummy DDR Controller is added. Signed-off-by: Yannick Voßen --- hw/arm/beckhoff_CX7200.c | 13 +++++++++++++ 1 file changed, 13 insertions(+) diff --git a/hw/arm/beckhoff_CX7200.c b/hw/arm/beckhoff_CX7200.c index 0fe03f570f..8c1379aab4 100644 --- a/hw/arm/beckhoff_CX7200.c +++ b/hw/arm/beckhoff_CX7200.c @@ -141,6 +141,17 @@ static void ccat_init(uint32_t base) sysbus_mmio_map(busdev, 0, base); } +static void ddr_ctrl_init(uint32_t base) +{ + DeviceState *dev; + SysBusDevice *busdev; + + dev = qdev_new("zynq.ddr-ctlr"); + busdev = SYS_BUS_DEVICE(dev); + sysbus_realize_and_unref(busdev, &error_fatal); + sysbus_mmio_map(busdev, 0, base); +} + static inline int beckhoff_cx7200_init_spi_flashes(uint32_t base_addr, qemu_irq irq, bool is_qspi, int unit0) { @@ -326,6 +337,8 @@ static void beckhoff_cx7200_init(MachineState *machine) ccat_init(0x40000000); + ddr_ctrl_init(0xF8006000); + /* * Compatible with: * - SD Host Controller Specification Version 2.0 Part A2 From patchwork Tue Mar 18 13:08:12 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Corvin_K=C3=B6hne?= X-Patchwork-Id: 14020996 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 17E93C35FFA for ; Tue, 18 Mar 2025 13:16:25 +0000 (UTC) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1tuWlo-0005M9-Ra; Tue, 18 Mar 2025 09:14:13 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1tuWkL-0002qF-LU; Tue, 18 Mar 2025 09:12:42 -0400 Received: from mail-ej1-x62d.google.com ([2a00:1450:4864:20::62d]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1tuWjw-00041J-Ur; Tue, 18 Mar 2025 09:12:18 -0400 Received: by mail-ej1-x62d.google.com with SMTP id a640c23a62f3a-ac2aeada833so1094994766b.0; Tue, 18 Mar 2025 06:12:15 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20230601; t=1742303534; x=1742908334; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=thjTRy17yqeXC7hJLQ3q6JhWsNnlTRLfGO55CMsgDr8=; b=c16QddkDenQayHHAkLf4oa/Ls3DNBZ5JfApZeHj/V2E0Y2J8eD9sGFdq1Z3OTi8pDI gfO8mv0Q1bEm940+KnuoJqFUa+CNnsEyi7V7zj5CDJBLdlWBM2p64ppTlAS9KQG9+P77 Y9Opm82OFHCCTcxOyOhWdLg+5WWG/diU6TI6IXj7iAZHehYE2/KW5+VmNlQUodxjtmPt ttMzliMelk9ToqoFzD0H2eQ0qul/d8yD92oRcYGZcSxnASe0a0YOj5EhOl6VQhWniWwI zu2Ku3+cnfWUFaceoIqvywl3DYcZ3OzSnG2lS1/rFs0Iz4A7MiImlyWBqdTFIRhHzctL 4C4w== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1742303534; x=1742908334; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=thjTRy17yqeXC7hJLQ3q6JhWsNnlTRLfGO55CMsgDr8=; b=ihZGBnKh0RY+FlkcP/jWabFC+tRTxv9vX+m03OcY7AfbvO/7MVHXECvbYEsZDNkifr MQXOomyp6fGIx3DNyOSCUXL5rX3dx4URMR3IjRa7JkMrlv8jlXoiHzChnySUPlm8yYTW X0uBUL0g9GgXN6Jg67OiUIQgrqlmRgHAURNx79HM7ewrm+iV2G2R93l0878Z3zO2FTP0 xSbuScajiN+KnXrLgSmWi+0ClAQp+syc8TrILyX1kxoS0wTGtFWY46byWxh8tDeioDTe nWJkg7ewtyLmXmwDMvuvO23fuV8Vs84kCiG1Cqz7/6M4CPRxLpVA3SRQKl5dmev7wIhK +JPQ== X-Forwarded-Encrypted: i=1; AJvYcCXCcFoDcauZwi0PMZs+9gNH+H3FlZFTEZGwfnxa96IJ4UBUwTFkSi91rsq4qhqnUygM20rjmuqu+g==@nongnu.org X-Gm-Message-State: AOJu0Yw81DENe321HmPsbfiwijq4kth0S7Nas+NtY0+XHNl3P2vx5tt4 vFIA01ACxtljrvpyccrbu3GxpMw+TcNYjTdgC9EDz1cR8YMsgz6ddE1fvlgN X-Gm-Gg: ASbGncu7SrXm9MgM27VWX5Xol04E0yNqO6bKAZD3wodMU47ULqBYANYzFWpO+/MRrW1 7Zw/3F0txkPdO+2HHjuN7sgvdnF96MgslTBdsbYRz6mVZwmRMX3VDoLlQKu0lE68coyvzF9h9w4 PNkD8iuXlYj2VVSLD+PezzZwRk1tcf6HpWHSVoqmUJJCjaeXptlam2a3OY/oJUJ+2bABgN2H3sc xuR4PonFAvzZE0e4BAGxNCvemuiTlxPl63mLVxM71DO7THOziWHH5RS3OsSEi3KSMMB1vRoN4o5 6UzacxHc8BOT/W90k0gN4SpI4lWkZREAzsFbyyUK3T6Y5zXY47nw1weuOE6z10QB9/OCwK2m65D Ibg== X-Google-Smtp-Source: AGHT+IFWh7K6FTJ9EfxAuzqL9izAfxIeFOjUOlr/N83G9SMhg8w+wNRbH0z8Y/VRza/Mx24k2k00ZA== X-Received: by 2002:a17:907:2da6:b0:ac1:e45f:9c71 with SMTP id a640c23a62f3a-ac38f709234mr314946466b.1.1742303533896; Tue, 18 Mar 2025 06:12:13 -0700 (PDT) Received: from corvink-nb.beckhoff.com ([195.226.174.194]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-ac3147f3101sm850678066b.69.2025.03.18.06.12.13 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 18 Mar 2025 06:12:13 -0700 (PDT) From: =?utf-8?q?Corvin_K=C3=B6hne?= To: qemu-devel@nongnu.org Cc: =?utf-8?q?Yannick_Vo=C3=9Fen?= , "Edgar E. Iglesias" , qemu-arm@nongnu.org, Peter Maydell , Alistair Francis , =?utf-8?q?Corvin_K=C3=B6hne?= , Paolo Bonzini Subject: [PATCH 21/21] MAINTAINERS: add myself as reviewer for Beckhoff devices Date: Tue, 18 Mar 2025 14:08:12 +0100 Message-ID: <20250318130817.119636-22-corvin.koehne@gmail.com> X-Mailer: git-send-email 2.49.0 In-Reply-To: <20250318130817.119636-1-corvin.koehne@gmail.com> References: <20250318130817.119636-1-corvin.koehne@gmail.com> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::62d; envelope-from=corvin.koehne@gmail.com; helo=mail-ej1-x62d.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org From: Corvin Köhne I don't have commit privileges, so I can't merge any changes. However, someone from Beckhoff should review changes made to their board emulations. Signed-off-by: Corvin Köhne --- MAINTAINERS | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/MAINTAINERS b/MAINTAINERS index 8f470a1c9b..88d1d51e2a 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -720,6 +720,13 @@ F: hw/arm/b-l475e-iot01a.c F: hw/display/dm163.c F: tests/qtest/dm163-test.c +Beckhoff CX7200 +R: Corvin Köhne +L: qemu-arm@nongnu.org +S: Supported +F: hw/arm/beckhoff_CX7200.c +F: hw/misc/beckhoff_ccat.c + Exynos M: Igor Mitsyanko M: Peter Maydell