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Tue, 18 Mar 2025 14:49:47 GMT Received: from pps.reinject (localhost [127.0.0.1]) by APBLRPPMTA02.qualcomm.com (PPS) with ESMTP id 45dkgmfv8e-1; Tue, 18 Mar 2025 14:49:47 +0000 Received: from APBLRPPMTA02.qualcomm.com (APBLRPPMTA02.qualcomm.com [127.0.0.1]) by pps.reinject (8.17.1.5/8.17.1.5) with ESMTP id 52IEnl7V004275; Tue, 18 Mar 2025 14:49:47 GMT Received: from hu-maiyas-hyd.qualcomm.com (hu-nitirawa-hyd.qualcomm.com [10.213.109.152]) by APBLRPPMTA02.qualcomm.com (PPS) with ESMTP id 52IEnlOi004270; Tue, 18 Mar 2025 14:49:47 +0000 Received: by hu-maiyas-hyd.qualcomm.com (Postfix, from userid 2342877) id C406C501583; Tue, 18 Mar 2025 20:19:46 +0530 (+0530) From: Nitin Rawat To: vkoul@kernel.org, kishon@kernel.org, manivannan.sadhasivam@linaro.org, James.Bottomley@HansenPartnership.com, martin.petersen@oracle.com, konrad.dybcio@oss.qualcomm.com Cc: quic_rdwivedi@quicinc.com, linux-arm-msm@vger.kernel.org, linux-phy@lists.infradead.org, linux-kernel@vger.kernel.org, linux-scsi@vger.kernel.org, Nitin Rawat Subject: [PATCH V2 1/6] phy: qcom-qmp-ufs: Rename qmp_ufs_enable and qmp_ufs_power_on Date: Tue, 18 Mar 2025 20:19:39 +0530 Message-ID: <20250318144944.19749-2-quic_nitirawa@quicinc.com> X-Mailer: git-send-email 2.48.1 In-Reply-To: <20250318144944.19749-1-quic_nitirawa@quicinc.com> References: <20250318144944.19749-1-quic_nitirawa@quicinc.com> MIME-Version: 1.0 X-QCInternal: smtphost X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Authority-Analysis: v=2.4 cv=VLPdn8PX c=1 sm=1 tr=0 ts=67d9880f cx=c_pps a=Ou0eQOY4+eZoSc0qltEV5Q==:117 a=Ou0eQOY4+eZoSc0qltEV5Q==:17 a=Vs1iUdzkB0EA:10 a=COk6AnOGAAAA:8 a=2vqdgNe2dnITDK9_AgkA:9 a=7K3s5E3rCzI1cAiLShGS:22 a=TjNXssC_j7lpFel5tvFf:22 X-Proofpoint-ORIG-GUID: D3X0-hv7rrR5lHaMHdraiMXykgvzUgYd X-Proofpoint-GUID: D3X0-hv7rrR5lHaMHdraiMXykgvzUgYd X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1093,Hydra:6.0.680,FMLib:17.12.68.34 definitions=2025-03-18_07,2025-03-17_03,2024-11-22_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 adultscore=0 priorityscore=1501 clxscore=1015 mlxscore=0 lowpriorityscore=0 phishscore=0 mlxlogscore=999 impostorscore=0 suspectscore=0 malwarescore=0 bulkscore=0 spamscore=0 classifier=spam authscore=0 authtc=n/a authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.19.0-2502280000 definitions=main-2503180109 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20250318_074956_336554_DBADE2A1 X-CRM114-Status: GOOD ( 11.02 ) X-BeenThere: linux-phy@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: Linux Phy Mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-phy" Errors-To: linux-phy-bounces+linux-phy=archiver.kernel.org@lists.infradead.org Rename qmp_ufs_enable to qmp_ufs_power_on and qmp_ufs_power_on to qmp_ufs_phy_calibrate to better reflect functionality. Also update function calls and structure assignments accordingly. Co-developed-by: Ram Kumar Dwivedi Signed-off-by: Ram Kumar Dwivedi Signed-off-by: Nitin Rawat Reviewed-by: Neil Armstrong --- drivers/phy/qualcomm/phy-qcom-qmp-ufs.c | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) -- 2.48.1 diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-ufs.c b/drivers/phy/qualcomm/phy-qcom-qmp-ufs.c index 45b3b792696e..bb836bc0f736 100644 --- a/drivers/phy/qualcomm/phy-qcom-qmp-ufs.c +++ b/drivers/phy/qualcomm/phy-qcom-qmp-ufs.c @@ -1837,7 +1837,7 @@ static int qmp_ufs_init(struct phy *phy) return 0; } -static int qmp_ufs_power_on(struct phy *phy) +static int qmp_ufs_phy_calibrate(struct phy *phy) { struct qmp_ufs *qmp = phy_get_drvdata(phy); const struct qmp_phy_cfg *cfg = qmp->cfg; @@ -1898,7 +1898,7 @@ static int qmp_ufs_exit(struct phy *phy) return 0; } -static int qmp_ufs_enable(struct phy *phy) +static int qmp_ufs_power_on(struct phy *phy) { int ret; @@ -1906,7 +1906,7 @@ static int qmp_ufs_enable(struct phy *phy) if (ret) return ret; - ret = qmp_ufs_power_on(phy); + ret = qmp_ufs_phy_calibrate(phy); if (ret) qmp_ufs_exit(phy); @@ -1940,7 +1940,7 @@ static int qmp_ufs_set_mode(struct phy *phy, enum phy_mode mode, int submode) } static const struct phy_ops qcom_qmp_ufs_phy_ops = { - .power_on = qmp_ufs_enable, + .power_on = qmp_ufs_power_on, .power_off = qmp_ufs_disable, .set_mode = qmp_ufs_set_mode, .owner = THIS_MODULE, From patchwork Tue Mar 18 14:49:40 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Nitin Rawat X-Patchwork-Id: 14021105 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 9A109C28B2F for ; Tue, 18 Mar 2025 14:49:59 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; 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Tue, 18 Mar 2025 14:49:51 +0000 (GMT) Received: from pps.filterd (APBLRPPMTA02.qualcomm.com [127.0.0.1]) by APBLRPPMTA02.qualcomm.com (8.18.1.2/8.18.1.2) with ESMTP id 52IEnm1o004305; Tue, 18 Mar 2025 14:49:48 GMT Received: from pps.reinject (localhost [127.0.0.1]) by APBLRPPMTA02.qualcomm.com (PPS) with ESMTP id 45dkgmfv8n-1; Tue, 18 Mar 2025 14:49:48 +0000 Received: from APBLRPPMTA02.qualcomm.com (APBLRPPMTA02.qualcomm.com [127.0.0.1]) by pps.reinject (8.17.1.5/8.17.1.5) with ESMTP id 52IEnmWL004296; Tue, 18 Mar 2025 14:49:48 GMT Received: from hu-maiyas-hyd.qualcomm.com (hu-nitirawa-hyd.qualcomm.com [10.213.109.152]) by APBLRPPMTA02.qualcomm.com (PPS) with ESMTP id 52IEnmLU004293; Tue, 18 Mar 2025 14:49:48 +0000 Received: by hu-maiyas-hyd.qualcomm.com (Postfix, from userid 2342877) id 8233B501582; Tue, 18 Mar 2025 20:19:47 +0530 (+0530) From: Nitin Rawat To: vkoul@kernel.org, kishon@kernel.org, manivannan.sadhasivam@linaro.org, James.Bottomley@HansenPartnership.com, martin.petersen@oracle.com, konrad.dybcio@oss.qualcomm.com Cc: quic_rdwivedi@quicinc.com, linux-arm-msm@vger.kernel.org, linux-phy@lists.infradead.org, linux-kernel@vger.kernel.org, linux-scsi@vger.kernel.org, Nitin Rawat , Can Guo Subject: [PATCH V2 2/6] phy: qcom-qmp-ufs: Refactor phy_power_on and phy_calibrate callbacks Date: Tue, 18 Mar 2025 20:19:40 +0530 Message-ID: <20250318144944.19749-3-quic_nitirawa@quicinc.com> X-Mailer: git-send-email 2.48.1 In-Reply-To: <20250318144944.19749-1-quic_nitirawa@quicinc.com> References: <20250318144944.19749-1-quic_nitirawa@quicinc.com> MIME-Version: 1.0 X-QCInternal: smtphost X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-GUID: iz_eQCwoZu1Xq-qOAv7NDsu9HosJF4GH X-Proofpoint-ORIG-GUID: iz_eQCwoZu1Xq-qOAv7NDsu9HosJF4GH X-Authority-Analysis: v=2.4 cv=XKcwSRhE c=1 sm=1 tr=0 ts=67d98810 cx=c_pps a=Ou0eQOY4+eZoSc0qltEV5Q==:117 a=Ou0eQOY4+eZoSc0qltEV5Q==:17 a=Vs1iUdzkB0EA:10 a=COk6AnOGAAAA:8 a=ZEhkBkkNTqPGxlI-GDwA:9 a=TjNXssC_j7lpFel5tvFf:22 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1093,Hydra:6.0.680,FMLib:17.12.68.34 definitions=2025-03-18_07,2025-03-17_03,2024-11-22_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 lowpriorityscore=0 mlxlogscore=999 priorityscore=1501 clxscore=1015 phishscore=0 impostorscore=0 adultscore=0 mlxscore=0 malwarescore=0 suspectscore=0 spamscore=0 bulkscore=0 classifier=spam authscore=0 authtc=n/a authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.19.0-2502280000 definitions=main-2503180109 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20250318_074956_628935_FF5D7839 X-CRM114-Status: GOOD ( 11.72 ) X-BeenThere: linux-phy@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: Linux Phy Mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-phy" Errors-To: linux-phy-bounces+linux-phy=archiver.kernel.org@lists.infradead.org Commit 052553af6a31 ("ufs/phy: qcom: Refactor to use phy_init call") puts enabling regulators & clks, calibrating UFS PHY, starting serdes and polling PCS ready status into phy_power_on. In Current code regulators enable, clks enable, calibrating UFS PHY, start_serdes and polling PCS_ready_status are part of phy_power_on. UFS PHY registers are retained after power collapse, meaning calibrating UFS PHY, start_serdes and polling PCS_ready_status can be done only when hba is powered_on, and not needed every time when phy_power_on is called during resume. Hence keep the code which enables PHY's regulators & clks in phy_power_on and move the rest steps into phy_calibrate function. Refactor the code to retain PHY regulators & clks in phy_power_on and move out rest of the code to new phy_calibrate function. Co-developed-by: Can Guo Signed-off-by: Can Guo Signed-off-by: Nitin Rawat --- drivers/phy/qualcomm/phy-qcom-qmp-ufs.c | 18 ++---------------- 1 file changed, 2 insertions(+), 16 deletions(-) -- 2.48.1 diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-ufs.c b/drivers/phy/qualcomm/phy-qcom-qmp-ufs.c index bb836bc0f736..0089ee80f852 100644 --- a/drivers/phy/qualcomm/phy-qcom-qmp-ufs.c +++ b/drivers/phy/qualcomm/phy-qcom-qmp-ufs.c @@ -1796,7 +1796,7 @@ static int qmp_ufs_com_exit(struct qmp_ufs *qmp) return 0; } -static int qmp_ufs_init(struct phy *phy) +static int qmp_ufs_power_on(struct phy *phy) { struct qmp_ufs *qmp = phy_get_drvdata(phy); const struct qmp_phy_cfg *cfg = qmp->cfg; @@ -1898,21 +1898,6 @@ static int qmp_ufs_exit(struct phy *phy) return 0; } -static int qmp_ufs_power_on(struct phy *phy) -{ - int ret; - - ret = qmp_ufs_init(phy); - if (ret) - return ret; - - ret = qmp_ufs_phy_calibrate(phy); - if (ret) - qmp_ufs_exit(phy); - - return ret; -} - static int qmp_ufs_disable(struct phy *phy) { int ret; @@ -1942,6 +1927,7 @@ static int qmp_ufs_set_mode(struct phy *phy, enum phy_mode mode, int submode) static const struct phy_ops qcom_qmp_ufs_phy_ops = { .power_on = qmp_ufs_power_on, .power_off = qmp_ufs_disable, + .calibrate = qmp_ufs_phy_calibrate, .set_mode = qmp_ufs_set_mode, .owner = THIS_MODULE, }; From patchwork Tue Mar 18 14:49:41 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Nitin Rawat X-Patchwork-Id: 14021110 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id E4311C282EC for ; Tue, 18 Mar 2025 14:49:59 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; 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Tue, 18 Mar 2025 14:49:52 +0000 (GMT) Received: from pps.filterd (APBLRPPMTA02.qualcomm.com [127.0.0.1]) by APBLRPPMTA02.qualcomm.com (8.18.1.2/8.18.1.2) with ESMTP id 52IEnnoY004320; Tue, 18 Mar 2025 14:49:49 GMT Received: from pps.reinject (localhost [127.0.0.1]) by APBLRPPMTA02.qualcomm.com (PPS) with ESMTP id 45dkgmfv8v-1; Tue, 18 Mar 2025 14:49:49 +0000 Received: from APBLRPPMTA02.qualcomm.com (APBLRPPMTA02.qualcomm.com [127.0.0.1]) by pps.reinject (8.17.1.5/8.17.1.5) with ESMTP id 52IEnmWO004296; Tue, 18 Mar 2025 14:49:49 GMT Received: from hu-maiyas-hyd.qualcomm.com (hu-nitirawa-hyd.qualcomm.com [10.213.109.152]) by APBLRPPMTA02.qualcomm.com (PPS) with ESMTP id 52IEnmLW004293; Tue, 18 Mar 2025 14:49:49 +0000 Received: by hu-maiyas-hyd.qualcomm.com (Postfix, from userid 2342877) id 27D99501583; Tue, 18 Mar 2025 20:19:48 +0530 (+0530) From: Nitin Rawat To: vkoul@kernel.org, kishon@kernel.org, manivannan.sadhasivam@linaro.org, James.Bottomley@HansenPartnership.com, martin.petersen@oracle.com, konrad.dybcio@oss.qualcomm.com Cc: quic_rdwivedi@quicinc.com, linux-arm-msm@vger.kernel.org, linux-phy@lists.infradead.org, linux-kernel@vger.kernel.org, linux-scsi@vger.kernel.org, Nitin Rawat Subject: [PATCH V2 3/6] phy: qcom-qmp-ufs: Refactor UFS PHY reset Date: Tue, 18 Mar 2025 20:19:41 +0530 Message-ID: <20250318144944.19749-4-quic_nitirawa@quicinc.com> X-Mailer: git-send-email 2.48.1 In-Reply-To: <20250318144944.19749-1-quic_nitirawa@quicinc.com> References: <20250318144944.19749-1-quic_nitirawa@quicinc.com> MIME-Version: 1.0 X-QCInternal: smtphost X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Authority-Analysis: v=2.4 cv=W/I4VQWk c=1 sm=1 tr=0 ts=67d98810 cx=c_pps a=Ou0eQOY4+eZoSc0qltEV5Q==:117 a=Ou0eQOY4+eZoSc0qltEV5Q==:17 a=Vs1iUdzkB0EA:10 a=COk6AnOGAAAA:8 a=UAcMnp6sUDXSVpzIzAMA:9 a=TjNXssC_j7lpFel5tvFf:22 X-Proofpoint-GUID: NAxzUAMnxFfuNPSBFnlylnzm7KkBJ1y7 X-Proofpoint-ORIG-GUID: NAxzUAMnxFfuNPSBFnlylnzm7KkBJ1y7 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1093,Hydra:6.0.680,FMLib:17.12.68.34 definitions=2025-03-18_07,2025-03-17_03,2024-11-22_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 bulkscore=0 phishscore=0 impostorscore=0 adultscore=0 spamscore=0 mlxlogscore=999 mlxscore=0 priorityscore=1501 suspectscore=0 malwarescore=0 lowpriorityscore=0 clxscore=1015 classifier=spam authscore=0 authtc=n/a authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.19.0-2502280000 definitions=main-2503180109 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20250318_074957_613335_1905946B X-CRM114-Status: GOOD ( 15.96 ) X-BeenThere: linux-phy@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: Linux Phy Mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-phy" Errors-To: linux-phy-bounces+linux-phy=archiver.kernel.org@lists.infradead.org Refactor the UFS PHY reset handling to parse the reset logic only once during probe, instead of every resume. Move the UFS PHY reset parsing logic from qmp_phy_power_on to qmp_ufs_probe to avoid unnecessary parsing during resume. Co-developed-by: Ram Kumar Dwivedi Signed-off-by: Ram Kumar Dwivedi Signed-off-by: Nitin Rawat --- drivers/phy/qualcomm/phy-qcom-qmp-ufs.c | 104 ++++++++++++------------ 1 file changed, 50 insertions(+), 54 deletions(-) -- 2.48.1 diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-ufs.c b/drivers/phy/qualcomm/phy-qcom-qmp-ufs.c index 0089ee80f852..3a80c2c110d2 100644 --- a/drivers/phy/qualcomm/phy-qcom-qmp-ufs.c +++ b/drivers/phy/qualcomm/phy-qcom-qmp-ufs.c @@ -1757,32 +1757,6 @@ static void qmp_ufs_init_registers(struct qmp_ufs *qmp, const struct qmp_phy_cfg qmp_ufs_init_all(qmp, &cfg->tbls_hs_b); } -static int qmp_ufs_com_init(struct qmp_ufs *qmp) -{ - const struct qmp_phy_cfg *cfg = qmp->cfg; - void __iomem *pcs = qmp->pcs; - int ret; - - ret = regulator_bulk_enable(cfg->num_vregs, qmp->vregs); - if (ret) { - dev_err(qmp->dev, "failed to enable regulators, err=%d\n", ret); - return ret; - } - - ret = clk_bulk_prepare_enable(qmp->num_clks, qmp->clks); - if (ret) - goto err_disable_regulators; - - qphy_setbits(pcs, cfg->regs[QPHY_PCS_POWER_DOWN_CONTROL], SW_PWRDN); - - return 0; - -err_disable_regulators: - regulator_bulk_disable(cfg->num_vregs, qmp->vregs); - - return ret; -} - static int qmp_ufs_com_exit(struct qmp_ufs *qmp) { const struct qmp_phy_cfg *cfg = qmp->cfg; @@ -1800,41 +1774,27 @@ static int qmp_ufs_power_on(struct phy *phy) { struct qmp_ufs *qmp = phy_get_drvdata(phy); const struct qmp_phy_cfg *cfg = qmp->cfg; + void __iomem *pcs = qmp->pcs; int ret; - dev_vdbg(qmp->dev, "Initializing QMP phy\n"); - - if (cfg->no_pcs_sw_reset) { - /* - * Get UFS reset, which is delayed until now to avoid a - * circular dependency where UFS needs its PHY, but the PHY - * needs this UFS reset. - */ - if (!qmp->ufs_reset) { - qmp->ufs_reset = - devm_reset_control_get_exclusive(qmp->dev, - "ufsphy"); - - if (IS_ERR(qmp->ufs_reset)) { - ret = PTR_ERR(qmp->ufs_reset); - dev_err(qmp->dev, - "failed to get UFS reset: %d\n", - ret); - - qmp->ufs_reset = NULL; - return ret; - } - } - ret = reset_control_assert(qmp->ufs_reset); - if (ret) - return ret; + ret = regulator_bulk_enable(cfg->num_vregs, qmp->vregs); + if (ret) { + dev_err(qmp->dev, "failed to enable regulators, err=%d\n", ret); + return ret; } - ret = qmp_ufs_com_init(qmp); + ret = clk_bulk_prepare_enable(qmp->num_clks, qmp->clks); if (ret) - return ret; + goto err_disable_regulators; + + qphy_setbits(pcs, cfg->regs[QPHY_PCS_POWER_DOWN_CONTROL], SW_PWRDN); return 0; + +err_disable_regulators: + regulator_bulk_disable(cfg->num_vregs, qmp->vregs); + + return ret; } static int qmp_ufs_phy_calibrate(struct phy *phy) @@ -1846,6 +1806,10 @@ static int qmp_ufs_phy_calibrate(struct phy *phy) unsigned int val; int ret; + ret = reset_control_assert(qmp->ufs_reset); + if (ret) + return ret; + qmp_ufs_init_registers(qmp, cfg); ret = reset_control_deassert(qmp->ufs_reset); @@ -2088,6 +2052,34 @@ static int qmp_ufs_parse_dt(struct qmp_ufs *qmp) return 0; } +static int qmp_ufs_get_phy_reset(struct qmp_ufs *qmp) +{ + const struct qmp_phy_cfg *cfg = qmp->cfg; + int ret; + + if (!cfg->no_pcs_sw_reset) + return 0; + + /* + * Get UFS reset, which is delayed until now to avoid a + * circular dependency where UFS needs its PHY, but the PHY + * needs this UFS reset. + */ + if (!qmp->ufs_reset) { + qmp->ufs_reset = + devm_reset_control_get_exclusive(qmp->dev, "ufsphy"); + + if (IS_ERR(qmp->ufs_reset)) { + ret = PTR_ERR(qmp->ufs_reset); + dev_err(qmp->dev, "failed to get PHY reset: %d\n", ret); + qmp->ufs_reset = NULL; + return ret; + } + } + + return 0; +} + static int qmp_ufs_probe(struct platform_device *pdev) { struct device *dev = &pdev->dev; @@ -2114,6 +2106,10 @@ static int qmp_ufs_probe(struct platform_device *pdev) if (ret) return ret; + ret = qmp_ufs_get_phy_reset(qmp); + if (ret) + return ret; + /* Check for legacy binding with child node. */ np = of_get_next_available_child(dev->of_node, NULL); if (np) { From patchwork Tue Mar 18 14:49:42 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Nitin Rawat X-Patchwork-Id: 14021106 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 72136C35FFA for ; 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Date: Tue, 18 Mar 2025 20:19:42 +0530 Message-ID: <20250318144944.19749-5-quic_nitirawa@quicinc.com> X-Mailer: git-send-email 2.48.1 In-Reply-To: <20250318144944.19749-1-quic_nitirawa@quicinc.com> References: <20250318144944.19749-1-quic_nitirawa@quicinc.com> MIME-Version: 1.0 X-QCInternal: smtphost X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-ORIG-GUID: DgxSMTydO0xIicwKNVSexuwLhnVCg75T X-Proofpoint-GUID: DgxSMTydO0xIicwKNVSexuwLhnVCg75T X-Authority-Analysis: v=2.4 cv=aMLwqa9m c=1 sm=1 tr=0 ts=67d98811 cx=c_pps a=Ou0eQOY4+eZoSc0qltEV5Q==:117 a=Ou0eQOY4+eZoSc0qltEV5Q==:17 a=Vs1iUdzkB0EA:10 a=COk6AnOGAAAA:8 a=2ghFC8B1GUYIoq9qLGUA:9 a=7K3s5E3rCzI1cAiLShGS:22 a=TjNXssC_j7lpFel5tvFf:22 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1093,Hydra:6.0.680,FMLib:17.12.68.34 definitions=2025-03-18_07,2025-03-17_03,2024-11-22_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 impostorscore=0 priorityscore=1501 spamscore=0 clxscore=1015 phishscore=0 mlxscore=0 suspectscore=0 malwarescore=0 mlxlogscore=999 bulkscore=0 adultscore=0 lowpriorityscore=0 classifier=spam authscore=0 authtc=n/a authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.19.0-2502280000 definitions=main-2503180109 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20250318_074958_488390_9AECB945 X-CRM114-Status: GOOD ( 12.15 ) X-BeenThere: linux-phy@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: Linux Phy Mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-phy" Errors-To: linux-phy-bounces+linux-phy=archiver.kernel.org@lists.infradead.org Rename qmp_ufs_disable to qmp_ufs_power_off and refactor the code to move all the power off sequence to qmp_ufs_power_off. Co-developed-by: Ram Kumar Dwivedi Signed-off-by: Ram Kumar Dwivedi Signed-off-by: Nitin Rawat --- drivers/phy/qualcomm/phy-qcom-qmp-ufs.c | 41 ++----------------------- 1 file changed, 3 insertions(+), 38 deletions(-) -- 2.48.1 diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-ufs.c b/drivers/phy/qualcomm/phy-qcom-qmp-ufs.c index 3a80c2c110d2..675fef106d3b 100644 --- a/drivers/phy/qualcomm/phy-qcom-qmp-ufs.c +++ b/drivers/phy/qualcomm/phy-qcom-qmp-ufs.c @@ -1757,19 +1757,6 @@ static void qmp_ufs_init_registers(struct qmp_ufs *qmp, const struct qmp_phy_cfg qmp_ufs_init_all(qmp, &cfg->tbls_hs_b); } -static int qmp_ufs_com_exit(struct qmp_ufs *qmp) -{ - const struct qmp_phy_cfg *cfg = qmp->cfg; - - reset_control_assert(qmp->ufs_reset); - - clk_bulk_disable_unprepare(qmp->num_clks, qmp->clks); - - regulator_bulk_disable(cfg->num_vregs, qmp->vregs); - - return 0; -} - static int qmp_ufs_power_on(struct phy *phy) { struct qmp_ufs *qmp = phy_get_drvdata(phy); @@ -1839,39 +1826,17 @@ static int qmp_ufs_power_off(struct phy *phy) struct qmp_ufs *qmp = phy_get_drvdata(phy); const struct qmp_phy_cfg *cfg = qmp->cfg; - /* PHY reset */ - if (!cfg->no_pcs_sw_reset) - qphy_setbits(qmp->pcs, cfg->regs[QPHY_SW_RESET], SW_RESET); - - /* stop SerDes */ - qphy_clrbits(qmp->pcs, cfg->regs[QPHY_START_CTRL], SERDES_START); - /* Put PHY into POWER DOWN state: active low */ qphy_clrbits(qmp->pcs, cfg->regs[QPHY_PCS_POWER_DOWN_CONTROL], SW_PWRDN); - return 0; -} - -static int qmp_ufs_exit(struct phy *phy) -{ - struct qmp_ufs *qmp = phy_get_drvdata(phy); + clk_bulk_disable_unprepare(qmp->num_clks, qmp->clks); - qmp_ufs_com_exit(qmp); + regulator_bulk_disable(cfg->num_vregs, qmp->vregs); return 0; } -static int qmp_ufs_disable(struct phy *phy) -{ - int ret; - - ret = qmp_ufs_power_off(phy); - if (ret) - return ret; - return qmp_ufs_exit(phy); -} - static int qmp_ufs_set_mode(struct phy *phy, enum phy_mode mode, int submode) { struct qmp_ufs *qmp = phy_get_drvdata(phy); @@ -1890,7 +1855,7 @@ static int qmp_ufs_set_mode(struct phy *phy, enum phy_mode mode, int submode) static const struct phy_ops qcom_qmp_ufs_phy_ops = { .power_on = qmp_ufs_power_on, - .power_off = qmp_ufs_disable, + .power_off = qmp_ufs_power_off, .calibrate = qmp_ufs_phy_calibrate, .set_mode = qmp_ufs_set_mode, .owner = THIS_MODULE, From patchwork Tue Mar 18 14:49:43 2025 Content-Type: text/plain; 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Tue, 18 Mar 2025 14:49:50 +0000 Received: from APBLRPPMTA02.qualcomm.com (APBLRPPMTA02.qualcomm.com [127.0.0.1]) by pps.reinject (8.17.1.5/8.17.1.5) with ESMTP id 52IEnmWU004296; Tue, 18 Mar 2025 14:49:50 GMT Received: from hu-maiyas-hyd.qualcomm.com (hu-nitirawa-hyd.qualcomm.com [10.213.109.152]) by APBLRPPMTA02.qualcomm.com (PPS) with ESMTP id 52IEnmLa004293; Tue, 18 Mar 2025 14:49:50 +0000 Received: by hu-maiyas-hyd.qualcomm.com (Postfix, from userid 2342877) id 94536501583; Tue, 18 Mar 2025 20:19:49 +0530 (+0530) From: Nitin Rawat To: vkoul@kernel.org, kishon@kernel.org, manivannan.sadhasivam@linaro.org, James.Bottomley@HansenPartnership.com, martin.petersen@oracle.com, konrad.dybcio@oss.qualcomm.com Cc: quic_rdwivedi@quicinc.com, linux-arm-msm@vger.kernel.org, linux-phy@lists.infradead.org, linux-kernel@vger.kernel.org, linux-scsi@vger.kernel.org, Nitin Rawat , Can Guo Subject: [PATCH V2 5/6] scsi: ufs: qcom : Refactor phy_power_on/off calls Date: Tue, 18 Mar 2025 20:19:43 +0530 Message-ID: <20250318144944.19749-6-quic_nitirawa@quicinc.com> X-Mailer: git-send-email 2.48.1 In-Reply-To: <20250318144944.19749-1-quic_nitirawa@quicinc.com> References: <20250318144944.19749-1-quic_nitirawa@quicinc.com> MIME-Version: 1.0 X-QCInternal: smtphost X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-GUID: 22gcK7MD6rPyO5oBHuloKAN1Ib_Rp7sz X-Proofpoint-ORIG-GUID: 22gcK7MD6rPyO5oBHuloKAN1Ib_Rp7sz X-Authority-Analysis: v=2.4 cv=Jem8rVKV c=1 sm=1 tr=0 ts=67d98812 cx=c_pps a=Ou0eQOY4+eZoSc0qltEV5Q==:117 a=Ou0eQOY4+eZoSc0qltEV5Q==:17 a=Vs1iUdzkB0EA:10 a=COk6AnOGAAAA:8 a=ylzO3PbLlNu0Q4qtwUgA:9 a=TjNXssC_j7lpFel5tvFf:22 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1093,Hydra:6.0.680,FMLib:17.12.68.34 definitions=2025-03-18_07,2025-03-17_03,2024-11-22_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 suspectscore=0 mlxlogscore=999 spamscore=0 mlxscore=0 malwarescore=0 adultscore=0 phishscore=0 impostorscore=0 priorityscore=1501 lowpriorityscore=0 bulkscore=0 clxscore=1015 classifier=spam authscore=0 authtc=n/a authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.19.0-2502280000 definitions=main-2503180107 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20250318_075001_831555_AFA04DF0 X-CRM114-Status: GOOD ( 17.02 ) X-BeenThere: linux-phy@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: Linux Phy Mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-phy" Errors-To: linux-phy-bounces+linux-phy=archiver.kernel.org@lists.infradead.org Commit 3f6d1767b1a0 ("phy: ufs-qcom: Refactor all init steps into phy_poweron") removes the phy_power_on/off from ufs_qcom_setup_clocks to suspend/resume func. To have a better power saving, remove the phy_power_on/off calls from resume/suspend path and put them back to ufs_qcom_setup_clocks, so that PHY regulators & clks can be turned on/off along with UFS's clocks. Since phy phy_power_on is separated out from phy calibrate, make separate calls to phy_power_on and phy_calibrate calls from ufs qcom driver. Co-developed-by: Can Guo Signed-off-by: Can Guo Co-developed-by: Ram Kumar Dwivedi Signed-off-by: Ram Kumar Dwivedi Signed-off-by: Nitin Rawat --- drivers/ufs/host/ufs-qcom.c | 58 +++++++++++++++++-------------------- 1 file changed, 26 insertions(+), 32 deletions(-) -- 2.48.1 diff --git a/drivers/ufs/host/ufs-qcom.c b/drivers/ufs/host/ufs-qcom.c index 1b37449fbffc..5c7b6c75d669 100644 --- a/drivers/ufs/host/ufs-qcom.c +++ b/drivers/ufs/host/ufs-qcom.c @@ -473,6 +473,11 @@ static int ufs_qcom_power_up_sequence(struct ufs_hba *hba) goto out_disable_phy; } + ret = phy_calibrate(phy); + if (ret) { + dev_err(hba->dev, "Failed to calibrate PHY %d\n", ret); + goto out_disable_phy; + } ufs_qcom_select_unipro_mode(host); return 0; @@ -633,26 +638,17 @@ static int ufs_qcom_suspend(struct ufs_hba *hba, enum ufs_pm_op pm_op, enum ufs_notify_change_status status) { struct ufs_qcom_host *host = ufshcd_get_variant(hba); - struct phy *phy = host->generic_phy; if (status == PRE_CHANGE) return 0; - if (ufs_qcom_is_link_off(hba)) { - /* - * Disable the tx/rx lane symbol clocks before PHY is - * powered down as the PLL source should be disabled - * after downstream clocks are disabled. - */ + if (!ufs_qcom_is_link_active(hba)) ufs_qcom_disable_lane_clks(host); - phy_power_off(phy); - /* reset the connected UFS device during power down */ - ufs_qcom_device_reset_ctrl(hba, true); - } else if (!ufs_qcom_is_link_active(hba)) { - ufs_qcom_disable_lane_clks(host); - } + /* reset the connected UFS device during power down */ + if (ufs_qcom_is_link_off(hba) && host->device_reset) + ufs_qcom_device_reset_ctrl(hba, true); return ufs_qcom_ice_suspend(host); } @@ -660,26 +656,11 @@ static int ufs_qcom_suspend(struct ufs_hba *hba, enum ufs_pm_op pm_op, static int ufs_qcom_resume(struct ufs_hba *hba, enum ufs_pm_op pm_op) { struct ufs_qcom_host *host = ufshcd_get_variant(hba); - struct phy *phy = host->generic_phy; int err; - if (ufs_qcom_is_link_off(hba)) { - err = phy_power_on(phy); - if (err) { - dev_err(hba->dev, "%s: failed PHY power on: %d\n", - __func__, err); - return err; - } - - err = ufs_qcom_enable_lane_clks(host); - if (err) - return err; - - } else if (!ufs_qcom_is_link_active(hba)) { - err = ufs_qcom_enable_lane_clks(host); - if (err) - return err; - } + err = ufs_qcom_enable_lane_clks(host); + if (err) + return err; return ufs_qcom_ice_resume(host); } @@ -1036,6 +1017,8 @@ static int ufs_qcom_setup_clocks(struct ufs_hba *hba, bool on, enum ufs_notify_change_status status) { struct ufs_qcom_host *host = ufshcd_get_variant(hba); + struct phy *phy = host->generic_phy; + int err; /* * In case ufs_qcom_init() is not yet done, simply ignore. @@ -1054,10 +1037,20 @@ static int ufs_qcom_setup_clocks(struct ufs_hba *hba, bool on, /* disable device ref_clk */ ufs_qcom_dev_ref_clk_ctrl(host, false); } + err = phy_power_off(phy); + if (err) { + dev_err(hba->dev, "phy power off failed, ret=%d\n", err); + return err; + } } break; case POST_CHANGE: if (on) { + err = phy_power_on(phy); + if (err) { + dev_err(hba->dev, "phy power on failed, ret = %d\n", err); + return err; + } /* enable the device ref clock for HS mode*/ if (ufshcd_is_hs_mode(&hba->pwr_info)) ufs_qcom_dev_ref_clk_ctrl(host, true); @@ -1240,9 +1233,10 @@ static int ufs_qcom_init(struct ufs_hba *hba) static void ufs_qcom_exit(struct ufs_hba *hba) { struct ufs_qcom_host *host = ufshcd_get_variant(hba); + struct phy *phy = host->generic_phy; ufs_qcom_disable_lane_clks(host); - phy_power_off(host->generic_phy); + phy_power_off(phy); phy_exit(host->generic_phy); } From patchwork Tue Mar 18 14:49:44 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Nitin Rawat X-Patchwork-Id: 14021111 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 4728CC35FFB for ; Tue, 18 Mar 2025 14:50:05 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To: Message-ID:Date:Subject:Cc:To:From:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; 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Tue, 18 Mar 2025 14:49:51 GMT Received: from pps.reinject (localhost [127.0.0.1]) by APBLRPPMTA02.qualcomm.com (PPS) with ESMTP id 45dkgmfv9d-1; Tue, 18 Mar 2025 14:49:51 +0000 Received: from APBLRPPMTA02.qualcomm.com (APBLRPPMTA02.qualcomm.com [127.0.0.1]) by pps.reinject (8.17.1.5/8.17.1.5) with ESMTP id 52IEnmWX004296; Tue, 18 Mar 2025 14:49:51 GMT Received: from hu-maiyas-hyd.qualcomm.com (hu-nitirawa-hyd.qualcomm.com [10.213.109.152]) by APBLRPPMTA02.qualcomm.com (PPS) with ESMTP id 52IEnmLc004293; Tue, 18 Mar 2025 14:49:51 +0000 Received: by hu-maiyas-hyd.qualcomm.com (Postfix, from userid 2342877) id 67007501582; Tue, 18 Mar 2025 20:19:50 +0530 (+0530) From: Nitin Rawat To: vkoul@kernel.org, kishon@kernel.org, manivannan.sadhasivam@linaro.org, James.Bottomley@HansenPartnership.com, martin.petersen@oracle.com, konrad.dybcio@oss.qualcomm.com Cc: quic_rdwivedi@quicinc.com, linux-arm-msm@vger.kernel.org, linux-phy@lists.infradead.org, linux-kernel@vger.kernel.org, linux-scsi@vger.kernel.org, Nitin Rawat , Can Guo Subject: [PATCH V2 6/6] scsi: ufs: host : Introduce phy_power_on/off wrapper function Date: Tue, 18 Mar 2025 20:19:44 +0530 Message-ID: <20250318144944.19749-7-quic_nitirawa@quicinc.com> X-Mailer: git-send-email 2.48.1 In-Reply-To: <20250318144944.19749-1-quic_nitirawa@quicinc.com> References: <20250318144944.19749-1-quic_nitirawa@quicinc.com> MIME-Version: 1.0 X-QCInternal: smtphost X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-ORIG-GUID: QS5i6desbJK_NXXjAiLvF8OMGpN0-plh X-Proofpoint-GUID: QS5i6desbJK_NXXjAiLvF8OMGpN0-plh X-Authority-Analysis: v=2.4 cv=aMLwqa9m c=1 sm=1 tr=0 ts=67d98812 cx=c_pps a=Ou0eQOY4+eZoSc0qltEV5Q==:117 a=Ou0eQOY4+eZoSc0qltEV5Q==:17 a=Vs1iUdzkB0EA:10 a=COk6AnOGAAAA:8 a=Dj_YmL__GzIFt5dFpcoA:9 a=TjNXssC_j7lpFel5tvFf:22 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1093,Hydra:6.0.680,FMLib:17.12.68.34 definitions=2025-03-18_07,2025-03-17_03,2024-11-22_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 impostorscore=0 priorityscore=1501 spamscore=0 clxscore=1015 phishscore=0 mlxscore=0 suspectscore=0 malwarescore=0 mlxlogscore=999 bulkscore=0 adultscore=0 lowpriorityscore=0 classifier=spam authscore=0 authtc=n/a authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.19.0-2502280000 definitions=main-2503180109 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20250318_075002_772549_4838BDC2 X-CRM114-Status: GOOD ( 15.63 ) X-BeenThere: linux-phy@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: Linux Phy Mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-phy" Errors-To: linux-phy-bounces+linux-phy=archiver.kernel.org@lists.infradead.org Introduce ufs_qcom_phy_power_on and ufs_qcom_phy_power_off wrapper functions with mutex protection to ensure safe usage of is_phy_pwr_on and prevent possible race conditions. Co-developed-by: Can Guo Signed-off-by: Can Guo Signed-off-by: Nitin Rawat --- drivers/ufs/host/ufs-qcom.c | 44 +++++++++++++++++++++++++++++++------ drivers/ufs/host/ufs-qcom.h | 4 ++++ 2 files changed, 41 insertions(+), 7 deletions(-) -- 2.48.1 diff --git a/drivers/ufs/host/ufs-qcom.c b/drivers/ufs/host/ufs-qcom.c index 5c7b6c75d669..8f80724e64b9 100644 --- a/drivers/ufs/host/ufs-qcom.c +++ b/drivers/ufs/host/ufs-qcom.c @@ -421,6 +421,38 @@ static u32 ufs_qcom_get_hs_gear(struct ufs_hba *hba) return UFS_HS_G3; } +static int ufs_qcom_phy_power_on(struct ufs_hba *hba) +{ + struct ufs_qcom_host *host = ufshcd_get_variant(hba); + struct phy *phy = host->generic_phy; + int ret = 0; + + guard(mutex)(&host->phy_mutex); + if (!host->is_phy_pwr_on) { + ret = phy_power_on(phy); + if (!ret) + host->is_phy_pwr_on = true; + } + + return ret; +} + +static int ufs_qcom_phy_power_off(struct ufs_hba *hba) +{ + struct ufs_qcom_host *host = ufshcd_get_variant(hba); + struct phy *phy = host->generic_phy; + int ret = 0; + + guard(mutex)(&host->phy_mutex); + if (host->is_phy_pwr_on) { + ret = phy_power_off(phy); + if (!ret) + host->is_phy_pwr_on = false; + } + + return ret; +} + static int ufs_qcom_power_up_sequence(struct ufs_hba *hba) { struct ufs_qcom_host *host = ufshcd_get_variant(hba); @@ -449,7 +481,7 @@ static int ufs_qcom_power_up_sequence(struct ufs_hba *hba) return ret; if (phy->power_count) { - phy_power_off(phy); + ufs_qcom_phy_power_off(hba); phy_exit(phy); } @@ -466,7 +498,7 @@ static int ufs_qcom_power_up_sequence(struct ufs_hba *hba) goto out_disable_phy; /* power on phy - start serdes and phy's power and clocks */ - ret = phy_power_on(phy); + ret = ufs_qcom_phy_power_on(hba); if (ret) { dev_err(hba->dev, "%s: phy power on failed, ret = %d\n", __func__, ret); @@ -1017,7 +1049,6 @@ static int ufs_qcom_setup_clocks(struct ufs_hba *hba, bool on, enum ufs_notify_change_status status) { struct ufs_qcom_host *host = ufshcd_get_variant(hba); - struct phy *phy = host->generic_phy; int err; /* @@ -1037,7 +1068,7 @@ static int ufs_qcom_setup_clocks(struct ufs_hba *hba, bool on, /* disable device ref_clk */ ufs_qcom_dev_ref_clk_ctrl(host, false); } - err = phy_power_off(phy); + err = ufs_qcom_phy_power_off(hba); if (err) { dev_err(hba->dev, "phy power off failed, ret=%d\n", err); return err; @@ -1046,7 +1077,7 @@ static int ufs_qcom_setup_clocks(struct ufs_hba *hba, bool on, break; case POST_CHANGE: if (on) { - err = phy_power_on(phy); + err = ufs_qcom_phy_power_on(hba); if (err) { dev_err(hba->dev, "phy power on failed, ret = %d\n", err); return err; @@ -1233,10 +1264,9 @@ static int ufs_qcom_init(struct ufs_hba *hba) static void ufs_qcom_exit(struct ufs_hba *hba) { struct ufs_qcom_host *host = ufshcd_get_variant(hba); - struct phy *phy = host->generic_phy; ufs_qcom_disable_lane_clks(host); - phy_power_off(phy); + ufs_qcom_phy_power_off(hba); phy_exit(host->generic_phy); } diff --git a/drivers/ufs/host/ufs-qcom.h b/drivers/ufs/host/ufs-qcom.h index d0e6ec9128e7..3db29fbcd40b 100644 --- a/drivers/ufs/host/ufs-qcom.h +++ b/drivers/ufs/host/ufs-qcom.h @@ -252,6 +252,10 @@ struct ufs_qcom_host { u32 phy_gear; bool esi_enabled; + /* flag to check if phy is powered on */ + bool is_phy_pwr_on; + /* Protect the usage of is_phy_pwr_on against racing */ + struct mutex phy_mutex; }; struct ufs_qcom_drvdata {