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Miller" , Jakub Kicinski , Paolo Abeni , Eric Dumazet , "Andrew Lunn" CC: Gal Pressman , Leon Romanovsky , "Saeed Mahameed" , Leon Romanovsky , Tariq Toukan , , , , Moshe Shemesh , Mark Bloch Subject: [PATCH net-next 1/5] net/mlx5: Lag, use port selection tables when available Date: Wed, 19 Mar 2025 16:02:59 +0200 Message-ID: <1742392983-153050-2-git-send-email-tariqt@nvidia.com> X-Mailer: git-send-email 2.8.0 In-Reply-To: <1742392983-153050-1-git-send-email-tariqt@nvidia.com> References: <1742392983-153050-1-git-send-email-tariqt@nvidia.com> Precedence: bulk X-Mailing-List: netdev@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-NV-OnPremToCloud: AnonymousSubmission X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: CY4PEPF0000EE36:EE_|PH7PR12MB8039:EE_ X-MS-Office365-Filtering-Correlation-Id: be7c1365-8ffc-48fb-8e6d-08dd66eef603 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|1800799024|36860700013|82310400026|376014; X-Microsoft-Antispam-Message-Info: Gk1jms/bRV71z0nVdrdx94pvd9LTjHAFu50lJki3G9OLF8X+mYTZuEceS1YlWCFw/ucXyvetIJk5hDfIoTUhZtSh3tf80TyrpTyaUyQbhSWQT5rmTpasIsLEM2BgqSRo4JyPO/7kn5HmSimRgHVwdOBoW2nJww2EjoNVEWGu2t2TZNdlFpNX7Hv3xfhjnnmdfp96UWEHps1xS7xuBys3I/1tzUv3VmP3vnHntsdyyDNR+90ergClbwrhu7RqarFPYBOyEmoECfksQ/loTLiQgLL5XB/g22346nhz78Gpx+FXR32nbzd6U/hM+DbrFQtFPFYCezH0P4Iz1hOBcdM+86OsghNBC9u64dc2J/IxCFrAd5CUmWZwDoP0v1EnG8Tc+q0al8WVuGtl4LbC9Yusmw9g0M9lfXk9ocRWMqjbW2Rlxi3XVE7dvdv5Xuq8PtgH2bDvEus9Wp4pHnkZI3hMLn1UMTJBrt1JY/GUDBKmEdpJ+52CEvt8TK1jvRNkCRDyiSW5ZEUL4xXOa9EjPGMAKtlI9NzhDliXB5aCSoFoCW1J06o24mbmP2oGOomy7iK4GRjRlIShavvZdhUbTmcRXHweI03y97PjgXfMLw1dCfDzRo1J9XCZgqItMOiw4W+gPdXRB0+64WJfuzf81XLOcSwYPfTC4IiSgz9bGusY7+VN/yyq/v5ho1ZqYPecZL51siLXL2B3BFzZ0XaFxGHAjvYTt9OLLfJa0T8xExBMlwsWTmjKFVahIzkC2RbmJ95gaHFUbxSNU1Lt2fOr47WO7pfqECeovEbdkDFxZ3ChLQ7muv8FgnSdpMQgTAeiiXGivCPw/w8bXI9ayNgWsuLWylo92S083fMDT5p0Oo1gBvEjVj5GtXybYaxUOwdbLnQC5VKMWwn31MwI9oOqeHvd6sPeGpLYVyZji/L9q7aWNZ8ESZD/IxzZ4kKEIb2logEErP87GkIQ+fnLMddFm0YDnHSwg0C7iptD0bFr1X6j1D9RVMYkMnLLBpA2NtWha3eaikHgDIVXZUc2Xo5ywBkDUpGqvw9wgyv+0/kJ7/3TQP2+sLB0lHbuQdwoLNDR6Cif1FFPsq7mcelH9XP794EP/cK8TujN1pQkmSZWd/2wFoF/BpYcnmX8XL6BPB0RF9suU0f0VYPNntBp58tzK5DdoLlcnOX/Vc0R1RZCPW0manfiIwM0vH0j4+XssVPKTTxu7t/6X62U/U4ZnUvK4MnhlrK+hebbWE+nBaCnJ1BOManCjQ0a7hBf6qV8bJN2kJqWI7aopqFT2M11dPR2sZpuyYQ2Rry0Zu1i3XQiVo8HDrJAOPiDM8HJs/sk/kIDJwpnHkLLsabgMFumRzLOJUHNnZu42xffKAluH1Sg8RPbP81abyLS5wEJvAJFBqe3B03cs/c8ObfzYQ27gacIHXknwzSasoapGlMourfsCIjpo54GyXi7IjznUNx5axO5san7i8T+YJMGCv5xfatTr6PUpw== X-Forefront-Antispam-Report: CIP:216.228.118.232;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:dc7edge1.nvidia.com;CAT:NONE;SFS:(13230040)(1800799024)(36860700013)(82310400026)(376014);DIR:OUT;SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 19 Mar 2025 14:04:27.1375 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: be7c1365-8ffc-48fb-8e6d-08dd66eef603 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.118.232];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: CY4PEPF0000EE36.namprd05.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: PH7PR12MB8039 X-Patchwork-Delegate: kuba@kernel.org From: Mark Bloch As queue affinity is being deprecated and will no longer be supported in the future, Always check for the presence of the port selection namespace. When available, leverage it to distribute traffic across the physical ports via steering, ensuring compatibility with future NICs. Signed-off-by: Mark Bloch Reviewed-by: Maor Gottlieb Signed-off-by: Tariq Toukan --- .../net/ethernet/mellanox/mlx5/core/lag/lag.c | 38 +++++-------------- 1 file changed, 9 insertions(+), 29 deletions(-) diff --git a/drivers/net/ethernet/mellanox/mlx5/core/lag/lag.c b/drivers/net/ethernet/mellanox/mlx5/core/lag/lag.c index ed2ba272946b..e856edf6bbb5 100644 --- a/drivers/net/ethernet/mellanox/mlx5/core/lag/lag.c +++ b/drivers/net/ethernet/mellanox/mlx5/core/lag/lag.c @@ -584,8 +584,9 @@ void mlx5_modify_lag(struct mlx5_lag *ldev, } } -static int mlx5_lag_set_port_sel_mode_roce(struct mlx5_lag *ldev, - unsigned long *flags) +static int mlx5_lag_set_port_sel_mode(struct mlx5_lag *ldev, + enum mlx5_lag_mode mode, + unsigned long *flags) { int first_idx = mlx5_lag_get_dev_index_by_seq(ldev, MLX5_LAG_P1); struct mlx5_core_dev *dev0; @@ -593,7 +594,12 @@ static int mlx5_lag_set_port_sel_mode_roce(struct mlx5_lag *ldev, if (first_idx < 0) return -EINVAL; + if (mode == MLX5_LAG_MODE_MPESW || + mode == MLX5_LAG_MODE_MULTIPATH) + return 0; + dev0 = ldev->pf[first_idx].dev; + if (!MLX5_CAP_PORT_SELECTION(dev0, port_select_flow_table)) { if (ldev->ports > 2) return -EINVAL; @@ -608,32 +614,10 @@ static int mlx5_lag_set_port_sel_mode_roce(struct mlx5_lag *ldev, return 0; } -static void mlx5_lag_set_port_sel_mode_offloads(struct mlx5_lag *ldev, - struct lag_tracker *tracker, - enum mlx5_lag_mode mode, - unsigned long *flags) -{ - int first_idx = mlx5_lag_get_dev_index_by_seq(ldev, MLX5_LAG_P1); - struct lag_func *dev0; - - if (first_idx < 0 || mode == MLX5_LAG_MODE_MPESW) - return; - - dev0 = &ldev->pf[first_idx]; - if (MLX5_CAP_PORT_SELECTION(dev0->dev, port_select_flow_table) && - tracker->tx_type == NETDEV_LAG_TX_TYPE_HASH) { - if (ldev->ports > 2) - ldev->buckets = MLX5_LAG_MAX_HASH_BUCKETS; - set_bit(MLX5_LAG_MODE_FLAG_HASH_BASED, flags); - } -} - static int mlx5_lag_set_flags(struct mlx5_lag *ldev, enum mlx5_lag_mode mode, struct lag_tracker *tracker, bool shared_fdb, unsigned long *flags) { - bool roce_lag = mode == MLX5_LAG_MODE_ROCE; - *flags = 0; if (shared_fdb) { set_bit(MLX5_LAG_MODE_FLAG_SHARED_FDB, flags); @@ -643,11 +627,7 @@ static int mlx5_lag_set_flags(struct mlx5_lag *ldev, enum mlx5_lag_mode mode, if (mode == MLX5_LAG_MODE_MPESW) set_bit(MLX5_LAG_MODE_FLAG_FDB_SEL_MODE_NATIVE, flags); - if (roce_lag) - return mlx5_lag_set_port_sel_mode_roce(ldev, flags); - - mlx5_lag_set_port_sel_mode_offloads(ldev, tracker, mode, flags); - return 0; + return mlx5_lag_set_port_sel_mode(ldev, mode, flags); } char *mlx5_get_str_port_sel_mode(enum mlx5_lag_mode mode, unsigned long flags) From patchwork Wed Mar 19 14:03:00 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Tariq Toukan X-Patchwork-Id: 14022619 X-Patchwork-Delegate: kuba@kernel.org Received: from NAM11-BN8-obe.outbound.protection.outlook.com (mail-bn8nam11on2079.outbound.protection.outlook.com [40.107.236.79]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id CA68B1A3BD7; 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Miller" , Jakub Kicinski , Paolo Abeni , Eric Dumazet , "Andrew Lunn" CC: Gal Pressman , Leon Romanovsky , "Saeed Mahameed" , Leon Romanovsky , Tariq Toukan , , , , Moshe Shemesh , Mark Bloch , Amir Tzin , Aya Levin Subject: [PATCH net-next 2/5] net/mlx5: fw reset, check bridge accessibility at earlier stage Date: Wed, 19 Mar 2025 16:03:00 +0200 Message-ID: <1742392983-153050-3-git-send-email-tariqt@nvidia.com> X-Mailer: git-send-email 2.8.0 In-Reply-To: <1742392983-153050-1-git-send-email-tariqt@nvidia.com> References: <1742392983-153050-1-git-send-email-tariqt@nvidia.com> Precedence: bulk X-Mailing-List: netdev@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-NV-OnPremToCloud: AnonymousSubmission X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: CY4PEPF0000EE36:EE_|CY5PR12MB6624:EE_ X-MS-Office365-Filtering-Correlation-Id: 0201ca6b-7cde-42ab-e3c7-08dd66eef91f X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|82310400026|1800799024|376014|36860700013; X-Microsoft-Antispam-Message-Info: 5FXnxGSEulYY4+X93W3Mo+Jh407n+o8REoAU/wWuidQcRl4keX08cvyJ3r8iwJCVI0bMdnFF++D48AnYaaImyg+S5Gx0iMV7bkVxcelf34Im1S1K5vHJ7iQ3/iV64YHuQwzUxfvUkAjXw+Md6K5MrPjmWFbuuv1WBkSiDPlO1Anp1tdul7Qolst2n0lyWPNnb35p4cG0z1kIXAlQQxqxfcIn+HMHQ0vX4EhRYPD+0ZjoE5euKgdI+bkxGJ+zG52VE91UyvQLKCwOOj3fTFWdk4rmsSoKe0HWEOomyITDFQBo6XtEdL5+bVaWHLnBmv8X78ol8tOsDfqUwM+C+zussuNzK0BXnfy4+eDUo923PH4e8EDNTNfQEDdVhLAUDnfCxOhwVWAE6pqOM++xpQkt3OStJAngUOExOMQ7DTj1mg0OZMRWc7GhFxq8DoRxUq7DDyGAD/+eX4r/zz5srhopDLkNn97L1MxK7VLZhn5V6OpttXgbJa5WOZ/0TT9FL5bxmm6aTSdE9ZjXjZuoLbKkF5fozpiQJ0ylBvwMd+czKLk/SHnYaZpOh8R6l/jMG9Oi3jbIiHJn3xiqPZJ+2Ox7XDLAA8OAT78jf2eDmM5KX9AwpTMTEWfhmrtfDAOmG+/V8k4OfhpSOQ5JP8LT6gGF/DmLaCEvfqXCDRwqei1wHsoRHgWWWra6raJXWZBfEftr0o476D36dNxN215irexj3Bi/cCNppXIW63GFE1q3wt9jQo4fZ6IymVXo2EiPUsWJWjrZK3i91G+kSMIk429QcoKVGLwPClzpVtQUGHe7L+P8XkD14YG+2hVZMJ0eT1uziO+hl/6LMc+VP+fgOzEXmd6WhEMHOI/LUs18Lc+ICBS94RBGdNq8JlCb2gDqQVmkKbSl39Y5MwYE80Jec4k79HdL+EVUtqZr7F3w5MtzAEof/1q+UbITekK4qJhlPc9xKeStgN8zCG7Jtnub72K71xKnDMBR5i3pW/+dTs+zTzYzB352xNvAFchZhmrIjHfWoWJ6WzPttULCbMylHI2XKKvbinLA0vApii4uDwRl5p6ZMqiZlLEy/wW3y3yOr1mbdReuT0NKRsCjh7mm2A0b31j0YpsgpzA+iWI4vmPKLpNeIhcHn/Zm8IlhJRlFd5AmfdQoln6ECDW49zAzTmHDGY330HcSFuK1tWuCeBjrY6qhhYaO0eBgJY4BbIzuTs+jFfpHBOeVCxYPB+kG2f1s5z05e4afI3wwV3o0521z0+OQ3GbkQQv16tPjFk3pL0kw3hF58ua94is1Mh7ZLKwIeJMUKImqFSMnvLFTneo5z+7NwWX1KN7fh2/38mSX492z46JoYv7ZzvoX6bqitcEAeK7nV9/+43cF2cxoImYygnVf2K4PlKko8dOweW6rawRswWajPh6Wbv3oe5tecXrvfKCpDf8kYhWe161AEvQDFGlMYYVs1QJNYFZHu71hTSSxv1LS68L3vG9GxaUWkPiit6Vjd6AlKSqY77Ky4hBtFPU= X-Forefront-Antispam-Report: CIP:216.228.118.232;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:dc7edge1.nvidia.com;CAT:NONE;SFS:(13230040)(82310400026)(1800799024)(376014)(36860700013);DIR:OUT;SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 19 Mar 2025 14:04:32.3407 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 0201ca6b-7cde-42ab-e3c7-08dd66eef91f X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.118.232];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: CY4PEPF0000EE36.namprd05.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: CY5PR12MB6624 X-Patchwork-Delegate: kuba@kernel.org From: Amir Tzin Currently, mlx5_is_reset_now_capable() checks whether the pci bridge is accessible only on bridge hot plug capability check. If the pci bridge is not accessible, reset now will fail regardless of bridge hotplug capability. Move this check to function mlx5_is_reset_now_capable() which, in such case, aborts the reset and does so in the request phase instead of the reset now phase. Signed-off-by: Aya Levin Signed-off-by: Moshe Shemesh Signed-off-by: Amir Tzin Signed-off-by: Tariq Toukan --- .../net/ethernet/mellanox/mlx5/core/fw_reset.c | 15 +++++++++------ 1 file changed, 9 insertions(+), 6 deletions(-) diff --git a/drivers/net/ethernet/mellanox/mlx5/core/fw_reset.c b/drivers/net/ethernet/mellanox/mlx5/core/fw_reset.c index 566710d34a7b..6830a49fe682 100644 --- a/drivers/net/ethernet/mellanox/mlx5/core/fw_reset.c +++ b/drivers/net/ethernet/mellanox/mlx5/core/fw_reset.c @@ -345,15 +345,12 @@ static void mlx5_fw_live_patch_event(struct work_struct *work) } #if IS_ENABLED(CONFIG_HOTPLUG_PCI_PCIE) -static int mlx5_check_hotplug_interrupt(struct mlx5_core_dev *dev) +static int mlx5_check_hotplug_interrupt(struct mlx5_core_dev *dev, + struct pci_dev *bridge) { - struct pci_dev *bridge = dev->pdev->bus->self; u16 reg16; int err; - if (!bridge) - return -EOPNOTSUPP; - err = pcie_capability_read_word(bridge, PCI_EXP_SLTCTL, ®16); if (err) return err; @@ -416,9 +413,15 @@ static int mlx5_check_dev_ids(struct mlx5_core_dev *dev, u16 dev_id) static bool mlx5_is_reset_now_capable(struct mlx5_core_dev *dev, u8 reset_method) { + struct pci_dev *bridge = dev->pdev->bus->self; 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Miller" , Jakub Kicinski , Paolo Abeni , Eric Dumazet , "Andrew Lunn" CC: Gal Pressman , Leon Romanovsky , "Saeed Mahameed" , Leon Romanovsky , Tariq Toukan , , , , Moshe Shemesh , Mark Bloch , Shay Drory Subject: [PATCH net-next 3/5] net/mlx5: Update pfnum retrieval for devlink port attributes Date: Wed, 19 Mar 2025 16:03:01 +0200 Message-ID: <1742392983-153050-4-git-send-email-tariqt@nvidia.com> X-Mailer: git-send-email 2.8.0 In-Reply-To: <1742392983-153050-1-git-send-email-tariqt@nvidia.com> References: <1742392983-153050-1-git-send-email-tariqt@nvidia.com> Precedence: bulk X-Mailing-List: netdev@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-NV-OnPremToCloud: AnonymousSubmission X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: CY4PEPF0000EE36:EE_|IA1PR12MB7712:EE_ X-MS-Office365-Filtering-Correlation-Id: fddf63a7-fe89-48b2-6ea0-08dd66eefaee X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|1800799024|36860700013|376014|82310400026; X-Microsoft-Antispam-Message-Info: AKSvmIT6qdLPT2YBd5iv+k2R6TnRtgDGnppkBX9syWmLE9cGf0muHfQQCvBd/YgEYQnuxkuw68NNk7bqwr0mv4sOfPcmqq/e2+ritDUMzCYHXJFEiidmW83K/Ue+KzugGaoXmgXDMMRxVJGInq20zRzPYUJqgBly6LGMZxYfAAdVblUTGTVdpW1Y3kheZemACAxaTRucKHjdj/PnCVOcA++8A3aRfG2hk9E23oxGGqaZA9p3UB8p+gis2oQoWvPcE/Gps7fgPNKJd1K2VVlNUbrdmd0j8Pn08BMDblkLIwI1D05dmywTPrqBB1FtCo+1QRMZJppTqrmxlBPplTsFKiSbh7WetrqdYk6tX+OmuUVPLlK3xUdXUt0n+9+VTKW+d4q3gfcx+vWnELQ9efqyR+tSc4rTLTiqgOMl4qKXO6SdRVVJgOpWrMK1tifr/i2jUef+1/EPFHBuBubW6MUTtfxk6FmzetCS1CU97EKT+XVvb38h9gS5QBrUaLStmhrHDST6PvqFOzMnjPRj0G4PWKqyzTFlPzh6SVHOpe6KqDcyR2dfGTI9698OpgVDGWrdxfWJkp38LI3/z2stx3dcxnAm8sHMZbnh31sJ8FYbdVKastgBMJQ2sFk1985dUz7f/Rv3/v2qfG6lxKN8f3DbJ2p+RS43YNseHfH9ih2RMOalYMLJj8dDkVYwxyX4OHH07/q+9pVIRMwy0LYdSxJW4BhoNlPOj9RWa5NKO7pHTJ6bn1Il5O2jk4d/2CEEZ51ob0SQ1d9xedbazof5OLUZICeUUWKG1W/MXPwE9GKURYGKF141BiKckTtYpU7GMFKiY7AfxhGQBo9y4f4BT92W4taddMjH9NI4K5K9Hoe/eSsiTdAEFdvn3fYPphuGC/iBUNBPGpwFfbnNkvBPf1wD+U3eXT/aSGWbfrKe+D4Pw3itCNSCWXMLPKLsFIoqziBddUeJLCFpR6Km6r+3Uy95ZN3+/5u/F7xvtltnrVi5EuoOrGWZ1ZazRUWGG4DaTuY6OwRfzaL9VjdDn9fhRRBY2iu/MbZwMNoUWP8dmbSOoE0gtxcQTwvUa2eEGGv0IikI3rjI5G2TWwyCBPpA94VvJFQ72VuYB23d/xSS6JnPaL/SrMRyre06gjKRKyQ81UoCgOLUdQL3PGrOqUz1Z3ycSyI0g1rBNHzZoEX2PavKO0cQ6Jq1jBW0Dd0WL2yMqlV15uBbcws50lVRtQbOG9/VDqhjOHOW53buSBn4RyzUpZEI0ELZUPbwdI9Rw3Cg19zKCwCYEJQPvM6eJFNG1ZKhJsklXk9mmXvWCqSOeIvOjK/PPzOl0T28nYaLDnwPzynNIxKd5Cp0hNZvoaTw+ydtWYz+d3Cgu+G10N+q0rc5miLEnNSZeV/M5lFhHn+1OSHmR8DAzSpvy5yJwuAJX0P1Bx4McV9eQX5CGLmDzNQPmd7YbpIGY+aUHELk1ByzDbE4Y9rM4DO7NiN4Pwb14iztZBuzp5iPx7AtoxjJ8ImdO3I= X-Forefront-Antispam-Report: CIP:216.228.118.232;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:dc7edge1.nvidia.com;CAT:NONE;SFS:(13230040)(1800799024)(36860700013)(376014)(82310400026);DIR:OUT;SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 19 Mar 2025 14:04:35.3876 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: fddf63a7-fe89-48b2-6ea0-08dd66eefaee X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.118.232];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: CY4PEPF0000EE36.namprd05.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: IA1PR12MB7712 X-Patchwork-Delegate: kuba@kernel.org From: Shay Drory Align mlx5 driver usage of 'pfnum' with the documentation clarification introduced in commit bb70b0d48d8e ("devlink: Improve the port attributes description"). Signed-off-by: Shay Drory Reviewed-by: Mark Bloch Signed-off-by: Tariq Toukan --- drivers/net/ethernet/mellanox/mlx5/core/esw/devlink_port.c | 4 ++-- drivers/net/ethernet/mellanox/mlx5/core/sf/devlink.c | 2 +- 2 files changed, 3 insertions(+), 3 deletions(-) diff --git a/drivers/net/ethernet/mellanox/mlx5/core/esw/devlink_port.c b/drivers/net/ethernet/mellanox/mlx5/core/esw/devlink_port.c index 982fe3714683..b7102e14d23d 100644 --- a/drivers/net/ethernet/mellanox/mlx5/core/esw/devlink_port.c +++ b/drivers/net/ethernet/mellanox/mlx5/core/esw/devlink_port.c @@ -32,7 +32,7 @@ static void mlx5_esw_offloads_pf_vf_devlink_port_attrs_set(struct mlx5_eswitch * u16 pfnum; mlx5_esw_get_port_parent_id(dev, &ppid); - pfnum = mlx5_get_dev_index(dev); + pfnum = PCI_FUNC(dev->pdev->devfn); external = mlx5_core_is_ecpf_esw_manager(dev); if (external) controller_num = dev->priv.eswitch->offloads.host_number + 1; @@ -110,7 +110,7 @@ static void mlx5_esw_offloads_sf_devlink_port_attrs_set(struct mlx5_eswitch *esw struct netdev_phys_item_id ppid = {}; u16 pfnum; - pfnum = mlx5_get_dev_index(dev); + pfnum = PCI_FUNC(dev->pdev->devfn); mlx5_esw_get_port_parent_id(dev, &ppid); memcpy(dl_port->attrs.switch_id.id, &ppid.id[0], ppid.id_len); dl_port->attrs.switch_id.id_len = ppid.id_len; diff --git a/drivers/net/ethernet/mellanox/mlx5/core/sf/devlink.c b/drivers/net/ethernet/mellanox/mlx5/core/sf/devlink.c index b96909fbeb12..0864ba625c07 100644 --- a/drivers/net/ethernet/mellanox/mlx5/core/sf/devlink.c +++ b/drivers/net/ethernet/mellanox/mlx5/core/sf/devlink.c @@ -285,7 +285,7 @@ mlx5_sf_new_check_attr(struct mlx5_core_dev *dev, const struct devlink_port_new_ NL_SET_ERR_MSG_MOD(extack, "External controller is unsupported"); return -EOPNOTSUPP; } - if (new_attr->pfnum != mlx5_get_dev_index(dev)) { + if (new_attr->pfnum != PCI_FUNC(dev->pdev->devfn)) { NL_SET_ERR_MSG_MOD(extack, "Invalid pfnum supplied"); return -EOPNOTSUPP; } From patchwork Wed Mar 19 14:03:02 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Tariq Toukan X-Patchwork-Id: 14022621 X-Patchwork-Delegate: kuba@kernel.org Received: from NAM12-BN8-obe.outbound.protection.outlook.com (mail-bn8nam12on2040.outbound.protection.outlook.com [40.107.237.40]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id EB3ED1C5D79; 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Miller" , Jakub Kicinski , Paolo Abeni , Eric Dumazet , "Andrew Lunn" CC: Gal Pressman , Leon Romanovsky , "Saeed Mahameed" , Leon Romanovsky , Tariq Toukan , , , , Moshe Shemesh , Mark Bloch , Paul Blakey Subject: [PATCH net-next 4/5] net/mlx5e: CT: Filter legacy rules that are unrelated to nic Date: Wed, 19 Mar 2025 16:03:02 +0200 Message-ID: <1742392983-153050-5-git-send-email-tariqt@nvidia.com> X-Mailer: git-send-email 2.8.0 In-Reply-To: <1742392983-153050-1-git-send-email-tariqt@nvidia.com> References: <1742392983-153050-1-git-send-email-tariqt@nvidia.com> Precedence: bulk X-Mailing-List: netdev@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-NV-OnPremToCloud: AnonymousSubmission X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: DS3PEPF000099DF:EE_|PH7PR12MB6762:EE_ X-MS-Office365-Filtering-Correlation-Id: b26a7430-e7a4-4a3f-51d0-08dd66eefa40 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|82310400026|36860700013|1800799024|376014; X-Microsoft-Antispam-Message-Info: 5R1516HOp3OI7Ei6xcT1N2o3AZrbmMIykiu4iQYFIO4WAlcO3xO0RV3cQZhwrCPnZVyiplnE7yiqmHfySFw0zj1YLDyzR4j2jMQ3zuzP8XFcI4PNoSbWKCoJA1Wfcr8VW5QOF+bilFSDjwTmv3ewwII3lPaVOUOGIS77C7X17RUygLLDvCccfsyl/yhhI8dIeCMGn+ZNMnCLfqILxojZJpPUV1Htvo3ZUU2ff2PwjLizltzXRpKGO2j3INh0N9z+w+KWjqnd8rfiPZ/7Y6BtE6vaH95JDXkiBUfyW3uGNqMNivHuD9p7OvPrx4+NJinpK5+dpq86QONL2P5Z8LVf/O2DoPGdyMfbcVArqtpL1ysqMgIGWK6Wtz5mY2PAWCBnB3Le3vZdhZQaSJ8aQQmSlW7Pr+fZn2eP9Kx8SVw+UnX74ILIBYbt9YmilY5qriErp/c+pVsIGFP9Do4akfC0mVPKC4PVfA/gOX3O5+VGpZ4RLM/9MQO+x8uI1O/O3HC794gLe48Q30U10yiNqVu31KR7ZGfd75w5aJx2sfRAJu34iVDnz3Y/gskNUE+VyNAVhuqV+eqq4RUAZPmM2YmhYTDaNYH4ITo6zH3v7xhlL+gWytpf07qnt2Z+NRkUfgSpsstlJ2e2hfaKNmQ6pfpXr3RwYUeQrsvKV+txEVMuZzgZG0lGMgbUM1EeHP/wP5GCqUza7nZjGHr4NblZkKTgsgMUCY4oLsxsAbQBzFR9mP8nbKvjhfVE0GMBnPxvktHJiePdVLyagAmnw/6qh+hHhewGyHZVWmcfRkPBDEbK4gIcsfBfoOMdRtJQVN67k1m9SnYHYRCBDODu4vJtQ+3/x+fSh93z+rc+zE8XePYfiMA2cgyOGGLhEos6hX1UnvIEOsvUwz6c+sg22MKiy9dVHMm2o9PBFPsU7do19Lsj7wO1DcyUamYQzF7kjhFbe75t+KezIKIhhm95+VPBSMZUt/lPwbaPGsNSj0vz5E1oWq3lIVvJ00l729+pe/zYINO+WvhkfXie9k/aFAX6uCKgntUCMbY+sYA0Ef2ussC7M+oxAQLeC47br/MHweiyhK0CjlY+Yxjm8qDnVO/MY5DeySxaU0NtHzWwYCOm/YoxZQyMTaK1hdwQimYiAzL3ugFWeaOT1O6rFkBKmIVqAE6svJ2G12WZ2C9UPrwvPrK6FuRhgPoHnvZ19mXJy6JSUOa5zyznIiDnFo+r/l4FW6IRsPo71xdltgQLHm8S7qZkGsyYzLVzGMo7mJtOVF9AHbqiWx+amN09bmmTGniCbUSkO8gdfrOShlU4oB8iVHxOaFhUt6dZ9BSu6UUgr3/gwF35YyK0jeeaxC9ujqObV7KeELthfAnRUBOpP7yhSIs5+fnNI/MUfMqXM2c3n2j+SdAP2OWiUfeUEms5CevTu2Fj0Or5NhJr+kW5ql05F7yE2AajAJMfZjT7vsC/f84xk+hvkTIRgI7XsLbvagt13/ygZDJ68sWO40F4Cx5mgHafJDI= X-Forefront-Antispam-Report: CIP:216.228.118.233;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:dc7edge2.nvidia.com;CAT:NONE;SFS:(13230040)(82310400026)(36860700013)(1800799024)(376014);DIR:OUT;SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 19 Mar 2025 14:04:34.2153 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: b26a7430-e7a4-4a3f-51d0-08dd66eefa40 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.118.233];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: DS3PEPF000099DF.namprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: PH7PR12MB6762 X-Patchwork-Delegate: kuba@kernel.org From: Paul Blakey In nic mode CT setup where we do hairpin between the two nics, both nics register to the same flow table (per zone), and try to offload all rules on it. Instead, filter the rules that originated from the relevant nic (so only one side is offloaded for each nic). Signed-off-by: Paul Blakey Reviewed-by: Jianbo Liu Signed-off-by: Tariq Toukan --- .../ethernet/mellanox/mlx5/core/en/tc_ct.c | 29 +++++++++++++++++++ 1 file changed, 29 insertions(+) diff --git a/drivers/net/ethernet/mellanox/mlx5/core/en/tc_ct.c b/drivers/net/ethernet/mellanox/mlx5/core/en/tc_ct.c index a065e8fafb1d..81332cd4a582 100644 --- a/drivers/net/ethernet/mellanox/mlx5/core/en/tc_ct.c +++ b/drivers/net/ethernet/mellanox/mlx5/core/en/tc_ct.c @@ -1349,6 +1349,32 @@ mlx5_tc_ct_block_flow_offload_stats(struct mlx5_ct_ft *ft, return 0; } +static bool +mlx5_tc_ct_filter_legacy_non_nic_flows(struct mlx5_ct_ft *ft, + struct flow_cls_offload *flow) +{ + struct flow_rule *rule = flow_cls_offload_flow_rule(flow); + struct mlx5_tc_ct_priv *ct_priv = ft->ct_priv; + struct flow_match_meta match; + struct net_device *netdev; + bool same_dev = false; + + if (!is_mdev_legacy_mode(ct_priv->dev) || + !flow_rule_match_key(rule, FLOW_DISSECTOR_KEY_META)) + return true; + + flow_rule_match_meta(rule, &match); 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Miller" , Jakub Kicinski , Paolo Abeni , Eric Dumazet , "Andrew Lunn" CC: Gal Pressman , Leon Romanovsky , "Saeed Mahameed" , Leon Romanovsky , Tariq Toukan , , , , Moshe Shemesh , Mark Bloch , Jianbo Liu Subject: [PATCH net-next 5/5] net/mlx5e: TC, Don't offload CT commit if it's the last action Date: Wed, 19 Mar 2025 16:03:03 +0200 Message-ID: <1742392983-153050-6-git-send-email-tariqt@nvidia.com> X-Mailer: git-send-email 2.8.0 In-Reply-To: <1742392983-153050-1-git-send-email-tariqt@nvidia.com> References: <1742392983-153050-1-git-send-email-tariqt@nvidia.com> Precedence: bulk X-Mailing-List: netdev@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-NV-OnPremToCloud: AnonymousSubmission X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: CY4PEPF0000EE32:EE_|CY5PR12MB6648:EE_ X-MS-Office365-Filtering-Correlation-Id: ef8c6700-243e-4cd7-f78b-08dd66ef00ef X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|1800799024|36860700013|376014|82310400026; X-Microsoft-Antispam-Message-Info: nANyrNjQsE9eiA0qK2nQjvS4qTeJt0AD7alDHP1/E6j11aLWKFJqEIMWZnjDqw2VzHBfzUnLViQrfJ4XcE58pMwC/Ag9QCSWvvPWQEi1R268wSNTV0BctFuczH/BQZlqt7vVeSNeF54SkvDqI9ps/fFNl9GnRsizAzqjpDMEEx0QfqAlwNFuMNQzewUF3v6vBXqa9uWg45WoE55j57PNgQEJeXTeiIZNA6Nix6+E/Idbl6j+ThLCoQFH5LG2Hlw+5pWWD4oB8XgWo2UuHBbLVZNbFu2iUl9AwNYmmzxN9p1CobHSzgqMca6mZhk7q0SIJUYdkG3Ch4M3WgUmhAdJc3PAi5368NeZXZMurHQ8qPsNTZ/nVoectIRawQD+TdAiFFqOsKGbjXMsqceYnvkHAixFlT7FwEYO5nMR/ZrPcpijYXIN8P0qUd9+zF1BBJKaDx3MMCtHR4S0ri+BW3Ugkg3ZIQSFxQ/GJQRFes2hQ1YtFUucgvRxLXGseLJma4qJpSxKO3ba3OSPnHMHvGBvNF32XP2Wi37cZlB177V9ngY8y42JD+P3qbAVIPjugvy1wiG38ucFoQoVg5RyFuFAbrDmB1w+9qeSkjaIhZ16+iyuAW4gLPZTC5LMco4VG4AApWeDmpYueURPn6xYzgCQLeGHqW1ba+Eu8y29Ruo+xHYNajww558P7XXZa4xoGCFMBFO0BfDCwNvD1+DKZHCnfNrBlnrVUT89OjXUR/+YNf5F3Qosd4ey1qS/TRXbFUB3nxU2t9wTcaGe66QaOLG5BFtQK6+iZSRELAyUDNw68cMPaeNNfOwomp037mPVvo9oZu5m0XxQdElt/UAbVEtLsyStMVsGZbGogc6LLNvGBhVTW8x/LDadlq1ibn5kkxH6woeU41ZXZP6IAeB1pX6oaNoIkcxg2LGQo+Q4ZVl4YNXc6v2M5wjrhN1eVo55ojAmmzEfYM6e37HOi7McM4lmRL3scJ1f5BESDHW/TUlMgLhuOfMDlS+DFGRFEpu3IrJRdS+5D1Z85owOIPm+h3g+KR+oO0NlGqyX/E9qWpR2P8G7iqVpsBO6x3WRMYN5KyODoCADmav4mjOrmfYxyiKdGtcVuEvlPc4OKSVoo57nCJH8vkbhINAxCJiG2Tz8EPAd6D7ZgZO1CIt1OpCk3AUlL00ZUYOLTubn1DXhYwEGGsFSgXfB9lgzbSgirL+U2Rb9RYQX1o3YmNBMS2qqTe6FAUhGF7EPGomBNJsqbmZvXIZZwfGtw0Bm1kPCNzrLzWoKG5bgSY9tq2aqHREyMedqBMNN6KaycKdPdsfk1o2si5rFy2Jua91xVc0G3OGl2XaGhblEEpm1OZvZjdO9DqB6OjDuvjuFZUP3krn+jnaD1FZqtg93+XGii7vLaTrZrCkvX+TpFmk6AYlQYsDklu7yaWeY+q4HWiZhrto1eLKsgLRsouxHKrdMQCMD1Y+ETeR25ORHBnRc4qWWKHGTCy1xjg== X-Forefront-Antispam-Report: CIP:216.228.118.232;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:dc7edge1.nvidia.com;CAT:NONE;SFS:(13230040)(1800799024)(36860700013)(376014)(82310400026);DIR:OUT;SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 19 Mar 2025 14:04:45.4796 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: ef8c6700-243e-4cd7-f78b-08dd66ef00ef X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.118.232];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: CY4PEPF0000EE32.namprd05.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: CY5PR12MB6648 X-Patchwork-Delegate: kuba@kernel.org From: Jianbo Liu For CT action with commit argument, it's usually followed by the forward action, either to the output netdev or next chain. The default behavior for software is to drop by setting action attribute to TC_ACT_SHOT instead of TC_ACT_PIPE if it's the last action. But driver can't handle it, so block the offload for such case. Signed-off-by: Jianbo Liu Reviewed-by: Roi Dayan Signed-off-by: Tariq Toukan --- .../net/ethernet/mellanox/mlx5/core/en/tc/act/ct.c | 11 +++++++++++ 1 file changed, 11 insertions(+) diff --git a/drivers/net/ethernet/mellanox/mlx5/core/en/tc/act/ct.c b/drivers/net/ethernet/mellanox/mlx5/core/en/tc/act/ct.c index feeb41693c17..b6cabe829f19 100644 --- a/drivers/net/ethernet/mellanox/mlx5/core/en/tc/act/ct.c +++ b/drivers/net/ethernet/mellanox/mlx5/core/en/tc/act/ct.c @@ -5,6 +5,16 @@ #include "en/tc_priv.h" #include "en/tc_ct.h" +static bool +tc_act_can_offload_ct(struct mlx5e_tc_act_parse_state *parse_state, + const struct flow_action_entry *act, + int act_index, + struct mlx5_flow_attr *attr) +{ + return !((act->ct.action & TCA_CT_ACT_COMMIT) && + flow_action_is_last_entry(parse_state->flow_action, act)); +} + static int tc_act_parse_ct(struct mlx5e_tc_act_parse_state *parse_state, const struct flow_action_entry *act, @@ -56,6 +66,7 @@ tc_act_is_missable_ct(const struct flow_action_entry *act) } struct mlx5e_tc_act mlx5e_tc_act_ct = { + .can_offload = tc_act_can_offload_ct, .parse_action = tc_act_parse_ct, .post_parse = tc_act_post_parse_ct, .is_multi_table_act = tc_act_is_multi_table_act_ct,