From patchwork Thu Mar 20 10:54:40 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Pinkesh Vaghela X-Patchwork-Id: 14023700 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 5B13BC36008 for ; Thu, 20 Mar 2025 10:55:09 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To: Message-Id:Date:Subject:Cc:To:From:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=XKr6iiqsF/4njot5dK+jCyQWiwwO75H7G+RlT7EQxcc=; b=c359UkrbXxHden LhH2pygPCjmKDF1UPzSAS8w8SDCZyHrZUofZ/2mP+JKgPFVaGRF6iLX/mSPUd7OGWiIgt4MNS8BO4 GfrKDe4+r4DaDIP63Ef+cZqjirfEW25CdMeIVHWf+7WI7P1wHEQh3oT1J8q3tDp3d/DtXg77hnl/E 7rLTx7U267lt/SbCPZmckpkeN7pE4OAkeqhsx+zlYIDqYqcTm4siijIrQMm5x/SwdbaMYF9KpnV9I fqKB5MpSh4NKQrP9Rg95/CzzoFbWfIZ+7KG+QF0JJ3ny7NVz2Cml+PppTaLnq/y+btrRAZGsyOjJ5 jgSeWmWjeQj7jhK606qg==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.98 #2 (Red Hat Linux)) id 1tvDY8-0000000Brwi-1AuN; Thu, 20 Mar 2025 10:54:56 +0000 Received: from naesa03.arrow.com ([216.150.161.23]) by bombadil.infradead.org with esmtps (Exim 4.98 #2 (Red Hat Linux)) id 1tvDY5-0000000BrvA-43x6 for linux-riscv@lists.infradead.org; Thu, 20 Mar 2025 10:54:55 +0000 DKIM-Signature: v=1; a=rsa-sha256; c=simple/simple; d=einfochips.com; i=@einfochips.com; l=984; q=dns/txt; s=NAESA-Selector1; t=1742468094; x=1774004094; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=48tAi45I8uFpjXnUr6Whz6NO1YAMjCklEIDkcMApDYw=; b=b2u1QVxlnmcBIjDdVhR0eVPS1/dDN7P+pmMgWaIoaU1otyv9qjMbCrgL OQQHVe9DX3d+INpi2hVLOdvETiEgeYsc0yg404QNjpg6kMuwyGk5Xdal7 YCOSOX8RCBw0gYyC0S/mTQYyVjb4UsIEEVP+5mPG8RFzzzLn3/n4ZfqFO J+jcJlQM0p0wMSxhErnyjc92d5i3LX7JTqtt5mn8nucZK1DmzhBKAHFYC LEb5/FlEigZDdjzeBJrQYzLKd7OC4NGzUz3akiLrelu1FTCPGTfRV80Ia tBCfsp+RGbGfDtFNsFyYeGMO9kgKK64fl4jb+YL8WUoDUgMh49pvy3x6l g==; X-CSE-ConnectionGUID: LjMWKreeTb6AXkiy6xRnuw== X-CSE-MsgGUID: ooJxgaMMQeioREujX2HGqw== X-IronPort-AV: E=Sophos;i="6.14,261,1736838000"; d="scan'208";a="80317528" Received: from unknown (HELO eicahmirelay01.einfochips.com) ([10.100.49.50]) by naesa03out.arrow.com with ESMTP; 20 Mar 2025 04:54:52 -0600 Received: from AHMCPU1888.ap.corp.arrow.com ([172.25.5.100]) by eicahmirelay01.einfochips.com with Microsoft SMTPSVC(10.0.14393.4169); Thu, 20 Mar 2025 16:24:49 +0530 From: Pinkesh Vaghela To: Conor Dooley , Rob Herring , Krzysztof Kozlowski , Thomas Gleixner Cc: Paul Walmsley , Samuel Holland , Palmer Dabbelt , Albert Ou , Daniel Lezcano , Min Lin , Pinkesh Vaghela , Pritesh Patel , Yangyu Chen , Lad Prabhakar , Yu Chien Peter Lin , Charlie Jenkins , Kanak Shilledar , Darshan Prajapati , Neil Armstrong , Heiko Stuebner , Aradhya Bhatia , rafal@milecki.pl, Anup Patel , devicetree@vger.kernel.org, linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org Subject: [PATCH v2 01/10] dt-bindings: riscv: Add SiFive P550 CPU compatible Date: Thu, 20 Mar 2025 16:24:40 +0530 Message-Id: <20250320105449.2094192-2-pinkesh.vaghela@einfochips.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20250320105449.2094192-1-pinkesh.vaghela@einfochips.com> References: <20250320105449.2094192-1-pinkesh.vaghela@einfochips.com> MIME-Version: 1.0 X-OriginalArrivalTime: 20 Mar 2025 10:54:49.0757 (UTC) FILETIME=[8077E4D0:01DB9986] X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20250320_035454_068317_D390835C X-CRM114-Status: UNSURE ( 6.97 ) X-CRM114-Notice: Please train this message. X-BeenThere: linux-riscv@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-riscv" Errors-To: linux-riscv-bounces+linux-riscv=archiver.kernel.org@lists.infradead.org From: Darshan Prajapati Update Documentation for supporting SiFive P550 based CPU Signed-off-by: Darshan Prajapati Reviewed-by: Samuel Holland Signed-off-by: Pinkesh Vaghela Acked-by: Conor Dooley --- Documentation/devicetree/bindings/riscv/cpus.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/riscv/cpus.yaml b/Documentation/devicetree/bindings/riscv/cpus.yaml index 2c72f148a74b..3ee7468001f6 100644 --- a/Documentation/devicetree/bindings/riscv/cpus.yaml +++ b/Documentation/devicetree/bindings/riscv/cpus.yaml @@ -51,6 +51,7 @@ properties: - sifive,e5 - sifive,e7 - sifive,e71 + - sifive,p550 - sifive,rocket0 - sifive,s7 - sifive,u5 From patchwork Thu Mar 20 10:54:41 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Pinkesh Vaghela X-Patchwork-Id: 14023694 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 96F8BC36000 for ; Thu, 20 Mar 2025 10:55:04 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To: Message-Id:Date:Subject:Cc:To:From:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=RtbUAFvpFlcy7/xJnOAvNJIoQdWlFIpqtpQKAQKT5/4=; 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X-BeenThere: linux-riscv@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-riscv" Errors-To: linux-riscv-bounces+linux-riscv=archiver.kernel.org@lists.infradead.org Create a config option to build ESWIN SoC specific resources Signed-off-by: Pinkesh Vaghela Reviewed-by: Samuel Holland Acked-by: Conor Dooley --- arch/riscv/Kconfig.socs | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/arch/riscv/Kconfig.socs b/arch/riscv/Kconfig.socs index 1916cf7ba450..35594e365ca6 100644 --- a/arch/riscv/Kconfig.socs +++ b/arch/riscv/Kconfig.socs @@ -1,5 +1,11 @@ menu "SoC selection" +config ARCH_ESWIN + bool "ESWIN SoCs" + help + This enables support for ESWIN SoC platform hardware, + including the ESWIN EIC7700 SoC. + config ARCH_MICROCHIP_POLARFIRE def_bool ARCH_MICROCHIP From patchwork Thu Mar 20 10:54:42 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Pinkesh Vaghela X-Patchwork-Id: 14023695 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 74882C28B30 for ; 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d="scan'208";a="80317538" Received: from unknown (HELO eicahmirelay01.einfochips.com) ([10.100.49.50]) by naesa03out.arrow.com with ESMTP; 20 Mar 2025 04:54:54 -0600 Received: from AHMCPU1888.ap.corp.arrow.com ([172.25.5.100]) by eicahmirelay01.einfochips.com with Microsoft SMTPSVC(10.0.14393.4169); Thu, 20 Mar 2025 16:24:49 +0530 From: Pinkesh Vaghela To: Conor Dooley , Rob Herring , Krzysztof Kozlowski , Thomas Gleixner Cc: Paul Walmsley , Samuel Holland , Palmer Dabbelt , Albert Ou , Daniel Lezcano , Min Lin , Pinkesh Vaghela , Pritesh Patel , Yangyu Chen , Lad Prabhakar , Yu Chien Peter Lin , Charlie Jenkins , Kanak Shilledar , Darshan Prajapati , Neil Armstrong , Heiko Stuebner , Aradhya Bhatia , rafal@milecki.pl, Anup Patel , devicetree@vger.kernel.org, linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org Subject: [PATCH v2 03/10] dt-bindings: vendor-prefixes: add eswin Date: Thu, 20 Mar 2025 16:24:42 +0530 Message-Id: <20250320105449.2094192-4-pinkesh.vaghela@einfochips.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20250320105449.2094192-1-pinkesh.vaghela@einfochips.com> References: <20250320105449.2094192-1-pinkesh.vaghela@einfochips.com> MIME-Version: 1.0 X-OriginalArrivalTime: 20 Mar 2025 10:54:49.0819 (UTC) FILETIME=[80815AB0:01DB9986] X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20250320_035455_406225_08D6A145 X-CRM114-Status: UNSURE ( 7.53 ) X-CRM114-Notice: Please train this message. X-BeenThere: linux-riscv@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-riscv" Errors-To: linux-riscv-bounces+linux-riscv=archiver.kernel.org@lists.infradead.org From: Pritesh Patel Add new vendor string to dt bindings. This new vendor string is used by - ESWIN EIC770X SoC - HiFive Premier P550 board which uses EIC7700 SoC. Link: https://www.eswin.com/en/ Signed-off-by: Pritesh Patel Reviewed-by: Samuel Holland Signed-off-by: Pinkesh Vaghela Acked-by: Conor Dooley --- Documentation/devicetree/bindings/vendor-prefixes.yaml | 2 ++ 1 file changed, 2 insertions(+) diff --git a/Documentation/devicetree/bindings/vendor-prefixes.yaml b/Documentation/devicetree/bindings/vendor-prefixes.yaml index 5079ca6ce1d1..07ff140e67dc 100644 --- a/Documentation/devicetree/bindings/vendor-prefixes.yaml +++ b/Documentation/devicetree/bindings/vendor-prefixes.yaml @@ -490,6 +490,8 @@ patternProperties: description: Espressif Systems Co. Ltd. "^est,.*": description: ESTeem Wireless Modems + "^eswin,.*": + description: Beijing ESWIN Technology Group Co. Ltd. "^ettus,.*": description: NI Ettus Research "^eukrea,.*": From patchwork Thu Mar 20 10:54:43 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Pinkesh Vaghela X-Patchwork-Id: 14023696 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 58974C36002 for ; Thu, 20 Mar 2025 10:55:06 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To: Message-Id:Date:Subject:Cc:To:From:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; 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bh=eS3MaGonIoU9nAIFGQh9EPnwWnxVAYDNEq2SAR0mRpQ=; b=MEQLRdxa+7l6uLHbzorpU9NOeCPeJ4W6NUartNrC6F34CJK5FhG8JvlU e8ihSQlS7g2202aaFLlRj1nmk6G5wu7o+myboZViUcJZlGlkMFMD6UQTW 7HQqGSrU5+HNTas9ktjSekH7vlyLtDP8PZhDkgo0vXF1Uma5t5W4ss9B/ kjgsjODdQym4tc1OtmHZ93MUemuXEhZ5epFfkPGrukF53S8HDLv9hrTHV 4rqKzffGi4egCO9ez5e1rHAzlDmYZjvISMI4QH6+APTvfX7uooga/cw/Y 6RcwK1ml1TU2Gj8Ce2akLACwj3FFJFOHolZScbk2A/GGZ1t6U/mM9pKJ/ Q==; X-CSE-ConnectionGUID: TXbtMtAZQ/Oo06xXHZP0jQ== X-CSE-MsgGUID: hLc8YZSxTG+EJLYX6BLXKA== X-IronPort-AV: E=Sophos;i="6.14,261,1736838000"; d="scan'208";a="80317543" Received: from unknown (HELO eicahmirelay01.einfochips.com) ([10.100.49.50]) by naesa03out.arrow.com with ESMTP; 20 Mar 2025 04:54:55 -0600 Received: from AHMCPU1888.ap.corp.arrow.com ([172.25.5.100]) by eicahmirelay01.einfochips.com with Microsoft SMTPSVC(10.0.14393.4169); Thu, 20 Mar 2025 16:24:49 +0530 From: Pinkesh Vaghela To: Conor Dooley , Rob Herring , Krzysztof Kozlowski , Thomas Gleixner Cc: Paul Walmsley , Samuel Holland , Palmer Dabbelt , Albert Ou , Daniel Lezcano , Min Lin , Pinkesh Vaghela , Pritesh Patel , Yangyu Chen , Lad Prabhakar , Yu Chien Peter Lin , Charlie Jenkins , Kanak Shilledar , Darshan Prajapati , Neil Armstrong , Heiko Stuebner , Aradhya Bhatia , rafal@milecki.pl, Anup Patel , devicetree@vger.kernel.org, linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org Subject: [PATCH v2 04/10] dt-bindings: riscv: Add SiFive HiFive Premier P550 board Date: Thu, 20 Mar 2025 16:24:43 +0530 Message-Id: <20250320105449.2094192-5-pinkesh.vaghela@einfochips.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20250320105449.2094192-1-pinkesh.vaghela@einfochips.com> References: <20250320105449.2094192-1-pinkesh.vaghela@einfochips.com> MIME-Version: 1.0 X-OriginalArrivalTime: 20 Mar 2025 10:54:49.0835 (UTC) FILETIME=[8083CBB0:01DB9986] X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20250320_035456_132945_52DF8771 X-CRM114-Status: GOOD ( 11.26 ) X-BeenThere: linux-riscv@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-riscv" Errors-To: linux-riscv-bounces+linux-riscv=archiver.kernel.org@lists.infradead.org From: Pritesh Patel Add DT binding documentation for the ESWIN EIC7700 SoC and HiFive Premier P550 Board Signed-off-by: Pritesh Patel Reviewed-by: Samuel Holland Signed-off-by: Pinkesh Vaghela Reviewed-by: Matthias Brugger Reviewed-by: Rob Herring (Arm) --- .../devicetree/bindings/riscv/eswin.yaml | 29 +++++++++++++++++++ MAINTAINERS | 7 +++++ 2 files changed, 36 insertions(+) create mode 100644 Documentation/devicetree/bindings/riscv/eswin.yaml diff --git a/Documentation/devicetree/bindings/riscv/eswin.yaml b/Documentation/devicetree/bindings/riscv/eswin.yaml new file mode 100644 index 000000000000..c603c45eef22 --- /dev/null +++ b/Documentation/devicetree/bindings/riscv/eswin.yaml @@ -0,0 +1,29 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/riscv/eswin.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: ESWIN SoC-based boards + +maintainers: + - Min Lin + - Pinkesh Vaghela + - Pritesh Patel + +description: + ESWIN SoC-based boards + +properties: + $nodename: + const: '/' + compatible: + oneOf: + - items: + - enum: + - sifive,hifive-premier-p550 + - const: eswin,eic7700 + +additionalProperties: true + +... diff --git a/MAINTAINERS b/MAINTAINERS index 25c86f47353d..fc3c9191b00f 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -8572,6 +8572,13 @@ L: linux-can@vger.kernel.org S: Maintained F: drivers/net/can/usb/esd_usb.c +ESWIN DEVICETREES +M: Min Lin +M: Pinkesh Vaghela +M: Pritesh Patel +S: Maintained +F: Documentation/devicetree/bindings/riscv/eswin.yaml + ET131X NETWORK DRIVER M: Mark Einon S: Odd Fixes From patchwork Thu Mar 20 10:54:44 2025 Content-Type: text/plain; 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bh=H3wnlGqXSSS/oiZRRPE2KJNofPHwThcoVMkEwdUNQ7I=; b=Q2uDmJz2pkVaWcMTjjiPi1FiFTzunse/QANRHrjOIIFXVMzyXbP1OgGs oFiukTWMDGSoiK9EXnerkkdwwXF4ylgC3F56d8Bc+4XFk1VaQNLPlNsea 0/ymjBwd/X0COfkOc4Gue3tDpDHKo15yfbmouqy2ZSFXaKl8oRxBpVVLw eroitUkOBfXJCZuhDf2fdw7Ql5tE4KTeyXDV0Yf30MUsRcWAVMcaf5D/2 x0kj7YsVJygA7pwFDFw+q3ia+pqvJuzq24NM56ZA0AHWdW+zKZDygLw7C 2iuruPwpQrTWiUhHHew5kxcx9uh7ExxUobwouoXpB9mKTp8tmu5e6ylwl A==; X-CSE-ConnectionGUID: JNpILgqOTVW0rkGPMHwoIg== X-CSE-MsgGUID: WihiOzVeR26qmgZs1p7IAw== X-IronPort-AV: E=Sophos;i="6.14,261,1736838000"; d="scan'208";a="80317548" Received: from unknown (HELO eicahmirelay01.einfochips.com) ([10.100.49.50]) by naesa03out.arrow.com with ESMTP; 20 Mar 2025 04:54:56 -0600 Received: from AHMCPU1888.ap.corp.arrow.com ([172.25.5.100]) by eicahmirelay01.einfochips.com with Microsoft SMTPSVC(10.0.14393.4169); Thu, 20 Mar 2025 16:24:49 +0530 From: Pinkesh Vaghela To: Conor Dooley , Rob Herring , Krzysztof Kozlowski , Thomas Gleixner Cc: Paul Walmsley , Samuel Holland , Palmer Dabbelt , Albert Ou , Daniel Lezcano , Min Lin , Pinkesh Vaghela , Pritesh Patel , Yangyu Chen , Lad Prabhakar , Yu Chien Peter Lin , Charlie Jenkins , Kanak Shilledar , Darshan Prajapati , Neil Armstrong , Heiko Stuebner , Aradhya Bhatia , rafal@milecki.pl, Anup Patel , devicetree@vger.kernel.org, linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org Subject: [PATCH v2 05/10] dt-bindings: cache: sifive,ccache0: Add ESWIN EIC7700 SoC compatibility Date: Thu, 20 Mar 2025 16:24:44 +0530 Message-Id: <20250320105449.2094192-6-pinkesh.vaghela@einfochips.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20250320105449.2094192-1-pinkesh.vaghela@einfochips.com> References: <20250320105449.2094192-1-pinkesh.vaghela@einfochips.com> MIME-Version: 1.0 X-OriginalArrivalTime: 20 Mar 2025 10:54:49.0944 (UTC) FILETIME=[80946D80:01DB9986] X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20250320_035457_567845_FC433BAD X-CRM114-Status: UNSURE ( 8.72 ) X-CRM114-Notice: Please train this message. X-BeenThere: linux-riscv@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-riscv" Errors-To: linux-riscv-bounces+linux-riscv=archiver.kernel.org@lists.infradead.org From: Pritesh Patel This cache controller is also used on the ESWIN EIC7700 SoC. However, it have 256KB private L2 Cache and shared L3 Cache of 4MB. So add dedicated compatible string for it. Signed-off-by: Pritesh Patel Reviewed-by: Samuel Holland Signed-off-by: Pinkesh Vaghela --- .../bindings/cache/sifive,ccache0.yaml | 44 +++++++++++++++++-- 1 file changed, 41 insertions(+), 3 deletions(-) diff --git a/Documentation/devicetree/bindings/cache/sifive,ccache0.yaml b/Documentation/devicetree/bindings/cache/sifive,ccache0.yaml index 7e8cebe21584..579bacb66f34 100644 --- a/Documentation/devicetree/bindings/cache/sifive,ccache0.yaml +++ b/Documentation/devicetree/bindings/cache/sifive,ccache0.yaml @@ -39,6 +39,7 @@ properties: - const: cache - items: - enum: + - eswin,eic7700-l3-cache - starfive,jh7100-ccache - starfive,jh7110-ccache - const: sifive,ccache0 @@ -55,10 +56,10 @@ properties: enum: [2, 3] cache-sets: - enum: [1024, 2048] + enum: [1024, 2048, 4096] cache-size: - const: 2097152 + enum: [2097152, 4194304] cache-unified: true @@ -89,6 +90,7 @@ allOf: compatible: contains: enum: + - eswin,eic7700-l3-cache - sifive,fu740-c000-ccache - starfive,jh7100-ccache - starfive,jh7110-ccache @@ -108,6 +110,22 @@ allOf: Must contain entries for DirError, DataError and DataFail signals. maxItems: 3 + - if: + properties: + compatible: + contains: + const: eswin,eic7700-l3-cache + + then: + properties: + cache-size: + const: 4194304 + + else: + properties: + cache-size: + const: 2097152 + - if: properties: compatible: @@ -122,11 +140,31 @@ allOf: cache-sets: const: 2048 - else: + - if: + properties: + compatible: + contains: + enum: + - microchip,mpfs-ccache + - sifive,fu540-c000-ccache + + then: properties: cache-sets: const: 1024 + - if: + properties: + compatible: + contains: + enum: + - eswin,eic7700-l3-cache + + then: + properties: + cache-sets: + const: 4096 + - if: properties: compatible: From patchwork Thu Mar 20 10:54:45 2025 Content-Type: text/plain; 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bh=3hrFC8akR20pQMYn01FDGTaAf1FudakKyQp4tQR7was=; b=jf1y+RuJXyu0wMHExul2CG1kGNxOYFBbHhag43mWr+qUb+zKBmuR3fwF AZSIO4iAT1ia7ooLPBOS+RzBddtkW+l4bt52yAb3Ctaymb6nAuHs1/1qE IK+xxel63M86HgFb19AuNx3/t+fUodDMVVClDjcewXs2a2/X0MNMYf+Et NcUts3zWWscsAlvWdhzvwpC5H6gR33d8GyiDEI8vKaXUnHlxn6fxKELWB QDOCoYycKWebeqMqt/5XYxG2iWQVj2w+9ZmFmjkkbokHJWcaN1miqnDks CxLg3+Wtu5Abf4qOX60uFoRfulVv9vN5egXzIcJUiIQO8viTwKdzkqBKa g==; X-CSE-ConnectionGUID: dAytgUP7QIOBurYnS2bGIg== X-CSE-MsgGUID: dRZAc7HFTRapXu84HJUhOQ== X-IronPort-AV: E=Sophos;i="6.14,261,1736838000"; d="scan'208";a="80317552" Received: from unknown (HELO eicahmirelay01.einfochips.com) ([10.100.49.50]) by naesa03out.arrow.com with ESMTP; 20 Mar 2025 04:54:58 -0600 Received: from AHMCPU1888.ap.corp.arrow.com ([172.25.5.100]) by eicahmirelay01.einfochips.com with Microsoft SMTPSVC(10.0.14393.4169); Thu, 20 Mar 2025 16:24:49 +0530 From: Pinkesh Vaghela To: Conor Dooley , Rob Herring , Krzysztof Kozlowski , Thomas Gleixner Cc: Paul Walmsley , Samuel Holland , Palmer Dabbelt , Albert Ou , Daniel Lezcano , Min Lin , Pinkesh Vaghela , Pritesh Patel , Yangyu Chen , Lad Prabhakar , Yu Chien Peter Lin , Charlie Jenkins , Kanak Shilledar , Darshan Prajapati , Neil Armstrong , Heiko Stuebner , Aradhya Bhatia , rafal@milecki.pl, Anup Patel , devicetree@vger.kernel.org, linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org Subject: [PATCH v2 06/10] cache: sifive_ccache: Add ESWIN EIC7700 support Date: Thu, 20 Mar 2025 16:24:45 +0530 Message-Id: <20250320105449.2094192-7-pinkesh.vaghela@einfochips.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20250320105449.2094192-1-pinkesh.vaghela@einfochips.com> References: <20250320105449.2094192-1-pinkesh.vaghela@einfochips.com> MIME-Version: 1.0 X-OriginalArrivalTime: 20 Mar 2025 10:54:49.0975 (UTC) FILETIME=[80992870:01DB9986] X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20250320_035458_530562_057503C8 X-CRM114-Status: UNSURE ( 9.57 ) X-CRM114-Notice: Please train this message. X-BeenThere: linux-riscv@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-riscv" Errors-To: linux-riscv-bounces+linux-riscv=archiver.kernel.org@lists.infradead.org This adds support for the ESWIN EIC7700 SoC which also features this SiFive composable cache controller. Signed-off-by: Pinkesh Vaghela Reviewed-by: Samuel Holland --- drivers/cache/sifive_ccache.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/drivers/cache/sifive_ccache.c b/drivers/cache/sifive_ccache.c index 6874b72ec59d..e1a283805ea7 100644 --- a/drivers/cache/sifive_ccache.c +++ b/drivers/cache/sifive_ccache.c @@ -118,6 +118,8 @@ static void ccache_config_read(void) } static const struct of_device_id sifive_ccache_ids[] = { + { .compatible = "eswin,eic7700-l3-cache", + .data = (void *)(QUIRK_NONSTANDARD_CACHE_OPS) }, { .compatible = "sifive,fu540-c000-ccache" }, { .compatible = "sifive,fu740-c000-ccache" }, { .compatible = "starfive,jh7100-ccache", From patchwork Thu Mar 20 10:54:46 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Pinkesh Vaghela X-Patchwork-Id: 14023698 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id D6800C36000 for ; Thu, 20 Mar 2025 10:55:07 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To: Message-Id:Date:Subject:Cc:To:From:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=IBJNAsWYcd+KeJbBwAjM6s+BTZAfMoIJO8wBycMqFmY=; b=ovrdLVPjw4BDOm MZWe+qcQviOvxg5ZYEoqd8yvuDmlTye5dCm2aP/gC9ALcD5S5QedF1j+1PCSvo4/FbLZFsgqcrmpN mRMy7Zwq3gVCFdoGkxn/a9UEGpd0d5BhAvJemlEAwDjD/IwBSFuyUM6ROQswtShAeytZPMbcjACLe L8dxnSHot+t1+nin63umRBn1iQSCBT5o1PFvasEGdCFdB571PNTHmVhKYOIiNz6yovB4B60khc0ra baXR7QIaEFlAlDenEA4RAxZFg2izKBB2UD5wYORLKbl7RJC9oPyGpTUoQsDr/M7LCoAqCGzw0XFo8 2VA73tySXNCmery40/PA==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.98 #2 (Red Hat Linux)) id 1tvDYF-0000000Bs3n-2eZo; Thu, 20 Mar 2025 10:55:03 +0000 Received: from naesa03.arrow.com ([216.150.161.23]) by bombadil.infradead.org with esmtps (Exim 4.98 #2 (Red Hat Linux)) id 1tvDYB-0000000BrxO-2c6f for linux-riscv@lists.infradead.org; Thu, 20 Mar 2025 10:55:01 +0000 DKIM-Signature: v=1; a=rsa-sha256; c=simple/simple; d=einfochips.com; i=@einfochips.com; l=1119; q=dns/txt; s=NAESA-Selector1; t=1742468100; x=1774004100; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=0ALTharMqIir38+9/Eaz/083RGv8Pd04I92YF3XKwHA=; b=eCIK0jhqHitbcDVvMvAzRq2eP7h8gvH6W4p2rSOqgAnn4I+nLm1YbhXc IebSlcN3Tp/EUaaUDzs9Sc+iJGzrPfk00Uk7fbdTR0hm0MIpS3kmohVCo 5x/Fl09lHUHByOu0dwypCuzksnG1bdlxQMBxWEwmFQ2/A3UPoc63hJGN9 zPVeaezwYuYzMYBFjZJ5z5/PZRE+RSUKpke6MNQfphlLkns6KYFv/9wUh ynru1oy5Wq4WTkcLTfkTOay4uhROyId4PvI/ThqhKrQf7pqsuSplAISC3 Q3v6yQ5ma4rXLLubr7/t1V4zQOg8yypnWwYmCu51TmILJmbHE1ie7y6eq g==; X-CSE-ConnectionGUID: 3esQwa8aTaefx7i5/w/UNQ== X-CSE-MsgGUID: tKjRUMaGSIWpi+a6WLTKFw== X-IronPort-AV: E=Sophos;i="6.14,261,1736838000"; d="scan'208";a="80317558" Received: from unknown (HELO eicahmirelay01.einfochips.com) ([10.100.49.50]) by naesa03out.arrow.com with ESMTP; 20 Mar 2025 04:54:59 -0600 Received: from AHMCPU1888.ap.corp.arrow.com ([172.25.5.100]) by eicahmirelay01.einfochips.com with Microsoft SMTPSVC(10.0.14393.4169); Thu, 20 Mar 2025 16:24:50 +0530 From: Pinkesh Vaghela To: Conor Dooley , Rob Herring , Krzysztof Kozlowski , Thomas Gleixner Cc: Paul Walmsley , Samuel Holland , Palmer Dabbelt , Albert Ou , Daniel Lezcano , Min Lin , Pinkesh Vaghela , Pritesh Patel , Yangyu Chen , Lad Prabhakar , Yu Chien Peter Lin , Charlie Jenkins , Kanak Shilledar , Darshan Prajapati , Neil Armstrong , Heiko Stuebner , Aradhya Bhatia , rafal@milecki.pl, Anup Patel , devicetree@vger.kernel.org, linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org Subject: [PATCH v2 07/10] dt-bindings: interrupt-controller: Add ESWIN EIC7700 PLIC Date: Thu, 20 Mar 2025 16:24:46 +0530 Message-Id: <20250320105449.2094192-8-pinkesh.vaghela@einfochips.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20250320105449.2094192-1-pinkesh.vaghela@einfochips.com> References: <20250320105449.2094192-1-pinkesh.vaghela@einfochips.com> MIME-Version: 1.0 X-OriginalArrivalTime: 20 Mar 2025 10:54:50.0007 (UTC) FILETIME=[809E0A70:01DB9986] X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20250320_035459_786331_21CB120F X-CRM114-Status: UNSURE ( 6.97 ) X-CRM114-Notice: Please train this message. X-BeenThere: linux-riscv@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-riscv" Errors-To: linux-riscv-bounces+linux-riscv=archiver.kernel.org@lists.infradead.org From: Darshan Prajapati Add compatible string for ESWIN EIC7700 PLIC. Signed-off-by: Darshan Prajapati Reviewed-by: Samuel Holland Signed-off-by: Pinkesh Vaghela Acked-by: Conor Dooley --- .../bindings/interrupt-controller/sifive,plic-1.0.0.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/interrupt-controller/sifive,plic-1.0.0.yaml b/Documentation/devicetree/bindings/interrupt-controller/sifive,plic-1.0.0.yaml index 3dfe425909d1..ea7093fde060 100644 --- a/Documentation/devicetree/bindings/interrupt-controller/sifive,plic-1.0.0.yaml +++ b/Documentation/devicetree/bindings/interrupt-controller/sifive,plic-1.0.0.yaml @@ -58,6 +58,7 @@ properties: - items: - enum: - canaan,k210-plic + - eswin,eic7700-plic - sifive,fu540-c000-plic - spacemit,k1-plic - starfive,jh7100-plic From patchwork Thu Mar 20 10:54:47 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Pinkesh Vaghela X-Patchwork-Id: 14023701 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id B168EC36009 for ; Thu, 20 Mar 2025 10:55:09 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To: Message-Id:Date:Subject:Cc:To:From:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=oHtQBKz6M/JIbgZQ8h5ny1h4iiyyW0ft11Y63eNEUeM=; b=EeBjOulNkj30ku 2td07GfmFtTELvK5WeavmPS7etUtygaV+LnGoQknGJjSxYVC0mzsnjSz4q3Fg4JfuvkhE0R2GFQe4 APbgTK/eplrp6quJgW6TNzp+j/GWEMPkQOxsohk3YTo+SGQBlrt8xVQbIjB6nWHK7NRZs2GagLnTb 1iUFQsOtGCDLTm8Kw5s7pZ3FrLHelhKbrsa3DuqIDlGoE6YsRwvx4PevTpZ2z+V55BpHQ3jPFRkKD zjhQ5ZuzCbivZkb/ys3HpSGTwQwqvOUkKdrDScU7fCl8R2ci4np8lR0OtifnlcF8MJUIILlbOvUjW 68PTp0FiJCQQhBcH0vlw==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.98 #2 (Red Hat Linux)) id 1tvDYH-0000000Bs51-1G2k; Thu, 20 Mar 2025 10:55:05 +0000 Received: from naesa03.arrow.com ([216.150.161.23]) by bombadil.infradead.org with esmtps (Exim 4.98 #2 (Red Hat Linux)) id 1tvDYC-0000000Brv6-3SpA for linux-riscv@lists.infradead.org; Thu, 20 Mar 2025 10:55:02 +0000 DKIM-Signature: v=1; a=rsa-sha256; c=simple/simple; d=einfochips.com; i=@einfochips.com; l=1142; q=dns/txt; s=NAESA-Selector1; t=1742468101; x=1774004101; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=/DfX64G/gD+2bC60ieqN4nFImELPORhEeqU2sLa5/xM=; b=JMb6s+/jM92iL5mi6blRk1za6rLWmH/TurToEy8wB8D4gwIeFdYZCQP8 +vz0J+u86o0pLe62XY9dwDwUY18PiV/btODJF0NR50OODzRoyfcI7HoCq bGPvgH41Xlr2ifM0KgsP4rresDagZ13lMi49CiEzeKFBC0xcg3mGmno1Q HRXAJSVCL5WXm1VTuTttMxkbc+SMHKBpOWlTp5B5D4Pv9wrrmwnKY7ouv QxAIKc33IaGLJk3oV/HhC8zL4bZpqIm/X1nWBqpdeV8c/09XBUYl4oMTe HVvxeMmYQcO3GHmWKf5btc+nzKzptFtlCMESZdXZY2CCdKCIhoaluXJ9p Q==; X-CSE-ConnectionGUID: H535aqlvTUWHVParSJ3T4g== X-CSE-MsgGUID: 8h5E3CcoQtmsv/32AVCEZw== X-IronPort-AV: E=Sophos;i="6.14,261,1736838000"; d="scan'208";a="80317563" Received: from unknown (HELO eicahmirelay01.einfochips.com) ([10.100.49.50]) by naesa03out.arrow.com with ESMTP; 20 Mar 2025 04:55:00 -0600 Received: from AHMCPU1888.ap.corp.arrow.com ([172.25.5.100]) by eicahmirelay01.einfochips.com with Microsoft SMTPSVC(10.0.14393.4169); Thu, 20 Mar 2025 16:24:50 +0530 From: Pinkesh Vaghela To: Conor Dooley , Rob Herring , Krzysztof Kozlowski , Thomas Gleixner Cc: Paul Walmsley , Samuel Holland , Palmer Dabbelt , Albert Ou , Daniel Lezcano , Min Lin , Pinkesh Vaghela , Pritesh Patel , Yangyu Chen , Lad Prabhakar , Yu Chien Peter Lin , Charlie Jenkins , Kanak Shilledar , Darshan Prajapati , Neil Armstrong , Heiko Stuebner , Aradhya Bhatia , rafal@milecki.pl, Anup Patel , devicetree@vger.kernel.org, linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org Subject: [PATCH v2 08/10] dt-bindings: timer: Add ESWIN EIC7700 CLINT Date: Thu, 20 Mar 2025 16:24:47 +0530 Message-Id: <20250320105449.2094192-9-pinkesh.vaghela@einfochips.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20250320105449.2094192-1-pinkesh.vaghela@einfochips.com> References: <20250320105449.2094192-1-pinkesh.vaghela@einfochips.com> MIME-Version: 1.0 X-OriginalArrivalTime: 20 Mar 2025 10:54:50.0022 (UTC) FILETIME=[80A05460:01DB9986] X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20250320_035501_000075_3650F0AB X-CRM114-Status: UNSURE ( 6.96 ) X-CRM114-Notice: Please train this message. X-BeenThere: linux-riscv@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-riscv" Errors-To: linux-riscv-bounces+linux-riscv=archiver.kernel.org@lists.infradead.org From: Darshan Prajapati Add compatible string for ESWIN EIC7700 CLINT. Signed-off-by: Darshan Prajapati Reviewed-by: Samuel Holland Signed-off-by: Pinkesh Vaghela Acked-by: Conor Dooley --- Documentation/devicetree/bindings/timer/sifive,clint.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/timer/sifive,clint.yaml b/Documentation/devicetree/bindings/timer/sifive,clint.yaml index 76d83aea4e2b..eb03a0602315 100644 --- a/Documentation/devicetree/bindings/timer/sifive,clint.yaml +++ b/Documentation/devicetree/bindings/timer/sifive,clint.yaml @@ -30,6 +30,7 @@ properties: - items: - enum: - canaan,k210-clint # Canaan Kendryte K210 + - eswin,eic7700-clint # ESWIN EIC7700 - sifive,fu540-c000-clint # SiFive FU540 - spacemit,k1-clint # SpacemiT K1 - starfive,jh7100-clint # StarFive JH7100 From patchwork Thu Mar 20 10:54:48 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Pinkesh Vaghela X-Patchwork-Id: 14023703 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 3736EC36000 for ; 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d="scan'208";a="80317569" Received: from unknown (HELO eicahmirelay01.einfochips.com) ([10.100.49.50]) by naesa03out.arrow.com with ESMTP; 20 Mar 2025 04:55:01 -0600 Received: from AHMCPU1888.ap.corp.arrow.com ([172.25.5.100]) by eicahmirelay01.einfochips.com with Microsoft SMTPSVC(10.0.14393.4169); Thu, 20 Mar 2025 16:24:50 +0530 From: Pinkesh Vaghela To: Conor Dooley , Rob Herring , Krzysztof Kozlowski , Thomas Gleixner Cc: Paul Walmsley , Samuel Holland , Palmer Dabbelt , Albert Ou , Daniel Lezcano , Min Lin , Pinkesh Vaghela , Pritesh Patel , Yangyu Chen , Lad Prabhakar , Yu Chien Peter Lin , Charlie Jenkins , Kanak Shilledar , Darshan Prajapati , Neil Armstrong , Heiko Stuebner , Aradhya Bhatia , rafal@milecki.pl, Anup Patel , devicetree@vger.kernel.org, linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org Subject: [PATCH v2 09/10] riscv: dts: add initial support for EIC7700 SoC Date: Thu, 20 Mar 2025 16:24:48 +0530 Message-Id: <20250320105449.2094192-10-pinkesh.vaghela@einfochips.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20250320105449.2094192-1-pinkesh.vaghela@einfochips.com> References: <20250320105449.2094192-1-pinkesh.vaghela@einfochips.com> MIME-Version: 1.0 X-OriginalArrivalTime: 20 Mar 2025 10:54:50.0119 (UTC) FILETIME=[80AF2170:01DB9986] X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20250320_035502_090850_CC01CB5E X-CRM114-Status: GOOD ( 13.56 ) X-BeenThere: linux-riscv@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-riscv" Errors-To: linux-riscv-bounces+linux-riscv=archiver.kernel.org@lists.infradead.org From: Min Lin Add initial support for EIC7700 SoC that uses a SiFive Quad-Core P550 CPU cluster. This file is expected to grow as more device drivers are added to the kernel. Signed-off-by: Min Lin Co-developed-by: Pritesh Patel Signed-off-by: Pritesh Patel Co-developed-by: Darshan Prajapati Signed-off-by: Darshan Prajapati Reviewed-by: Samuel Holland Tested-by: Samuel Holland Signed-off-by: Pinkesh Vaghela --- MAINTAINERS | 1 + arch/riscv/boot/dts/eswin/eic7700.dtsi | 344 +++++++++++++++++++++++++ 2 files changed, 345 insertions(+) create mode 100644 arch/riscv/boot/dts/eswin/eic7700.dtsi diff --git a/MAINTAINERS b/MAINTAINERS index fc3c9191b00f..2c29023c6725 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -8578,6 +8578,7 @@ M: Pinkesh Vaghela M: Pritesh Patel S: Maintained F: Documentation/devicetree/bindings/riscv/eswin.yaml +F: arch/riscv/boot/dts/eswin/ ET131X NETWORK DRIVER M: Mark Einon diff --git a/arch/riscv/boot/dts/eswin/eic7700.dtsi b/arch/riscv/boot/dts/eswin/eic7700.dtsi new file mode 100644 index 000000000000..9cef940f07e4 --- /dev/null +++ b/arch/riscv/boot/dts/eswin/eic7700.dtsi @@ -0,0 +1,344 @@ +// SPDX-License-Identifier: (GPL-2.0 OR MIT) +/* + * Copyright (c) 2024 Beijing ESWIN Computing Technology Co., Ltd. + */ + +/dts-v1/; + +/ { + #address-cells = <2>; + #size-cells = <2>; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + timebase-frequency = <1000000>; + + cpu0: cpu@0 { + compatible = "sifive,p550", "riscv"; + device_type = "cpu"; + d-cache-block-size = <64>; + d-cache-sets = <128>; + d-cache-size = <32768>; + d-tlb-sets = <1>; + d-tlb-size = <32>; + i-cache-block-size = <64>; + i-cache-sets = <128>; + i-cache-size = <32768>; + i-tlb-sets = <1>; + i-tlb-size = <32>; + mmu-type = "riscv,sv48"; + next-level-cache = <&l2_cache_0>; + reg = <0x0>; + riscv,isa-base = "rv64i"; + riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "h", "sscofpmf", + "zba", "zbb", "zicsr", "zifencei"; + tlb-split; + + cpu0_intc: interrupt-controller { + compatible = "riscv,cpu-intc"; + #interrupt-cells = <1>; + interrupt-controller; + }; + }; + + cpu1: cpu@1 { + compatible = "sifive,p550", "riscv"; + d-cache-block-size = <64>; + d-cache-sets = <128>; + d-cache-size = <32768>; + d-tlb-sets = <1>; + d-tlb-size = <32>; + device_type = "cpu"; + i-cache-block-size = <64>; + i-cache-sets = <128>; + i-cache-size = <32768>; + i-tlb-sets = <1>; + i-tlb-size = <32>; + mmu-type = "riscv,sv48"; + next-level-cache = <&l2_cache_1>; + reg = <0x1>; + riscv,isa-base = "rv64i"; + riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "h", "sscofpmf", + "zba", "zbb", "zicsr", "zifencei"; + tlb-split; + + cpu1_intc: interrupt-controller { + compatible = "riscv,cpu-intc"; + #interrupt-cells = <1>; + interrupt-controller; + }; + }; + + cpu2: cpu@2 { + compatible = "sifive,p550", "riscv"; + d-cache-block-size = <64>; + d-cache-sets = <128>; + d-cache-size = <32768>; + d-tlb-sets = <1>; + d-tlb-size = <32>; + device_type = "cpu"; + i-cache-block-size = <64>; + i-cache-sets = <128>; + i-cache-size = <32768>; + i-tlb-sets = <1>; + i-tlb-size = <32>; + mmu-type = "riscv,sv48"; + next-level-cache = <&l2_cache_2>; + reg = <0x2>; + riscv,isa-base = "rv64i"; + riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "h", "sscofpmf", + "zba", "zbb", "zicsr", "zifencei"; + tlb-split; + + cpu2_intc: interrupt-controller { + compatible = "riscv,cpu-intc"; + #interrupt-cells = <1>; + interrupt-controller; + }; + }; + + cpu3: cpu@3 { + compatible = "sifive,p550", "riscv"; + d-cache-block-size = <64>; + d-cache-sets = <128>; + d-cache-size = <32768>; + d-tlb-sets = <1>; + d-tlb-size = <32>; + device_type = "cpu"; + i-cache-block-size = <64>; + i-cache-sets = <128>; + i-cache-size = <32768>; + i-tlb-sets = <1>; + i-tlb-size = <32>; + mmu-type = "riscv,sv48"; + next-level-cache = <&l2_cache_3>; + reg = <0x3>; + riscv,isa-base = "rv64i"; + riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "h", "sscofpmf", + "zba", "zbb", "zicsr", "zifencei"; + tlb-split; + + cpu3_intc: interrupt-controller { + compatible = "riscv,cpu-intc"; + #interrupt-cells = <1>; + interrupt-controller; + }; + }; + + l2_cache_0: l2-cache0 { + compatible = "cache"; + cache-block-size = <64>; + cache-level = <2>; + cache-sets = <512>; + cache-size = <262144>; + cache-unified; + next-level-cache = <&ccache>; + }; + + l2_cache_1: l2-cache1 { + compatible = "cache"; + cache-block-size = <64>; + cache-level = <2>; + cache-sets = <512>; + cache-size = <262144>; + cache-unified; + next-level-cache = <&ccache>; + }; + + l2_cache_2: l2-cache2 { + compatible = "cache"; + cache-block-size = <64>; + cache-level = <2>; + cache-sets = <512>; + cache-size = <262144>; + cache-unified; + next-level-cache = <&ccache>; + }; + + l2_cache_3: l2-cache3 { + compatible = "cache"; + cache-block-size = <64>; + cache-level = <2>; + cache-sets = <512>; + cache-size = <262144>; + cache-unified; + next-level-cache = <&ccache>; + }; + }; + + pmu { + compatible = "riscv,pmu"; + riscv,event-to-mhpmcounters = + <0x00001 0x00001 0x00000001>, + <0x00002 0x00002 0x00000004>, + <0x00004 0x00006 0x00000078>, + <0x10009 0x10009 0x00000078>, + <0x10019 0x10019 0x00000078>, + <0x10021 0x10021 0x00000078>; + riscv,event-to-mhpmevent = + <0x00004 0x00000000 0x00000202>, + <0x00005 0x00000000 0x00004000>, + <0x00006 0x00000000 0x00002001>, + <0x10009 0x00000000 0x00000102>, + <0x10019 0x00000000 0x00001002>, + <0x10021 0x00000000 0x00000802>; + riscv,raw-event-to-mhpmcounters = + <0x00000000 0x00000000 0xffffffff 0xfc0000ff 0x00000078>, + <0x00000000 0x00000001 0xffffffff 0xfffe07ff 0x00000078>, + <0x00000000 0x00000002 0xffffffff 0xfffe00ff 0x00000078>, + <0x00000000 0x00000003 0xfffffffc 0x000000ff 0x00000078>, + <0x00000000 0x00000004 0xffffffc0 0x000000ff 0x00000078>, + <0x00000000 0x00000005 0xffffffff 0xfffffdff 0x00000078>, + <0x00000000 0x00000006 0xfffffe00 0x110204ff 0x00000078>, + <0x00000000 0x00000007 0xffffffff 0xf00000ff 0x00000078>, + <0x00000000 0x00000008 0xfffffe04 0x000000ff 0x00000078>, + <0x00000000 0x00000009 0xffffffff 0xffffc0ff 0x00000078>, + <0x00000000 0x0000000a 0xffffffff 0xf00000ff 0x00000078>, + <0x00000000 0x0000000b 0xffffffff 0xfffffcff 0x00000078>, + <0x00000000 0x0000000c 0xfffffff0 0x000000ff 0x00000078>, + <0x00000000 0x0000000d 0xffffffff 0x800000ff 0x00000078>, + <0x00000000 0x0000000e 0xffffffff 0xf80000ff 0x00000078>, + <0x00000000 0x0000000f 0xfffffffc 0x000000ff 0x00000078>; + }; + + soc { + compatible = "simple-bus"; + ranges; + interrupt-parent = <&plic>; + #address-cells = <2>; + #size-cells = <2>; + + clint: timer@2000000 { + compatible = "eswin,eic7700-clint", "sifive,clint0"; + reg = <0x0 0x02000000 0x0 0x10000>; + interrupts-extended = + <&cpu0_intc 3>, <&cpu0_intc 7>, + <&cpu1_intc 3>, <&cpu1_intc 7>, + <&cpu2_intc 3>, <&cpu2_intc 7>, + <&cpu3_intc 3>, <&cpu3_intc 7>; + }; + + ccache: cache-controller@2010000 { + compatible = "eswin,eic7700-l3-cache", "sifive,ccache0", "cache"; + reg = <0x0 0x2010000 0x0 0x4000>; + interrupts = <1>, <3>, <4>, <2>; + cache-block-size = <64>; + cache-level = <3>; + cache-sets = <4096>; + cache-size = <4194304>; + cache-unified; + }; + + plic: interrupt-controller@c000000 { + compatible = "eswin,eic7700-plic", "sifive,plic-1.0.0"; + reg = <0x0 0xc000000 0x0 0x4000000>; + interrupt-controller; + interrupts-extended = + <&cpu0_intc 11>, <&cpu0_intc 9>, + <&cpu1_intc 11>, <&cpu1_intc 9>, + <&cpu2_intc 11>, <&cpu2_intc 9>, + <&cpu3_intc 11>, <&cpu3_intc 9>; + riscv,ndev = <520>; + #address-cells = <0>; + #interrupt-cells = <1>; + }; + + uart0: serial@50900000 { + compatible = "snps,dw-apb-uart"; + reg = <0x0 0x50900000 0x0 0x10000>; + interrupts = <100>; + clock-frequency = <200000000>; + reg-io-width = <4>; + reg-shift = <2>; + status = "disabled"; + }; + + uart1: serial@50910000 { + compatible = "snps,dw-apb-uart"; + reg = <0x0 0x50910000 0x0 0x10000>; + interrupts = <101>; + clock-frequency = <200000000>; + reg-io-width = <4>; + reg-shift = <2>; + status = "disabled"; + }; + + uart2: serial@50920000 { + compatible = "snps,dw-apb-uart"; + reg = <0x0 0x50920000 0x0 0x10000>; + interrupts = <102>; + clock-frequency = <200000000>; + reg-io-width = <4>; + reg-shift = <2>; + status = "disabled"; + }; + + uart3: serial@50930000 { + compatible = "snps,dw-apb-uart"; + reg = <0x0 0x50930000 0x0 0x10000>; + interrupts = <103>; + clock-frequency = <200000000>; + reg-io-width = <4>; + reg-shift = <2>; + status = "disabled"; + }; + + uart4: serial@50940000 { + compatible = "snps,dw-apb-uart"; + reg = <0x0 0x50940000 0x0 0x10000>; + interrupts = <104>; + clock-frequency = <200000000>; + reg-io-width = <4>; + reg-shift = <2>; + status = "disabled"; + }; + + gpio@51600000 { + compatible = "snps,dw-apb-gpio"; + reg = <0x0 0x51600000 0x0 0x80>; + #address-cells = <1>; + #size-cells = <0>; + + porta: gpio-port@0 { + compatible = "snps,dw-apb-gpio-port"; + reg = <0>; + interrupt-controller; + #interrupt-cells = <2>; + interrupts = + <303>, <304>, <305>, <306>, <307>, <308>, <309>, + <310>, <311>, <312>, <313>, <314>, <315>, <316>, + <317>, <318>, <319>, <320>, <321>, <322>, <323>, + <324>, <325>, <326>, <327>, <328>, <329>, <330>, + <331>, <332>, <333>, <334>; + gpio-controller; + ngpios = <32>; + #gpio-cells = <2>; + }; + + portb: gpio-port@1 { + compatible = "snps,dw-apb-gpio-port"; + reg = <1>; + gpio-controller; + ngpios = <32>; + #gpio-cells = <2>; + }; + + portc: gpio-port@2 { + compatible = "snps,dw-apb-gpio-port"; + reg = <2>; + gpio-controller; + ngpios = <32>; + #gpio-cells = <2>; + }; + + portd: gpio-port@3 { + compatible = "snps,dw-apb-gpio-port"; + reg = <3>; + gpio-controller; + ngpios = <16>; + #gpio-cells = <2>; + }; + }; + }; +}; From patchwork Thu Mar 20 10:54:49 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Pinkesh Vaghela X-Patchwork-Id: 14023702 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 46FAFC36002 for ; Thu, 20 Mar 2025 10:55:12 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To: Message-Id:Date:Subject:Cc:To:From:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; 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bh=5heB6PuMYbbcCT5z+UhKDkhRC7FHz+vObUOuQmwwSh4=; b=Na7bmkCHu4lCNvdMbXdPmCOGj1VJ/VRBRiZ1rgT6Lny3Y/+5SEplNDnT gE26zVHGh4cP4WqdotVlSfz2C9Z1AQpXsG7pQ+UD3+fMx5K+aLh9B5nI9 XiPmnDnqN5rchn3IRpPo3fGirwliIJs5J0JCPDsEWC4gImGhSxUPxDYXG Prub4t9RcGBxKK3VUlGSWAEeSa+fke+4GqFajEYl8fJZHqpatqaM4Cx9j c6iZ79VKrxt0oux/RQwfHFXhW1RVCvSkXKm6CgNBBhc48sT75e6WIS1/A +VnlRZrkR1bhnTITb51uhhBGYM4+oSqqa/gR+ZcYmXdNct1mU/2VuxT5i Q==; X-CSE-ConnectionGUID: c00AVAyyRf+inAtPhDc0oQ== X-CSE-MsgGUID: 3KmseeC1QHeIPGaMUt46Ig== X-IronPort-AV: E=Sophos;i="6.14,261,1736838000"; d="scan'208";a="80317575" Received: from unknown (HELO eicahmirelay01.einfochips.com) ([10.100.49.50]) by naesa03out.arrow.com with ESMTP; 20 Mar 2025 04:55:02 -0600 Received: from AHMCPU1888.ap.corp.arrow.com ([172.25.5.100]) by eicahmirelay01.einfochips.com with Microsoft SMTPSVC(10.0.14393.4169); Thu, 20 Mar 2025 16:24:50 +0530 From: Pinkesh Vaghela To: Conor Dooley , Rob Herring , Krzysztof Kozlowski , Thomas Gleixner Cc: Paul Walmsley , Samuel Holland , Palmer Dabbelt , Albert Ou , Daniel Lezcano , Min Lin , Pinkesh Vaghela , Pritesh Patel , Yangyu Chen , Lad Prabhakar , Yu Chien Peter Lin , Charlie Jenkins , Kanak Shilledar , Darshan Prajapati , Neil Armstrong , Heiko Stuebner , Aradhya Bhatia , rafal@milecki.pl, Anup Patel , devicetree@vger.kernel.org, linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org Subject: [PATCH v2 10/10] riscv: dts: eswin: add HiFive Premier P550 board device tree Date: Thu, 20 Mar 2025 16:24:49 +0530 Message-Id: <20250320105449.2094192-11-pinkesh.vaghela@einfochips.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20250320105449.2094192-1-pinkesh.vaghela@einfochips.com> References: <20250320105449.2094192-1-pinkesh.vaghela@einfochips.com> MIME-Version: 1.0 X-OriginalArrivalTime: 20 Mar 2025 10:54:50.0214 (UTC) FILETIME=[80BDA060:01DB9986] X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20250320_035503_362258_1403C1D0 X-CRM114-Status: GOOD ( 12.36 ) X-BeenThere: linux-riscv@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-riscv" Errors-To: linux-riscv-bounces+linux-riscv=archiver.kernel.org@lists.infradead.org From: Min Lin Add initial board data for HiFive Premier P550 Development board Currently the data populated in this DT file describes the board DRAM configuration, UART and GPIO. Signed-off-by: Min Lin Co-developed-by: Pinkesh Vaghela Signed-off-by: Pinkesh Vaghela Reviewed-by: Samuel Holland Tested-by: Samuel Holland --- arch/riscv/boot/dts/Makefile | 1 + arch/riscv/boot/dts/eswin/Makefile | 2 ++ .../dts/eswin/eic7700-hifive-premier-p550.dts | 29 +++++++++++++++++++ 3 files changed, 32 insertions(+) create mode 100644 arch/riscv/boot/dts/eswin/Makefile create mode 100644 arch/riscv/boot/dts/eswin/eic7700-hifive-premier-p550.dts diff --git a/arch/riscv/boot/dts/Makefile b/arch/riscv/boot/dts/Makefile index bff887d38abe..286a9939a8cb 100644 --- a/arch/riscv/boot/dts/Makefile +++ b/arch/riscv/boot/dts/Makefile @@ -1,6 +1,7 @@ # SPDX-License-Identifier: GPL-2.0 subdir-y += allwinner subdir-y += canaan +subdir-y += eswin subdir-y += microchip subdir-y += renesas subdir-y += sifive diff --git a/arch/riscv/boot/dts/eswin/Makefile b/arch/riscv/boot/dts/eswin/Makefile new file mode 100644 index 000000000000..224101ae471e --- /dev/null +++ b/arch/riscv/boot/dts/eswin/Makefile @@ -0,0 +1,2 @@ +# SPDX-License-Identifier: GPL-2.0 +dtb-$(CONFIG_ARCH_ESWIN) += eic7700-hifive-premier-p550.dtb diff --git a/arch/riscv/boot/dts/eswin/eic7700-hifive-premier-p550.dts b/arch/riscv/boot/dts/eswin/eic7700-hifive-premier-p550.dts new file mode 100644 index 000000000000..131ed1fc6b2e --- /dev/null +++ b/arch/riscv/boot/dts/eswin/eic7700-hifive-premier-p550.dts @@ -0,0 +1,29 @@ +// SPDX-License-Identifier: (GPL-2.0 OR MIT) +/* + * Copyright (c) 2024, Beijing ESWIN Computing Technology Co., Ltd. + */ + +/dts-v1/; + +#include "eic7700.dtsi" + +/ { + compatible = "sifive,hifive-premier-p550", "eswin,eic7700"; + model = "SiFive HiFive Premier P550"; + + aliases { + serial0 = &uart0; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; +}; + +&uart0 { + status = "okay"; +}; + +&uart2 { + status = "okay"; +};