From patchwork Thu Mar 20 16:41:16 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Biju Das X-Patchwork-Id: 14024170 X-Patchwork-Delegate: geert@linux-m68k.org Received: from relmlie5.idc.renesas.com (relmlor1.renesas.com [210.160.252.171]) by smtp.subspace.kernel.org (Postfix) with ESMTP id BA19D221F33; Thu, 20 Mar 2025 16:41:31 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=210.160.252.171 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1742488894; cv=none; b=F3WCOTgDFVRs68eyjyg7sbkkPCRQIE2EgHqW63VgcDOervXc9HVoBxrwvM6xL4CWt2xm8f1kozHsubhkvgcMlvNZflF/wrjHoRgarJIQSHKu3Uluu2Gxol4fgpTqYDghhWfHfKLEIhtvB+t+HpANAvmGqYG87fNeQnx85MuJS4I= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1742488894; c=relaxed/simple; bh=kztYI4lTgmXoH9G3B0QADdnl61quhlzjNkyX0oAig/0=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=ha3TuEiNTovwtbeFEG8TP0JVJeoDcGtaT+TgaBwHPEqqviO2MckR9L/p7ZwxNdSbNf/SDAcxaMJN2rGrIAuNG/TCIEUjVxmKEEOWj5YzL9X6CCSiQY+prQk7RY5VY+/VHjqY+M90R45ok9ie76sHs37ihelawy5GWMUi2vTJQIs= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=bp.renesas.com; spf=pass smtp.mailfrom=bp.renesas.com; arc=none smtp.client-ip=210.160.252.171 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=bp.renesas.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=bp.renesas.com X-CSE-ConnectionGUID: QCjPX9rRQ3+jHt7lvhQrkQ== X-CSE-MsgGUID: bGEcIBFQR9OlNdt6zeGkjw== Received: from unknown (HELO relmlir5.idc.renesas.com) ([10.200.68.151]) by relmlie5.idc.renesas.com with ESMTP; 21 Mar 2025 01:41:30 +0900 Received: from localhost.localdomain (unknown [10.226.93.24]) by relmlir5.idc.renesas.com (Postfix) with ESMTP id 90E24400721F; Fri, 21 Mar 2025 01:41:27 +0900 (JST) From: Biju Das To: Geert Uytterhoeven , Magnus Damm , Rob Herring , Krzysztof Kozlowski , Conor Dooley Cc: Biju Das , linux-renesas-soc@vger.kernel.org, devicetree@vger.kernel.org, Prabhakar Mahadev Lad , Biju Das Subject: [PATCH v2 1/3] arm64: dts: renesas: r9a09g047: Add CANFD node Date: Thu, 20 Mar 2025 16:41:16 +0000 Message-ID: <20250320164121.193857-2-biju.das.jz@bp.renesas.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250320164121.193857-1-biju.das.jz@bp.renesas.com> References: <20250320164121.193857-1-biju.das.jz@bp.renesas.com> Precedence: bulk X-Mailing-List: linux-renesas-soc@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Add CANFD node to RZ/G3E ("R9A09G047") SoC DTSI. Signed-off-by: Biju Das --- v1->v2: * Replaced integer with hexadecimal for module clock and reset numbers. --- arch/arm64/boot/dts/renesas/r9a09g047.dtsi | 60 ++++++++++++++++++++++ 1 file changed, 60 insertions(+) diff --git a/arch/arm64/boot/dts/renesas/r9a09g047.dtsi b/arch/arm64/boot/dts/renesas/r9a09g047.dtsi index 4bc0b77f721a..b8a78adcdba2 100644 --- a/arch/arm64/boot/dts/renesas/r9a09g047.dtsi +++ b/arch/arm64/boot/dts/renesas/r9a09g047.dtsi @@ -272,6 +272,66 @@ scif0: serial@11c01400 { status = "disabled"; }; + canfd: can@12440000 { + compatible = "renesas,r9a09g047-canfd"; + reg = <0 0x12440000 0 0x40000>; + interrupts = , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + ; + interrupt-names = "g_err", "g_recc", + "ch0_err", "ch0_rec", "ch0_trx", + "ch1_err", "ch1_rec", "ch1_trx", + "ch2_err", "ch2_rec", "ch2_trx", + "ch3_err", "ch3_rec", "ch3_trx", + "ch4_err", "ch4_rec", "ch4_trx", + "ch5_err", "ch5_rec", "ch5_trx"; + clocks = <&cpg CPG_MOD 0x9c>, <&cpg CPG_MOD 0x9d>, + <&cpg CPG_MOD 0x9e>; + clock-names = "fck", "ram_clk", "can_clk"; + assigned-clocks = <&cpg CPG_MOD 0x9e>; + assigned-clock-rates = <80000000>; + resets = <&cpg 0xa1>, <&cpg 0xa2>; + reset-names = "rstp_n", "rstc_n"; + power-domains = <&cpg>; + status = "disabled"; + + channel0 { + status = "disabled"; + }; + channel1 { + status = "disabled"; + }; + channel2 { + status = "disabled"; + }; + channel3 { + status = "disabled"; + }; + channel4 { + status = "disabled"; + }; + channel5 { + status = "disabled"; + }; + }; + wdt1: watchdog@14400000 { compatible = "renesas,r9a09g047-wdt", "renesas,r9a09g057-wdt"; reg = <0 0x14400000 0 0x400>; From patchwork Thu Mar 20 16:41:17 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Biju Das X-Patchwork-Id: 14024171 X-Patchwork-Delegate: geert@linux-m68k.org Received: from relmlie5.idc.renesas.com (relmlor1.renesas.com [210.160.252.171]) by smtp.subspace.kernel.org (Postfix) with ESMTP id 733F42222B6; Thu, 20 Mar 2025 16:41:34 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=210.160.252.171 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1742488896; cv=none; b=gqWyamflr9IID03tvvQtlYshRZ0xqrSRryqPecw7ywbP8U1Dm7pnBECVonwrhYnbeGu+Akme3GLQxLrEtVtc6jiVGbMb4mQrc4W+FdIq/3p/ikrUb+NHDU3WC7GQdDVmazZWHdEOk6i7rUJn4GpVZcBexGNZlYYh+6YuNroevRQ= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1742488896; c=relaxed/simple; bh=CKyUVq5PWzBL3D3yLl9aE8loKt4vD6wzpn3KOHgi2IM=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=MsOyOxaYdkn8cdcgjXQlM16KixIAgmabte28cveGjBuV3ajnSQVTKN3EnaIDtwXAAB7VOihJKanZPGsliAQfi/YnNKDlRZ5kcvhrJM2ypsjsRmpU7YxvO0rlapXbabAT8nNfrgBRjzbJwjyvrteDChv6vIhv6IdO1nHEDjGck1w= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=bp.renesas.com; spf=pass smtp.mailfrom=bp.renesas.com; arc=none smtp.client-ip=210.160.252.171 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=bp.renesas.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=bp.renesas.com X-CSE-ConnectionGUID: ZoQ9MbluS0qwRHl45FzUaA== X-CSE-MsgGUID: gc+TnhLNSZOf8wKY9T0beg== Received: from unknown (HELO relmlir5.idc.renesas.com) ([10.200.68.151]) by relmlie5.idc.renesas.com with ESMTP; 21 Mar 2025 01:41:34 +0900 Received: from localhost.localdomain (unknown [10.226.93.24]) by relmlir5.idc.renesas.com (Postfix) with ESMTP id 4C0A4400721F; Fri, 21 Mar 2025 01:41:31 +0900 (JST) From: Biju Das To: Geert Uytterhoeven , Magnus Damm , Rob Herring , Krzysztof Kozlowski , Conor Dooley Cc: Biju Das , linux-renesas-soc@vger.kernel.org, devicetree@vger.kernel.org, Prabhakar Mahadev Lad , Biju Das Subject: [PATCH v2 2/3] arm64: dts: renesas: r9a09g047e57-smarc: Enable CANFD Date: Thu, 20 Mar 2025 16:41:17 +0000 Message-ID: <20250320164121.193857-3-biju.das.jz@bp.renesas.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250320164121.193857-1-biju.das.jz@bp.renesas.com> References: <20250320164121.193857-1-biju.das.jz@bp.renesas.com> Precedence: bulk X-Mailing-List: linux-renesas-soc@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Enable CANFD on the RZ/G3E SMARC EVK platform. Signed-off-by: Biju Das --- v1->v2: * Split the patch into two. * Enabling CANFD done in this patch and CAN Transceiver on next patch. * Defined the macros SW_LCD_EN and SW_PDM_EN which routes signals to CAN0 and CAN1 based on SYS.5 and BOOT.6 switches. --- .../boot/dts/renesas/r9a09g047e57-smarc.dts | 31 +++++++++++++++++++ .../boot/dts/renesas/renesas-smarc2.dtsi | 4 +++ .../boot/dts/renesas/rzg3e-smarc-som.dtsi | 14 +++++++-- 3 files changed, 46 insertions(+), 3 deletions(-) diff --git a/arch/arm64/boot/dts/renesas/r9a09g047e57-smarc.dts b/arch/arm64/boot/dts/renesas/r9a09g047e57-smarc.dts index 5d7983812c70..7e1daaabce8a 100644 --- a/arch/arm64/boot/dts/renesas/r9a09g047e57-smarc.dts +++ b/arch/arm64/boot/dts/renesas/r9a09g047e57-smarc.dts @@ -8,6 +8,8 @@ /dts-v1/; /* Switch selection settings */ +#define SW_LCD_EN 0 +#define SW_PDM_EN 0 #define SW_SD0_DEV_SEL 0 #define SW_SDIO_M2E 0 @@ -33,7 +35,36 @@ vqmmc_sd1_pvdd: regulator-vqmmc-sd1-pvdd { }; }; +&canfd { + pinctrl-0 = <&canfd_pins>; + pinctrl-names = "default"; + +#if (!SW_PDM_EN) + channel1 { + status = "okay"; + }; +#endif + +#if (!SW_LCD_EN) + channel4 { + status = "okay"; + }; +#endif +}; + &pinctrl { + canfd_pins: canfd { + can1_pins: can1 { + pinmux = , /* RX */ + ; /* TX */ + }; + + can4_pins: can4 { + pinmux = , /* RX */ + ; /* TX */ + }; + }; + scif_pins: scif { pins = "SCIF_TXD", "SCIF_RXD"; renesas,output-impedance = <1>; diff --git a/arch/arm64/boot/dts/renesas/renesas-smarc2.dtsi b/arch/arm64/boot/dts/renesas/renesas-smarc2.dtsi index fd82df8adc1e..1d3a844174b3 100644 --- a/arch/arm64/boot/dts/renesas/renesas-smarc2.dtsi +++ b/arch/arm64/boot/dts/renesas/renesas-smarc2.dtsi @@ -29,6 +29,10 @@ aliases { }; }; +&canfd { + status = "okay"; +}; + &scif0 { status = "okay"; }; diff --git a/arch/arm64/boot/dts/renesas/rzg3e-smarc-som.dtsi b/arch/arm64/boot/dts/renesas/rzg3e-smarc-som.dtsi index 72b42a81bcf3..f63f988f786a 100644 --- a/arch/arm64/boot/dts/renesas/rzg3e-smarc-som.dtsi +++ b/arch/arm64/boot/dts/renesas/rzg3e-smarc-som.dtsi @@ -6,12 +6,20 @@ */ /* - * Please set the switch position SYS.1 on the SoM and the corresponding macro - * SW_SD0_DEV_SEL on the board DTS: + * Please set the below switch position on the SoM and the corresponding macro + * on the board DTS: * - * SW_SD0_DEV_SEL: + * Switch position SYS.1, Macro SW_SD0_DEV_SEL: * 0 - SD0 is connected to eMMC (default) * 1 - SD0 is connected to uSD0 card + * + * Switch position SYS.5, Macro SW_LCD_EN: + * 0 - Select Misc. Signals routing + * 1 - Select LCD + * + * Switch position BOOT.6, Macro SW_PDM_EN: + * 0 - Select CAN routing + * 1 - Select PDM */ / { From patchwork Thu Mar 20 16:41:18 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Biju Das X-Patchwork-Id: 14024172 X-Patchwork-Delegate: geert@linux-m68k.org Received: from relmlie5.idc.renesas.com (relmlor1.renesas.com [210.160.252.171]) by smtp.subspace.kernel.org (Postfix) with ESMTP id DB87721C9F2; Thu, 20 Mar 2025 16:41:38 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=210.160.252.171 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1742488900; cv=none; b=TBrUGYdhSm+oNIyIWc2upm0qcn7J6QSP6vHbzZQL1RjgmcmXN5VHB6jw1F6BZL8s8ksvYBTjjZagNYPQpDiIXYCt3PwHtoMYBe3TdaSa1lRbqX4SIeNjUI/ekno3iCI7eIChAQs013Q/wBMrTcSe3tgMD688iFHEyqbNeByyY4U= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1742488900; c=relaxed/simple; bh=xi1iKXhZWCLdT2pVoZvOrzPhwd9Oc06didJRRgDtptg=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=DIC3LogLYCLiYiNNXWlf469FE9jDG4S2M/y7ZQh1h2xqHWzCLVtfL+VXP6RDuFB47q0YNRs2HctWFKaEHLWK4B83FZM3byVCIv9eSeLeN+XyepnMk+zN8kUYnbyhw50BY4SM07q2pjrHFR8UnC3G9QJ0WNswKv4gAoTnNTseSTU= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=bp.renesas.com; spf=pass smtp.mailfrom=bp.renesas.com; arc=none smtp.client-ip=210.160.252.171 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=bp.renesas.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=bp.renesas.com X-CSE-ConnectionGUID: secjPJA4R36WIFw8ZfzM7w== X-CSE-MsgGUID: lKwdLtCBTgC2oxvCOjms6w== Received: from unknown (HELO relmlir5.idc.renesas.com) ([10.200.68.151]) by relmlie5.idc.renesas.com with ESMTP; 21 Mar 2025 01:41:37 +0900 Received: from localhost.localdomain (unknown [10.226.93.24]) by relmlir5.idc.renesas.com (Postfix) with ESMTP id B3E1C400721F; Fri, 21 Mar 2025 01:41:34 +0900 (JST) From: Biju Das To: Geert Uytterhoeven , Magnus Damm , Rob Herring , Krzysztof Kozlowski , Conor Dooley Cc: Biju Das , linux-renesas-soc@vger.kernel.org, devicetree@vger.kernel.org, Prabhakar Mahadev Lad , Biju Das Subject: [PATCH v2 3/3] arm64: dts: renesas: r9a09g047e57-smarc: Enable CAN Transceiver Date: Thu, 20 Mar 2025 16:41:18 +0000 Message-ID: <20250320164121.193857-4-biju.das.jz@bp.renesas.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250320164121.193857-1-biju.das.jz@bp.renesas.com> References: <20250320164121.193857-1-biju.das.jz@bp.renesas.com> Precedence: bulk X-Mailing-List: linux-renesas-soc@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Enable TCAN1046V-Q1 CAN Transceiver populated on RZ/G3E SMARC EVK by modelling it as two instances of tcan1042. Signed-off-by: Biju Das --- v1->v2: * Replaced GPIO hog with CAN Transceiver. --- .../boot/dts/renesas/r9a09g047e57-smarc.dts | 22 ++++++++++++++++ .../boot/dts/renesas/renesas-smarc2.dtsi | 25 +++++++++++++++++++ 2 files changed, 47 insertions(+) diff --git a/arch/arm64/boot/dts/renesas/r9a09g047e57-smarc.dts b/arch/arm64/boot/dts/renesas/r9a09g047e57-smarc.dts index 7e1daaabce8a..1f5e61a73c35 100644 --- a/arch/arm64/boot/dts/renesas/r9a09g047e57-smarc.dts +++ b/arch/arm64/boot/dts/renesas/r9a09g047e57-smarc.dts @@ -8,6 +8,8 @@ /dts-v1/; /* Switch selection settings */ +#define SW_GPIO8_CAN0_STB 0 +#define SW_GPIO9_CAN1_STB 0 #define SW_LCD_EN 0 #define SW_PDM_EN 0 #define SW_SD0_DEV_SEL 0 @@ -42,16 +44,36 @@ &canfd { #if (!SW_PDM_EN) channel1 { status = "okay"; +#if (!SW_LCD_EN) && (SW_GPIO9_CAN1_STB) + phys = <&can_transceiver1>; +#endif }; #endif #if (!SW_LCD_EN) channel4 { status = "okay"; +#if (SW_GPIO8_CAN0_STB) + phys = <&can_transceiver0>; +#endif }; #endif }; +#if (!SW_LCD_EN) && (SW_GPIO8_CAN0_STB) +&can_transceiver0 { + standby-gpios = <&pinctrl RZG3E_GPIO(5, 4) GPIO_ACTIVE_HIGH>; + status = "okay"; +}; +#endif + +#if (!SW_LCD_EN) && (SW_GPIO9_CAN1_STB) +&can_transceiver1 { + standby-gpios = <&pinctrl RZG3E_GPIO(5, 5) GPIO_ACTIVE_HIGH>; + status = "okay"; +}; +#endif + &pinctrl { canfd_pins: canfd { can1_pins: can1 { diff --git a/arch/arm64/boot/dts/renesas/renesas-smarc2.dtsi b/arch/arm64/boot/dts/renesas/renesas-smarc2.dtsi index 1d3a844174b3..afdc1940e24a 100644 --- a/arch/arm64/boot/dts/renesas/renesas-smarc2.dtsi +++ b/arch/arm64/boot/dts/renesas/renesas-smarc2.dtsi @@ -12,6 +12,17 @@ * SW_SDIO_M2E: * 0 - SMARC SDIO signal is connected to uSD1 * 1 - SMARC SDIO signal is connected to M.2 Key E connector + * + * Please set the switch position SW_GPIO_CAN_PMOD on the carrier board and the + * corresponding macro SW_GPIO8_CAN0_STB/SW_GPIO8_CAN0_STB on the board DTS: + * + * SW_GPIO8_CAN0_STB: + * 0 - Connect to GPIO8 PMOD (default) + * 1 - Connect to CAN0 transceiver STB pin + * + * SW_GPIO9_CAN1_STB: + * 0 - Connect to GPIO9 PMOD (default) + * 1 - Connect to CAN1 transceiver STB pin */ / { @@ -27,6 +38,20 @@ aliases { serial3 = &scif0; mmc1 = &sdhi1; }; + + can_transceiver0: can-phy0 { + compatible = "ti,tcan1042"; + #phy-cells = <0>; + max-bitrate = <8000000>; + status = "disabled"; + }; + + can_transceiver1: can-phy1 { + compatible = "ti,tcan1042"; + #phy-cells = <0>; + max-bitrate = <8000000>; + status = "disabled"; + }; }; &canfd {