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([188.163.112.51]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-ac3ef869f19sm122300866b.33.2025.03.21.02.56.15 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 21 Mar 2025 02:56:16 -0700 (PDT) From: Svyatoslav Ryhel To: Thierry Reding , Jonathan Hunter , Peter De Schrijver , Prashant Gaikwad , Michael Turquette , Stephen Boyd , "Rafael J. Wysocki" , Viresh Kumar , Philipp Zabel , Svyatoslav Ryhel Cc: linux-tegra@vger.kernel.org, linux-kernel@vger.kernel.org, linux-clk@vger.kernel.org, linux-pm@vger.kernel.org Subject: [PATCH v1 1/3] drivers: cpufreq: add Tegra 4 support Date: Fri, 21 Mar 2025 11:55:54 +0200 Message-ID: <20250321095556.91425-2-clamor95@gmail.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250321095556.91425-1-clamor95@gmail.com> References: <20250321095556.91425-1-clamor95@gmail.com> Precedence: bulk X-Mailing-List: linux-pm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Tegra 4 is fully compatible with existing Tegra K1 cpufreq driver. Signed-off-by: Svyatoslav Ryhel --- drivers/cpufreq/cpufreq-dt-platdev.c | 1 + drivers/cpufreq/tegra124-cpufreq.c | 5 +++-- 2 files changed, 4 insertions(+), 2 deletions(-) diff --git a/drivers/cpufreq/cpufreq-dt-platdev.c b/drivers/cpufreq/cpufreq-dt-platdev.c index 18942bfe9c95..7d15a1224d37 100644 --- a/drivers/cpufreq/cpufreq-dt-platdev.c +++ b/drivers/cpufreq/cpufreq-dt-platdev.c @@ -140,6 +140,7 @@ static const struct of_device_id blocklist[] __initconst = { { .compatible = "nvidia,tegra20", }, { .compatible = "nvidia,tegra30", }, + { .compatible = "nvidia,tegra114", }, { .compatible = "nvidia,tegra124", }, { .compatible = "nvidia,tegra210", }, { .compatible = "nvidia,tegra234", }, diff --git a/drivers/cpufreq/tegra124-cpufreq.c b/drivers/cpufreq/tegra124-cpufreq.c index 514146d98bca..6ff2ccc08e5e 100644 --- a/drivers/cpufreq/tegra124-cpufreq.c +++ b/drivers/cpufreq/tegra124-cpufreq.c @@ -189,8 +189,9 @@ static int __init tegra_cpufreq_init(void) int ret; struct platform_device *pdev; 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([188.163.112.51]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-ac3ef869f19sm122300866b.33.2025.03.21.02.56.17 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 21 Mar 2025 02:56:18 -0700 (PDT) From: Svyatoslav Ryhel To: Thierry Reding , Jonathan Hunter , Peter De Schrijver , Prashant Gaikwad , Michael Turquette , Stephen Boyd , "Rafael J. Wysocki" , Viresh Kumar , Philipp Zabel , Svyatoslav Ryhel Cc: linux-tegra@vger.kernel.org, linux-kernel@vger.kernel.org, linux-clk@vger.kernel.org, linux-pm@vger.kernel.org Subject: [PATCH v1 2/3] drivers: clk: tegra: add DFLL support for Tegra 4 Date: Fri, 21 Mar 2025 11:55:55 +0200 Message-ID: <20250321095556.91425-3-clamor95@gmail.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250321095556.91425-1-clamor95@gmail.com> References: <20250321095556.91425-1-clamor95@gmail.com> Precedence: bulk X-Mailing-List: linux-pm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Extend the Tegra124 driver to include DFLL configuration settings required for Tegra114 compatibility. Signed-off-by: Svyatoslav Ryhel --- drivers/clk/tegra/Kconfig | 2 +- drivers/clk/tegra/clk-tegra114.c | 30 +++++- drivers/clk/tegra/clk-tegra124-dfll-fcpu.c | 104 +++++++++++++++++++++ drivers/clk/tegra/clk.h | 2 - include/dt-bindings/reset/tegra114-car.h | 13 +++ 5 files changed, 144 insertions(+), 7 deletions(-) create mode 100644 include/dt-bindings/reset/tegra114-car.h diff --git a/drivers/clk/tegra/Kconfig b/drivers/clk/tegra/Kconfig index 90df619dc087..62147a069606 100644 --- a/drivers/clk/tegra/Kconfig +++ b/drivers/clk/tegra/Kconfig @@ -4,7 +4,7 @@ config CLK_TEGRA_BPMP depends on TEGRA_BPMP config TEGRA_CLK_DFLL - depends on ARCH_TEGRA_124_SOC || ARCH_TEGRA_210_SOC + depends on ARCH_TEGRA_114_SOC || ARCH_TEGRA_124_SOC || ARCH_TEGRA_210_SOC select PM_OPP def_bool y diff --git a/drivers/clk/tegra/clk-tegra114.c b/drivers/clk/tegra/clk-tegra114.c index b19dd4e6e17c..9b6794b951a2 100644 --- a/drivers/clk/tegra/clk-tegra114.c +++ b/drivers/clk/tegra/clk-tegra114.c @@ -11,6 +11,7 @@ #include #include #include +#include #include "clk.h" #include "clk-id.h" @@ -1260,7 +1261,7 @@ EXPORT_SYMBOL(tegra114_clock_tune_cpu_trimmers_init); * * Assert the reset line of the DFLL's DVCO. No return value. */ -void tegra114_clock_assert_dfll_dvco_reset(void) +static void tegra114_clock_assert_dfll_dvco_reset(void) { u32 v; @@ -1269,7 +1270,6 @@ void tegra114_clock_assert_dfll_dvco_reset(void) writel_relaxed(v, clk_base + RST_DFLL_DVCO); tegra114_car_barrier(); } -EXPORT_SYMBOL(tegra114_clock_assert_dfll_dvco_reset); /** * tegra114_clock_deassert_dfll_dvco_reset - deassert the DFLL's DVCO reset @@ -1277,7 +1277,7 @@ EXPORT_SYMBOL(tegra114_clock_assert_dfll_dvco_reset); * Deassert the reset line of the DFLL's DVCO, allowing the DVCO to * operate. No return value. */ -void tegra114_clock_deassert_dfll_dvco_reset(void) +static void tegra114_clock_deassert_dfll_dvco_reset(void) { u32 v; @@ -1286,7 +1286,26 @@ void tegra114_clock_deassert_dfll_dvco_reset(void) writel_relaxed(v, clk_base + RST_DFLL_DVCO); tegra114_car_barrier(); } -EXPORT_SYMBOL(tegra114_clock_deassert_dfll_dvco_reset); + +static int tegra114_reset_assert(unsigned long id) +{ + if (id == TEGRA114_RST_DFLL_DVCO) + tegra114_clock_assert_dfll_dvco_reset(); + else + return -EINVAL; + + return 0; +} + +static int tegra114_reset_deassert(unsigned long id) +{ + if (id == TEGRA114_RST_DFLL_DVCO) + tegra114_clock_deassert_dfll_dvco_reset(); + else + return -EINVAL; + + return 0; +} #ifdef CONFIG_TEGRA124_CLK_EMC static struct clk *tegra114_clk_src_onecell_get(struct of_phandle_args *clkspec, @@ -1357,6 +1376,9 @@ static void __init tegra114_clock_init(struct device_node *np) tegra_super_clk_gen4_init(clk_base, pmc_base, tegra114_clks, &pll_x_params); + tegra_init_special_resets(1, tegra114_reset_assert, + tegra114_reset_deassert); + #ifdef CONFIG_TEGRA124_CLK_EMC tegra_add_of_provider(np, tegra114_clk_src_onecell_get); clks[TEGRA114_CLK_EMC] = tegra124_clk_register_emc(clk_base, np, diff --git a/drivers/clk/tegra/clk-tegra124-dfll-fcpu.c b/drivers/clk/tegra/clk-tegra124-dfll-fcpu.c index 0251618b82c8..7a43380ce519 100644 --- a/drivers/clk/tegra/clk-tegra124-dfll-fcpu.c +++ b/drivers/clk/tegra/clk-tegra124-dfll-fcpu.c @@ -28,6 +28,99 @@ struct dfll_fcpu_data { unsigned int cpu_cvb_tables_size; }; +/* Maximum CPU frequency, indexed by CPU speedo id */ +static const unsigned long tegra114_cpu_max_freq_table[] = { + [0] = 2040000000UL, + [1] = 1810500000UL, + [2] = 1912500000UL, + [3] = 1810500000UL, +}; + +#define T114_CPU_CVB_TABLE \ + .min_millivolts = 1000, \ + .max_millivolts = 1320, \ + .speedo_scale = 100, \ + .voltage_scale = 1000, \ + .entries = { \ + { 306000000UL, { 2190643, -141851, 3576 } }, \ + { 408000000UL, { 2250968, -144331, 3576 } }, \ + { 510000000UL, { 2313333, -146811, 3576 } }, \ + { 612000000UL, { 2377738, -149291, 3576 } }, \ + { 714000000UL, { 2444183, -151771, 3576 } }, \ + { 816000000UL, { 2512669, -154251, 3576 } }, \ + { 918000000UL, { 2583194, -156731, 3576 } }, \ + { 1020000000UL, { 2655759, -159211, 3576 } }, \ + { 1122000000UL, { 2730365, -161691, 3576 } }, \ + { 1224000000UL, { 2807010, -164171, 3576 } }, \ + { 1326000000UL, { 2885696, -166651, 3576 } }, \ + { 1428000000UL, { 2966422, -169131, 3576 } }, \ + { 1530000000UL, { 3049183, -171601, 3576 } }, \ + { 1606500000UL, { 3112179, -173451, 3576 } }, \ + { 1708500000UL, { 3198504, -175931, 3576 } }, \ + { 1810500000UL, { 3304747, -179126, 3576 } }, \ + { 1912500000UL, { 3395401, -181606, 3576 } }, \ + { 0UL, { 0, 0, 0 } }, \ + }, \ + .cpu_dfll_data = { \ + .tune0_low = 0x00b0039d, \ + .tune0_high = 0x00b0009d, \ + .tune1 = 0x0000001f, \ + .tune_high_min_millivolts = 1050, \ + } + +static const struct cvb_table tegra114_cpu_cvb_tables[] = { + { + .speedo_id = 0, + .process_id = -1, + .min_millivolts = 1000, + .max_millivolts = 1250, + .speedo_scale = 100, + .voltage_scale = 100, + .entries = { + { 306000000UL, { 107330, -1569, 0 } }, + { 408000000UL, { 111250, -1666, 0 } }, + { 510000000UL, { 110000, -1460, 0 } }, + { 612000000UL, { 117290, -1745, 0 } }, + { 714000000UL, { 122700, -1910, 0 } }, + { 816000000UL, { 125620, -1945, 0 } }, + { 918000000UL, { 130560, -2076, 0 } }, + { 1020000000UL, { 137280, -2303, 0 } }, + { 1122000000UL, { 146440, -2660, 0 } }, + { 1224000000UL, { 152190, -2825, 0 } }, + { 1326000000UL, { 157520, -2953, 0 } }, + { 1428000000UL, { 166100, -3261, 0 } }, + { 1530000000UL, { 176410, -3647, 0 } }, + { 1632000000UL, { 189620, -4186, 0 } }, + { 1734000000UL, { 203190, -4725, 0 } }, + { 1836000000UL, { 222670, -5573, 0 } }, + { 1938000000UL, { 256210, -7165, 0 } }, + { 2040000000UL, { 250050, -6544, 0 } }, + { 0UL, { 0, 0, 0 } }, + }, + .cpu_dfll_data = { + .tune0_low = 0x00b0019d, + .tune0_high = 0x00b0019d, + .tune1 = 0x0000001f, + .tune_high_min_millivolts = 1000, + } + }, + { + .speedo_id = 1, + .process_id = -1, + T114_CPU_CVB_TABLE + }, + { + .speedo_id = 2, + .process_id = -1, + T114_CPU_CVB_TABLE + }, + { + .speedo_id = 3, + .process_id = -1, + T114_CPU_CVB_TABLE + }, +}; + /* Maximum CPU frequency, indexed by CPU speedo id */ static const unsigned long tegra124_cpu_max_freq_table[] = { [0] = 2014500000UL, @@ -494,6 +587,13 @@ static struct cvb_table tegra210_cpu_cvb_tables[] = { }, }; +static const struct dfll_fcpu_data tegra114_dfll_fcpu_data = { + .cpu_max_freq_table = tegra114_cpu_max_freq_table, + .cpu_max_freq_table_size = ARRAY_SIZE(tegra114_cpu_max_freq_table), + .cpu_cvb_tables = tegra114_cpu_cvb_tables, + .cpu_cvb_tables_size = ARRAY_SIZE(tegra114_cpu_cvb_tables) +}; + static const struct dfll_fcpu_data tegra124_dfll_fcpu_data = { .cpu_max_freq_table = tegra124_cpu_max_freq_table, .cpu_max_freq_table_size = ARRAY_SIZE(tegra124_cpu_max_freq_table), @@ -509,6 +609,10 @@ static const struct dfll_fcpu_data tegra210_dfll_fcpu_data = { }; static const struct of_device_id tegra124_dfll_fcpu_of_match[] = { + { + .compatible = "nvidia,tegra114-dfll", + .data = &tegra114_dfll_fcpu_data, + }, { .compatible = "nvidia,tegra124-dfll", .data = &tegra124_dfll_fcpu_data, diff --git a/drivers/clk/tegra/clk.h b/drivers/clk/tegra/clk.h index 5d80d8b79b8e..58e860b18e5e 100644 --- a/drivers/clk/tegra/clk.h +++ b/drivers/clk/tegra/clk.h @@ -898,8 +898,6 @@ static inline bool tegra124_clk_emc_driver_available(struct clk_hw *emc_hw) void tegra114_clock_tune_cpu_trimmers_high(void); void tegra114_clock_tune_cpu_trimmers_low(void); void tegra114_clock_tune_cpu_trimmers_init(void); -void tegra114_clock_assert_dfll_dvco_reset(void); -void tegra114_clock_deassert_dfll_dvco_reset(void); typedef void (*tegra_clk_apply_init_table_func)(void); extern tegra_clk_apply_init_table_func tegra_clk_apply_init_table; diff --git a/include/dt-bindings/reset/tegra114-car.h b/include/dt-bindings/reset/tegra114-car.h new file mode 100644 index 000000000000..d7908d810ddf --- /dev/null +++ b/include/dt-bindings/reset/tegra114-car.h @@ -0,0 +1,13 @@ +/* SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause */ +/* + * This header provides Tegra114-specific constants for binding + * nvidia,tegra114-car. + */ + +#ifndef _DT_BINDINGS_RESET_TEGRA114_CAR_H +#define _DT_BINDINGS_RESET_TEGRA114_CAR_H + +#define TEGRA114_RESET(x) (5 * 32 + (x)) +#define TEGRA114_RST_DFLL_DVCO TEGRA114_RESET(0) + +#endif /* _DT_BINDINGS_RESET_TEGRA114_CAR_H */ From patchwork Fri Mar 21 09:55:56 2025 Content-Type: text/plain; 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([188.163.112.51]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-ac3ef869f19sm122300866b.33.2025.03.21.02.56.18 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 21 Mar 2025 02:56:19 -0700 (PDT) From: Svyatoslav Ryhel To: Thierry Reding , Jonathan Hunter , Peter De Schrijver , Prashant Gaikwad , Michael Turquette , Stephen Boyd , "Rafael J. Wysocki" , Viresh Kumar , Philipp Zabel , Svyatoslav Ryhel Cc: linux-tegra@vger.kernel.org, linux-kernel@vger.kernel.org, linux-clk@vger.kernel.org, linux-pm@vger.kernel.org Subject: [PATCH v1 3/3] ARM: tegra: Add DFLL clock support on Tegra 4 Date: Fri, 21 Mar 2025 11:55:56 +0200 Message-ID: <20250321095556.91425-4-clamor95@gmail.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250321095556.91425-1-clamor95@gmail.com> References: <20250321095556.91425-1-clamor95@gmail.com> Precedence: bulk X-Mailing-List: linux-pm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Add DFLL clock node to common Tegra114 device tree along with clocks property to cpu node. Signed-off-by: Svyatoslav Ryhel --- arch/arm/boot/dts/nvidia/tegra114.dtsi | 34 ++++++++++++++++++++++++++ 1 file changed, 34 insertions(+) diff --git a/arch/arm/boot/dts/nvidia/tegra114.dtsi b/arch/arm/boot/dts/nvidia/tegra114.dtsi index 341ec0962460..25d063a47ca5 100644 --- a/arch/arm/boot/dts/nvidia/tegra114.dtsi +++ b/arch/arm/boot/dts/nvidia/tegra114.dtsi @@ -4,6 +4,7 @@ #include #include #include +#include #include #include "tegra114-peripherals-opp.dtsi" @@ -710,6 +711,30 @@ mipi: mipi@700e3000 { #nvidia,mipi-calibrate-cells = <1>; }; + dfll: clock@70110000 { + compatible = "nvidia,tegra114-dfll"; + reg = <0x70110000 0x100>, /* DFLL control */ + <0x70110000 0x100>, /* I2C output control */ + <0x70110100 0x100>, /* Integrated I2C controller */ + <0x70110200 0x100>; /* Look-up table RAM */ + interrupts = ; + clocks = <&tegra_car TEGRA114_CLK_DFLL_SOC>, + <&tegra_car TEGRA114_CLK_DFLL_REF>, + <&tegra_car TEGRA114_CLK_I2C5>; + clock-names = "soc", "ref", "i2c"; + resets = <&tegra_car TEGRA114_RST_DFLL_DVCO>; + reset-names = "dvco"; + #clock-cells = <0>; + clock-output-names = "dfllCPU_out"; + nvidia,sample-rate = <11500>; + nvidia,droop-ctrl = <0x00000f00>; + nvidia,force-mode = <1>; + nvidia,cf = <10>; + nvidia,ci = <0>; + nvidia,cg = <2>; + status = "disabled"; + }; + mmc@78000000 { compatible = "nvidia,tegra114-sdhci"; reg = <0x78000000 0x200>; @@ -841,6 +866,15 @@ cpu@0 { device_type = "cpu"; compatible = "arm,cortex-a15"; reg = <0>; + + clocks = <&tegra_car TEGRA114_CLK_CCLK_G>, + <&tegra_car TEGRA114_CLK_CCLK_LP>, + <&tegra_car TEGRA114_CLK_PLL_X>, + <&tegra_car TEGRA114_CLK_PLL_P>, + <&dfll>; + clock-names = "cpu_g", "cpu_lp", "pll_x", "pll_p", "dfll"; + /* FIXME: what's the actual transition time? */ + clock-latency = <300000>; }; cpu@1 {