From patchwork Fri Mar 21 13:46:26 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Caleb James DeLisle X-Patchwork-Id: 14025471 Received: from mail.cjdns.fr (mail.cjdns.fr [5.135.140.105]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 9CEAA14AD2D; Fri, 21 Mar 2025 13:53:01 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=5.135.140.105 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1742565183; cv=none; b=i/ry/q39cYOMNTHIGgJQyrESOJC47W/b/30iH8iDumm1lIIkoDxyfujFARqQjkf8bVqySI3tWmfpwI58wo2HvGvkg7gFeuoc4JvCI+9ihe2svSWhnHMguCOUnojVGn9e9uqDvJo6fH6TIzGOtymhsjTj0WKAqxTrPNT5om3yqfE= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1742565183; c=relaxed/simple; bh=4vXekzsWHmvR94GsE6lgMrIwMkPY5qevNSy1oBeUqIk=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=QeHvTum6NcBkBDfk8z/K+XZDD7K4qxa3Zqt2KYcjQNPNEDObiy2BB8EoZJIovUetvx2ZkwocdD9k0aUDBFCV2CZunu0Po7u/DGRFoDo++NZEXqJjcWRcy82TbLeJ0yr3timKqBF5sjgGKjWu0rFihcHWIo5DVfw5+kS8UIx2mmE= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=cjdns.fr; spf=none smtp.mailfrom=cjdns.fr; dkim=pass (2048-bit key) header.d=cjdns.fr header.i=@cjdns.fr header.b=deIesldz; arc=none smtp.client-ip=5.135.140.105 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=cjdns.fr Authentication-Results: smtp.subspace.kernel.org; spf=none smtp.mailfrom=cjdns.fr Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=cjdns.fr header.i=@cjdns.fr header.b="deIesldz" Received: from [127.0.0.1] (localhost [127.0.0.1]) by localhost (Mailerdaemon) with ESMTPSA id 88A2F2A3957; Fri, 21 Mar 2025 14:46:55 +0100 (CET) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=cjdns.fr; s=dkim; t=1742564816; h=from:subject:date:message-id:to:cc:mime-version: content-transfer-encoding:in-reply-to:references; bh=rItGop7/a5/qbko2Ss3dBjIuYcyFS3TGR+2NriB9xKs=; b=deIesldzqmdXxkc20gVll0bhzIfYrBsqfpy3avf93I0bjC0LI5n0Ppu7XBLXIEUEfw1lk7 SZc4Mkw3MxkGi1S/fajKOrw4rGsrsFxUo4tzhGG1bSuGA5abL2Ex+ewyTjhvfSRHhyc0y7 gxiiRR2ORjCBx96R1tsbU41qV/D/yJkRvvMwoJ7yNW3PL92/clbLfsty6kpM1NT7eAYFkN /ce7esEmnhCjq/fh+SB7zCh5dBqK85Y+HImRgUgseoUBD3nzNFU7tmJkBAUxnBlFLmb5Br tosrfnxQLBlsgYEFHDWZ4ptl8NxcAnJcVCzXflGVGiAUqpdOvJ2CSGDUhdHyDg== From: Caleb James DeLisle To: linux-mips@vger.kernel.org Cc: Thomas Gleixner , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Thomas Bogendoerfer , Daniel Lezcano , devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, benjamin.larsson@genexis.eu, Caleb James DeLisle Subject: [PATCH v1 1/8] dt-bindings: vendor-prefixes: Add EcoNet Date: Fri, 21 Mar 2025 13:46:26 +0000 Message-Id: <20250321134633.2155141-2-cjd@cjdns.fr> In-Reply-To: <20250321134633.2155141-1-cjd@cjdns.fr> References: <20250321134633.2155141-1-cjd@cjdns.fr> Precedence: bulk X-Mailing-List: linux-mips@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-Last-TLS-Session-Version: TLSv1.3 Add the "econet" vendor prefix for EcoNet devices, to be used in upcoming device tree bindings. Signed-off-by: Caleb James DeLisle --- Documentation/devicetree/bindings/vendor-prefixes.yaml | 2 ++ 1 file changed, 2 insertions(+) diff --git a/Documentation/devicetree/bindings/vendor-prefixes.yaml b/Documentation/devicetree/bindings/vendor-prefixes.yaml index 5079ca6ce1d1..4cd050e50743 100644 --- a/Documentation/devicetree/bindings/vendor-prefixes.yaml +++ b/Documentation/devicetree/bindings/vendor-prefixes.yaml @@ -416,6 +416,8 @@ patternProperties: description: dServe Technology B.V. "^dynaimage,.*": description: Dyna-Image + "^econet,.*": + description: EcoNet (HK) Limited "^ea,.*": description: Embedded Artists AB "^ebang,.*": From patchwork Fri Mar 21 13:46:27 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Caleb James DeLisle X-Patchwork-Id: 14025473 Received: from mail.cjdns.fr (mail.cjdns.fr [5.135.140.105]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 9CEF014F117; Fri, 21 Mar 2025 13:53:01 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=5.135.140.105 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1742565183; cv=none; b=QTbE2INfFBgPrtDNZ61og+ociMJYoSFAu18o5ZW6PfHuExnHyBFS9APh31Sl9AaGWAYSpKQuFrgvsHx4+e/3GcN1csgZUkFJxrNiDBWoddaxp8uWpc7ZUZ2mCxwigMwokjH5gRVyE4TZWG/KZCpqSvmxpBoMWO7Uc1nLNtcJNkI= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1742565183; c=relaxed/simple; bh=FrkGkbafNVVQ5VlfcNrmmi6yR64NW4tC8cjY+bGy+Jg=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=Xpal8sH202NEorcyRNM57XQcpqxOVpj+p+eezaz8s2BvUYxON3IS5g7H7BZPBUZpTk/tGbNmEyzjQY7BaUFc4D9OoNLMRXruskIHEFroZqdgRFVCnqcvs9XMvAsE6uOEPuahSbsp0wW4ifNCpSrcp/HPPCzQKwFN1qyWvbBAGGc= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=cjdns.fr; spf=none smtp.mailfrom=cjdns.fr; dkim=pass (2048-bit key) header.d=cjdns.fr header.i=@cjdns.fr header.b=gLIB9Txd; arc=none smtp.client-ip=5.135.140.105 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=cjdns.fr Authentication-Results: smtp.subspace.kernel.org; spf=none smtp.mailfrom=cjdns.fr Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=cjdns.fr header.i=@cjdns.fr header.b="gLIB9Txd" Received: from [127.0.0.1] (localhost [127.0.0.1]) by localhost (Mailerdaemon) with ESMTPSA id 2487D2A4019; Fri, 21 Mar 2025 14:46:57 +0100 (CET) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=cjdns.fr; s=dkim; t=1742564818; h=from:subject:date:message-id:to:cc:mime-version: content-transfer-encoding:in-reply-to:references; bh=EoOOrMmp/Q6BDztUeD0REz7b6REoGXkazpSywa1RF54=; b=gLIB9TxdZInwzdzhVWTMz97BwbeMud4u+ItDrNk2XOWU7hr4xxcfkXffx8Qx26VhS+CAo+ nz39TTVLg4UI92rTQ/+62IeUy9rI6noCwLrVc2Z2X4uVbM9vOiP4mDgmQUchdAA7ApZhm7 HLoaFEKzERv3Cd28Qstn/TjJVhCrjUVTp5DB7sLmCrbjPORVmW5Clx1MwogyxVhYdy8mqK e1wCj2r2YMq+IUrMGq0/g0tNl2N4WZn498HQAXcGJnWJhGcNyc+8efZQ9NDwm5JQYt2Njh fwBkVW27Yazig3x7gfPf8ncmsYDf5ZfDxGkwuOHawBgjNf/ZfTJ+I27tHjb90w== From: Caleb James DeLisle To: linux-mips@vger.kernel.org Cc: Thomas Gleixner , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Thomas Bogendoerfer , Daniel Lezcano , devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, benjamin.larsson@genexis.eu, Caleb James DeLisle Subject: [PATCH v1 2/8] dt-bindings: interrupt-controller: Add EcoNet EN751221 INTC Date: Fri, 21 Mar 2025 13:46:27 +0000 Message-Id: <20250321134633.2155141-3-cjd@cjdns.fr> In-Reply-To: <20250321134633.2155141-1-cjd@cjdns.fr> References: <20250321134633.2155141-1-cjd@cjdns.fr> Precedence: bulk X-Mailing-List: linux-mips@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-Last-TLS-Session-Version: TLSv1.3 Document the device tree binding for the interrupt controller in the EcoNet EN751221 MIPS SoC. Signed-off-by: Caleb James DeLisle --- If anyone is aware of a standard name for this "shadow interrupt" pattern, please let me know and I will re-send with updated naming. --- .../econet,en751221-intc.yaml | 77 +++++++++++++++++++ 1 file changed, 77 insertions(+) create mode 100644 Documentation/devicetree/bindings/interrupt-controller/econet,en751221-intc.yaml diff --git a/Documentation/devicetree/bindings/interrupt-controller/econet,en751221-intc.yaml b/Documentation/devicetree/bindings/interrupt-controller/econet,en751221-intc.yaml new file mode 100644 index 000000000000..1b0f262c9630 --- /dev/null +++ b/Documentation/devicetree/bindings/interrupt-controller/econet,en751221-intc.yaml @@ -0,0 +1,77 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/interrupt-controller/econet,en751221-intc.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: EcoNet EN751221 Interrupt Controller + +maintainers: + - Caleb James DeLisle + +description: | + The EcoNet EN751221 Interrupt Controller is a simple interrupt controller + designed for the MIPS 34Kc MT SMP processor with 2 VPEs. Each interrupt can + be routed to either VPE but not both, so to support per-CPU interrupts, a + secondary IRQ number is allocated to control masking/unmasking on VPE#1. For + lack of a better term we call these "shadow interrupts". The assignment of + shadow interrupts is defined by the SoC integrator when wiring the interrupt + lines, so they are configurable in the device tree. + +allOf: + - $ref: /schemas/interrupt-controller.yaml# + +properties: + compatible: + const: econet,en751221-intc + + reg: + maxItems: 1 + + "#interrupt-cells": + const: 1 + + interrupt-controller: true + + interrupts: + maxItems: 1 + description: Interrupt line connecting this controller to its parent. + + econet,shadow-interrupts: + $ref: /schemas/types.yaml#/definitions/uint32-array + description: | + An array of interrupt number pairs where each pair represents a shadow + interrupt relationship. The first number in each pair is the primary IRQ, + and the second is its shadow IRQ used for VPE#1 control. For example, + <8 3> means IRQ 8 is shadowed by IRQ 3, so IRQ 3 cannot be mapped, but + when VPE#1 requests IRQ 8, it will use manipulate the IRQ 3 mask bit. + maxItems: 40 + items: + minimum: 0 + maximum: 40 + +required: + - compatible + - reg + - interrupt-controller + - "#interrupt-cells" + - interrupt-parent + - interrupts + +additionalProperties: false + +examples: + - | + intc: interrupt-controller@1fb40000 { + compatible = "econet,en751221-intc"; + reg = <0x1fb40000 0x100>; + + interrupt-controller; + #interrupt-cells = <1>; + + interrupt-parent = <&cpuintc>; + interrupts = <2>; + + econet,shadow-interrupts = <7 2>, <8 3>, <13 12>, <30 29>; + }; +... From patchwork Fri Mar 21 13:46:28 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Caleb James DeLisle X-Patchwork-Id: 14025474 Received: from mail.cjdns.fr (mail.cjdns.fr [5.135.140.105]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 90CEA14A62B; Fri, 21 Mar 2025 13:53:01 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=5.135.140.105 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1742565183; cv=none; b=njOGA3VAY/I6cbPXCig0AIEddFne36UFmQJjwqUt6P42kmJ8kJY006dFNDgMXmpmPVgjcAP2V7/kht68tHl9FDixrgS6ZQCk2ha0Vla/JebYwZ+4/H7lHv0h/ZHhduTwiuLNvFnrCzCY94VzvaGVxUPhNVGQNHmhr8I2iOLOz0Q= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1742565183; c=relaxed/simple; bh=7jtpfirCjXZyKVm5kgQc0owO+pKYugs44KRwq67U/HQ=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=uWheNRpwr6AM2cAPE5cfMXLQqn1paygpNsvU03tR6qZy8KeNyet7RevyLzSaDfrcggup4tHkkoPZrRJf++AR9BgiPIvPIUFH8d/sY6/jRqWlqNx3UPYNgaiPICwrvMbh+51ApaW8wG1PQF8n47PGPG/jaS9RtB5RuJlTy8QlEBU= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=cjdns.fr; spf=none smtp.mailfrom=cjdns.fr; dkim=pass (2048-bit key) header.d=cjdns.fr header.i=@cjdns.fr header.b=ZzMj8bdZ; arc=none smtp.client-ip=5.135.140.105 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=cjdns.fr Authentication-Results: smtp.subspace.kernel.org; spf=none smtp.mailfrom=cjdns.fr Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=cjdns.fr header.i=@cjdns.fr header.b="ZzMj8bdZ" Received: from [127.0.0.1] (localhost [127.0.0.1]) by localhost (Mailerdaemon) with ESMTPSA id D503C2A4048; Fri, 21 Mar 2025 14:46:58 +0100 (CET) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=cjdns.fr; s=dkim; t=1742564820; h=from:subject:date:message-id:to:cc:mime-version: content-transfer-encoding:in-reply-to:references; bh=uVYceoWg9ocI3yoOIXEQp6iVhUeDIwRtsFmbffeV5yE=; b=ZzMj8bdZVNAzIJ6vcHZH6ERMHmuwiM+mq/oxiIKDCeNHh7ozQflFulxcMlptnIYCGDCWST EgSf/dsT6cqBDOUpbJQfQoEpmbRVLRVpuTlMQMQGwV1JFna/jSXyf7PO+ALUCZOKL7ZSOE g+9unX44wTh0ks05qBc0fm39rZxuSCipGWfU5J4rSbxLQfW+uGjuU2BaV3qAXLyKeOrpCA KwusVHRhMmMEZyEN3uYd6GA3hCHiiABncdaMGMrZdFzzvob6QBDNzT2bvQL5QaBLJ+e7C5 QoWqBT3ewYwgaotIyqn32N/149uwXDVRzSc4c22UeKTbygeHCjmKnzSt9v4RHA== From: Caleb James DeLisle To: linux-mips@vger.kernel.org Cc: Thomas Gleixner , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Thomas Bogendoerfer , Daniel Lezcano , devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, benjamin.larsson@genexis.eu, Caleb James DeLisle Subject: [PATCH v1 3/8] irqchip: Add EcoNet EN751221 INTC Date: Fri, 21 Mar 2025 13:46:28 +0000 Message-Id: <20250321134633.2155141-4-cjd@cjdns.fr> In-Reply-To: <20250321134633.2155141-1-cjd@cjdns.fr> References: <20250321134633.2155141-1-cjd@cjdns.fr> Precedence: bulk X-Mailing-List: linux-mips@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-Last-TLS-Session-Version: TLSv1.3 Add a driver for the interrupt controller in the EcoNet EN751221 MIPS SoC. Signed-off-by: Caleb James DeLisle --- If CPU_MIPSR2_IRQ_EI / CPU_MIPSR2_IRQ_VI are enabled in the build, this device switches to sending all interrupts as vectored - which IRQ_MIPS_CPU is not prepared to handle. If anybody knows how to either disable this behavior, or handle vectored interrupts without ugly code that breaks cascading, please let me know and I will implement that and add MIPS_MT_SMP in a future patchset. --- drivers/irqchip/Kconfig | 5 + drivers/irqchip/Makefile | 1 + drivers/irqchip/irq-econet-en751221.c | 280 ++++++++++++++++++++++++++ 3 files changed, 286 insertions(+) create mode 100644 drivers/irqchip/irq-econet-en751221.c diff --git a/drivers/irqchip/Kconfig b/drivers/irqchip/Kconfig index c11b9965c4ad..a591ad3156dc 100644 --- a/drivers/irqchip/Kconfig +++ b/drivers/irqchip/Kconfig @@ -147,6 +147,11 @@ config DW_APB_ICTL select GENERIC_IRQ_CHIP select IRQ_DOMAIN_HIERARCHY +config ECONET_EN751221_INTC + bool + select GENERIC_IRQ_CHIP + select IRQ_DOMAIN + config FARADAY_FTINTC010 bool select IRQ_DOMAIN diff --git a/drivers/irqchip/Makefile b/drivers/irqchip/Makefile index 25e9ad29b8c4..1ee83823928d 100644 --- a/drivers/irqchip/Makefile +++ b/drivers/irqchip/Makefile @@ -10,6 +10,7 @@ obj-$(CONFIG_ARCH_BCM2835) += irq-bcm2836.o obj-$(CONFIG_ARCH_ACTIONS) += irq-owl-sirq.o obj-$(CONFIG_DAVINCI_CP_INTC) += irq-davinci-cp-intc.o obj-$(CONFIG_EXYNOS_IRQ_COMBINER) += exynos-combiner.o +obj-$(CONFIG_ECONET_EN751221_INTC) += irq-econet-en751221.o obj-$(CONFIG_FARADAY_FTINTC010) += irq-ftintc010.o obj-$(CONFIG_ARCH_HIP04) += irq-hip04.o obj-$(CONFIG_ARCH_LPC32XX) += irq-lpc32xx.o diff --git a/drivers/irqchip/irq-econet-en751221.c b/drivers/irqchip/irq-econet-en751221.c new file mode 100644 index 000000000000..edbb8a3d6d51 --- /dev/null +++ b/drivers/irqchip/irq-econet-en751221.c @@ -0,0 +1,280 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * EN751221 Interrupt Controller Driver. + * + * Copyright (C) 2025 Caleb James DeLisle + */ + +#include +#include +#include +#include +#include +#include +#include + +#define INTC_IRQ_COUNT 40 + +#define INTC_NO_SHADOW 0xff +#define INTC_IS_SHADOW 0xfe + +#define REG_MASK0 0x04 +#define REG_MASK1 0x50 +#define REG_PENDING0 0x08 +#define REG_PENDING1 0x54 + +static const struct econet_intc { + const struct irq_chip chip; + + const struct irq_domain_ops domain_ops; +} econet_intc; + +static struct { + void __iomem *membase; + u8 shadow_interrupts[INTC_IRQ_COUNT]; +} econet_intc_rai __ro_after_init; + +static DEFINE_RAW_SPINLOCK(irq_lock); + +static void econet_wreg(u32 reg, u32 val, u32 mask) +{ + unsigned long flags; + u32 v; + + raw_spin_lock_irqsave(&irq_lock, flags); + + v = ioread32(econet_intc_rai.membase + reg); + v &= ~mask; + v |= val & mask; + iowrite32(v, econet_intc_rai.membase + reg); + + raw_spin_unlock_irqrestore(&irq_lock, flags); +} + +static void econet_chmask(u32 hwirq, bool unmask) +{ + u32 reg; + u32 mask; + u32 bit; + u8 shadow; + + shadow = econet_intc_rai.shadow_interrupts[hwirq]; + if (WARN_ON_ONCE(shadow == INTC_IS_SHADOW)) + return; + else if (shadow < INTC_NO_SHADOW && smp_processor_id() > 0) + hwirq = shadow; + + if (hwirq >= 32) { + reg = REG_MASK1; + mask = BIT(hwirq - 32); + } else { + reg = REG_MASK0; + mask = BIT(hwirq); + } + bit = (unmask) ? mask : 0; + + econet_wreg(reg, bit, mask); +} + +static void econet_intc_mask(struct irq_data *d) +{ + econet_chmask(d->hwirq, false); +} + +static void econet_intc_unmask(struct irq_data *d) +{ + econet_chmask(d->hwirq, true); +} + +static void econet_mask_all(void) +{ + econet_wreg(REG_MASK0, 0, ~0); + econet_wreg(REG_MASK1, 0, ~0); +} + +static void econet_intc_handle_pending(struct irq_domain *d, u32 pending, u32 offset) +{ + int hwirq; + + while (pending) { + hwirq = fls(pending) - 1; + generic_handle_domain_irq(d, hwirq + offset); + pending &= ~BIT(hwirq); + } +} + +static void econet_intc_from_parent(struct irq_desc *desc) +{ + struct irq_chip *chip = irq_desc_get_chip(desc); + struct irq_domain *domain; + u32 pending0; + u32 pending1; + + chained_irq_enter(chip, desc); + + pending0 = ioread32(econet_intc_rai.membase + REG_PENDING0); + pending1 = ioread32(econet_intc_rai.membase + REG_PENDING1); + + if (unlikely(!(pending0 | pending1))) { + spurious_interrupt(); + goto out; + } + + domain = irq_desc_get_handler_data(desc); + + econet_intc_handle_pending(domain, pending0, 0); + econet_intc_handle_pending(domain, pending1, 32); + +out: + chained_irq_exit(chip, desc); +} + +static int econet_intc_map(struct irq_domain *d, u32 irq, irq_hw_number_t hwirq) +{ + int ret; + + if (hwirq >= INTC_IRQ_COUNT) { + pr_err("%s: hwirq %lu out of range\n", __func__, hwirq); + return -EINVAL; + } else if (econet_intc_rai.shadow_interrupts[hwirq] == INTC_IS_SHADOW) { + pr_err("%s: can't map hwirq %lu, it is a shadow interrupt\n", + __func__, hwirq); + return -EINVAL; + } + if (econet_intc_rai.shadow_interrupts[hwirq] != INTC_NO_SHADOW) { + irq_set_chip_and_handler( + irq, &econet_intc.chip, handle_percpu_devid_irq); + ret = irq_set_percpu_devid(irq); + if (ret) { + pr_warn("%s: Failed irq_set_percpu_devid for %u: %d\n", + d->name, irq, ret); + } + } else { + irq_set_chip_and_handler( + irq, &econet_intc.chip, handle_level_irq); + } + irq_set_chip_data(irq, NULL); + return 0; +} + +static const struct econet_intc econet_intc = { + .chip = { + .name = "en751221-intc", + .irq_unmask = econet_intc_unmask, + .irq_mask = econet_intc_mask, + .irq_mask_ack = econet_intc_mask, + }, + .domain_ops = { + .xlate = irq_domain_xlate_onecell, + .map = econet_intc_map, + }, +}; + +static int __init get_shadow_interrupts(struct device_node *node) +{ + const char *field = "econet,shadow-interrupts"; + int n_shadow_interrupts; + u32 *shadow_interrupts; + + n_shadow_interrupts = of_property_count_u32_elems(node, field); + memset(econet_intc_rai.shadow_interrupts, INTC_NO_SHADOW, + sizeof(econet_intc_rai.shadow_interrupts)); + if (n_shadow_interrupts <= 0) { + return 0; + } else if (n_shadow_interrupts % 2) { + pr_err("%pOF: %s count is odd, ignoring\n", node, field); + return 0; + } + shadow_interrupts = kmalloc_array(n_shadow_interrupts, sizeof(u32), + GFP_KERNEL); + if (!shadow_interrupts) + return -ENOMEM; + if (of_property_read_u32_array(node, field, + shadow_interrupts, n_shadow_interrupts) + ) { + pr_err("%pOF: Failed to read %s\n", node, field); + kfree(shadow_interrupts); + return -EINVAL; + } + for (int i = 0; i < n_shadow_interrupts; i += 2) { + u32 shadow = shadow_interrupts[i + 1]; + u32 target = shadow_interrupts[i]; + + if (shadow > INTC_IRQ_COUNT) { + pr_err("%pOF: %s[%d] shadow(%d) out of range\n", + node, field, i, shadow); + continue; + } + if (target >= INTC_IRQ_COUNT) { + pr_err("%pOF: %s[%d] target(%d) out of range\n", + node, field, i + 1, target); + continue; + } + econet_intc_rai.shadow_interrupts[target] = shadow; + econet_intc_rai.shadow_interrupts[shadow] = INTC_IS_SHADOW; + } + kfree(shadow_interrupts); + return 0; +} + +static int __init econet_intc_of_init(struct device_node *node, struct device_node *parent) +{ + int ret; + int irq; + struct resource res; + struct irq_domain *domain; + + ret = get_shadow_interrupts(node); + if (ret) + return ret; + + irq = irq_of_parse_and_map(node, 0); + if (!irq) { + pr_err("%pOF: DT: Failed to get IRQ from 'interrupts'\n", node); + return -EINVAL; + } + + if (of_address_to_resource(node, 0, &res)) { + pr_err("%pOF: DT: Failed to get 'reg'\n", node); + ret = -EINVAL; + goto err_dispose_mapping; + } + + if (!request_mem_region(res.start, resource_size(&res), res.name)) { + pr_err("%pOF: Failed to request memory\n", node); + ret = -EBUSY; + goto err_dispose_mapping; + } + + econet_intc_rai.membase = ioremap(res.start, resource_size(&res)); + if (!econet_intc_rai.membase) { + pr_err("%pOF: Failed to remap membase\n", node); + ret = -ENOMEM; + goto err_release; + } + + econet_mask_all(); + + domain = irq_domain_add_linear( + node, INTC_IRQ_COUNT, + &econet_intc.domain_ops, NULL); + if (!domain) { + pr_err("%pOF: Failed to add irqdomain\n", node); + ret = -ENOMEM; + goto err_unmap; + } + + irq_set_chained_handler_and_data(irq, econet_intc_from_parent, domain); + + return 0; + +err_unmap: + iounmap(econet_intc_rai.membase); +err_release: + release_mem_region(res.start, resource_size(&res)); +err_dispose_mapping: + irq_dispose_mapping(irq); + return ret; +} + +IRQCHIP_DECLARE(econet_en751221_intc, "econet,en751221-intc", econet_intc_of_init); From patchwork Fri Mar 21 13:46:29 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Caleb James DeLisle X-Patchwork-Id: 14025475 Received: from mail.cjdns.fr (mail.cjdns.fr [5.135.140.105]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id B0BC08634D; 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Signed-off-by: Caleb James DeLisle --- .../bindings/timer/econet,timer-hpt.yaml | 58 +++++++++++++++++++ 1 file changed, 58 insertions(+) create mode 100644 Documentation/devicetree/bindings/timer/econet,timer-hpt.yaml diff --git a/Documentation/devicetree/bindings/timer/econet,timer-hpt.yaml b/Documentation/devicetree/bindings/timer/econet,timer-hpt.yaml new file mode 100644 index 000000000000..8b7ff9bce947 --- /dev/null +++ b/Documentation/devicetree/bindings/timer/econet,timer-hpt.yaml @@ -0,0 +1,58 @@ +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/timer/econet,timer-hpt.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: EcoNet High Precision Timer (HPT) + +maintainers: + - Calev James DeLisle + +description: | + The EcoNet High Precision Timer (HPT) is a timer peripheral found in various + EcoNet SoCs, including the EN751221 and EN751627 families. It provides per-VPE + count/compare registers and a per-CPU control register, with a single interrupt + line using a percpu-devid interrupt mechanism. + +properties: + compatible: + const: econet,timer-hpt + + reg: + minItems: 1 + maxItems: 2 + description: | + Physical base address and size of the timer's register space. On 34Kc + processors, a single region is used. On 1004Kc processors, two regions are + used, one for each core. + + interrupts: + maxItems: 1 + description: | + The interrupt number for the timer. This is a percpu-devid interrupt shared + across CPUs. + + clocks: + maxItems: 1 + description: | + A clock to get the frequency of the timer. + +required: + - compatible + - reg + - interrupts + - clocks + +additionalProperties: false + +examples: + - | + timer_hpt@1fbf0400 { + compatible = "econet,timer-hpt"; + reg = <0x1fbf0400 0x100>; + interrupt-parent = <&intc>; + interrupts = <30>; + clocks = <&hpt_clock>; + }; +... From patchwork Fri Mar 21 13:46:30 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Caleb James DeLisle X-Patchwork-Id: 14025466 Received: from mail.cjdns.fr (mail.cjdns.fr [5.135.140.105]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 277FACA5E; Fri, 21 Mar 2025 13:47:05 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=5.135.140.105 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1742564828; cv=none; b=f+AVKLO0am5h/oSwFoHtcHtlCEZ4R01e6vG8AgUAMQQb1ngZhyk1PLhPI27EuZHU5R0eQYnEqPaP/8pfA/mZaldBJYq5QGLuWNVgoUbN1k41Sl1ovtK6Ct4q5vIpi/40eTS+46gheMEsbqrONuefPhZ71U8E5aSjnZskoklS5+Q= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1742564828; c=relaxed/simple; bh=TpABEAnb+6PAavBpSFVYZohOAr2+z0k2jFWbIUj+o9s=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=OJe41Lvjk9SD9Qh58j30q29G4igVNigaoJ+wfIOP9yVZQ0ah5fuJNVU3Lubq44/CI2+THFdoweQ/Ud8BGgbOMhMCRxlAQi4Ou3PkOod6JcInVkPTANLM2bJz+3sEH2AgxSdZFZ/3p9a5ws5JWrRNmRspGnUsNceViO9XbJCKvsc= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=cjdns.fr; spf=none smtp.mailfrom=cjdns.fr; dkim=pass (2048-bit key) header.d=cjdns.fr header.i=@cjdns.fr header.b=tX8es49g; arc=none smtp.client-ip=5.135.140.105 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=cjdns.fr Authentication-Results: smtp.subspace.kernel.org; spf=none smtp.mailfrom=cjdns.fr Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=cjdns.fr header.i=@cjdns.fr header.b="tX8es49g" Received: from [127.0.0.1] (localhost [127.0.0.1]) by localhost (Mailerdaemon) with ESMTPSA id 10C6B2A3840; Fri, 21 Mar 2025 14:47:01 +0100 (CET) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=cjdns.fr; s=dkim; t=1742564823; h=from:subject:date:message-id:to:cc:mime-version: content-transfer-encoding:in-reply-to:references; bh=MTYMH0v2jEQGAhbRnoLg7A3Wz662nCTmYG/rRM34Q1M=; b=tX8es49ghOks0m2x3SEgxLe3X/NPy2OXVDonEqSHvVL5xdPnNmyWl46TQHsSG++AO22zrZ JFE6CLnLYPZQCYC2Wh3bkcFyFr7eySKKvnelF2jFn2cBnbJDlS4WT86Kw2HKjuqUkWIKVt w3BDu4oVviRzrDBqGbuJqG8TPh/gBbdU/9AqMyUZUpYtIAI3b513zZRp9GfnDmG3a79lk/ 2sveQjQMwbYbHVxv7gom455pK9Vxq8dKES/hR1LqOfy90qvFbq6NdhOjx/rTVG6XkAfd50 GVelMmRj0c0LX1zwSsx9/S/ajMhqXalnQe3D0pEJx7YBi1bL36Ye/ywCYrLT6w== From: Caleb James DeLisle To: linux-mips@vger.kernel.org Cc: Thomas Gleixner , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Thomas Bogendoerfer , Daniel Lezcano , devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, benjamin.larsson@genexis.eu, Caleb James DeLisle Subject: [PATCH v1 5/8] clocksource/drivers: Add EcoNet Timer HPT driver Date: Fri, 21 Mar 2025 13:46:30 +0000 Message-Id: <20250321134633.2155141-6-cjd@cjdns.fr> In-Reply-To: <20250321134633.2155141-1-cjd@cjdns.fr> References: <20250321134633.2155141-1-cjd@cjdns.fr> Precedence: bulk X-Mailing-List: linux-mips@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-Last-TLS-Session-Version: TLSv1.3 Introduce a clocksource driver for the so-called high-precision timer (HPT) in the EcoNet EN751221 MIPS SoC. Signed-off-by: Caleb James DeLisle --- The name HPT derives from a log line "Using XXX.XX MHz high precision timer" which originated in mips/kernel/time.c and was copied into the vendor driver. Subsequent generations of vendor and 3rd party out-of-tree drivers preserved the log line long after it had been removed from the kernel proper. This device began to be known as "the HPT", so we preserve the naming and log line. --- drivers/clocksource/Kconfig | 8 + drivers/clocksource/Makefile | 1 + drivers/clocksource/timer-econet-hpt.c | 221 +++++++++++++++++++++++++ 3 files changed, 230 insertions(+) create mode 100644 drivers/clocksource/timer-econet-hpt.c diff --git a/drivers/clocksource/Kconfig b/drivers/clocksource/Kconfig index 487c85259967..1a7a9b4f16f9 100644 --- a/drivers/clocksource/Kconfig +++ b/drivers/clocksource/Kconfig @@ -73,6 +73,14 @@ config DW_APB_TIMER_OF select DW_APB_TIMER select TIMER_OF +config ECONET_TIMER_HPT + bool "EcoNet High Precision Timer" if COMPILE_TEST + depends on HAS_IOMEM + select CLKSRC_MMIO + select TIMER_OF + help + Support for CPU timer found on EcoNet MIPS based SoCs. + config FTTMR010_TIMER bool "Faraday Technology timer driver" if COMPILE_TEST depends on HAS_IOMEM diff --git a/drivers/clocksource/Makefile b/drivers/clocksource/Makefile index 43ef16a4efa6..a3dd2a9d2a37 100644 --- a/drivers/clocksource/Makefile +++ b/drivers/clocksource/Makefile @@ -17,6 +17,7 @@ obj-$(CONFIG_CLKBLD_I8253) += i8253.o obj-$(CONFIG_CLKSRC_MMIO) += mmio.o obj-$(CONFIG_DAVINCI_TIMER) += timer-davinci.o obj-$(CONFIG_DIGICOLOR_TIMER) += timer-digicolor.o +obj-$(CONFIG_ECONET_TIMER_HPT) += timer-econet-hpt.o obj-$(CONFIG_OMAP_DM_TIMER) += timer-ti-dm.o obj-$(CONFIG_OMAP_DM_SYSTIMER) += timer-ti-dm-systimer.o obj-$(CONFIG_DW_APB_TIMER) += dw_apb_timer.o diff --git a/drivers/clocksource/timer-econet-hpt.c b/drivers/clocksource/timer-econet-hpt.c new file mode 100644 index 000000000000..defd797426c5 --- /dev/null +++ b/drivers/clocksource/timer-econet-hpt.c @@ -0,0 +1,221 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Timer present on EcoNet EN75xx MIPS based SoCs. + * + * Copyright (C) 2025 by Caleb James DeLisle + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#define ECONET_BITS 32 +#define ECONET_MIN_DELTA 0x00001000 +#define ECONET_MAX_DELTA GENMASK(ECONET_BITS - 2, 0) +/* 34Kc hardware has 1 block and 1004Kc has 2. */ +#define ECONET_NUM_BLOCKS DIV_ROUND_UP(NR_CPUS, 2) + +static struct { + void __iomem *membase[ECONET_NUM_BLOCKS]; + u32 freq_hz; +} econet_timer __ro_after_init; + +static DEFINE_PER_CPU(struct clock_event_device, econet_timer_pcpu_m); + +/* Each memory block has 2 timers, the order of registers is: + * CTL, CMR0, CNT0, CMR1, CNT1 + */ +static inline void __iomem *reg_ctl(u32 timer_n) +{ + return econet_timer.membase[timer_n >> 1]; +} + +static inline void __iomem *reg_compare(u32 timer_n) +{ + return econet_timer.membase[timer_n >> 1] + (timer_n & 1) * 0x08 + 0x04; +} + +static inline void __iomem *reg_count(u32 timer_n) +{ + return econet_timer.membase[timer_n >> 1] + (timer_n & 1) * 0x08 + 0x08; +} + +static inline u32 ctl_bit_enabled(u32 timer_n) +{ + return 1U << (timer_n & 1); +} + +static inline u32 ctl_bit_pending(u32 timer_n) +{ + return 1U << ((timer_n & 1) + 16); +} + +static bool cevt_is_pending(int cpu_id) +{ + return ioread32(reg_ctl(cpu_id)) & ctl_bit_pending(cpu_id); +} + +static irqreturn_t cevt_interrupt(int irq, void *dev_id) +{ + struct clock_event_device *dev = this_cpu_ptr(&econet_timer_pcpu_m); + int cpu = cpumask_first(dev->cpumask); + + if (!cevt_is_pending(cpu)) { + pr_debug("%s IRQ %d on CPU %d is not pending\n", __func__, irq, cpu); + return IRQ_NONE; + } + + iowrite32(ioread32(reg_count(cpu)), reg_compare(cpu)); + dev->event_handler(dev); + return IRQ_HANDLED; +} + +static int cevt_set_next_event(ulong delta, struct clock_event_device *dev) +{ + int cpu; + u32 next; + + cpu = cpumask_first(dev->cpumask); + next = ioread32(reg_count(cpu)) + delta; + iowrite32(next, reg_compare(cpu)); + + if ((s32)(next - ioread32(reg_count(cpu))) < ECONET_MIN_DELTA / 2) + return -ETIME; + + return 0; +} + +static int cevt_init_cpu(uint cpu) +{ + u32 reg; + struct clock_event_device *cd = &per_cpu(econet_timer_pcpu_m, cpu); + + pr_info("%s: Setting up clockevent for CPU %d\n", cd->name, cpu); + + reg = ioread32(reg_ctl(cpu)) | ctl_bit_enabled(cpu); + iowrite32(reg, reg_ctl(cpu)); + + enable_percpu_irq(cd->irq, IRQ_TYPE_NONE); + + /* Do this last because it synchronously configures the timer */ + clockevents_config_and_register( + cd, econet_timer.freq_hz, + ECONET_MIN_DELTA, ECONET_MAX_DELTA); + + return 0; +} + +static u64 notrace sched_clock_read(void) +{ + /* Always read from clock zero no matter the CPU */ + return (u64)ioread32(reg_count(0)); +} + +/* Init */ + +static void __init cevt_dev_init(uint cpu) +{ + iowrite32(0, reg_count(cpu)); + iowrite32(U32_MAX, reg_compare(cpu)); +} + +static int __init cevt_init(struct device_node *np) +{ + int i; + int irq; + int ret; + + irq = irq_of_parse_and_map(np, 0); + if (irq <= 0) { + pr_err("%pOFn: irq_of_parse_and_map failed", np); + return -EINVAL; + } + + ret = request_percpu_irq( + irq, cevt_interrupt, + np->name, &econet_timer_pcpu_m); + + if (ret < 0) { + pr_err("%pOFn: IRQ %d setup failed (%d)\n", np, irq, ret); + goto err_unmap_irq; + } + + for_each_possible_cpu(i) { + struct clock_event_device *cd = &per_cpu(econet_timer_pcpu_m, i); + + cd->rating = 310, + cd->features = CLOCK_EVT_FEAT_ONESHOT | + CLOCK_EVT_FEAT_C3STOP | + CLOCK_EVT_FEAT_PERCPU; + cd->set_next_event = cevt_set_next_event; + cd->irq = irq; + cd->cpumask = cpumask_of(i); + cd->name = np->name; + + cevt_dev_init(i); + } + + cpuhp_setup_state(CPUHP_AP_MIPS_GIC_TIMER_STARTING, + "clockevents/en75/timer:starting", + cevt_init_cpu, NULL); + return 0; + +err_unmap_irq: + irq_dispose_mapping(irq); + return ret; +} + +static int __init timer_init(struct device_node *np) +{ + int num_blocks = DIV_ROUND_UP(num_possible_cpus(), 2); + struct clk *clk; + int ret; + + clk = of_clk_get(np, 0); + if (IS_ERR(clk)) { + pr_err("%pOFn: Failed to get CPU clock from DT %ld\n", np, + PTR_ERR(clk)); + return PTR_ERR(clk); + } + + econet_timer.freq_hz = clk_get_rate(clk); + + for (int i = 0; i < num_blocks; i++) { + econet_timer.membase[i] = of_iomap(np, i); + if (!econet_timer.membase[i]) { + pr_err("%pOFn: failed to map register [%d]\n", np, i); + return -ENXIO; + } + } + + /* For clocksource purposes always read clock zero, whatever the CPU */ + ret = clocksource_mmio_init(reg_count(0), np->name, + econet_timer.freq_hz, 301, ECONET_BITS, + clocksource_mmio_readl_up); + if (ret) { + pr_err("%pOFn: clocksource_mmio_init failed: %d", np, ret); + return ret; + } + + ret = cevt_init(np); + if (ret < 0) + return ret; + + sched_clock_register(sched_clock_read, ECONET_BITS, + econet_timer.freq_hz); + + pr_info("%pOFn: using %u.%03u MHz high precision timer\n", np, + econet_timer.freq_hz / 1000000, + (econet_timer.freq_hz / 1000) % 1000); + + return 0; +} + +TIMER_OF_DECLARE(econet_timer_hpt, "econet,timer-hpt", timer_init); From patchwork Fri Mar 21 13:46:31 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Caleb James DeLisle X-Patchwork-Id: 14025467 Received: from mail.cjdns.fr (mail.cjdns.fr [5.135.140.105]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 14ED11EA80; Fri, 21 Mar 2025 13:47:06 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=5.135.140.105 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; 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spf=none smtp.mailfrom=cjdns.fr Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=cjdns.fr header.i=@cjdns.fr header.b="d0PxIvHZ" Received: from [127.0.0.1] (localhost [127.0.0.1]) by localhost (Mailerdaemon) with ESMTPSA id A6A782A406E; Fri, 21 Mar 2025 14:47:03 +0100 (CET) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=cjdns.fr; s=dkim; t=1742564824; h=from:subject:date:message-id:to:cc:mime-version: content-transfer-encoding:in-reply-to:references; bh=cBr/AN+Dmtl1pCcesD8ZmV7b9FGEZvfEmYXFEbydOBE=; b=d0PxIvHZ8tL+JyFiShYmhEaoIBNno1UWX++Elx+egOXJ8AC+niiMIxpSTyDeL37y6s/WD3 2Q9gLeiu1NBklb1px2/Dv+eM8ZnfG6cLPsd0jw5nw4IVqt+74xd+iEkq0BwR93pjyx/T/C RtKQ2YGH6JSEHHxrJZgcPHseLYxtTtytze0vuF2KdsLvgPRhMgxc+aZd89WxWNKZf6jtH8 CuCs2Fa7eYq6MBe6o9bNbK2vaRZgZA4/DaUbuQ2GDxc+w6yDqjUk3JnaxASld6pfqJMPwE WFb/YA/ZflETh0hkJyqeEsLD39jihREZB4g7pJzrVkWmzeKD5iqpy2tT1UnnqQ== From: Caleb James DeLisle To: linux-mips@vger.kernel.org Cc: Thomas Gleixner , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Thomas Bogendoerfer , Daniel Lezcano , devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, benjamin.larsson@genexis.eu, Caleb James DeLisle Subject: [PATCH v1 6/8] dt-bindings: mips: Add EcoNet platform binding Date: Fri, 21 Mar 2025 13:46:31 +0000 Message-Id: <20250321134633.2155141-7-cjd@cjdns.fr> In-Reply-To: <20250321134633.2155141-1-cjd@cjdns.fr> References: <20250321134633.2155141-1-cjd@cjdns.fr> Precedence: bulk X-Mailing-List: linux-mips@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-Last-TLS-Session-Version: TLSv1.3 Document the top-level device tree binding for EcoNet MIPS-based SoCs. Signed-off-by: Caleb James DeLisle --- .../devicetree/bindings/mips/econet.yaml | 27 +++++++++++++++++++ 1 file changed, 27 insertions(+) create mode 100644 Documentation/devicetree/bindings/mips/econet.yaml diff --git a/Documentation/devicetree/bindings/mips/econet.yaml b/Documentation/devicetree/bindings/mips/econet.yaml new file mode 100644 index 000000000000..44da78dc1e29 --- /dev/null +++ b/Documentation/devicetree/bindings/mips/econet.yaml @@ -0,0 +1,27 @@ +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/mips/econet.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: EcoNet MIPS SoCs + +maintainers: + - Caleb James DeLisle + +description: + Boards with an EcoNet SoC shall have the following properties. + +properties: + $nodename: + const: '/' + + compatible: + oneOf: + - description: Boards with EcoNet EN751221 family SoC + items: + - const: econet,en751221 + +additionalProperties: true + +... From patchwork Fri Mar 21 13:46:32 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Caleb James DeLisle X-Patchwork-Id: 14025468 Received: from mail.cjdns.fr (mail.cjdns.fr [5.135.140.105]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 09C4D78F5D; Fri, 21 Mar 2025 13:47:08 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=5.135.140.105 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1742564831; cv=none; b=qxHLYI3tCijkPGParh4t52sS5aqw0szcUsw5RaqwTgoGyz9AACPnzxPsGf2vNo9yFmQ62kK9MmzH0tjWOvPAQ0CbUdgTPLcnAg25HNMwC7jf2l5aCIAzLVVdL/A/NR/0dAWmBwmmbyrF5bmwjzzsvyWeU6QGA/4r/rW3qYzTP8w= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1742564831; c=relaxed/simple; bh=t3Vul1Mcdv+1GMUsDvialCECw43EJgBk3CYtRwp26xs=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=R0xaSLNWAab30Es3/IOJxoD3F9LWpLMuBmWibYn85GzfCEytlL53gsxFjP9+Q4eCshMYtEBGiw0pJMzM4CQQQi8jfKPDt9HorGvYpJlEy/kcgPIXZA8kDrYDCY0FkAYsNFozKEnQ5CSJ1Tx1njcAzCoszuPPsgcqSbXDKdoCLhs= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=cjdns.fr; spf=none smtp.mailfrom=cjdns.fr; dkim=pass (2048-bit key) header.d=cjdns.fr header.i=@cjdns.fr header.b=ssfsiju5; arc=none smtp.client-ip=5.135.140.105 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=cjdns.fr Authentication-Results: smtp.subspace.kernel.org; spf=none smtp.mailfrom=cjdns.fr Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=cjdns.fr header.i=@cjdns.fr header.b="ssfsiju5" Received: from [127.0.0.1] (localhost [127.0.0.1]) by localhost (Mailerdaemon) with ESMTPSA id 55AAA2A40B8; Fri, 21 Mar 2025 14:47:05 +0100 (CET) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=cjdns.fr; s=dkim; t=1742564826; h=from:subject:date:message-id:to:cc:mime-version: content-transfer-encoding:in-reply-to:references; bh=VDAr/VH2Lf+cycxyiwdi2azDuqbXm7Z7t4Q1guYYuPs=; b=ssfsiju5hvXNTnRo+4qZzf7lMxY+1o0ogc5+aNiiL6cj0b/domA1Z4TXeeddQl5FEiveCT eFCW7I5ZSl01RAjh4gHklDTQ0W9weLOGsAbH+m8WJ/5rC4sdAQjjJ4+NeDPCqLrzu2hRlk vNcJ/VcHjl4WXH6SpV6OPQJJKYtOAd/JXYs/hT9lVKwdaBgAe77PBv5wBRLTkVw0x9+MbI yeJmoQLu0lceR/bFzpszTXAH0Zamh/ILHtbg2UA24dHJ6FSlAgh0kkwAnVT2MBByL1WMlv M+OMiDta25Xe+QaJx9D52Z2208GzUfSddG9ffFdBfjRpdVKCMj1SYzbPM6kapg== From: Caleb James DeLisle To: linux-mips@vger.kernel.org Cc: Thomas Gleixner , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Thomas Bogendoerfer , Daniel Lezcano , devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, benjamin.larsson@genexis.eu, Caleb James DeLisle Subject: [PATCH v1 7/8] mips: Add EcoNet MIPS platform support Date: Fri, 21 Mar 2025 13:46:32 +0000 Message-Id: <20250321134633.2155141-8-cjd@cjdns.fr> In-Reply-To: <20250321134633.2155141-1-cjd@cjdns.fr> References: <20250321134633.2155141-1-cjd@cjdns.fr> Precedence: bulk X-Mailing-List: linux-mips@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-Last-TLS-Session-Version: TLSv1.3 Add platform support for EcoNet MIPS SoCs. Signed-off-by: Caleb James DeLisle --- As is typical of embedded platforms, it's not realistic to imagine building a fully functioning system from kernel sources alone. In the interest of providing something without external dependencies, I have included build and device tree for a minimal testing / PoC image that can be booted from memory on these devices. --- arch/mips/Kbuild.platforms | 1 + arch/mips/Kconfig | 25 ++++++ arch/mips/boot/compressed/uart-16550.c | 5 ++ arch/mips/boot/dts/Makefile | 1 + arch/mips/boot/dts/econet/Makefile | 2 + arch/mips/boot/dts/econet/en751221.dtsi | 62 +++++++++++++++ .../boot/dts/econet/en751221_test_image.dts | 19 +++++ arch/mips/econet/Kconfig | 42 ++++++++++ arch/mips/econet/Makefile | 2 + arch/mips/econet/Platform | 5 ++ arch/mips/econet/init.c | 78 +++++++++++++++++++ 11 files changed, 242 insertions(+) create mode 100644 arch/mips/boot/dts/econet/Makefile create mode 100644 arch/mips/boot/dts/econet/en751221.dtsi create mode 100644 arch/mips/boot/dts/econet/en751221_test_image.dts create mode 100644 arch/mips/econet/Kconfig create mode 100644 arch/mips/econet/Makefile create mode 100644 arch/mips/econet/Platform create mode 100644 arch/mips/econet/init.c diff --git a/arch/mips/Kbuild.platforms b/arch/mips/Kbuild.platforms index bca37ddf974b..41a00fa860c1 100644 --- a/arch/mips/Kbuild.platforms +++ b/arch/mips/Kbuild.platforms @@ -11,6 +11,7 @@ platform-$(CONFIG_CAVIUM_OCTEON_SOC) += cavium-octeon/ platform-$(CONFIG_EYEQ) += mobileye/ platform-$(CONFIG_MIPS_COBALT) += cobalt/ platform-$(CONFIG_MACH_DECSTATION) += dec/ +platform-$(CONFIG_ECONET) += econet/ platform-$(CONFIG_MIPS_GENERIC) += generic/ platform-$(CONFIG_MACH_JAZZ) += jazz/ platform-$(CONFIG_LANTIQ) += lantiq/ diff --git a/arch/mips/Kconfig b/arch/mips/Kconfig index 1924f2d83932..593ff00855b6 100644 --- a/arch/mips/Kconfig +++ b/arch/mips/Kconfig @@ -390,6 +390,30 @@ config MACH_DECSTATION otherwise choose R3000. +config ECONET + bool "EcoNet MIPS family" + select BOOT_RAW + select CPU_BIG_ENDIAN + select DEBUG_ZBOOT + select EARLY_PRINTK_8250 + select ECONET_TIMER_HPT + select SERIAL_OF_PLATFORM + select SYS_SUPPORTS_BIG_ENDIAN + select SYS_HAS_CPU_MIPS32_R1 + select SYS_HAS_CPU_MIPS32_R2 + select SYS_HAS_EARLY_PRINTK + select SYS_SUPPORTS_32BIT_KERNEL + select SYS_SUPPORTS_MIPS16 + select SYS_SUPPORTS_ZBOOT_UART16550 + select USE_GENERIC_EARLY_PRINTK_8250 + select USE_OF + help + EcoNet EN75xx MIPS devices are big endian MIPS machines used + in XPON (fiber) and DSL applications. They have SPI, PCI, USB, + GPIO, and Ethernet, with optional XPON, DSL, and VoIP DSP cores. + Don't confuse these with the Airoha ARM devices sometimes referred + to as "EcoNet", this family is for MIPS based devices only. + config MACH_JAZZ bool "Jazz family of machines" select ARC_MEMORY @@ -1019,6 +1043,7 @@ source "arch/mips/ath79/Kconfig" source "arch/mips/bcm47xx/Kconfig" source "arch/mips/bcm63xx/Kconfig" source "arch/mips/bmips/Kconfig" +source "arch/mips/econet/Kconfig" source "arch/mips/generic/Kconfig" source "arch/mips/ingenic/Kconfig" source "arch/mips/jazz/Kconfig" diff --git a/arch/mips/boot/compressed/uart-16550.c b/arch/mips/boot/compressed/uart-16550.c index db618e72a0c4..529e77a6487c 100644 --- a/arch/mips/boot/compressed/uart-16550.c +++ b/arch/mips/boot/compressed/uart-16550.c @@ -20,6 +20,11 @@ #define PORT(offset) (CKSEG1ADDR(INGENIC_UART_BASE_ADDR) + (4 * offset)) #endif +#ifdef CONFIG_ECONET +#define EN75_UART_BASE 0x1fbf0003 +#define PORT(offset) (CKSEG1ADDR(EN75_UART_BASE) + (4 * (offset))) +#endif + #ifndef IOTYPE #define IOTYPE char #endif diff --git a/arch/mips/boot/dts/Makefile b/arch/mips/boot/dts/Makefile index ff468439a8c4..7375c6ced82b 100644 --- a/arch/mips/boot/dts/Makefile +++ b/arch/mips/boot/dts/Makefile @@ -1,6 +1,7 @@ # SPDX-License-Identifier: GPL-2.0 subdir-$(CONFIG_BMIPS_GENERIC) += brcm subdir-$(CONFIG_CAVIUM_OCTEON_SOC) += cavium-octeon +subdir-$(CONFIG_ECONET) += econet subdir-$(CONFIG_EYEQ) += mobileye subdir-$(CONFIG_FIT_IMAGE_FDT_MARDUK) += img subdir-$(CONFIG_FIT_IMAGE_FDT_BOSTON) += img diff --git a/arch/mips/boot/dts/econet/Makefile b/arch/mips/boot/dts/econet/Makefile new file mode 100644 index 000000000000..524ba10ce750 --- /dev/null +++ b/arch/mips/boot/dts/econet/Makefile @@ -0,0 +1,2 @@ +# SPDX-License-Identifier: GPL-2.0 +dtb-$(CONFIG_SOC_ECONET_EN751221_TEST_IMAGE) += en751221_test_image.dtb diff --git a/arch/mips/boot/dts/econet/en751221.dtsi b/arch/mips/boot/dts/econet/en751221.dtsi new file mode 100644 index 000000000000..e4404aed5705 --- /dev/null +++ b/arch/mips/boot/dts/econet/en751221.dtsi @@ -0,0 +1,62 @@ +// SPDX-License-Identifier: GPL-2.0 +/dts-v1/; + +/ { + compatible = "econet,en751221"; + #address-cells = <1>; + #size-cells = <1>; + + hpt_clock: hpt_clock { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <200000000>; /* 200 MHz */ + }; + + cpus: cpus { + #address-cells = <1>; + #size-cells = <0>; + + cpu@0 { + device_type = "cpu"; + compatible = "mips,mips24KEc"; + reg = <0>; + }; + }; + + cpuintc: interrupt-controller { + #address-cells = <0>; + #interrupt-cells = <1>; + interrupt-controller; + compatible = "mti,cpu-interrupt-controller"; + }; + + intc: interrupt-controller@1fb40000 { + compatible = "econet,en751221-intc"; + reg = <0x1fb40000 0x100>; + interrupt-parent = <&cpuintc>; + interrupts = <2>; + + interrupt-controller; + #interrupt-cells = <1>; + econet,shadow-interrupts = <7 2>, <8 3>, <13 12>, <30 29>; + }; + + uart: serial@1fbf0000 { + compatible = "ns16550"; + reg = <0x1fbf0000 0x30>; + reg-io-width = <4>; + reg-shift = <2>; + interrupt-parent = <&intc>; + interrupts = <0>; + clock-frequency = <1843200>; + }; + + timer_hpt: timer_hpt@1fbf0400 { + compatible = "econet,timer-hpt"; + reg = <0x1fbf0400 0x100>; + + interrupt-parent = <&intc>; + interrupts = <30>; + clocks = <&hpt_clock>; + }; +}; diff --git a/arch/mips/boot/dts/econet/en751221_test_image.dts b/arch/mips/boot/dts/econet/en751221_test_image.dts new file mode 100644 index 000000000000..bc140c4043b2 --- /dev/null +++ b/arch/mips/boot/dts/econet/en751221_test_image.dts @@ -0,0 +1,19 @@ +// SPDX-License-Identifier: GPL-2.0 +/dts-v1/; + +#include "en751221.dtsi" + +/ { + model = "Generic EN751221"; + + memory@0 { + /* We hope at least 64MB will be available wherever we are run */ + device_type = "memory"; + reg = <0x00000000 0x4000000>; + }; + + chosen { + bootargs = "console=ttyS0,115200"; + linux,usable-memory-range = <0x00020000 0x3fe0000>; + }; +}; diff --git a/arch/mips/econet/Kconfig b/arch/mips/econet/Kconfig new file mode 100644 index 000000000000..12f85d638e47 --- /dev/null +++ b/arch/mips/econet/Kconfig @@ -0,0 +1,42 @@ +# SPDX-License-Identifier: GPL-2.0 +if ECONET + +config SOC_ECONET_EN751221 + bool + select COMMON_CLK + select ECONET_EN751221_INTC + select IRQ_MIPS_CPU + select SMP + select SMP_UP + select SYS_SUPPORTS_SMP + +choice + prompt "EcoNet SoC selection" + default SOC_ECONET_EN751221_FAMILY + help + Select EcoNet MIPS SoC type. Individual SoCs within a family are + similar enough that is it enough to select the right family, and + then customize to the specific SoC using the device tree only. + + config SOC_ECONET_EN751221_FAMILY + bool "EN751221 family" + select SOC_ECONET_EN751221 + help + The EN751221 family includes EN7512, RN7513, EN7521, EN7526. + They are based on single core MIPS 34Kc processors. To boot + this kernel, you will need a device tree such as + MIPS_RAW_APPENDED_DTB=y, and a root filesystem. + + config SOC_ECONET_EN751221_TEST_IMAGE + bool "EN751221 test image" + select SOC_ECONET_EN751221 + select BUILTIN_DTB + help + Build a minimal kernel that will boot on any EN751221 board + with at least 64MB of memory. This has a builtin device tree + so it can boot with nothing more than an appended initramfs. + This is good for validating that a given SoC is EN751221 + compatible, or for regression testing. +endchoice + +endif diff --git a/arch/mips/econet/Makefile b/arch/mips/econet/Makefile new file mode 100644 index 000000000000..7e4529e7d3d7 --- /dev/null +++ b/arch/mips/econet/Makefile @@ -0,0 +1,2 @@ + +obj-y := init.o diff --git a/arch/mips/econet/Platform b/arch/mips/econet/Platform new file mode 100644 index 000000000000..bb659876d855 --- /dev/null +++ b/arch/mips/econet/Platform @@ -0,0 +1,5 @@ +# To address a 7.2MB kernel size limit in the EcoNet SDK bootloader, +# we put the load address well above where the bootloader loads and then use +# zboot. So please set CONFIG_ZBOOT_LOAD_ADDRESS to the address where your +# bootloader actually places the kernel. +load-$(CONFIG_ECONET) += 0xffffffff81000000 \ No newline at end of file diff --git a/arch/mips/econet/init.c b/arch/mips/econet/init.c new file mode 100644 index 000000000000..6f43ffb209cb --- /dev/null +++ b/arch/mips/econet/init.c @@ -0,0 +1,78 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * EcoNet setup code + * + * Copyright (C) 2025 Caleb James DeLisle + */ + +#include +#include +#include + +#include +#include +#include +#include +#include +#include +#include + +#define CR_AHB_RSTCR ((void __iomem *)CKSEG1ADDR(0x1fb00040)) +#define RESET BIT(31) + +#define UART_BASE CKSEG1ADDR(0x1fbf0003) +#define UART_REG_SHIFT 2 + +static void hw_reset(char *command) +{ + iowrite32(RESET, CR_AHB_RSTCR); +} + +/* 1. Bring up early printk. */ +void __init prom_init(void) +{ + setup_8250_early_printk_port(UART_BASE, UART_REG_SHIFT, 0); + _machine_restart = hw_reset; +} + +/* 2. Parse the DT and find memory */ +void __init plat_mem_setup(void) +{ + void *dtb; + + set_io_port_base(KSEG1); + + dtb = get_fdt(); + if (!dtb) + panic("no dtb found"); + + __dt_setup_arch(dtb); + + early_init_dt_scan_memory(); +} + +/* 3. Overload __weak device_tree_init(), add SMP_UP ops */ +void __init device_tree_init(void) +{ + unflatten_and_copy_device_tree(); + + register_up_smp_ops(); +} + +const char *get_system_type(void) +{ + return "EcoNet-EN75xx"; +} + +/* 4. Initialize the IRQ subsystem */ +void __init arch_init_irq(void) +{ + irqchip_init(); +} + +/* 5. Timers */ +void __init plat_time_init(void) +{ + of_clk_init(NULL); + timer_probe(); +} From patchwork Fri Mar 21 13:46:33 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Caleb James DeLisle X-Patchwork-Id: 14025469 Received: from mail.cjdns.fr (mail.cjdns.fr [5.135.140.105]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id E7BDD1411EB; Fri, 21 Mar 2025 13:47:10 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=5.135.140.105 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1742564833; cv=none; b=LTI+Dwl4FH9rF5APSRlHlL9lXleBMc+6N7gCR6Ana4RqaMXAKN0D7fb1tjHg7+qR7eVQliaAOhjmOp5grT4ii3wK4AZc6TeGxEbfkTzW9jTjo+zgDNeF4zNS37e3H8g4aDAdPdLVB6r8s0giXMI1SpN/KsQf+50I9WmOxXJYfog= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1742564833; c=relaxed/simple; bh=osWE5O1iRBWe7qclvdbCFGuXogiHJ5z7z7iF7pq+164=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=HKVtpT1CXu0vrph4b8VXWnhma3n5uU9NTwaYlC8KPElseaRnjW14+nEhE3azwqdbv8f878Xf/aDFfvLEnyZ95ylrey9R49KS3VQl4V31c98CT5Fh+PVvOtC07yE81QAdNmwkJmcnx5h6izLj8LwxWazWWM8WoZ5lfeNcqCvxbBY= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=cjdns.fr; spf=none smtp.mailfrom=cjdns.fr; dkim=pass (2048-bit key) header.d=cjdns.fr header.i=@cjdns.fr header.b=bDbDSjid; arc=none smtp.client-ip=5.135.140.105 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=cjdns.fr Authentication-Results: smtp.subspace.kernel.org; spf=none smtp.mailfrom=cjdns.fr Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=cjdns.fr header.i=@cjdns.fr header.b="bDbDSjid" Received: from [127.0.0.1] (localhost [127.0.0.1]) by localhost (Mailerdaemon) with ESMTPSA id 2E4102A46C6; Fri, 21 Mar 2025 14:47:07 +0100 (CET) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=cjdns.fr; s=dkim; t=1742564828; h=from:subject:date:message-id:to:cc:mime-version: content-transfer-encoding:in-reply-to:references; bh=z5J7Cym/+UR5PPjai7DjLogajBOo4PPQLYr4IkBxyls=; b=bDbDSjidark7vzWvNcXyhJXZVQMoElRVrqgZ9PivQUdxt0eUNVeK/A6iaHDnS7H8OSKxBX z1hXCLIlzeROVJdjKj8oLN3PFjhuy5lfVwoJt80ds5jxX9Xpo6t+0x0V74oTQhgQTmC2dc WIfZ4IgWHnYsrjwMASZZT77fNlnhfhE5y0SwY225B1UDI1GdIwckuVGvavO7YqmbJA8Ft/ bnEl0yokZ7TCywI9vQ5fU2wQBYWCnnSfWjXLMfkhfu9LBjFNKb4iwZb0KWEet9dGV9Q9rM FtawgE1r93//SP9bqTdd6GQg+7BeTHfyB0MyI4SMa1YIIuQEM1b+KX+7k+I06g== From: Caleb James DeLisle To: linux-mips@vger.kernel.org Cc: Thomas Gleixner , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Thomas Bogendoerfer , Daniel Lezcano , devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, benjamin.larsson@genexis.eu, Caleb James DeLisle Subject: [PATCH v1 8/8] MAINTAINERS: Add EcoNet MIPS platform entry Date: Fri, 21 Mar 2025 13:46:33 +0000 Message-Id: <20250321134633.2155141-9-cjd@cjdns.fr> In-Reply-To: <20250321134633.2155141-1-cjd@cjdns.fr> References: <20250321134633.2155141-1-cjd@cjdns.fr> Precedence: bulk X-Mailing-List: linux-mips@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-Last-TLS-Session-Version: TLSv1.3 Add a MAINTAINERS entry for the EcoNet EN751221 platform, covering its device tree bindings, platform code, interrupt controller, and timer drivers. Signed-off-by: Caleb James DeLisle --- MAINTAINERS | 12 ++++++++++++ 1 file changed, 12 insertions(+) diff --git a/MAINTAINERS b/MAINTAINERS index efee40ea589f..fcb1c49ee54e 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -8182,6 +8182,18 @@ W: https://linuxtv.org Q: http://patchwork.linuxtv.org/project/linux-media/list/ F: drivers/media/dvb-frontends/ec100* +ECONET MIPS PLATFORM +M: Caleb James DeLisle +S: Maintained +F: Documentation/devicetree/bindings/interrupt-controller/econet,en751221-intc.yaml +F: Documentation/devicetree/bindings/mips/econet.yaml +F: Documentation/devicetree/bindings/timer/econet,timer-hpt.yaml +F: Documentation/devicetree/bindings/vendor-prefixes.yaml +F: arch/mips/boot/dts/econet/ +F: arch/mips/econet/ +F: drivers/clocksource/timer-econet-hpt.c +F: drivers/irqchip/irq-econet-en751221.c + ECRYPT FILE SYSTEM M: Tyler Hicks L: ecryptfs@vger.kernel.org