From patchwork Fri Mar 21 14:53:22 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Svyatoslav Ryhel X-Patchwork-Id: 14025622 X-Patchwork-Delegate: daniel.lezcano@linaro.org Received: from mail-ej1-f54.google.com (mail-ej1-f54.google.com [209.85.218.54]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 04FE01D61A2; Fri, 21 Mar 2025 14:53:51 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.218.54 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1742568833; cv=none; b=XR3T5rtxfvov5J9+NK3D1iuu/MZ0/QXBgX5gTIIr+A6eghiIO93wHbi4rMzNpl05/UHtFWC6f0qzK+wQkMBTligKgEX4uoMb1VMjj9LtYjnnXkdfaPr3rb4iMOWihD/1wx1eO8fMPB6P52PhZ/krZ/sACMxay39j+kO6gRQcl+U= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1742568833; c=relaxed/simple; bh=3Qrlke3rV5UrcVx0LmV4fvmS1VaVNlCzegA6mWn9AFw=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=lajfKn5aUm0WboGRNmFJdZZrcCJA2OHAzXD1nRLFc2fQv0hms0hpo8erk+o4UsmfuwEL3r67c5xnbf6RfhBlBG0egyLTp1nbX3ehXkDzxdwyWLgKLRQ4dL6lE7z8MJD82hq3x7bH9sk6YQDD5UbkYjW/18+hQM0MUtvd+rvb4yY= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com; spf=pass smtp.mailfrom=gmail.com; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b=VDuuQsW6; arc=none smtp.client-ip=209.85.218.54 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=gmail.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="VDuuQsW6" Received: by mail-ej1-f54.google.com with SMTP id a640c23a62f3a-ac2c663a3daso416701066b.2; Fri, 21 Mar 2025 07:53:51 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20230601; t=1742568830; x=1743173630; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=VN46pr8HKLZnZ1CFeU+hmdbKJpGE/eibQxuH2e2XFMg=; b=VDuuQsW6NCNMPwGLYP4XQCk2x2ZkhPTb8hitjF6RCtQONkc2WitZT/IGoKdUwD2lkk I5lq9eRkz2kHnC585tJmjJofyFKhuBhFvBtwHibc5JiHei74nN2z8WbXM3clh55QdFkh pNsEoPayd3zUvkiWzqRbxCBltl/vXkF85Gi+nFHSoylCEk5ZXyyr/WNzJmHYDCWzdDyk jsv5LUdsTVWTEuuhhl1QCB8UoFyVtNeCZypvMm/LpN1wtkSQ3yBkmaP59Ub/64d9hre+ gFfnmKLE/c9Q6cCLFwFtoTBtPkSPwu8RLfRDbys+vTAM/tyGu5KHcRYbzbgOeoIo/mI+ NVUw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1742568830; x=1743173630; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=VN46pr8HKLZnZ1CFeU+hmdbKJpGE/eibQxuH2e2XFMg=; b=jnB5ad0ST701AJUYNwkO3iNAtSmVYp4UIcu513ikTSW34JEDtW8kXffjDWJbYrcXyH lIp9tFkOg7i5aDc2ggusS2d3Yo4qYVUFNGtLmFV+Ve1mtihK6urmzOPMjVqoQ23X6jDD Y078Y9mwlDD3cZNry2q758F3KXlsqxC6J4cqLOkjpT0Z5TEV+b3nJwKvF7F6bzMkSzlx 7bsLkC04zkr4oD3CW3C9xSSj2nhqyx8f22kSMS4D3Gnfl19Kmn0tNN3syYOJXw+NqYNG Wo8NDnqvicdns+jS9TDmUCmCuvANAQpduJhJrRv8xL2/IIlUaJJT7JL8NC/5M+Brn+DV 7qlw== X-Forwarded-Encrypted: i=1; AJvYcCU3M0RnTD7Fn0Y/Ck3wCLBXYXo/GSUz4PrULP2wMhabSfIpaxRWCO1mR0kKkTxzIIFi+WzOhz4zKdGM@vger.kernel.org, AJvYcCX3oztUgxxmrdI4kyA2W57LibQ89VQTcTqwqnJYUeTR9kZgI07Fd66BQgVLTpMxwlItY9iUd1pUs4RFL5vc@vger.kernel.org, AJvYcCXDH5iCp3aFOMu/GpstIAbO7yR8YVTGnmCzt5RqVOafRSuD9bALkD2hSOceHMS+CTbsXR7aShKxNpLdvsw=@vger.kernel.org X-Gm-Message-State: AOJu0YzRs4e2+cncOGkvrODJO6KkFbI3ZBK59/afRp1DLvyic6uXul0s oB5eB9Sv4dHIvN2osraIW3vkBLqvLVR+MSSbhXvjyMxgrjQajmjf X-Gm-Gg: ASbGncsf4hBM6Zn/g6OhZr/V0xqgNSjiMz7sds1erbf5on7eDpmtR4WT/p0h3D53jx5 15gkkjPqAwVYULvYdGsJPmSshJj4kEZz26YQwNI7kwcLWpyZuRFQ3/sD2AWdZaep/DbHI1gehV7 fbzsyLsZiDS7y4qv2EEja+/HjxYu/A4GCCHmi7rEd84FpO7S5lM0LkLFfvyiSLIYBtCv0U74XEv 7ltjDCgccDWL3XlFxqSfLFajuLk7/ZDuWjA0WVVxtDh1MbQ0rXVsSwm61VMUQIHCBEK3ENMMbF4 PzDWbeujSzX6uJ3OrY7rtQzJpa9JZnswDWGv X-Google-Smtp-Source: AGHT+IEUpAHBziOa+1Gni4ODGJ6MsL6ry/sr309JKf9G0utzeEBjsJ0p2oWTJWr/qCyNBupFys24SQ== X-Received: by 2002:a17:907:72c9:b0:ac3:bf36:80eb with SMTP id a640c23a62f3a-ac3f252f83dmr324556766b.48.1742568829910; Fri, 21 Mar 2025 07:53:49 -0700 (PDT) Received: from xeon.. ([188.163.112.51]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-ac3efbe038dsm163224666b.138.2025.03.21.07.53.48 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 21 Mar 2025 07:53:49 -0700 (PDT) From: Svyatoslav Ryhel To: "Rafael J. Wysocki" , Daniel Lezcano , Zhang Rui , Lukasz Luba , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Thierry Reding , Thierry Reding , Jonathan Hunter , Svyatoslav Ryhel Cc: linux-pm@vger.kernel.org, devicetree@vger.kernel.org, linux-tegra@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH v1 1/5] soc: tegra: fuse: add Tegra114 nvmem cells and fuse lookups Date: Fri, 21 Mar 2025 16:53:22 +0200 Message-ID: <20250321145326.113211-2-clamor95@gmail.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250321145326.113211-1-clamor95@gmail.com> References: <20250321145326.113211-1-clamor95@gmail.com> Precedence: bulk X-Mailing-List: linux-pm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Add missing Tegra114 nvmem cells and fuse lookups which were added for Tegra124+ but omitted for Tegra114. Signed-off-by: Svyatoslav Ryhel --- drivers/soc/tegra/fuse/fuse-tegra30.c | 122 ++++++++++++++++++++++++++ 1 file changed, 122 insertions(+) diff --git a/drivers/soc/tegra/fuse/fuse-tegra30.c b/drivers/soc/tegra/fuse/fuse-tegra30.c index eb14e5ff5a0a..a79f83d175d9 100644 --- a/drivers/soc/tegra/fuse/fuse-tegra30.c +++ b/drivers/soc/tegra/fuse/fuse-tegra30.c @@ -117,6 +117,124 @@ const struct tegra_fuse_soc tegra30_fuse_soc = { #endif #ifdef CONFIG_ARCH_TEGRA_114_SOC +static const struct nvmem_cell_info tegra114_fuse_cells[] = { + { + .name = "tsensor-cpu1", + .offset = 0x084, + .bytes = 4, + .bit_offset = 0, + .nbits = 32, + }, { + .name = "tsensor-cpu2", + .offset = 0x088, + .bytes = 4, + .bit_offset = 0, + .nbits = 32, + }, { + .name = "tsensor-common", + .offset = 0x08c, + .bytes = 4, + .bit_offset = 0, + .nbits = 32, + }, { + .name = "tsensor-cpu0", + .offset = 0x098, + .bytes = 4, + .bit_offset = 0, + .nbits = 32, + }, { + .name = "xusb-pad-calibration", + .offset = 0x0f0, + .bytes = 4, + .bit_offset = 0, + .nbits = 32, + }, { + .name = "tsensor-cpu3", + .offset = 0x12c, + .bytes = 4, + .bit_offset = 0, + .nbits = 32, + }, { + .name = "tsensor-gpu", + .offset = 0x154, + .bytes = 4, + .bit_offset = 0, + .nbits = 32, + }, { + .name = "tsensor-mem0", + .offset = 0x158, + .bytes = 4, + .bit_offset = 0, + .nbits = 32, + }, { + .name = "tsensor-mem1", + .offset = 0x15c, + .bytes = 4, + .bit_offset = 0, + .nbits = 32, + }, { + .name = "tsensor-pllx", + .offset = 0x160, + .bytes = 4, + .bit_offset = 0, + .nbits = 32, + }, +}; + +static const struct nvmem_cell_lookup tegra114_fuse_lookups[] = { + { + .nvmem_name = "fuse", + .cell_name = "xusb-pad-calibration", + .dev_id = "7009f000.padctl", + .con_id = "calibration", + }, { + .nvmem_name = "fuse", + .cell_name = "tsensor-common", + .dev_id = "700e2000.thermal-sensor", + .con_id = "common", + }, { + .nvmem_name = "fuse", + .cell_name = "tsensor-cpu0", + .dev_id = "700e2000.thermal-sensor", + .con_id = "cpu0", + }, { + .nvmem_name = "fuse", + .cell_name = "tsensor-cpu1", + .dev_id = "700e2000.thermal-sensor", + .con_id = "cpu1", + }, { + .nvmem_name = "fuse", + .cell_name = "tsensor-cpu2", + .dev_id = "700e2000.thermal-sensor", + .con_id = "cpu2", + }, { + .nvmem_name = "fuse", + .cell_name = "tsensor-cpu3", + .dev_id = "700e2000.thermal-sensor", + .con_id = "cpu3", + }, { + .nvmem_name = "fuse", + .cell_name = "tsensor-mem0", + .dev_id = "700e2000.thermal-sensor", + .con_id = "mem0", + }, { + .nvmem_name = "fuse", + .cell_name = "tsensor-mem1", + .dev_id = "700e2000.thermal-sensor", + .con_id = "mem1", + }, { + .nvmem_name = "fuse", + .cell_name = "tsensor-gpu", + .dev_id = "700e2000.thermal-sensor", + .con_id = "gpu", + }, { + .nvmem_name = "fuse", + .cell_name = "tsensor-pllx", + .dev_id = "700e2000.thermal-sensor", + .con_id = "pllx", + }, +}; + static const struct tegra_fuse_info tegra114_fuse_info = { .read = tegra30_fuse_read, .size = 0x2a0, @@ -127,6 +245,10 @@ const struct tegra_fuse_soc tegra114_fuse_soc = { .init = tegra30_fuse_init, .speedo_init = tegra114_init_speedo_data, .info = &tegra114_fuse_info, + .lookups = tegra114_fuse_lookups, + .num_lookups = ARRAY_SIZE(tegra114_fuse_lookups), + .cells = tegra114_fuse_cells, + .num_cells = ARRAY_SIZE(tegra114_fuse_cells), .soc_attr_group = &tegra_soc_attr_group, .clk_suspend_on = false, }; From patchwork Fri Mar 21 14:53:23 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Svyatoslav Ryhel X-Patchwork-Id: 14025623 X-Patchwork-Delegate: daniel.lezcano@linaro.org Received: from mail-ej1-f54.google.com (mail-ej1-f54.google.com [209.85.218.54]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 326E71DE4C2; Fri, 21 Mar 2025 14:53:52 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.218.54 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1742568835; cv=none; b=i73bOBgpPTh0KAx5/c4Y2quW2V74Mhu+R0QNQWD6xWE+CqbNcjf5qHtl0e3ymmjkk04Xy9VsJeH9JaGIUBU+W4bvM/U2PC/B0ZrjGfQgQCBjVoaAbKZyjqbwaq7BE5I3kz9uEEL4cVO+Hp5dlyB34cCLLeItZUAXEcyjby5O3AA= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1742568835; c=relaxed/simple; bh=2r/XLqMpuRk75VS21Su+p02gUYmY6ZQ8zSCpec3w54s=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=DVs0gWJWkWODOZ6NWEIYvmCWqWEKjI4NIVrERR2b59rs63vBv8XKBVsT8EDNPmsbxSBo3cMlwrdgUgge6/zZvJm9JS5iYwZTjbpAYdnCA90lzoWWbdxfj2k5r0xwO3RMD+NQb6/cUPPut4pbse1oC5AMhmUPVbLQzhr1wlSQTwo= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com; spf=pass smtp.mailfrom=gmail.com; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b=kRGdw87D; arc=none smtp.client-ip=209.85.218.54 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=gmail.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="kRGdw87D" Received: by mail-ej1-f54.google.com with SMTP id a640c23a62f3a-ac289147833so118358666b.2; Fri, 21 Mar 2025 07:53:52 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20230601; t=1742568831; x=1743173631; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=r+v1uOPvAi3S38CktsX9lJnZvb0WY6wb7L0THBmI/Cw=; b=kRGdw87DtPYn2eW5p9LIoQdVcj1gR6nZD3eITwb7TcmsoDkPoIRAsAfCh9lVizBztC p9xWibjmOStmsSebOAOQQBMr5xWqyCPr7mgGaGHeB46za/k+HcKmnkPxKXiJk1ogmZk+ gWWQepj/1yt6YwGhgOeAzSkHKzGc0g/qVMbsAdQAX3gftPCp/8vZv0hrtFhbt1rtOl0Y nnEtfJDbG19Ukze02/4E/r8cfPBzT8heugFIrrI9p7NUdZkd15Aj2UQwhNyUZ766iFEi ka9/MMNNlrNOinF31sxeDDZMl5MXskhiJEXxumh1/Hzkri1C824mkXGbuU6bpbGN0vq1 aIcw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1742568831; x=1743173631; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=r+v1uOPvAi3S38CktsX9lJnZvb0WY6wb7L0THBmI/Cw=; b=Xf+kEORccnNecy4HvhX7AgsRb7pb4IUiPoCMLwTn+CdvmDwQcisnrNeySgVUQBAWzt JTuImplHAWsoVFgtZ+Gsxzh/9pMmaJAVTlETDWDSHL+pxvLF+wUWAqKeLCNx6czgLKnr yYjAlCAW867aVzdcOSpDmN+1DP9FCFpIhQygy4Q7nVV1mNBIgNPAh7nxApGckfkvTUdY RfyY7KwXp5aJlAwuvKJCOeWnjkN8lGSA557rj1l7Vt2/TL/yo7G6cMeTy06w2zLPJ9YF 3Orljzfk/9YYkmHDbFtB9sjHhO/jBSuOZEJJH2NpLOjNvTrGfmav/AcxdaBuPfzByoX/ AZ5Q== X-Forwarded-Encrypted: i=1; AJvYcCUQBvjPxAhcOIr80iR7QIk35xHjLAEX5V/yy/QnsYPHEEmSBeeAOW+jA0xPEQZKaVhUosnz99SeMeBznR4=@vger.kernel.org, AJvYcCVe1JBgdd0PApVX71xqAoOsAj36mJI+JDGabgCkGiKNNjAh6IbwKXkx1cg8kaVGUD3k1g/ZJyQX6+NPuqaP@vger.kernel.org, AJvYcCVlzvbJ0Kxt7epsqyJce3Ag8Zns0dBD6n5CFfyeLiStUnl0zEtDbXmC1sGToEbRpID0/s8GI9KeKs3n@vger.kernel.org X-Gm-Message-State: AOJu0YyWuWdz4cPCmZTFaEbumS4MTSFPn6bMqSp2a9CeUMzNQ8PrfoiC joyiMtqSLASItV3sjrZdJEsfHce7tw58UWo4YCRVOfM+FLXy15kQ X-Gm-Gg: ASbGncvDF1mOVkUamKOgU1fKZSD9dY9+qT/jbw+kR3pGxFeFxyHw4e0935zO/esCNWX L1vb76rw/QndhyTEaN+xPzP6VpqXEkjTrzZAMxka2SggEwWBjXza8H0bHoNJvIcuZS3GV5+r3By l5bKwkndrfHHVEALDhlJvfbiizKdsmLi3L7N7ic+noL9RGxi/2x8dbhDlZYBmoqi+hiUALFyq+C 2NXh5xU02vDGKTkHJs2RDzEnIzDSmQ//dhPOEAUh/4LnglXWR2fYSTmbkoEEQmJ3h9B9vOux8qs YPKkL7x/sYc1JRnDVGYwZ8sLpkw/JTqi9uiI X-Google-Smtp-Source: AGHT+IEiGwGWAmAdFOT8Vz4MAwwffwvMYdqyjjzFqRIp6ititJJ1EOtxUtuKIG95Sv8TRxHDbgFxpw== X-Received: by 2002:a17:906:f59d:b0:ac3:8aaa:406a with SMTP id a640c23a62f3a-ac3f229377cmr366878266b.31.1742568831297; Fri, 21 Mar 2025 07:53:51 -0700 (PDT) Received: from xeon.. ([188.163.112.51]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-ac3efbe038dsm163224666b.138.2025.03.21.07.53.50 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 21 Mar 2025 07:53:50 -0700 (PDT) From: Svyatoslav Ryhel To: "Rafael J. Wysocki" , Daniel Lezcano , Zhang Rui , Lukasz Luba , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Thierry Reding , Thierry Reding , Jonathan Hunter , Svyatoslav Ryhel Cc: linux-pm@vger.kernel.org, devicetree@vger.kernel.org, linux-tegra@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH v1 2/5] dt-bindings: thermal: Document Tegra114 SOCTHERM Thermal Management System Date: Fri, 21 Mar 2025 16:53:23 +0200 Message-ID: <20250321145326.113211-3-clamor95@gmail.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250321145326.113211-1-clamor95@gmail.com> References: <20250321145326.113211-1-clamor95@gmail.com> Precedence: bulk X-Mailing-List: linux-pm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Document SOCTHERM Thermal Management System found in the Tegra 4 SoC. Signed-off-by: Svyatoslav Ryhel Acked-by: Rob Herring (Arm) --- .../devicetree/bindings/thermal/nvidia,tegra124-soctherm.yaml | 2 ++ 1 file changed, 2 insertions(+) diff --git a/Documentation/devicetree/bindings/thermal/nvidia,tegra124-soctherm.yaml b/Documentation/devicetree/bindings/thermal/nvidia,tegra124-soctherm.yaml index 19bb1f324183..2fd493fcca63 100644 --- a/Documentation/devicetree/bindings/thermal/nvidia,tegra124-soctherm.yaml +++ b/Documentation/devicetree/bindings/thermal/nvidia,tegra124-soctherm.yaml @@ -18,6 +18,7 @@ description: The SOCTHERM IP block contains thermal sensors, support for properties: compatible: enum: + - nvidia,tegra114-soctherm - nvidia,tegra124-soctherm - nvidia,tegra132-soctherm - nvidia,tegra210-soctherm @@ -205,6 +206,7 @@ allOf: compatible: contains: enum: + - nvidia,tegra114-soctherm - nvidia,tegra124-soctherm - nvidia,tegra210-soctherm then: From patchwork Fri Mar 21 14:53:24 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Svyatoslav Ryhel X-Patchwork-Id: 14025624 X-Patchwork-Delegate: daniel.lezcano@linaro.org Received: from mail-ed1-f43.google.com (mail-ed1-f43.google.com [209.85.208.43]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id A794D1DE882; Fri, 21 Mar 2025 14:53:54 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.208.43 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1742568836; cv=none; b=tPUWWauEU9WzTLhwRv8RBAPOaWve5DTM28MvmuUUrfPJnWsbaX8Mtp/C/F8Di4NENNQ/WafpaQrbg0td3AcYLOs4/WKM8x1Ehhc3/5UzRCPK+Qlq7z8MhA4wTarRQFGdMeEuryVX+S+Rdaj+uU03vFMR+UmOV7CJyUYkm4xoRyE= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1742568836; c=relaxed/simple; bh=bXozqz1zbgxcW/1dC2QTCWjrRSGB28IIieO7/kJwCZw=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=FD4nt93fbWn78FbHS2MqejxBqitJ/gg5MRn2h4ZftCfJXKr7W6+aflYTG2ZTbFgBrYAOF+6s/wjCnPx5Ff/6aZ2tIsQgPq2hATUANQl8qEAPm0AcVfoALk2ArY+rV/HCPsU02IIOiKkIZuVwHEtOK1GV36IJgYb/grMVoy133YY= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com; spf=pass smtp.mailfrom=gmail.com; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b=kbiyQVug; arc=none smtp.client-ip=209.85.208.43 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=gmail.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="kbiyQVug" Received: by mail-ed1-f43.google.com with SMTP id 4fb4d7f45d1cf-5e5cded3e2eso2956574a12.0; Fri, 21 Mar 2025 07:53:54 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20230601; t=1742568833; x=1743173633; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=ROgyACEQa48lDCk5T9eREvPyJ322tIX1J/JDdpDWQ9Q=; b=kbiyQVugQsQR+R2ASK0GIW3heLIDwcfQ9YC0hsVfEmj5ZSnnklWsI7zxH76Otk6Cyo pLdiLUIX/YagpBm02XUMmwqb1Qng0Y7ZOA+3dvkzs46w7YfSAFBrfSpwaQQYXbEKGnnu Y5bxx5ulo750eq+LebjsGkaHUHU85zx+bszqps/Z8WYkz0mwASdHSQmpplLveW9Y9iUB 7DYnqwbz2wyK3gOnibLdrPnO2IKCL3VJ8PoDg0LRVMaiMvFQVo8569cNiOSwhE6fiC2W zoQEMD/LEn/TD98KFpNESDJoEL2CDUSUf8NJdlw4lhy5q09b8DT9V8WXjvIa3NT1D2AO Zg4A== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1742568833; x=1743173633; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=ROgyACEQa48lDCk5T9eREvPyJ322tIX1J/JDdpDWQ9Q=; b=kvRYsyrZDpFdtpNwXxg/VUxAGNCbuzg4F1k1wDLrzFx4d24MZ6nuC1TbN62wEBDNa5 5+rGqt14CrhP2kikS6ezmLyQnGnatOBokdPU2Ii9RBk8VEIjVfNw3hxQ4LkUKM1MvNGv yt9EveWP4EAHtP1qZ3KX1Bk63t3o0iSm30OBuXdi7T2VJwrFguFzIBJLmFrQMj95WT7L sCFQzm6rRG91zHAfwHzIA4r5josN/WDHUEOBd80x76SJ0SynjwSKPiyGrCrars1xCldJ wDYAzZZp1qQPqms0E09xQWooFAFNma0gYosvic1jarefE+1CeJwD2wqV7JA17k2FBXot +Q8Q== X-Forwarded-Encrypted: i=1; AJvYcCUWJ0mGGjLc2YCL5gb5p8K9+YqaXBlqyrts46eG6Wt0oCRRsN60AUTQDXgL0XZzvzQ03Gayn31pFR77xMwo@vger.kernel.org, AJvYcCW7P/Afwq2Cvs3KUCn1Ch2eQryqCNeE+XXBDGSe7xQQhWMefca1f4zxPb9Pt37nd1eSjKWogQjPgWpYnp8=@vger.kernel.org, AJvYcCXPTaK2bvwF4Aa6SsdzADy9row/ROoHZzPRYEqGz9jbLoszEUcy44bMA2AN0Gb1fdXI4eyl1adX/vHC@vger.kernel.org X-Gm-Message-State: AOJu0YzJuH8fHuzdIpS5hgd1FIxSIjxm3ezUKUghpJP2Gd7Iy8ACuBPh BFi5xUUAZt9myKlkM2u1/dhuSYyasNlMGLsTtkoI9yV6RfLuiTso X-Gm-Gg: ASbGncsntLUD2Nac4nWJgWWe5z34qKyssGaoEHHUyykITHKYf5PIBX6DH1VtCMVc+Me 7YEPUYF3S6ID15oZITDwRMQoirHXD/2c8F6HVlMcFJBApVTSoDzGS9qMyb5Xlhyy2iMPuro+zxe I0GFq2/O//gr65gFEK6MzQGHS6JxJRya11ffBzM48mZgoEmNdNKth+axhmyETQr0UMnxHVfeE36 aGUCm0y+Fs+svpre89hKNNdqIHXQ6cTZLN8W0Di0nVs+Fq+MNdMllXUxv06J1P9s59C6tpjctRo TikEeVT8dxs9HbTui0Vf4aGM8/kecu9UryBJ X-Google-Smtp-Source: AGHT+IF0GxHEx1dybgdsD9nbFWz2jcD0dSzT7hPIH7uUUPWxq4fUeuv43PUsqPceCV34qwOnLnPqLw== X-Received: by 2002:a17:907:86a7:b0:ab7:9df1:e562 with SMTP id a640c23a62f3a-ac3f2534b34mr425692166b.48.1742568832721; Fri, 21 Mar 2025 07:53:52 -0700 (PDT) Received: from xeon.. ([188.163.112.51]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-ac3efbe038dsm163224666b.138.2025.03.21.07.53.51 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 21 Mar 2025 07:53:52 -0700 (PDT) From: Svyatoslav Ryhel To: "Rafael J. Wysocki" , Daniel Lezcano , Zhang Rui , Lukasz Luba , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Thierry Reding , Thierry Reding , Jonathan Hunter , Svyatoslav Ryhel Cc: linux-pm@vger.kernel.org, devicetree@vger.kernel.org, linux-tegra@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH v1 3/5] thermal: tegra: soctherm-fuse: parametrize configuration further Date: Fri, 21 Mar 2025 16:53:24 +0200 Message-ID: <20250321145326.113211-4-clamor95@gmail.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250321145326.113211-1-clamor95@gmail.com> References: <20250321145326.113211-1-clamor95@gmail.com> Precedence: bulk X-Mailing-List: linux-pm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Prepare soctherm fuse calibration for Tegra114 support. Signed-off-by: Svyatoslav Ryhel --- drivers/thermal/tegra/soctherm-fuse.c | 33 ++++++++++++++++------- drivers/thermal/tegra/soctherm.h | 13 ++++++++- drivers/thermal/tegra/tegra124-soctherm.c | 8 ++++++ drivers/thermal/tegra/tegra132-soctherm.c | 8 ++++++ drivers/thermal/tegra/tegra210-soctherm.c | 8 ++++++ 5 files changed, 59 insertions(+), 11 deletions(-) diff --git a/drivers/thermal/tegra/soctherm-fuse.c b/drivers/thermal/tegra/soctherm-fuse.c index 190f95280e0b..3b808c4521b8 100644 --- a/drivers/thermal/tegra/soctherm-fuse.c +++ b/drivers/thermal/tegra/soctherm-fuse.c @@ -9,15 +9,10 @@ #include "soctherm.h" -#define NOMINAL_CALIB_FT 105 -#define NOMINAL_CALIB_CP 25 - #define FUSE_TSENSOR_CALIB_CP_TS_BASE_MASK 0x1fff #define FUSE_TSENSOR_CALIB_FT_TS_BASE_MASK (0x1fff << 13) #define FUSE_TSENSOR_CALIB_FT_TS_BASE_SHIFT 13 -#define FUSE_TSENSOR_COMMON 0x180 - /* * Tegra210: Layout of bits in FUSE_TSENSOR_COMMON: * 3 2 1 0 @@ -44,6 +39,13 @@ * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ * |---------------------------------------------------| SHIFT_CP | * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ + * + * Tegra11x: Layout of bits in FUSE_TSENSOR_COMMON aka FUSE_VSENSOR_CALIB: + * 3 2 1 0 + * 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 + * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ + * | SHFT_FT | BASE_FT | SHIFT_CP | BASE_CP | + * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ */ #define CALIB_COEFFICIENT 1000000LL @@ -77,7 +79,7 @@ int tegra_calc_shared_calib(const struct tegra_soctherm_fuse *tfuse, s32 shifted_cp, shifted_ft; int err; - err = tegra_fuse_readl(FUSE_TSENSOR_COMMON, &val); + err = tegra_fuse_readl(tfuse->fuse_common_reg, &val); if (err) return err; @@ -88,7 +90,7 @@ int tegra_calc_shared_calib(const struct tegra_soctherm_fuse *tfuse, shifted_ft = (val & tfuse->fuse_shift_ft_mask) >> tfuse->fuse_shift_ft_shift; - shifted_ft = sign_extend32(shifted_ft, 4); + shifted_ft = sign_extend32(shifted_ft, tfuse->fuse_shift_ft_bits); if (tfuse->fuse_spare_realignment) { err = tegra_fuse_readl(tfuse->fuse_spare_realignment, &val); @@ -96,10 +98,21 @@ int tegra_calc_shared_calib(const struct tegra_soctherm_fuse *tfuse, return err; } - shifted_cp = sign_extend32(val, 5); + shifted_cp = (val & tfuse->fuse_shift_cp_mask) >> + tfuse->fuse_shift_cp_shift; + shifted_cp = sign_extend32(val, tfuse->fuse_shift_cp_bits); - shared->actual_temp_cp = 2 * NOMINAL_CALIB_CP + shifted_cp; - shared->actual_temp_ft = 2 * NOMINAL_CALIB_FT + shifted_ft; + shared->actual_temp_cp = 2 * tfuse->nominal_calib_cp + shifted_cp; + shared->actual_temp_ft = 2 * tfuse->nominal_calib_ft + shifted_ft; + + /* + * Tegra114 provides fuse thermal corrections in 0.5C while expected + * precision should be 1C + */ + if (tfuse->lower_precision) { + shared->actual_temp_cp /= 2; + shared->actual_temp_ft /= 2; + } return 0; } diff --git a/drivers/thermal/tegra/soctherm.h b/drivers/thermal/tegra/soctherm.h index 70501e73d586..6c0e0cc594a5 100644 --- a/drivers/thermal/tegra/soctherm.h +++ b/drivers/thermal/tegra/soctherm.h @@ -56,6 +56,13 @@ #define SENSOR_TEMP2_MEM_TEMP_MASK (0xffff << 16) #define SENSOR_TEMP2_PLLX_TEMP_MASK 0xffff +#define NOMINAL_CALIB_FT 105 +#define T114X_CALIB_FT 90 +#define NOMINAL_CALIB_CP 25 + +#define FUSE_VSENSOR_CALIB 0x08c +#define FUSE_TSENSOR_COMMON 0x180 + /** * struct tegra_tsensor_group - SOC_THERM sensor group data * @name: short name of the temperature sensor group @@ -109,9 +116,13 @@ struct tsensor_group_thermtrips { struct tegra_soctherm_fuse { u32 fuse_base_cp_mask, fuse_base_cp_shift; + u32 fuse_shift_cp_mask, fuse_shift_cp_shift; u32 fuse_base_ft_mask, fuse_base_ft_shift; u32 fuse_shift_ft_mask, fuse_shift_ft_shift; - u32 fuse_spare_realignment; + u32 fuse_shift_cp_bits, fuse_shift_ft_bits; + u32 fuse_common_reg, fuse_spare_realignment; + u32 nominal_calib_cp, nominal_calib_ft; + bool lower_precision; }; struct tsensor_shared_calib { diff --git a/drivers/thermal/tegra/tegra124-soctherm.c b/drivers/thermal/tegra/tegra124-soctherm.c index 20ad27f4d1a1..dd4dd7e9014d 100644 --- a/drivers/thermal/tegra/tegra124-soctherm.c +++ b/drivers/thermal/tegra/tegra124-soctherm.c @@ -200,11 +200,19 @@ static const struct tegra_tsensor tegra124_tsensors[] = { static const struct tegra_soctherm_fuse tegra124_soctherm_fuse = { .fuse_base_cp_mask = 0x3ff, .fuse_base_cp_shift = 0, + .fuse_shift_cp_mask = 0x1f, + .fuse_shift_cp_shift = 0, .fuse_base_ft_mask = 0x7ff << 10, .fuse_base_ft_shift = 10, .fuse_shift_ft_mask = 0x1f << 21, .fuse_shift_ft_shift = 21, + .fuse_shift_cp_bits = 5, + .fuse_shift_ft_bits = 4, + .fuse_common_reg = FUSE_TSENSOR_COMMON, .fuse_spare_realignment = 0x1fc, + .nominal_calib_cp = NOMINAL_CALIB_CP, + .nominal_calib_ft = NOMINAL_CALIB_FT, + .lower_precision = false, }; const struct tegra_soctherm_soc tegra124_soctherm = { diff --git a/drivers/thermal/tegra/tegra132-soctherm.c b/drivers/thermal/tegra/tegra132-soctherm.c index b76308fdad9e..926836426688 100644 --- a/drivers/thermal/tegra/tegra132-soctherm.c +++ b/drivers/thermal/tegra/tegra132-soctherm.c @@ -200,11 +200,19 @@ static struct tegra_tsensor tegra132_tsensors[] = { static const struct tegra_soctherm_fuse tegra132_soctherm_fuse = { .fuse_base_cp_mask = 0x3ff, .fuse_base_cp_shift = 0, + .fuse_shift_cp_mask = 0x1f, + .fuse_shift_cp_shift = 0, .fuse_base_ft_mask = 0x7ff << 10, .fuse_base_ft_shift = 10, .fuse_shift_ft_mask = 0x1f << 21, .fuse_shift_ft_shift = 21, + .fuse_shift_cp_bits = 5, + .fuse_shift_ft_bits = 4, + .fuse_common_reg = FUSE_TSENSOR_COMMON, .fuse_spare_realignment = 0x1fc, + .nominal_calib_cp = NOMINAL_CALIB_CP, + .nominal_calib_ft = NOMINAL_CALIB_FT, + .lower_precision = false, }; const struct tegra_soctherm_soc tegra132_soctherm = { diff --git a/drivers/thermal/tegra/tegra210-soctherm.c b/drivers/thermal/tegra/tegra210-soctherm.c index d0ff793f18c5..2877a7b43f2a 100644 --- a/drivers/thermal/tegra/tegra210-soctherm.c +++ b/drivers/thermal/tegra/tegra210-soctherm.c @@ -201,11 +201,19 @@ static const struct tegra_tsensor tegra210_tsensors[] = { static const struct tegra_soctherm_fuse tegra210_soctherm_fuse = { .fuse_base_cp_mask = 0x3ff << 11, .fuse_base_cp_shift = 11, + .fuse_shift_cp_mask = 0x1f, + .fuse_shift_cp_shift = 0, .fuse_base_ft_mask = 0x7ff << 21, .fuse_base_ft_shift = 21, .fuse_shift_ft_mask = 0x1f << 6, .fuse_shift_ft_shift = 6, + .fuse_shift_cp_bits = 5, + .fuse_shift_ft_bits = 4, + .fuse_common_reg = FUSE_TSENSOR_COMMON, .fuse_spare_realignment = 0, + .nominal_calib_cp = NOMINAL_CALIB_CP, + .nominal_calib_ft = NOMINAL_CALIB_FT, + .lower_precision = false, }; static struct tsensor_group_thermtrips tegra210_tsensor_thermtrips[] = { From patchwork Fri Mar 21 14:53:25 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Svyatoslav Ryhel X-Patchwork-Id: 14025625 X-Patchwork-Delegate: daniel.lezcano@linaro.org Received: from mail-ej1-f54.google.com (mail-ej1-f54.google.com [209.85.218.54]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 173BF1E47CC; Fri, 21 Mar 2025 14:53:55 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.218.54 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1742568838; cv=none; b=IcUwXbBsq2HTefrhbOJFuFGTX8LLL28kgHv5CvcUpBvbJwcBTseHp9lERMBIs2hH0TKJlhlUcJjm1DsOpjRO915ebuL1lQ6GpX2HMTG+AQ2ZmPLqmM0f95aTI69V/OsbIhjMJpx5JeXJlf0rdTtGOGg53q14IpiAVsTmwrv31MA= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1742568838; c=relaxed/simple; bh=2FLoquHqkq95j+BTbbuoOmsirAu6SJ/x5gWiBCwV75s=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=pIZK/KymPtiuylzVpGhJmd7nriA31aj2BeasuvQcWDEujzprf88PiXJNAAafK0k4+ha1pTYaU8QIJTiU4LAuzowZ0HYHO8PAkB0LOhZBOiU4lZwveJNW4lE1sLHytssc8PFoupTYzaL+egBD9dA6rp5fJj5oAn2EdOJf++Swld4= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com; spf=pass smtp.mailfrom=gmail.com; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b=TTXm30RO; arc=none smtp.client-ip=209.85.218.54 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=gmail.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="TTXm30RO" Received: by mail-ej1-f54.google.com with SMTP id a640c23a62f3a-ac2bb7ca40bso455490666b.3; Fri, 21 Mar 2025 07:53:55 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20230601; t=1742568834; x=1743173634; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=AWzJ96XhJyfSEt2rZUbqK0RHcX7x8UDPEhWBIKTUabE=; b=TTXm30ROLP3EJbER0hSUQekJ5FuUCAm9O6sNhV5Lx47ndllFsqpisTVvnwLRgN6Jgc Va7S1PgT5bjJ9nBTG2FpRXHjwxueuW2FbAnbJeHTI4/ApdLrfVKP+ui6eX8BMlFGn5/+ 0bBacbYaAooo5NKva3QolH2HvmBFKTjuPdgQwTpRoZEg3f5ONxPpIMaZYZsqxl6NN0o8 4RXxucml3cTT4Kev3rcuCOSQQ4shWmNv5j4sAi3p7b5m87JrjOrxG0TRUaDLNjKUkNZT wkKkjOQujdUm3+tZ9HxgMW5PlzxlYyR7ZKVc3AsdsypXp4dcaHwN7iVabDtMOjt8TLve uv8g== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1742568834; x=1743173634; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=AWzJ96XhJyfSEt2rZUbqK0RHcX7x8UDPEhWBIKTUabE=; b=TSXU0sJ8ZYKwbsmTuaJPEnUUymEeSITDiIoRjcf9raq0EQKBYtf3Tl2zHDxKXZktJ7 aJGSD6yn6cewgHUA3O8EOrjsba8dea5/lWvQGteDG5iG6jx+UjqeaQjqMCtnX9Yw1WfQ of9aFag3Wk6XcAHWQHu8edxaXkPL62qwFs7ElExiK++X14pyu0d//WqfcwopxVQPsYzH mgWs28p8qHDL8WEnpUfssRxRMagMXJxydZZoZ8bISW8cSQrTSdMLDzu1GOo9rvLf6734 zU7yY8EZdi4RfGf5Y+kIm1qXAhq01jxp65Is3IBLFPu5bnBkoOBX5FEmZYNeDcaM67Od BA2A== X-Forwarded-Encrypted: i=1; AJvYcCUq4XscQF/zqzj2axPjepDa9RL3AePmW4QDEXTTucH7zGjHxs/i4UAn4g/o4y0MKPhc3GQgteVL/irs@vger.kernel.org, AJvYcCWduP3a1ak/8QtSBy0IbR9mAJOHE+/wn+2n9L4860A2tdj2BgBOPWgawL08JDabTPNrSn58xhoy9iR3gunw@vger.kernel.org, AJvYcCXCkF0BnFuu4RFoLPNWnu2O228jHXlHqgEWDofYB7DptxKj4T7kskjbnMEK3xbXCHve8vVGwPEV94eBUQU=@vger.kernel.org X-Gm-Message-State: AOJu0Yw4gVMD2ZYcKD8dTxZ4NRNes3r01FGCP7dwyUxlgDUKypM4u7FP O9AiNEj4urzzPd/5w7Pbb2w1NvABA+bqCuKvZGgDIn2ReJge2OWO X-Gm-Gg: ASbGncvrMmZmJ0qAImLDtcMHIwbulQNXfnN3yF5sJA/dNrYPbZ17hzaoW5Jd7S8QnXg /O68O2LnxxXKlUl2nbxQaI5VyvMSRR3fWyaatBjaydy+FLYILtC9OdQW1V8sTsXc8LhDeELoT6Y sRWxXpPYh6LhDFXrlCf9YVQoo67DSBlC5YkxfmfTfEcZHhQ4ew5kE/5QprOcZTx2rlcYj6hKvfD 6x78Ba5IOAZfOSEVnWho3xfPhsI3KBUuvHGdoyxhA1dKUg0d8igfuwZoMzCvLbHn/4PC0RS0BD9 1mOrAu47WGRqqJuHzbF6p0efOkkn3Il3uH7t X-Google-Smtp-Source: AGHT+IGvDqpGgtceIfeAeqB5ZtatDYIz2iQuH7UnIToWNO8bF88kEkOM8yDIRQ4SI/yoMWRi41gcyw== X-Received: by 2002:a17:906:c109:b0:ac2:49de:45c1 with SMTP id a640c23a62f3a-ac3f257dd1amr395095366b.50.1742568834074; Fri, 21 Mar 2025 07:53:54 -0700 (PDT) Received: from xeon.. ([188.163.112.51]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-ac3efbe038dsm163224666b.138.2025.03.21.07.53.52 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 21 Mar 2025 07:53:53 -0700 (PDT) From: Svyatoslav Ryhel To: "Rafael J. Wysocki" , Daniel Lezcano , Zhang Rui , Lukasz Luba , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Thierry Reding , Thierry Reding , Jonathan Hunter , Svyatoslav Ryhel Cc: linux-pm@vger.kernel.org, devicetree@vger.kernel.org, linux-tegra@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH v1 4/5] thermal: tegra: add Tegra114 specific SOCTHERM driver Date: Fri, 21 Mar 2025 16:53:25 +0200 Message-ID: <20250321145326.113211-5-clamor95@gmail.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250321145326.113211-1-clamor95@gmail.com> References: <20250321145326.113211-1-clamor95@gmail.com> Precedence: bulk X-Mailing-List: linux-pm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Add Tegra114 specific SOCTHERM driver. Signed-off-by: Svyatoslav Ryhel --- drivers/thermal/tegra/Makefile | 1 + drivers/thermal/tegra/soctherm.c | 6 + drivers/thermal/tegra/soctherm.h | 4 + drivers/thermal/tegra/tegra114-soctherm.c | 213 ++++++++++++++++++++++ 4 files changed, 224 insertions(+) create mode 100644 drivers/thermal/tegra/tegra114-soctherm.c diff --git a/drivers/thermal/tegra/Makefile b/drivers/thermal/tegra/Makefile index eb27d194c583..9b3e91f7fb97 100644 --- a/drivers/thermal/tegra/Makefile +++ b/drivers/thermal/tegra/Makefile @@ -4,6 +4,7 @@ obj-$(CONFIG_TEGRA_BPMP_THERMAL) += tegra-bpmp-thermal.o obj-$(CONFIG_TEGRA30_TSENSOR) += tegra30-tsensor.o tegra-soctherm-y := soctherm.o soctherm-fuse.o +tegra-soctherm-$(CONFIG_ARCH_TEGRA_114_SOC) += tegra114-soctherm.o tegra-soctherm-$(CONFIG_ARCH_TEGRA_124_SOC) += tegra124-soctherm.o tegra-soctherm-$(CONFIG_ARCH_TEGRA_132_SOC) += tegra132-soctherm.o tegra-soctherm-$(CONFIG_ARCH_TEGRA_210_SOC) += tegra210-soctherm.o diff --git a/drivers/thermal/tegra/soctherm.c b/drivers/thermal/tegra/soctherm.c index a023c948afbd..78da82dc3b53 100644 --- a/drivers/thermal/tegra/soctherm.c +++ b/drivers/thermal/tegra/soctherm.c @@ -2049,6 +2049,12 @@ static void soctherm_init(struct platform_device *pdev) } static const struct of_device_id tegra_soctherm_of_match[] = { +#ifdef CONFIG_ARCH_TEGRA_114_SOC + { + .compatible = "nvidia,tegra114-soctherm", + .data = &tegra114_soctherm, + }, +#endif #ifdef CONFIG_ARCH_TEGRA_124_SOC { .compatible = "nvidia,tegra124-soctherm", diff --git a/drivers/thermal/tegra/soctherm.h b/drivers/thermal/tegra/soctherm.h index 6c0e0cc594a5..75ee2a520886 100644 --- a/drivers/thermal/tegra/soctherm.h +++ b/drivers/thermal/tegra/soctherm.h @@ -148,6 +148,10 @@ int tegra_calc_tsensor_calib(const struct tegra_tsensor *sensor, const struct tsensor_shared_calib *shared, u32 *calib); +#ifdef CONFIG_ARCH_TEGRA_114_SOC +extern const struct tegra_soctherm_soc tegra114_soctherm; +#endif + #ifdef CONFIG_ARCH_TEGRA_124_SOC extern const struct tegra_soctherm_soc tegra124_soctherm; #endif diff --git a/drivers/thermal/tegra/tegra114-soctherm.c b/drivers/thermal/tegra/tegra114-soctherm.c new file mode 100644 index 000000000000..eca65ec6f8c1 --- /dev/null +++ b/drivers/thermal/tegra/tegra114-soctherm.c @@ -0,0 +1,213 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (c) 2014-2018, NVIDIA CORPORATION. All rights reserved. + * Copyright (c) 2024, Svyatoslav Ryhel + */ + +#include +#include + +#include + +#include "soctherm.h" + +#define TEGRA114_THERMTRIP_ANY_EN_MASK (0x1 << 28) +#define TEGRA114_THERMTRIP_MEM_EN_MASK (0x1 << 27) +#define TEGRA114_THERMTRIP_GPU_EN_MASK (0x1 << 26) +#define TEGRA114_THERMTRIP_CPU_EN_MASK (0x1 << 25) +#define TEGRA114_THERMTRIP_TSENSE_EN_MASK (0x1 << 24) +#define TEGRA114_THERMTRIP_GPUMEM_THRESH_MASK (0xff << 16) +#define TEGRA114_THERMTRIP_CPU_THRESH_MASK (0xff << 8) +#define TEGRA114_THERMTRIP_TSENSE_THRESH_MASK 0xff + +#define TEGRA114_THERMCTL_LVL0_UP_THRESH_MASK (0xff << 17) +#define TEGRA114_THERMCTL_LVL0_DN_THRESH_MASK (0xff << 9) + +#define TEGRA114_THRESH_GRAIN 1000 +#define TEGRA114_BPTT 8 + +static const struct tegra_tsensor_configuration tegra114_tsensor_config = { + .tall = 16300, + .tiddq_en = 1, + .ten_count = 1, + .tsample = 163, + .tsample_ate = 655, +}; + +static const struct tegra_tsensor_group tegra114_tsensor_group_cpu = { + .id = TEGRA124_SOCTHERM_SENSOR_CPU, + .name = "cpu", + .sensor_temp_offset = SENSOR_TEMP1, + .sensor_temp_mask = SENSOR_TEMP1_CPU_TEMP_MASK, + .pdiv = 10, + .pdiv_ate = 10, + .pdiv_mask = SENSOR_PDIV_CPU_MASK, + .pllx_hotspot_diff = 10, + .pllx_hotspot_mask = SENSOR_HOTSPOT_CPU_MASK, + .thermtrip_any_en_mask = TEGRA114_THERMTRIP_ANY_EN_MASK, + .thermtrip_enable_mask = TEGRA114_THERMTRIP_CPU_EN_MASK, + .thermtrip_threshold_mask = TEGRA114_THERMTRIP_CPU_THRESH_MASK, + .thermctl_isr_mask = THERM_IRQ_CPU_MASK, + .thermctl_lvl0_offset = THERMCTL_LEVEL0_GROUP_CPU, + .thermctl_lvl0_up_thresh_mask = TEGRA114_THERMCTL_LVL0_UP_THRESH_MASK, + .thermctl_lvl0_dn_thresh_mask = TEGRA114_THERMCTL_LVL0_DN_THRESH_MASK, +}; + +static const struct tegra_tsensor_group tegra114_tsensor_group_gpu = { + .id = TEGRA124_SOCTHERM_SENSOR_GPU, + .name = "gpu", + .sensor_temp_offset = SENSOR_TEMP1, + .sensor_temp_mask = SENSOR_TEMP1_GPU_TEMP_MASK, + .pdiv = 10, + .pdiv_ate = 10, + .pdiv_mask = SENSOR_PDIV_GPU_MASK, + .pllx_hotspot_diff = 5, + .pllx_hotspot_mask = SENSOR_HOTSPOT_GPU_MASK, + .thermtrip_any_en_mask = TEGRA114_THERMTRIP_ANY_EN_MASK, + .thermtrip_enable_mask = TEGRA114_THERMTRIP_GPU_EN_MASK, + .thermtrip_threshold_mask = TEGRA114_THERMTRIP_GPUMEM_THRESH_MASK, + .thermctl_isr_mask = THERM_IRQ_GPU_MASK, + .thermctl_lvl0_offset = THERMCTL_LEVEL0_GROUP_GPU, + .thermctl_lvl0_up_thresh_mask = TEGRA114_THERMCTL_LVL0_UP_THRESH_MASK, + .thermctl_lvl0_dn_thresh_mask = TEGRA114_THERMCTL_LVL0_DN_THRESH_MASK, +}; + +static const struct tegra_tsensor_group tegra114_tsensor_group_pll = { + .id = TEGRA124_SOCTHERM_SENSOR_PLLX, + .name = "pll", + .sensor_temp_offset = SENSOR_TEMP2, + .sensor_temp_mask = SENSOR_TEMP2_PLLX_TEMP_MASK, + .pdiv = 10, + .pdiv_ate = 10, + .pdiv_mask = SENSOR_PDIV_PLLX_MASK, + .thermtrip_any_en_mask = TEGRA114_THERMTRIP_ANY_EN_MASK, + .thermtrip_enable_mask = TEGRA114_THERMTRIP_TSENSE_EN_MASK, + .thermtrip_threshold_mask = TEGRA114_THERMTRIP_TSENSE_THRESH_MASK, + .thermctl_isr_mask = THERM_IRQ_TSENSE_MASK, + .thermctl_lvl0_offset = THERMCTL_LEVEL0_GROUP_TSENSE, + .thermctl_lvl0_up_thresh_mask = TEGRA114_THERMCTL_LVL0_UP_THRESH_MASK, + .thermctl_lvl0_dn_thresh_mask = TEGRA114_THERMCTL_LVL0_DN_THRESH_MASK, +}; + +static const struct tegra_tsensor_group tegra114_tsensor_group_mem = { + .id = TEGRA124_SOCTHERM_SENSOR_MEM, + .name = "mem", + .sensor_temp_offset = SENSOR_TEMP2, + .sensor_temp_mask = SENSOR_TEMP2_MEM_TEMP_MASK, + .pdiv = 10, + .pdiv_ate = 10, + .pdiv_mask = SENSOR_PDIV_MEM_MASK, + .pllx_hotspot_diff = 0, + .pllx_hotspot_mask = SENSOR_HOTSPOT_MEM_MASK, + .thermtrip_any_en_mask = TEGRA114_THERMTRIP_ANY_EN_MASK, + .thermtrip_enable_mask = TEGRA114_THERMTRIP_MEM_EN_MASK, + .thermtrip_threshold_mask = TEGRA114_THERMTRIP_GPUMEM_THRESH_MASK, + .thermctl_isr_mask = THERM_IRQ_MEM_MASK, + .thermctl_lvl0_offset = THERMCTL_LEVEL0_GROUP_MEM, + .thermctl_lvl0_up_thresh_mask = TEGRA114_THERMCTL_LVL0_UP_THRESH_MASK, + .thermctl_lvl0_dn_thresh_mask = TEGRA114_THERMCTL_LVL0_DN_THRESH_MASK, +}; + +static const struct tegra_tsensor_group *tegra114_tsensor_groups[] = { + &tegra114_tsensor_group_cpu, + &tegra114_tsensor_group_gpu, + &tegra114_tsensor_group_pll, + &tegra114_tsensor_group_mem, +}; + +static const struct tegra_tsensor tegra114_tsensors[] = { + { + .name = "cpu0", + .base = 0xc0, + .config = &tegra114_tsensor_config, + .calib_fuse_offset = 0x098, + .fuse_corr_alpha = 1196400, + .fuse_corr_beta = -13600000, + .group = &tegra114_tsensor_group_cpu, + }, { + .name = "cpu1", + .base = 0xe0, + .config = &tegra114_tsensor_config, + .calib_fuse_offset = 0x084, + .fuse_corr_alpha = 1196400, + .fuse_corr_beta = -13600000, + .group = &tegra114_tsensor_group_cpu, + }, { + .name = "cpu2", + .base = 0x100, + .config = &tegra114_tsensor_config, + .calib_fuse_offset = 0x088, + .fuse_corr_alpha = 1196400, + .fuse_corr_beta = -13600000, + .group = &tegra114_tsensor_group_cpu, + }, { + .name = "cpu3", + .base = 0x120, + .config = &tegra114_tsensor_config, + .calib_fuse_offset = 0x12c, + .fuse_corr_alpha = 1196400, + .fuse_corr_beta = -13600000, + .group = &tegra114_tsensor_group_cpu, + }, { + .name = "mem0", + .base = 0x140, + .config = &tegra114_tsensor_config, + .calib_fuse_offset = 0x158, + .fuse_corr_alpha = 1000000, + .fuse_corr_beta = 0, + .group = &tegra114_tsensor_group_mem, + }, { + .name = "mem1", + .base = 0x160, + .config = &tegra114_tsensor_config, + .calib_fuse_offset = 0x15c, + .fuse_corr_alpha = 1000000, + .fuse_corr_beta = 0, + .group = &tegra114_tsensor_group_mem, + }, { + .name = "gpu", + .base = 0x180, + .config = &tegra114_tsensor_config, + .calib_fuse_offset = 0x154, + .fuse_corr_alpha = 1124500, + .fuse_corr_beta = -9793100, + .group = &tegra114_tsensor_group_gpu, + }, { + .name = "pllx", + .base = 0x1a0, + .config = &tegra114_tsensor_config, + .calib_fuse_offset = 0x160, + .fuse_corr_alpha = 1224200, + .fuse_corr_beta = -14665000, + .group = &tegra114_tsensor_group_pll, + }, +}; + +static const struct tegra_soctherm_fuse tegra114_soctherm_fuse = { + .fuse_base_cp_mask = 0x3ff, + .fuse_base_cp_shift = 0, + .fuse_shift_cp_mask = 0x3f << 10, + .fuse_shift_cp_shift = 10, + .fuse_base_ft_mask = 0x7ff << 16, + .fuse_base_ft_shift = 16, + .fuse_shift_ft_mask = 0x1f << 27, + .fuse_shift_ft_shift = 27, + .fuse_shift_cp_bits = 6, + .fuse_shift_ft_bits = 5, + .fuse_common_reg = FUSE_VSENSOR_CALIB, + .fuse_spare_realignment = 0, + .nominal_calib_cp = NOMINAL_CALIB_CP, + .nominal_calib_ft = T114X_CALIB_FT, + .lower_precision = true, +}; + +const struct tegra_soctherm_soc tegra114_soctherm = { + .tsensors = tegra114_tsensors, + .num_tsensors = ARRAY_SIZE(tegra114_tsensors), + .ttgs = tegra114_tsensor_groups, + .num_ttgs = ARRAY_SIZE(tegra114_tsensor_groups), + .tfuse = &tegra114_soctherm_fuse, + .thresh_grain = TEGRA114_THRESH_GRAIN, + .bptt = TEGRA114_BPTT, + .use_ccroc = false, +}; From patchwork Fri Mar 21 14:53:26 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Svyatoslav Ryhel X-Patchwork-Id: 14025626 X-Patchwork-Delegate: daniel.lezcano@linaro.org Received: from mail-ed1-f49.google.com (mail-ed1-f49.google.com [209.85.208.49]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 6428D22423F; Fri, 21 Mar 2025 14:53:57 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.208.49 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1742568839; cv=none; b=bjcq0+BzkeapPAYn8Lvrp/tL4k4wqjvaRd+0++roO38/vtAV4OARRJMgjCBrgpkVPepgcUmdvHBZxSRH4YmhIRryjVkuaZI5+XBbi1lhZ3jxIHXBcBFwRWugONmNzIaKKglXQbQM4OLNrQzcIrGqfplxdX08zlsEYsMh9gbk+Is= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1742568839; c=relaxed/simple; bh=LAZXLdh33TVoWxNdnrnsbyHRdRcyvTKSeX7w1LJ/e7I=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=HPC1JiIU5xcZmPKvD01ua6zeHd8/T6x6UfKtZwisoWDAisFAiAAGMajvIC9Ft4bEpS+Izzbp97bSA8twtOTUhYuv5BUWtCf2s742UcEqJO1KnGCW5hnhN3zzO3n79Zb0FDsgyRIqaXDpuMmesS9h4NCAuxeyin9EPFjHz+zOfls= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com; spf=pass smtp.mailfrom=gmail.com; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b=S3fFdsKb; arc=none smtp.client-ip=209.85.208.49 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=gmail.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="S3fFdsKb" Received: by mail-ed1-f49.google.com with SMTP id 4fb4d7f45d1cf-5e5c7d6b96fso3667220a12.3; Fri, 21 Mar 2025 07:53:57 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20230601; t=1742568836; x=1743173636; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=Fe2kbPTwvVNBxhNjMkTSBSLSKQIjeOhcHFESCXzkbkM=; b=S3fFdsKb5+9cwotDpPcW2IDeXckPWErw2yG7UrdUMxF5+uVPgz6OGocN7uDU7LZCrL GFglHLJILT29eQn1v6C2MuvTjwf78XrN8aE6Ebl/rkhAydkOPBjTp1MJPZGnSTHb9psJ B45zEk8JEf2qp+lccJrFVleoXD3RPQGgM89kc+QlXHmNdCgP6LooBTknAm6VlDLopA2n Lht8r/TFWB/on+ZqNYIDcDs4eHC0Tpz52/p/f3+vK8sd8W1U+dOFSXZyot2liDo0sLin KlPO7gPNlJ8+qOsrD9+i0iLkNXo8RkPODtg0KTnYPAfyuwhf4eM8ejFXqAHr5pHUdqHV W6og== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1742568836; x=1743173636; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=Fe2kbPTwvVNBxhNjMkTSBSLSKQIjeOhcHFESCXzkbkM=; b=bLY0oon9WSnxfWW/2HAtXFdbTz56oT18gz/0OlIGL0CkPe1Yz4xxcpFHY/KlWmPM9D ITG3WAkpP36RHSIh9Oa8U50O8raJRW1HMA9re3yCE6YyCCMw9v46LYE6Cb0wgKqOZPRz p1WVuCa/7hntRnCnFBawf7Ge8uf7WtcaCbVCP4vjWvHH6I0BuxMkRxVJCFZuUilFAag8 XNajn6UK1KFyMrSOtLHZpkKtDLYNVLnJpNR+Xv0lSYPfaitg+mPD9wuhhb/al3nCjTWj QRZXHx9ezimPrprb941ZJhn5xlrPMJ2VcufM9rRz0NuR4J6j/YciYkM13ZsRjA53Jre2 Q2RA== X-Forwarded-Encrypted: i=1; AJvYcCUqmPmv+YuAWlid1mqO+iC+wq8z1ijHcDM6vydTKWz2pX6cet9ctyDe3fojdhZ6CNZRbgYDd337HUIHNBM=@vger.kernel.org, AJvYcCVsKVxQE1Sru8rPFHTidTdKnsRaPHo5ttNd+1hnhfOeGJZ+uNXMw1hKAMajztov4ak3vrnv1kNuGAVa@vger.kernel.org, AJvYcCXdymBKluVesqLNcOppbz28hvZ6/n6ZirHnIXZDOZQcDSSGuBoV94G7qce4puMqyb+4u+DF8WJqAD7LUZok@vger.kernel.org X-Gm-Message-State: AOJu0YxsBm1U/nbch+f+qj4lt8H0cGJ9lYJmhU+fzwlBtLGpi8d4EfB4 iBBR6eZBHOJ2k6Qicm/LappJ5zqgJecsxDDJDxgS9+f+Fsu/13GZ X-Gm-Gg: ASbGncs8B/i/3054Zx/o4T5fBqk3v+U+Csz8Q5gjkAXsoajLGqFSull60WmkyBr4YOy AzGQFTBd8+ZRaFD8HZx8w4DNNORVFMJptsDE6CrrulMMMlD+zZZ/psezQbTvMvM7F+Xkyp5plYN vslmFYz6JRAmpY5Qnf/NsdBKBs9REiEYD6ZAD+n61VO1Uaopjh78g78htFjoisfUl2U/3tQvjIX OrQkUF9DRLcUlt2b/u1kQa50eVz1N1fMkEOp5Lxkn3qaoV571HPQINR3+xvxjmXh/JrAt67lwYS PneXPK8x4LXmpZezRoZJI5rSvPACjq0bLMap X-Google-Smtp-Source: AGHT+IEUbbaGuykcwI2+6K7THB2Xr1pAs3mKKDYroo/RmpQx3kMBZkIbx7+47szKzFfZODxKlY7kvQ== X-Received: by 2002:a17:907:2d20:b0:ac2:af42:4719 with SMTP id a640c23a62f3a-ac3f226e059mr307664166b.21.1742568835416; Fri, 21 Mar 2025 07:53:55 -0700 (PDT) Received: from xeon.. ([188.163.112.51]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-ac3efbe038dsm163224666b.138.2025.03.21.07.53.54 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 21 Mar 2025 07:53:55 -0700 (PDT) From: Svyatoslav Ryhel To: "Rafael J. Wysocki" , Daniel Lezcano , Zhang Rui , Lukasz Luba , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Thierry Reding , Thierry Reding , Jonathan Hunter , Svyatoslav Ryhel Cc: linux-pm@vger.kernel.org, devicetree@vger.kernel.org, linux-tegra@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH v1 5/5] ARM: tegra: Add SOCTHERM support on Tegra114 Date: Fri, 21 Mar 2025 16:53:26 +0200 Message-ID: <20250321145326.113211-6-clamor95@gmail.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250321145326.113211-1-clamor95@gmail.com> References: <20250321145326.113211-1-clamor95@gmail.com> Precedence: bulk X-Mailing-List: linux-pm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Add SOCTHERM and thermal zones nodes into common Tegra 4 device tree. Signed-off-by: Svyatoslav Ryhel --- arch/arm/boot/dts/nvidia/tegra114.dtsi | 204 +++++++++++++++++++++++++ 1 file changed, 204 insertions(+) diff --git a/arch/arm/boot/dts/nvidia/tegra114.dtsi b/arch/arm/boot/dts/nvidia/tegra114.dtsi index d95c1f99731e..7a4c5da76080 100644 --- a/arch/arm/boot/dts/nvidia/tegra114.dtsi +++ b/arch/arm/boot/dts/nvidia/tegra114.dtsi @@ -5,6 +5,7 @@ #include #include #include +#include #include #include "tegra114-peripherals-opp.dtsi" @@ -263,6 +264,7 @@ actmon: actmon@6000c800 { operating-points-v2 = <&emc_bw_dfs_opp_table>; interconnects = <&mc TEGRA114_MC_MPCORER &emc>; interconnect-names = "cpu-read"; + #cooling-cells = <2>; }; gpio: gpio@6000d000 { @@ -711,6 +713,48 @@ mipi: mipi@700e3000 { #nvidia,mipi-calibrate-cells = <1>; }; + soctherm: thermal-sensor@700e2000 { + compatible = "nvidia,tegra114-soctherm"; + reg = <0x700e2000 0x600>, /* SOC_THERM reg_base */ + <0x60006000 0x400>; /* CAR reg_base */ + reg-names = "soctherm-reg", "car-reg"; + interrupts = , + ; + interrupt-names = "thermal", "edp"; + clocks = <&tegra_car TEGRA114_CLK_TSENSOR>, + <&tegra_car TEGRA114_CLK_SOC_THERM>; + clock-names = "tsensor", "soctherm"; + resets = <&tegra_car 78>; + reset-names = "soctherm"; + + assigned-clocks = <&tegra_car TEGRA114_CLK_TSENSOR>, + <&tegra_car TEGRA114_CLK_SOC_THERM>; + assigned-clock-rates = <500000>, <51000000>; + + assigned-clock-parents = <&tegra_car TEGRA114_CLK_CLK_M>, + <&tegra_car TEGRA114_CLK_PLL_P>; + + #thermal-sensor-cells = <1>; + + throttle-cfgs { + throttle_heavy: heavy { + nvidia,priority = <100>; + nvidia,cpu-throt-percent = <80>; + nvidia,gpu-throt-level = ; + + #cooling-cells = <2>; + }; + + throttle_light: light { + nvidia,priority = <80>; + nvidia,cpu-throt-percent = <50>; + nvidia,gpu-throt-level = ; + + #cooling-cells = <2>; + }; + }; + }; + dfll: clock@70110000 { compatible = "nvidia,tegra114-dfll"; reg = <0x70110000 0x100>, /* DFLL control */ @@ -875,24 +919,32 @@ cpu0: cpu@0 { clock-names = "cpu_g", "cpu_lp", "pll_x", "pll_p", "dfll"; /* FIXME: what's the actual transition time? */ clock-latency = <300000>; + + #cooling-cells = <2>; }; cpu1: cpu@1 { device_type = "cpu"; compatible = "arm,cortex-a15"; reg = <1>; + + #cooling-cells = <2>; }; cpu2: cpu@2 { device_type = "cpu"; compatible = "arm,cortex-a15"; reg = <2>; + + #cooling-cells = <2>; }; cpu3: cpu@3 { device_type = "cpu"; compatible = "arm,cortex-a15"; reg = <3>; + + #cooling-cells = <2>; }; }; @@ -905,6 +957,158 @@ pmu { interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>; }; + thermal-zones { + cpu-thermal { + polling-delay-passive = <1000>; + polling-delay = <1000>; + + thermal-sensors = + <&soctherm TEGRA124_SOCTHERM_SENSOR_CPU>; + + trips { + cpu-shutdown-trip { + temperature = <102000>; + hysteresis = <0>; + type = "critical"; + }; + + cpu_throttle_trip: cpu-throttle-trip { + temperature = <100000>; + hysteresis = <1000>; + type = "hot"; + }; + + cpu_balanced_trip: cpu-balanced-trip { + temperature = <90000>; + hysteresis = <1000>; + type = "passive"; + }; + }; + + cooling-maps { + map0 { + trip = <&cpu_throttle_trip>; + cooling-device = <&throttle_heavy 1 1>; + }; + + map1 { + trip = <&cpu_balanced_trip>; + cooling-device = <&throttle_light 1 1>; + }; + }; + }; + + mem-thermal { + polling-delay-passive = <1000>; + polling-delay = <1000>; + + thermal-sensors = + <&soctherm TEGRA124_SOCTHERM_SENSOR_MEM>; + + trips { + mem-shutdown-trip { + temperature = <102000>; + hysteresis = <0>; + type = "critical"; + }; + + mem_throttle_trip: mem-throttle-trip { + temperature = <100000>; + hysteresis = <1000>; + type = "hot"; + }; + + mem_balanced_trip: mem-balanced-trip { + temperature = <90000>; + hysteresis = <1000>; + type = "passive"; + }; + }; + + cooling-maps { + /* + * There are currently no cooling maps, + * because there are no cooling devices. + */ + }; + }; + + gpu-thermal { + polling-delay-passive = <1000>; + polling-delay = <1000>; + + thermal-sensors = + <&soctherm TEGRA124_SOCTHERM_SENSOR_GPU>; + + trips { + gpu-shutdown-trip { + temperature = <102000>; + hysteresis = <0>; + type = "critical"; + }; + + gpu_throttle_trip: gpu-throttle-trip { + temperature = <100000>; + hysteresis = <1000>; + type = "hot"; + }; + + gpu_balanced_trip: gpu-balanced-trip { + temperature = <90000>; + hysteresis = <1000>; + type = "passive"; + }; + }; + + cooling-maps { + map0 { + trip = <&gpu_throttle_trip>; + cooling-device = <&throttle_heavy 1 1>; + }; + + map1 { + trip = <&gpu_balanced_trip>; + cooling-device = <&throttle_light 1 1>; + }; + }; + }; + + pllx-thermal { + polling-delay-passive = <1000>; + polling-delay = <1000>; + + thermal-sensors = + <&soctherm TEGRA124_SOCTHERM_SENSOR_PLLX>; + + trips { + pllx-shutdown-trip { + temperature = <102000>; + hysteresis = <0>; + type = "critical"; + }; + + pllx_throttle_trip: pllx-throttle-trip { + temperature = <100000>; + hysteresis = <1000>; + type = "hot"; + }; + + pllx_balanced_trip: pllx-balanced-trip { + temperature = <90000>; + hysteresis = <1000>; + type = "passive"; + }; + }; + + cooling-maps { + /* + * There are currently no cooling maps, + * because there are no cooling devices. + */ + }; + }; + }; + timer { compatible = "arm,armv7-timer"; interrupts =