From patchwork Fri Mar 21 14:56:24 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Imre Deak X-Patchwork-Id: 14025629 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 3D637C3600A for ; Fri, 21 Mar 2025 14:56:29 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id B857C10E7E6; Fri, 21 Mar 2025 14:56:28 +0000 (UTC) Authentication-Results: gabe.freedesktop.org; dkim=pass (2048-bit key; unprotected) header.d=intel.com header.i=@intel.com header.b="HdCxWp4w"; dkim-atps=neutral Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.14]) by gabe.freedesktop.org (Postfix) with ESMTPS id 29F2010E7E6; Fri, 21 Mar 2025 14:56:27 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1742568988; x=1774104988; h=from:to:subject:date:message-id:in-reply-to:references: mime-version:content-transfer-encoding; bh=BOwhzz4F6utuKOY+XDiWUgtk1HO9FKvg1gT0oTkBeYI=; b=HdCxWp4wR+4vEUfP6gNqUyQsaV/SgxLaOedOzDgua4Hc/LTUPfAgQ7a7 bamlHSluJSI26aYOKCYc1kBZPBsAwI8rU1p83ya+U5y5mYnMM7ZlqD4eH A/txHbkBi+F3WomM3VvAxqC5qITQQbM6VvKCFrPchke0XwSKem+LrFYmR AJWEi0wqVXmT+WybbycvcXmO+UkcyQlrrEKy9z2qdVwIo40LfuzwxVdOu K68vO+QSMAD+CNVr7WrhfY1DeEz/RMCertLHYAvEmK7DN6mw8S3TS6mHS GG9uPnu2GG47qZkNgZYcfiodBltw1152gQ8ueGDEPMrxVTDmsUQEnW1te Q==; X-CSE-ConnectionGUID: in9A4QGvQYWBqIRTJEPuuQ== X-CSE-MsgGUID: odGeU8+USIerptHlOzo2UA== X-IronPort-AV: E=McAfee;i="6700,10204,11380"; a="47617954" X-IronPort-AV: E=Sophos;i="6.14,264,1736841600"; d="scan'208";a="47617954" Received: from orviesa004.jf.intel.com ([10.64.159.144]) by orvoesa106.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 21 Mar 2025 07:56:27 -0700 X-CSE-ConnectionGUID: FkfS3jLaQnSVdkLaMa7tvA== X-CSE-MsgGUID: FWxfRGKJRh6MCDLlq8c36w== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.14,264,1736841600"; d="scan'208";a="128478338" Received: from ideak-desk.fi.intel.com ([10.237.72.78]) by orviesa004-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 21 Mar 2025 07:56:26 -0700 From: Imre Deak To: intel-gfx@lists.freedesktop.org, intel-xe@lists.freedesktop.org Subject: [PATCH 1/3] drm/i915/pps: Add helpers to lock PPS for AUX transfers Date: Fri, 21 Mar 2025 16:56:24 +0200 Message-ID: <20250321145626.94101-2-imre.deak@intel.com> X-Mailer: git-send-email 2.44.2 In-Reply-To: <20250321145626.94101-1-imre.deak@intel.com> References: <20250321145626.94101-1-imre.deak@intel.com> MIME-Version: 1.0 X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" Factor out from the DP AUX transfer function the logic to lock/unlock the Panel Power Sequencer state and enable/disable the VDD power required for the AUX transfer, adding these to helpers in intel_pps.c . This prepares for a follow-up change making these steps dependent on the platform and output type. Signed-off-by: Imre Deak --- drivers/gpu/drm/i915/display/intel_dp_aux.c | 16 ++---------- drivers/gpu/drm/i915/display/intel_pps.c | 29 ++++++++++++++++++++- drivers/gpu/drm/i915/display/intel_pps.h | 3 ++- 3 files changed, 32 insertions(+), 16 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_dp_aux.c b/drivers/gpu/drm/i915/display/intel_dp_aux.c index ec27bbd70bcf0..bf5ccfa24ca0b 100644 --- a/drivers/gpu/drm/i915/display/intel_dp_aux.c +++ b/drivers/gpu/drm/i915/display/intel_dp_aux.c @@ -272,15 +272,7 @@ intel_dp_aux_xfer(struct intel_dp *intel_dp, aux_domain = intel_aux_power_domain(dig_port); aux_wakeref = intel_display_power_get(display, aux_domain); - pps_wakeref = intel_pps_lock(intel_dp); - - /* - * We will be called with VDD already enabled for dpcd/edid/oui reads. - * In such cases we want to leave VDD enabled and it's up to upper layers - * to turn it off. But for eg. i2c-dev access we need to turn it on/off - * ourselves. - */ - vdd = intel_pps_vdd_on_unlocked(intel_dp); + pps_wakeref = intel_pps_lock_for_aux(intel_dp, &vdd); /* * dp aux is extremely sensitive to irq latency, hence request the @@ -289,8 +281,6 @@ intel_dp_aux_xfer(struct intel_dp *intel_dp, */ cpu_latency_qos_update_request(&intel_dp->pm_qos, 0); - intel_pps_check_power_unlocked(intel_dp); - /* * FIXME PSR should be disabled here to prevent * it using the same AUX CH simultaneously @@ -427,10 +417,8 @@ intel_dp_aux_xfer(struct intel_dp *intel_dp, out: cpu_latency_qos_update_request(&intel_dp->pm_qos, PM_QOS_DEFAULT_VALUE); - if (vdd) - intel_pps_vdd_off_unlocked(intel_dp, false); + intel_pps_unlock_for_aux(intel_dp, pps_wakeref, vdd); - intel_pps_unlock(intel_dp, pps_wakeref); intel_display_power_put_async(display, aux_domain, aux_wakeref); out_unlock: intel_digital_port_unlock(encoder); diff --git a/drivers/gpu/drm/i915/display/intel_pps.c b/drivers/gpu/drm/i915/display/intel_pps.c index 617ce49931726..3c078fd53fbfa 100644 --- a/drivers/gpu/drm/i915/display/intel_pps.c +++ b/drivers/gpu/drm/i915/display/intel_pps.c @@ -571,7 +571,7 @@ static bool edp_have_panel_vdd(struct intel_dp *intel_dp) return intel_de_read(display, _pp_ctrl_reg(intel_dp)) & EDP_FORCE_VDD; } -void intel_pps_check_power_unlocked(struct intel_dp *intel_dp) +static void intel_pps_check_power_unlocked(struct intel_dp *intel_dp) { struct intel_display *display = to_intel_display(intel_dp); struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp); @@ -955,6 +955,33 @@ void intel_pps_vdd_off(struct intel_dp *intel_dp) intel_pps_vdd_off_unlocked(intel_dp, false); } +intel_wakeref_t intel_pps_lock_for_aux(struct intel_dp *intel_dp, bool *vdd_ref) +{ + intel_wakeref_t wakeref; + + wakeref = intel_pps_lock(intel_dp); + + /* + * We will be called with VDD already enabled for dpcd/edid/oui reads. + * In such cases we want to leave VDD enabled and it's up to upper layers + * to turn it off. But for eg. i2c-dev access we need to turn it on/off + * ourselves. + */ + *vdd_ref = intel_pps_vdd_on_unlocked(intel_dp); + + intel_pps_check_power_unlocked(intel_dp); + + return wakeref; +} + +void intel_pps_unlock_for_aux(struct intel_dp *intel_dp, intel_wakeref_t wakeref, bool vdd_ref) +{ + if (vdd_ref) + intel_pps_vdd_off_unlocked(intel_dp, false); + + intel_pps_unlock(intel_dp, wakeref); +} + void intel_pps_on_unlocked(struct intel_dp *intel_dp) { struct intel_display *display = to_intel_display(intel_dp); diff --git a/drivers/gpu/drm/i915/display/intel_pps.h b/drivers/gpu/drm/i915/display/intel_pps.h index c83007152f07d..4390d05892325 100644 --- a/drivers/gpu/drm/i915/display/intel_pps.h +++ b/drivers/gpu/drm/i915/display/intel_pps.h @@ -31,10 +31,11 @@ bool intel_pps_vdd_on_unlocked(struct intel_dp *intel_dp); void intel_pps_vdd_off_unlocked(struct intel_dp *intel_dp, bool sync); void intel_pps_on_unlocked(struct intel_dp *intel_dp); void intel_pps_off_unlocked(struct intel_dp *intel_dp); -void intel_pps_check_power_unlocked(struct intel_dp *intel_dp); void intel_pps_vdd_on(struct intel_dp *intel_dp); void intel_pps_vdd_off(struct intel_dp *intel_dp); +intel_wakeref_t intel_pps_lock_for_aux(struct intel_dp *intel_dp, bool *vdd_ref); +void intel_pps_unlock_for_aux(struct intel_dp *intel_dp, intel_wakeref_t wakeref, bool vdd_ref); void intel_pps_on(struct intel_dp *intel_dp); void intel_pps_off(struct intel_dp *intel_dp); void intel_pps_vdd_off_sync(struct intel_dp *intel_dp); From patchwork Fri Mar 21 14:56:25 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Imre Deak X-Patchwork-Id: 14025628 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 49259C36002 for ; Fri, 21 Mar 2025 14:56:30 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id D853510E7EB; Fri, 21 Mar 2025 14:56:29 +0000 (UTC) Authentication-Results: gabe.freedesktop.org; dkim=pass (2048-bit key; unprotected) header.d=intel.com header.i=@intel.com header.b="PSEC59pu"; dkim-atps=neutral Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.14]) by gabe.freedesktop.org (Postfix) with ESMTPS id 6C3E210E7E6; Fri, 21 Mar 2025 14:56:28 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1742568989; x=1774104989; h=from:to:subject:date:message-id:in-reply-to:references: mime-version:content-transfer-encoding; bh=5/Q3mFBViPYg85BZLlfkDj46Y2Iv85V1ewe/oDWFZi4=; b=PSEC59puQYqU63ETguoQG/8dIuGKDnbakjdjm1uwLm0ofw+QL51pZ1x0 2Q2MHdz+pIzvTwEwGdZGqMb0k8AdM7Y0Tqi1nVvg31PfmGYeJBngdUSIv fA5ykKJVLSbuJl6wpBBuSSR4w4+/niHPJBozpJLOumqajtxrojDSB5ZEp ljTG2QOj+BEWhDNuzmmL7+OwHsrkaKqiux9E9wlM1Jm5u3pGsquvXoL5g iqISHmGm3ZVYYVTxs7A/M/grP0QcbxjSPooNqOl+tXeThn4RxI12SVuZ8 Edf/9rusGvMiyGb/oHzW8LsczIRJXOPdLl2GgP6TaUsommjm2lJdwZPMe A==; X-CSE-ConnectionGUID: 6/qIz0gLSAGGnmkGl7WP1Q== X-CSE-MsgGUID: QNplVI+NTtuVZAdJELnL0A== X-IronPort-AV: E=McAfee;i="6700,10204,11380"; a="47617962" X-IronPort-AV: E=Sophos;i="6.14,264,1736841600"; d="scan'208";a="47617962" Received: from orviesa004.jf.intel.com ([10.64.159.144]) by orvoesa106.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 21 Mar 2025 07:56:29 -0700 X-CSE-ConnectionGUID: clkXaSNXRM60aaEUCmOo+A== X-CSE-MsgGUID: 2G+sD8LRQy6TdEAv/g7ZeQ== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.14,264,1736841600"; d="scan'208";a="128478344" Received: from ideak-desk.fi.intel.com ([10.237.72.78]) by orviesa004-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 21 Mar 2025 07:56:27 -0700 From: Imre Deak To: intel-gfx@lists.freedesktop.org, intel-xe@lists.freedesktop.org Subject: [PATCH 2/3] drm/i915/dp_mst: Fix side-band message timeouts due to long PPS delays Date: Fri, 21 Mar 2025 16:56:25 +0200 Message-ID: <20250321145626.94101-3-imre.deak@intel.com> X-Mailer: git-send-email 2.44.2 In-Reply-To: <20250321145626.94101-1-imre.deak@intel.com> References: <20250321145626.94101-1-imre.deak@intel.com> MIME-Version: 1.0 X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" The Panel Power Sequencer lock held on an eDP port (a) blocks a DP AUX transfer on another port (b), since the PPS lock is device global, thus shared by all ports. The PPS lock can be held on port (a) for a longer period due to the various PPS delays (panel/backlight on/off, power-cycle delays). This in turn can cause an MST down-message request on port (b) time out, if the above PPS delay defers the handling of the reply to the request by more than 100ms: the MST branch device sending the reply (signaling this via the DP_DOWN_REP_MSG_RDY flag in the DP_DEVICE_SERVICE_IRQ_VECTOR DPCD register) may cancel the reply (clearing DP_DOWN_REP_MSG_RDY and the reply message buffer) after 110 ms, if the reply is not processed by that time. Avoid MST down-message timeouts described above, by locking the PPS state for AUX transfers only if this is actually required: on eDP ports, where the VDD power depends on the PPS state and on all DP and eDP ports on VLV/CHV, where the PPS is a pipe instance and hence a modeset on any port possibly affecting the PPS state. Signed-off-by: Imre Deak --- drivers/gpu/drm/i915/display/intel_pps.c | 34 ++++++++++++++++++++++++ 1 file changed, 34 insertions(+) diff --git a/drivers/gpu/drm/i915/display/intel_pps.c b/drivers/gpu/drm/i915/display/intel_pps.c index 3c078fd53fbfa..7d7157983f25e 100644 --- a/drivers/gpu/drm/i915/display/intel_pps.c +++ b/drivers/gpu/drm/i915/display/intel_pps.c @@ -26,6 +26,11 @@ static void vlv_steal_power_sequencer(struct intel_display *display, static void pps_init_delays(struct intel_dp *intel_dp); static void pps_init_registers(struct intel_dp *intel_dp, bool force_disable_vdd); +static bool intel_pps_is_pipe_instance(struct intel_display *display) +{ + return display->platform.valleyview || display->platform.cherryview; +} + static const char *pps_name(struct intel_dp *intel_dp) { struct intel_display *display = to_intel_display(intel_dp); @@ -955,10 +960,32 @@ void intel_pps_vdd_off(struct intel_dp *intel_dp) intel_pps_vdd_off_unlocked(intel_dp, false); } +static bool aux_needs_pps_lock(struct intel_dp *intel_dp) +{ + struct intel_display *display = to_intel_display(intel_dp); + + /* + * The PPS state needs to be locked for: + * - eDP on all platforms, since AUX transfers on eDP need VDD power + * (either forced or via panel power) which depends on the PPS + * state. + * - non-eDP on platforms where the PPS is a pipe instance (VLV/CHV), + * since changing the PPS state (via a parallel modeset for + * instance) may interfere with the AUX transfers on a non-eDP + * output as well. + */ + return intel_dp_is_edp(intel_dp) || intel_pps_is_pipe_instance(display); +} + intel_wakeref_t intel_pps_lock_for_aux(struct intel_dp *intel_dp, bool *vdd_ref) { intel_wakeref_t wakeref; + if (!aux_needs_pps_lock(intel_dp)) { + *vdd_ref = false; + return NULL; + } + wakeref = intel_pps_lock(intel_dp); /* @@ -976,6 +1003,13 @@ intel_wakeref_t intel_pps_lock_for_aux(struct intel_dp *intel_dp, bool *vdd_ref) void intel_pps_unlock_for_aux(struct intel_dp *intel_dp, intel_wakeref_t wakeref, bool vdd_ref) { + struct intel_display *display = to_intel_display(intel_dp); + + if (!wakeref) { + drm_WARN_ON(display->drm, vdd_ref || aux_needs_pps_lock(intel_dp)); + return; + } + if (vdd_ref) intel_pps_vdd_off_unlocked(intel_dp, false); From patchwork Fri Mar 21 14:56:26 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Imre Deak X-Patchwork-Id: 14025630 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id F18ABC36000 for ; Fri, 21 Mar 2025 14:56:31 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 933C110E7E9; Fri, 21 Mar 2025 14:56:31 +0000 (UTC) Authentication-Results: gabe.freedesktop.org; dkim=pass (2048-bit key; unprotected) header.d=intel.com header.i=@intel.com header.b="ZY/ZkuFU"; dkim-atps=neutral Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.14]) by gabe.freedesktop.org (Postfix) with ESMTPS id A8FBB10E7E8; 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21 Mar 2025 07:56:30 -0700 X-CSE-ConnectionGUID: F+doec4bQWSlJHGZfK+H0w== X-CSE-MsgGUID: qrdZQ9KJQRWQe/Ox8UqI5Q== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.14,264,1736841600"; d="scan'208";a="128478351" Received: from ideak-desk.fi.intel.com ([10.237.72.78]) by orviesa004-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 21 Mar 2025 07:56:28 -0700 From: Imre Deak To: intel-gfx@lists.freedesktop.org, intel-xe@lists.freedesktop.org Subject: [PATCH 3/3] drm/i915/pps: Use intel_pps_is_pipe_instance() instead of open-coding it Date: Fri, 21 Mar 2025 16:56:26 +0200 Message-ID: <20250321145626.94101-4-imre.deak@intel.com> X-Mailer: git-send-email 2.44.2 In-Reply-To: <20250321145626.94101-1-imre.deak@intel.com> References: <20250321145626.94101-1-imre.deak@intel.com> MIME-Version: 1.0 X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" Use intel_pps_is_pipe_instance() instead of open-coding the same for all conditional PPS programming required for a pipe instance PPS. Signed-off-by: Imre Deak --- drivers/gpu/drm/i915/display/g4x_dp.c | 6 +++--- drivers/gpu/drm/i915/display/intel_dp.c | 2 +- drivers/gpu/drm/i915/display/intel_pps.c | 18 +++++++++--------- drivers/gpu/drm/i915/display/intel_pps.h | 2 ++ 4 files changed, 15 insertions(+), 13 deletions(-) diff --git a/drivers/gpu/drm/i915/display/g4x_dp.c b/drivers/gpu/drm/i915/display/g4x_dp.c index 55b9e9bfcc4d0..f527b455ce904 100644 --- a/drivers/gpu/drm/i915/display/g4x_dp.c +++ b/drivers/gpu/drm/i915/display/g4x_dp.c @@ -474,7 +474,7 @@ intel_dp_link_down(struct intel_encoder *encoder, msleep(intel_dp->pps.panel_power_down_delay); - if (display->platform.valleyview || display->platform.cherryview) + if (intel_pps_is_pipe_instance(display)) vlv_pps_port_disable(encoder, old_crtc_state); } @@ -685,7 +685,7 @@ static void intel_enable_dp(struct intel_atomic_state *state, return; with_intel_pps_lock(intel_dp, wakeref) { - if (display->platform.valleyview || display->platform.cherryview) + if (intel_pps_is_pipe_instance(display)) vlv_pps_port_enable_unlocked(encoder, pipe_config); intel_dp_enable_port(intel_dp, pipe_config); @@ -1265,7 +1265,7 @@ static void intel_dp_encoder_reset(struct drm_encoder *encoder) intel_dp->reset_link_params = true; intel_dp_invalidate_source_oui(intel_dp); - if (display->platform.valleyview || display->platform.cherryview) + if (intel_pps_is_pipe_instance(display)) vlv_pps_pipe_reset(intel_dp); intel_pps_encoder_reset(intel_dp); diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c index e3821ccfabe30..b4a0e3775b7b4 100644 --- a/drivers/gpu/drm/i915/display/intel_dp.c +++ b/drivers/gpu/drm/i915/display/intel_dp.c @@ -6518,7 +6518,7 @@ intel_dp_init_connector(struct intel_digital_port *dig_port, intel_dp_set_default_sink_rates(intel_dp); intel_dp_set_default_max_sink_lane_count(intel_dp); - if (display->platform.valleyview || display->platform.cherryview) + if (intel_pps_is_pipe_instance(display)) vlv_pps_pipe_init(intel_dp); intel_dp_aux_init(intel_dp); diff --git a/drivers/gpu/drm/i915/display/intel_pps.c b/drivers/gpu/drm/i915/display/intel_pps.c index 7d7157983f25e..7b47346d4d559 100644 --- a/drivers/gpu/drm/i915/display/intel_pps.c +++ b/drivers/gpu/drm/i915/display/intel_pps.c @@ -26,7 +26,7 @@ static void vlv_steal_power_sequencer(struct intel_display *display, static void pps_init_delays(struct intel_dp *intel_dp); static void pps_init_registers(struct intel_dp *intel_dp, bool force_disable_vdd); -static bool intel_pps_is_pipe_instance(struct intel_display *display) +bool intel_pps_is_pipe_instance(struct intel_display *display) { return display->platform.valleyview || display->platform.cherryview; } @@ -36,7 +36,7 @@ static const char *pps_name(struct intel_dp *intel_dp) struct intel_display *display = to_intel_display(intel_dp); struct intel_pps *pps = &intel_dp->pps; - if (display->platform.valleyview || display->platform.cherryview) { + if (intel_pps_is_pipe_instance(display)) { switch (pps->vlv_pps_pipe) { case INVALID_PIPE: /* @@ -411,7 +411,7 @@ pps_initial_setup(struct intel_dp *intel_dp) lockdep_assert_held(&display->pps.mutex); - if (display->platform.valleyview || display->platform.cherryview) { + if (intel_pps_is_pipe_instance(display)) { vlv_initial_power_sequencer_setup(intel_dp); return true; } @@ -510,7 +510,7 @@ static void intel_pps_get_registers(struct intel_dp *intel_dp, memset(regs, 0, sizeof(*regs)); - if (display->platform.valleyview || display->platform.cherryview) + if (intel_pps_is_pipe_instance(display)) pps_idx = vlv_power_sequencer_pipe(intel_dp); else if (display->platform.geminilake || display->platform.broxton) pps_idx = bxt_power_sequencer_idx(intel_dp); @@ -556,7 +556,7 @@ static bool edp_have_panel_power(struct intel_dp *intel_dp) lockdep_assert_held(&display->pps.mutex); - if ((display->platform.valleyview || display->platform.cherryview) && + if (intel_pps_is_pipe_instance(display) && intel_dp->pps.vlv_pps_pipe == INVALID_PIPE) return false; @@ -569,7 +569,7 @@ static bool edp_have_panel_vdd(struct intel_dp *intel_dp) lockdep_assert_held(&display->pps.mutex); - if ((display->platform.valleyview || display->platform.cherryview) && + if (intel_pps_is_pipe_instance(display) && intel_dp->pps.vlv_pps_pipe == INVALID_PIPE) return false; @@ -1758,7 +1758,7 @@ void intel_pps_encoder_reset(struct intel_dp *intel_dp) * Reinit the power sequencer also on the resume path, in case * BIOS did something nasty with it. */ - if (display->platform.valleyview || display->platform.cherryview) + if (intel_pps_is_pipe_instance(display)) vlv_initial_power_sequencer_setup(intel_dp); pps_init_delays(intel_dp); @@ -1797,7 +1797,7 @@ static void pps_init_late(struct intel_dp *intel_dp) struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base; struct intel_connector *connector = intel_dp->attached_connector; - if (display->platform.valleyview || display->platform.cherryview) + if (intel_pps_is_pipe_instance(display)) return; if (intel_num_pps(display) < 2) @@ -1931,7 +1931,7 @@ void assert_pps_unlocked(struct intel_display *display, enum pipe pipe) MISSING_CASE(port_sel); break; } - } else if (display->platform.valleyview || display->platform.cherryview) { + } else if (intel_pps_is_pipe_instance(display)) { /* presumably write lock depends on pipe, not port select */ pp_reg = PP_CONTROL(display, pipe); panel_pipe = pipe; diff --git a/drivers/gpu/drm/i915/display/intel_pps.h b/drivers/gpu/drm/i915/display/intel_pps.h index 4390d05892325..1f4eed5fc55b8 100644 --- a/drivers/gpu/drm/i915/display/intel_pps.h +++ b/drivers/gpu/drm/i915/display/intel_pps.h @@ -17,6 +17,8 @@ struct intel_display; struct intel_dp; struct intel_encoder; +bool intel_pps_is_pipe_instance(struct intel_display *display); + intel_wakeref_t intel_pps_lock(struct intel_dp *intel_dp); intel_wakeref_t intel_pps_unlock(struct intel_dp *intel_dp, intel_wakeref_t wakeref);