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[88.187.86.199]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-3997f9efe61sm2747267f8f.97.2025.03.21.08.59.30 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Fri, 21 Mar 2025 08:59:30 -0700 (PDT) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: Richard Henderson , qemu-devel@nongnu.org Cc: Anton Johansson , Pierrick Bouvier , Paolo Bonzini , =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= Subject: [PATCH-for-10.1 1/4] target/riscv: Restrict RV128 MTTCG check on system emulation Date: Fri, 21 Mar 2025 16:59:21 +0100 Message-ID: <20250321155925.96626-2-philmd@linaro.org> X-Mailer: git-send-email 2.47.1 In-Reply-To: <20250321155925.96626-1-philmd@linaro.org> References: <20250321155925.96626-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::332; envelope-from=philmd@linaro.org; helo=mail-wm1-x332.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Multi-threaded TCG only concerns system emulation. Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Pierrick Bouvier --- target/riscv/tcg/tcg-cpu.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/target/riscv/tcg/tcg-cpu.c b/target/riscv/tcg/tcg-cpu.c index fb903992faa..60a26acc503 100644 --- a/target/riscv/tcg/tcg-cpu.c +++ b/target/riscv/tcg/tcg-cpu.c @@ -1050,6 +1050,7 @@ static bool riscv_tcg_cpu_realize(CPUState *cs, Error **errp) return false; } +#ifndef CONFIG_USER_ONLY if (mcc->misa_mxl_max >= MXL_RV128 && qemu_tcg_mttcg_enabled()) { /* Missing 128-bit aligned atomics */ error_setg(errp, @@ -1058,7 +1059,6 @@ static bool riscv_tcg_cpu_realize(CPUState *cs, Error **errp) return false; } -#ifndef CONFIG_USER_ONLY CPURISCVState *env = &cpu->env; tcg_cflags_set(CPU(cs), CF_PCREL); From patchwork Fri Mar 21 15:59:22 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 14025695 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 222ECC36000 for ; Fri, 21 Mar 2025 16:00:29 +0000 (UTC) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1tven0-0000jJ-KB; Fri, 21 Mar 2025 12:00:07 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1tvemZ-0000Yf-Qc for qemu-devel@nongnu.org; Fri, 21 Mar 2025 11:59:41 -0400 Received: from mail-wr1-x42b.google.com ([2a00:1450:4864:20::42b]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1tvemX-0004Qd-Vu for qemu-devel@nongnu.org; Fri, 21 Mar 2025 11:59:39 -0400 Received: by mail-wr1-x42b.google.com with SMTP id ffacd0b85a97d-3912baafc58so1765832f8f.1 for ; Fri, 21 Mar 2025 08:59:37 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1742572776; x=1743177576; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=NxKob2DIbt9NOZ+ogfI82gfyEiacJHXPNgMa/OVurRU=; b=OsHLmAXPg4/m51ZleFwJg6V6i2TaDSfwRx2kwP2HJXqoLu2SXBNJJI2BQMYsSiShxH 4rMj00szFD4O5fJU4bY5f6dvYuFc6SHSRuMhXzqa/jB40OZcZllhXZnyMrt6UabWpbHX 1mIy9sl5LQNrvjyP0BRxG9vrliZZhPRqV0nyTfxGt4iw6mTd6rABD9JTpjONy5RvVfwY tS5z8xG7uihfqq3lnQdX7DOkPkCJQ13Z9uCWi0Jr/hrCqOfhZ8xHDYROMy8l/m1I78IJ +8DEUIJbtlBBRlg8tsdym1Ocqs76TLAcDzGKhm7ywdjOywqlc4gErbNUp5OKAPm8LGwL 9NMA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1742572776; x=1743177576; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=NxKob2DIbt9NOZ+ogfI82gfyEiacJHXPNgMa/OVurRU=; b=fYzsFZx1OgoXLPoWEZv8+QCCQYxfOdlcabWO1vWsdY6jbaeR8HQ3qKC89SpybbBzBK pSgP+x6mrmsRUqeE2UXCL0RbQypQuF+WkeutqSeh/OcTbr2KBJAG7vxK2koQcyEhcN/T GO6LBN9mKmbbD59x5rK6dVaxWbtw4L9GTQMueyxbLPrwilnYFbC/s3vb67urxL33qGKd 7xK0Xnnr5AvCX0JRFKpCMiOjMO925rN3JOEnIWGztp68VkqOAssZpYciI/g+XIoMt3kC hAIa7yUGG6yLokjeLJos1QEFqvpb6AQBi93mcfQUOZSi1MjL6kLbyrvlX5J2BhNWF9ps ST6g== X-Forwarded-Encrypted: i=1; AJvYcCVO4R/4SLFoNCm0XphFzFFQTiYeDx+AadG1WvRP9ULWpZBcHAdDspnfWXgDC4NM8OfmlAPeon9SKyBy@nongnu.org X-Gm-Message-State: AOJu0YxDxZngbJXtN2Cy7DFh+TvUsnJlthte9NmwB1lTpcfyX8HQxCgn nCvzJY+mRUsDfpc8OeYQyhjCiMImL/Of+Jo/1NF7cn6inMnDR8ezx3Oo42zBnMw= X-Gm-Gg: ASbGncseo9lRa/pE6/lgmbUZRu+PA9/K3NkuvyadznYWYP08tJxye+vwKt/c7rj4lwv wZAPF+aESHv4FchK7c4jrQuH81cGWchGlvfhOQ5ZyTE6pnrUUQ1JpZJcqlYGAGIJSMVDxp2N9qO yY0WNKNBrwJVvyEuIm3jyv4/fXaqxeV2goPU5sOH6xnfGM7FREtP/BIqTouG5iIA/M1iLJTwfV8 aMV8Z5MLa3ygP0aOFKBrdKM2029bp0ehil2ZPPQylOSbCev825++jppTZPI2Q4H+AG3RrpMMwA7 ZpZdhT9Gac0k0Bdxp2rlRBCNZWAhkxsNqSpu/5BiqPEHbkBTkud1K2vMYbmPbsN5MTypMxO6c+j uyk0hhAdBuuXTxYiQh5Q= X-Google-Smtp-Source: AGHT+IE4p9vasf/iYUWv/c+rlijQe7X+UF0bcDtluSrlCKJu+UdsEOWlDGDc6IYkFJLQ8O06+JTo4Q== X-Received: by 2002:a05:6000:2b0a:b0:391:4977:5060 with SMTP id ffacd0b85a97d-3997f941223mr3371706f8f.53.1742572776090; Fri, 21 Mar 2025 08:59:36 -0700 (PDT) Received: from localhost.localdomain (88-187-86-199.subs.proxad.net. [88.187.86.199]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-3997f9ef063sm2652299f8f.83.2025.03.21.08.59.35 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Fri, 21 Mar 2025 08:59:35 -0700 (PDT) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: Richard Henderson , qemu-devel@nongnu.org Cc: Anton Johansson , Pierrick Bouvier , Paolo Bonzini , =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= Subject: [PATCH-for-10.1 2/4] tcg: Move qemu_tcg_mttcg_enabled() to 'system/tcg.h' Date: Fri, 21 Mar 2025 16:59:22 +0100 Message-ID: <20250321155925.96626-3-philmd@linaro.org> X-Mailer: git-send-email 2.47.1 In-Reply-To: <20250321155925.96626-1-philmd@linaro.org> References: <20250321155925.96626-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::42b; envelope-from=philmd@linaro.org; helo=mail-wr1-x42b.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org qemu_tcg_mttcg_enabled() is specific to 1/ TCG and 2/ system emulation. Move the prototype declaration to "system/tcg.h", reducing 'mttcg_enabled' variable scope. Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Pierrick Bouvier --- include/hw/core/cpu.h | 9 --------- include/system/tcg.h | 8 ++++++++ accel/tcg/tcg-all.c | 11 ++++++++++- target/riscv/tcg/tcg-cpu.c | 1 + tcg/region.c | 4 +++- 5 files changed, 22 insertions(+), 11 deletions(-) diff --git a/include/hw/core/cpu.h b/include/hw/core/cpu.h index 5d11d26556a..54570d21aea 100644 --- a/include/hw/core/cpu.h +++ b/include/hw/core/cpu.h @@ -597,15 +597,6 @@ extern CPUTailQ cpus_queue; extern __thread CPUState *current_cpu; -/** - * qemu_tcg_mttcg_enabled: - * Check whether we are running MultiThread TCG or not. - * - * Returns: %true if we are in MTTCG mode %false otherwise. - */ -extern bool mttcg_enabled; -#define qemu_tcg_mttcg_enabled() (mttcg_enabled) - /** * cpu_paging_enabled: * @cpu: The CPU whose state is to be inspected. diff --git a/include/system/tcg.h b/include/system/tcg.h index 73229648c63..7622dcea302 100644 --- a/include/system/tcg.h +++ b/include/system/tcg.h @@ -17,4 +17,12 @@ extern bool tcg_allowed; #define tcg_enabled() 0 #endif +/** + * qemu_tcg_mttcg_enabled: + * Check whether we are running MultiThread TCG or not. + * + * Returns: %true if we are in MTTCG mode %false otherwise. + */ +bool qemu_tcg_mttcg_enabled(void); + #endif diff --git a/accel/tcg/tcg-all.c b/accel/tcg/tcg-all.c index cb632cc8cc7..d75ecf531b6 100644 --- a/accel/tcg/tcg-all.c +++ b/accel/tcg/tcg-all.c @@ -38,6 +38,7 @@ #include "hw/qdev-core.h" #else #include "hw/boards.h" +#include "system/tcg.h" #endif #include "internal-common.h" #include "cpu-param.h" @@ -58,6 +59,15 @@ typedef struct TCGState TCGState; DECLARE_INSTANCE_CHECKER(TCGState, TCG_STATE, TYPE_TCG_ACCEL) +static bool mttcg_enabled; + +#ifndef CONFIG_USER_ONLY +bool qemu_tcg_mttcg_enabled(void) +{ + return mttcg_enabled; +} +#endif + /* * We default to false if we know other options have been enabled * which are currently incompatible with MTTCG. Otherwise when each @@ -97,7 +107,6 @@ static void tcg_accel_instance_init(Object *obj) #endif } -bool mttcg_enabled; bool one_insn_per_tb; static int tcg_init_machine(MachineState *ms) diff --git a/target/riscv/tcg/tcg-cpu.c b/target/riscv/tcg/tcg-cpu.c index 60a26acc503..5ccd7b9dc07 100644 --- a/target/riscv/tcg/tcg-cpu.c +++ b/target/riscv/tcg/tcg-cpu.c @@ -35,6 +35,7 @@ #include "tcg/tcg.h" #ifndef CONFIG_USER_ONLY #include "hw/boards.h" +#include "system/tcg.h" #endif /* Hash that stores user set extensions */ diff --git a/tcg/region.c b/tcg/region.c index 478ec051c4b..56d2e988719 100644 --- a/tcg/region.c +++ b/tcg/region.c @@ -34,7 +34,9 @@ #include "exec/translation-block.h" #include "tcg-internal.h" #include "host/cpuinfo.h" - +#ifndef CONFIG_USER_ONLY +#include "system/tcg.h" +#endif /* * Local source-level compatibility with Unix. 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[88.187.86.199]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-3997f9e674fsm2649634f8f.80.2025.03.21.08.59.40 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Fri, 21 Mar 2025 08:59:40 -0700 (PDT) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: Richard Henderson , qemu-devel@nongnu.org Cc: Anton Johansson , Pierrick Bouvier , Paolo Bonzini , =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= Subject: [PATCH-for-10.1 3/4] tcg: Convert TCGState::mttcg_enabled to TriState Date: Fri, 21 Mar 2025 16:59:23 +0100 Message-ID: <20250321155925.96626-4-philmd@linaro.org> X-Mailer: git-send-email 2.47.1 In-Reply-To: <20250321155925.96626-1-philmd@linaro.org> References: <20250321155925.96626-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::331; envelope-from=philmd@linaro.org; helo=mail-wm1-x331.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Use the OnOffAuto type as 3-state. Since the TCGState instance is zero-initialized, the mttcg_enabled is initialzed as AUTO (ON_OFF_AUTO_AUTO). In tcg_init_machine(), if mttcg_enabled is still AUTO, set a default value (effectively inlining the default_mttcg_enabled() method content). Instead of emiting a warning when the 'thread' property is set in tcg_set_thread(), emit it in tcg_init_machine() where it is consumed. In the tcg_get_thread() getter, consider AUTO / OFF states as "single", otherwise ON is "multi". Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Anton Johansson Reviewed-by: Richard Henderson --- accel/tcg/tcg-all.c | 68 ++++++++++++++++++++++----------------------- 1 file changed, 33 insertions(+), 35 deletions(-) diff --git a/accel/tcg/tcg-all.c b/accel/tcg/tcg-all.c index d75ecf531b6..2b7f89eaa20 100644 --- a/accel/tcg/tcg-all.c +++ b/accel/tcg/tcg-all.c @@ -32,6 +32,7 @@ #include "qemu/error-report.h" #include "qemu/accel.h" #include "qemu/atomic.h" +#include "qapi/qapi-types-common.h" #include "qapi/qapi-builtin-visit.h" #include "qemu/units.h" #if defined(CONFIG_USER_ONLY) @@ -47,7 +48,7 @@ struct TCGState { AccelState parent_obj; - bool mttcg_enabled; + OnOffAuto mttcg_enabled; bool one_insn_per_tb; int splitwx_enabled; unsigned long tb_size; @@ -68,37 +69,10 @@ bool qemu_tcg_mttcg_enabled(void) } #endif -/* - * We default to false if we know other options have been enabled - * which are currently incompatible with MTTCG. Otherwise when each - * guest (target) has been updated to support: - * - atomic instructions - * - memory ordering primitives (barriers) - * they can set the appropriate CONFIG flags in ${target}-softmmu.mak - * - * Once a guest architecture has been converted to the new primitives - * there is one remaining limitation to check: - * - The guest can't be oversized (e.g. 64 bit guest on 32 bit host) - */ - -static bool default_mttcg_enabled(void) -{ - if (icount_enabled()) { - return false; - } -#ifdef TARGET_SUPPORTS_MTTCG - return true; -#else - return false; -#endif -} - static void tcg_accel_instance_init(Object *obj) { TCGState *s = TCG_STATE(obj); - s->mttcg_enabled = default_mttcg_enabled(); - /* If debugging enabled, default "auto on", otherwise off. */ #if defined(CONFIG_DEBUG_TCG) && !defined(CONFIG_USER_ONLY) s->splitwx_enabled = -1; @@ -117,9 +91,37 @@ static int tcg_init_machine(MachineState *ms) #else unsigned max_cpus = ms->smp.max_cpus; #endif +#ifdef TARGET_SUPPORTS_MTTCG + bool mttcg_supported = true; +#else + bool mttcg_supported = false; +#endif tcg_allowed = true; mttcg_enabled = s->mttcg_enabled; + if (mttcg_enabled == ON_OFF_AUTO_AUTO) { + /* + * We default to false if we know other options have been enabled + * which are currently incompatible with MTTCG. Otherwise when each + * guest (target) has been updated to support: + * - atomic instructions + * - memory ordering primitives (barriers) + * they can set the appropriate CONFIG flags in ${target}-softmmu.mak + * + * Once a guest architecture has been converted to the new primitives + * there is one remaining limitation to check: + * - The guest can't be oversized (e.g. 64 bit guest on 32 bit host) + */ + if (icount_enabled()) { + mttcg_enabled = ON_OFF_AUTO_OFF; + } else { + mttcg_enabled = mttcg_supported; + } + } + if (mttcg_enabled == ON_OFF_AUTO_ON && !mttcg_supported) { + warn_report("Guest not yet converted to MTTCG - " + "you may get unexpected results"); + } page_init(); tb_htable_init(); @@ -144,7 +146,7 @@ static char *tcg_get_thread(Object *obj, Error **errp) { TCGState *s = TCG_STATE(obj); - return g_strdup(s->mttcg_enabled ? "multi" : "single"); + return g_strdup(s->mttcg_enabled == ON_OFF_AUTO_ON ? "multi" : "single"); } static void tcg_set_thread(Object *obj, const char *value, Error **errp) @@ -155,14 +157,10 @@ static void tcg_set_thread(Object *obj, const char *value, Error **errp) if (icount_enabled()) { error_setg(errp, "No MTTCG when icount is enabled"); } else { -#ifndef TARGET_SUPPORTS_MTTCG - warn_report("Guest not yet converted to MTTCG - " - "you may get unexpected results"); -#endif - s->mttcg_enabled = true; + s->mttcg_enabled = ON_OFF_AUTO_ON; } } else if (strcmp(value, "single") == 0) { - s->mttcg_enabled = false; + s->mttcg_enabled = ON_OFF_AUTO_OFF; } else { error_setg(errp, "Invalid 'thread' setting %s", value); } From patchwork Fri Mar 21 15:59:24 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 14025697 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 1BF81C36005 for ; Fri, 21 Mar 2025 16:01:43 +0000 (UTC) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1tveoU-0001mO-4W; Fri, 21 Mar 2025 12:01:38 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1tvemk-0000d9-VJ for qemu-devel@nongnu.org; Fri, 21 Mar 2025 11:59:57 -0400 Received: from mail-wm1-x32e.google.com ([2a00:1450:4864:20::32e]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1tvemh-0004RX-L9 for qemu-devel@nongnu.org; Fri, 21 Mar 2025 11:59:50 -0400 Received: by mail-wm1-x32e.google.com with SMTP id 5b1f17b1804b1-43cf034d4abso22772225e9.3 for ; Fri, 21 Mar 2025 08:59:47 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1742572786; x=1743177586; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=dXpyXRlk1mV6j3CJQ2ag1OnZd2L/6aCZGApR0YJeQRw=; b=nuxPiQnxR5bXQKgVIcf90Tm4L+ns8t3SLrRYxJSdXnLHZAQGiknZjTAjRW8O50x8Rt 6CZUU6WLD2FScdQq2awdp1s9IcneAXjGf4T/M6BGEWAvHL0S08kwzoY6PSSxzxgF8KAn LpadO0wLXsERF5bcE/cNrL1xIBRnCEMhaqWFPMIVW/T+5XHvZw1nM2xJcUu2WnCfw0Eg 9rG1hFWfDh2xjj/UC8VQNMr0f0KwUG+y48i3++h+zUL560gw1hJ7Jx2sksZpdTJmNfBU U7MYLWmC6j4wSZkEYxkZPUAOusxmtxijtZu6eLiGTjVYT1GokQm/mcP7yLNyQ3yAgUBA G0BA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1742572786; x=1743177586; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=dXpyXRlk1mV6j3CJQ2ag1OnZd2L/6aCZGApR0YJeQRw=; b=HN9p6PeEzxyFKDEtuduNy6aZSoUrI4QHVblhuDyB2EjE64nb1xThUG/Pn/7iCt3cvw lYaZq2yF73D8Z0NQ2D7tw1ihCTkwDK/0kapFyOPxLWwbs/fU5iDAz8eQQRfs+LLjcAOw RA9+D8XiA6XompZw8ljxEP6bVRPUr/ahBnDgA4fv6+Xqw4682Jb27zNaDLmHiYN9U19t +lzy0WmxEm5gSPFadIiNPg/Lvfay/IZHxCpeo26z0IZuNAHDttfK9Wr+VG/t1Y0p0cyy jQg+elXbgJ5jWck5dC8ysqDqOwsVoYIqD/uHeVPgSfzBZGk6ncEHJnqEkBa4rYigF8yX eW4Q== X-Forwarded-Encrypted: i=1; AJvYcCX9ySa7GeEmedjBnw5q9OkBDJX89hjKWKENGjYL/K122rCFeuFcWB4K4hamVNmdqRETJFBp+C67nYUx@nongnu.org X-Gm-Message-State: AOJu0YzGPyAM5OJdtKX3of1NHQBTQ3cik3CY3GrCbS9rtqX0DaSrOx7C yl1mvCeHdP4yMc3+FhkNKVMzc8hWTF8H6MVeMcE1xP9AJC5bo3HDyuxjwid8YYs= X-Gm-Gg: ASbGncuR33a8Zc8SM73Qs6237BhCwDBv9CuNZ6l5lE2VVgijh7AreKKlzEo9sqYVkb4 dqfOEOwA5pGDlLhCGDS56/KQRu8nj/LWGSD57Y5bEgcPpdKNX0lw4cwZBTmW0NTqbh3ZPojQH8Z eIWw+KZ+W+cLTFnWkMaLeTVxAPcdKBupo6FbTsyXVjQu37ADWLnk9YeEy5xjDQPygOXlAf0IQQC kaQ9Ct/BCgqIrY/9HJimfV5+ppBB5repFH8gsENiLDI27k82/34GRGWuU0Ba1qyI2YCyQl8+sgZ hLyHTZafGodsVkKCczcVku7RR++40Wrx4OG5wPGcj6RHBA9rsn6NjBrIac5TEd++P8hRDD3ooTO RroBhnFhCfiIYKuFXlxJpw296D+5Mdw== X-Google-Smtp-Source: AGHT+IEcX87Lc5sB8DrzF4GlO/fyqPCjptTHDiCNubBbR8TnoR+ddYeYVXD8++etivfi38XgblEyWw== X-Received: by 2002:a05:600c:35ca:b0:43b:c284:5bc2 with SMTP id 5b1f17b1804b1-43d50873bedmr42318745e9.0.1742572785688; Fri, 21 Mar 2025 08:59:45 -0700 (PDT) Received: from localhost.localdomain (88-187-86-199.subs.proxad.net. [88.187.86.199]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-43d43f47196sm80755545e9.16.2025.03.21.08.59.44 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Fri, 21 Mar 2025 08:59:45 -0700 (PDT) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: Richard Henderson , qemu-devel@nongnu.org Cc: Anton Johansson , Pierrick Bouvier , Paolo Bonzini , =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= Subject: [PATCH-for-10.1 4/4] tcg: Convert TARGET_SUPPORTS_MTTCG to TCGCPUOps::mttcg_supported field Date: Fri, 21 Mar 2025 16:59:24 +0100 Message-ID: <20250321155925.96626-5-philmd@linaro.org> X-Mailer: git-send-email 2.47.1 In-Reply-To: <20250321155925.96626-1-philmd@linaro.org> References: <20250321155925.96626-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::32e; envelope-from=philmd@linaro.org; helo=mail-wm1-x32e.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Instead of having a compile-time TARGET_SUPPORTS_MTTCG definition, have each target set the 'mttcg_supported' field in the TCGCPUOps structure. Since so far we only emulate one target architecture at a time, tcg_init_machine() gets whether MTTCG is supported via the &first_cpu global. Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Anton Johansson Reviewed-by: Pierrick Bouvier Reviewed-by: Richard Henderson --- docs/devel/multi-thread-tcg.rst | 2 +- configs/targets/aarch64-softmmu.mak | 1 - configs/targets/alpha-softmmu.mak | 1 - configs/targets/arm-softmmu.mak | 1 - configs/targets/hppa-softmmu.mak | 1 - configs/targets/i386-softmmu.mak | 1 - configs/targets/loongarch64-softmmu.mak | 1 - configs/targets/microblaze-softmmu.mak | 1 - configs/targets/microblazeel-softmmu.mak | 1 - configs/targets/mips-softmmu.mak | 1 - configs/targets/mipsel-softmmu.mak | 1 - configs/targets/or1k-softmmu.mak | 1 - configs/targets/ppc64-softmmu.mak | 1 - configs/targets/riscv32-softmmu.mak | 1 - configs/targets/riscv64-softmmu.mak | 1 - configs/targets/s390x-softmmu.mak | 1 - configs/targets/sparc-softmmu.mak | 1 - configs/targets/sparc64-softmmu.mak | 1 - configs/targets/x86_64-softmmu.mak | 1 - configs/targets/xtensa-softmmu.mak | 1 - configs/targets/xtensaeb-softmmu.mak | 1 - include/accel/tcg/cpu-ops.h | 8 ++++++++ include/exec/poison.h | 1 - accel/tcg/tcg-all.c | 7 ++----- target/alpha/cpu.c | 1 + target/arm/cpu.c | 1 + target/arm/tcg/cpu-v7m.c | 1 + target/avr/cpu.c | 1 + target/hexagon/cpu.c | 1 + target/hppa/cpu.c | 1 + target/i386/tcg/tcg-cpu.c | 1 + target/loongarch/cpu.c | 1 + target/m68k/cpu.c | 1 + target/microblaze/cpu.c | 1 + target/mips/cpu.c | 1 + target/openrisc/cpu.c | 1 + target/ppc/cpu_init.c | 1 + target/riscv/tcg/tcg-cpu.c | 1 + target/rx/cpu.c | 1 + target/s390x/cpu.c | 1 + target/sh4/cpu.c | 1 + target/sparc/cpu.c | 1 + target/tricore/cpu.c | 1 + target/xtensa/cpu.c | 1 + 44 files changed, 31 insertions(+), 27 deletions(-) diff --git a/docs/devel/multi-thread-tcg.rst b/docs/devel/multi-thread-tcg.rst index 14a2a9dc7b5..da9a1530c9f 100644 --- a/docs/devel/multi-thread-tcg.rst +++ b/docs/devel/multi-thread-tcg.rst @@ -30,7 +30,7 @@ user-space thread. This is enabled by default for all FE/BE combinations where the host memory model is able to accommodate the guest (TCGCPUOps::guest_default_memory_order & ~TCG_TARGET_DEFAULT_MO is zero) and the guest has had the required work done to support this safely -(TARGET_SUPPORTS_MTTCG). +(TCGCPUOps::mttcg_supported). System emulation will fall back to the original round robin approach if: diff --git a/configs/targets/aarch64-softmmu.mak b/configs/targets/aarch64-softmmu.mak index 82cb72cb83d..5dfeb35af90 100644 --- a/configs/targets/aarch64-softmmu.mak +++ b/configs/targets/aarch64-softmmu.mak @@ -1,6 +1,5 @@ TARGET_ARCH=aarch64 TARGET_BASE_ARCH=arm -TARGET_SUPPORTS_MTTCG=y TARGET_KVM_HAVE_GUEST_DEBUG=y TARGET_XML_FILES= gdb-xml/aarch64-core.xml gdb-xml/aarch64-fpu.xml gdb-xml/arm-core.xml gdb-xml/arm-vfp.xml gdb-xml/arm-vfp3.xml gdb-xml/arm-vfp-sysregs.xml gdb-xml/arm-neon.xml gdb-xml/arm-m-profile.xml gdb-xml/arm-m-profile-mve.xml gdb-xml/aarch64-pauth.xml # needed by boot.c diff --git a/configs/targets/alpha-softmmu.mak b/configs/targets/alpha-softmmu.mak index 89f3517aca0..5275076e50d 100644 --- a/configs/targets/alpha-softmmu.mak +++ b/configs/targets/alpha-softmmu.mak @@ -1,3 +1,2 @@ TARGET_ARCH=alpha -TARGET_SUPPORTS_MTTCG=y TARGET_LONG_BITS=64 diff --git a/configs/targets/arm-softmmu.mak b/configs/targets/arm-softmmu.mak index afc64f5927b..6a5a8eda949 100644 --- a/configs/targets/arm-softmmu.mak +++ b/configs/targets/arm-softmmu.mak @@ -1,5 +1,4 @@ TARGET_ARCH=arm -TARGET_SUPPORTS_MTTCG=y TARGET_XML_FILES= gdb-xml/arm-core.xml gdb-xml/arm-vfp.xml gdb-xml/arm-vfp3.xml gdb-xml/arm-vfp-sysregs.xml gdb-xml/arm-neon.xml gdb-xml/arm-m-profile.xml gdb-xml/arm-m-profile-mve.xml # needed by boot.c TARGET_NEED_FDT=y diff --git a/configs/targets/hppa-softmmu.mak b/configs/targets/hppa-softmmu.mak index 63ca74ed5e6..ea331107a08 100644 --- a/configs/targets/hppa-softmmu.mak +++ b/configs/targets/hppa-softmmu.mak @@ -1,4 +1,3 @@ TARGET_ARCH=hppa TARGET_BIG_ENDIAN=y -TARGET_SUPPORTS_MTTCG=y TARGET_LONG_BITS=64 diff --git a/configs/targets/i386-softmmu.mak b/configs/targets/i386-softmmu.mak index 5dd89217560..e9d89e8ab41 100644 --- a/configs/targets/i386-softmmu.mak +++ b/configs/targets/i386-softmmu.mak @@ -1,5 +1,4 @@ TARGET_ARCH=i386 -TARGET_SUPPORTS_MTTCG=y TARGET_KVM_HAVE_GUEST_DEBUG=y TARGET_KVM_HAVE_RESET_PARKED_VCPU=y TARGET_XML_FILES= gdb-xml/i386-32bit.xml diff --git a/configs/targets/loongarch64-softmmu.mak b/configs/targets/loongarch64-softmmu.mak index 351341132f6..fc44c54233d 100644 --- a/configs/targets/loongarch64-softmmu.mak +++ b/configs/targets/loongarch64-softmmu.mak @@ -1,7 +1,6 @@ TARGET_ARCH=loongarch64 TARGET_BASE_ARCH=loongarch TARGET_KVM_HAVE_GUEST_DEBUG=y -TARGET_SUPPORTS_MTTCG=y TARGET_XML_FILES= gdb-xml/loongarch-base32.xml gdb-xml/loongarch-base64.xml gdb-xml/loongarch-fpu.xml gdb-xml/loongarch-lsx.xml gdb-xml/loongarch-lasx.xml # all boards require libfdt TARGET_NEED_FDT=y diff --git a/configs/targets/microblaze-softmmu.mak b/configs/targets/microblaze-softmmu.mak index 99a33ed44a8..23457d0ae65 100644 --- a/configs/targets/microblaze-softmmu.mak +++ b/configs/targets/microblaze-softmmu.mak @@ -1,6 +1,5 @@ TARGET_ARCH=microblaze TARGET_BIG_ENDIAN=y -TARGET_SUPPORTS_MTTCG=y # needed by boot.c TARGET_NEED_FDT=y TARGET_XML_FILES=gdb-xml/microblaze-core.xml gdb-xml/microblaze-stack-protect.xml diff --git a/configs/targets/microblazeel-softmmu.mak b/configs/targets/microblazeel-softmmu.mak index 52cdeae1a28..c82c509623d 100644 --- a/configs/targets/microblazeel-softmmu.mak +++ b/configs/targets/microblazeel-softmmu.mak @@ -1,5 +1,4 @@ TARGET_ARCH=microblaze -TARGET_SUPPORTS_MTTCG=y # needed by boot.c TARGET_NEED_FDT=y TARGET_XML_FILES=gdb-xml/microblaze-core.xml gdb-xml/microblaze-stack-protect.xml diff --git a/configs/targets/mips-softmmu.mak b/configs/targets/mips-softmmu.mak index b62a0882499..c9588066b8d 100644 --- a/configs/targets/mips-softmmu.mak +++ b/configs/targets/mips-softmmu.mak @@ -1,4 +1,3 @@ TARGET_ARCH=mips TARGET_BIG_ENDIAN=y -TARGET_SUPPORTS_MTTCG=y TARGET_LONG_BITS=32 diff --git a/configs/targets/mipsel-softmmu.mak b/configs/targets/mipsel-softmmu.mak index 620ec681785..90e09bdc3e5 100644 --- a/configs/targets/mipsel-softmmu.mak +++ b/configs/targets/mipsel-softmmu.mak @@ -1,3 +1,2 @@ TARGET_ARCH=mips -TARGET_SUPPORTS_MTTCG=y TARGET_LONG_BITS=32 diff --git a/configs/targets/or1k-softmmu.mak b/configs/targets/or1k-softmmu.mak index adfddb1a8ac..0e47d9878b0 100644 --- a/configs/targets/or1k-softmmu.mak +++ b/configs/targets/or1k-softmmu.mak @@ -1,5 +1,4 @@ TARGET_ARCH=openrisc -TARGET_SUPPORTS_MTTCG=y TARGET_BIG_ENDIAN=y # needed by boot.c and all boards TARGET_NEED_FDT=y diff --git a/configs/targets/ppc64-softmmu.mak b/configs/targets/ppc64-softmmu.mak index 7cee0e97f43..74572864b36 100644 --- a/configs/targets/ppc64-softmmu.mak +++ b/configs/targets/ppc64-softmmu.mak @@ -1,7 +1,6 @@ TARGET_ARCH=ppc64 TARGET_BASE_ARCH=ppc TARGET_BIG_ENDIAN=y -TARGET_SUPPORTS_MTTCG=y TARGET_KVM_HAVE_GUEST_DEBUG=y TARGET_XML_FILES= gdb-xml/power64-core.xml gdb-xml/power-fpu.xml gdb-xml/power-altivec.xml gdb-xml/power-spe.xml gdb-xml/power-vsx.xml # all boards require libfdt diff --git a/configs/targets/riscv32-softmmu.mak b/configs/targets/riscv32-softmmu.mak index c828066ce6b..db55275b868 100644 --- a/configs/targets/riscv32-softmmu.mak +++ b/configs/targets/riscv32-softmmu.mak @@ -1,6 +1,5 @@ TARGET_ARCH=riscv32 TARGET_BASE_ARCH=riscv -TARGET_SUPPORTS_MTTCG=y TARGET_XML_FILES= gdb-xml/riscv-32bit-cpu.xml gdb-xml/riscv-32bit-fpu.xml gdb-xml/riscv-64bit-fpu.xml gdb-xml/riscv-32bit-virtual.xml # needed by boot.c TARGET_NEED_FDT=y diff --git a/configs/targets/riscv64-softmmu.mak b/configs/targets/riscv64-softmmu.mak index 09f613d24a0..2bdd4a62cd2 100644 --- a/configs/targets/riscv64-softmmu.mak +++ b/configs/targets/riscv64-softmmu.mak @@ -1,6 +1,5 @@ TARGET_ARCH=riscv64 TARGET_BASE_ARCH=riscv -TARGET_SUPPORTS_MTTCG=y TARGET_KVM_HAVE_GUEST_DEBUG=y TARGET_XML_FILES= gdb-xml/riscv-64bit-cpu.xml gdb-xml/riscv-32bit-fpu.xml gdb-xml/riscv-64bit-fpu.xml gdb-xml/riscv-64bit-virtual.xml gdb-xml/riscv-32bit-cpu.xml gdb-xml/riscv-32bit-virtual.xml # needed by boot.c diff --git a/configs/targets/s390x-softmmu.mak b/configs/targets/s390x-softmmu.mak index 5242ebe7c2e..76dd5de6584 100644 --- a/configs/targets/s390x-softmmu.mak +++ b/configs/targets/s390x-softmmu.mak @@ -1,6 +1,5 @@ TARGET_ARCH=s390x TARGET_BIG_ENDIAN=y -TARGET_SUPPORTS_MTTCG=y TARGET_KVM_HAVE_GUEST_DEBUG=y TARGET_XML_FILES= gdb-xml/s390x-core64.xml gdb-xml/s390-acr.xml gdb-xml/s390-fpr.xml gdb-xml/s390-vx.xml gdb-xml/s390-cr.xml gdb-xml/s390-virt.xml gdb-xml/s390-virt-kvm.xml gdb-xml/s390-gs.xml TARGET_LONG_BITS=64 diff --git a/configs/targets/sparc-softmmu.mak b/configs/targets/sparc-softmmu.mak index 78c2e25bd13..57801faf1fc 100644 --- a/configs/targets/sparc-softmmu.mak +++ b/configs/targets/sparc-softmmu.mak @@ -1,4 +1,3 @@ TARGET_ARCH=sparc TARGET_BIG_ENDIAN=y -TARGET_SUPPORTS_MTTCG=y TARGET_LONG_BITS=32 diff --git a/configs/targets/sparc64-softmmu.mak b/configs/targets/sparc64-softmmu.mak index f7bab97a002..2504e31ae33 100644 --- a/configs/targets/sparc64-softmmu.mak +++ b/configs/targets/sparc64-softmmu.mak @@ -1,5 +1,4 @@ TARGET_ARCH=sparc64 TARGET_BASE_ARCH=sparc TARGET_BIG_ENDIAN=y -TARGET_SUPPORTS_MTTCG=y TARGET_LONG_BITS=64 diff --git a/configs/targets/x86_64-softmmu.mak b/configs/targets/x86_64-softmmu.mak index 1ceefde1313..5619b2bc686 100644 --- a/configs/targets/x86_64-softmmu.mak +++ b/configs/targets/x86_64-softmmu.mak @@ -1,6 +1,5 @@ TARGET_ARCH=x86_64 TARGET_BASE_ARCH=i386 -TARGET_SUPPORTS_MTTCG=y TARGET_KVM_HAVE_GUEST_DEBUG=y TARGET_KVM_HAVE_RESET_PARKED_VCPU=y TARGET_XML_FILES= gdb-xml/i386-64bit.xml diff --git a/configs/targets/xtensa-softmmu.mak b/configs/targets/xtensa-softmmu.mak index 65845df4ffa..2a9797338a6 100644 --- a/configs/targets/xtensa-softmmu.mak +++ b/configs/targets/xtensa-softmmu.mak @@ -1,3 +1,2 @@ TARGET_ARCH=xtensa -TARGET_SUPPORTS_MTTCG=y TARGET_LONG_BITS=32 diff --git a/configs/targets/xtensaeb-softmmu.mak b/configs/targets/xtensaeb-softmmu.mak index f1f789d6971..5204729af8b 100644 --- a/configs/targets/xtensaeb-softmmu.mak +++ b/configs/targets/xtensaeb-softmmu.mak @@ -1,4 +1,3 @@ TARGET_ARCH=xtensa TARGET_BIG_ENDIAN=y -TARGET_SUPPORTS_MTTCG=y TARGET_LONG_BITS=32 diff --git a/include/accel/tcg/cpu-ops.h b/include/accel/tcg/cpu-ops.h index 5fd299cefb6..31e63b8a663 100644 --- a/include/accel/tcg/cpu-ops.h +++ b/include/accel/tcg/cpu-ops.h @@ -19,6 +19,14 @@ #include "tcg/tcg-mo.h" struct TCGCPUOps { + /** + * mttcg_supported: multi-threaded TCG is supported + * + * Target (TCG frontend) supports: + * - atomic instructions + * - memory ordering primitives (barriers) + */ + bool mttcg_supported; /** * @guest_default_memory_order: default barrier that is required diff --git a/include/exec/poison.h b/include/exec/poison.h index 8ed04b31083..6df627868c6 100644 --- a/include/exec/poison.h +++ b/include/exec/poison.h @@ -35,7 +35,6 @@ #pragma GCC poison TARGET_HAS_BFLT #pragma GCC poison TARGET_NAME -#pragma GCC poison TARGET_SUPPORTS_MTTCG #pragma GCC poison TARGET_BIG_ENDIAN #pragma GCC poison BSWAP_NEEDED diff --git a/accel/tcg/tcg-all.c b/accel/tcg/tcg-all.c index 2b7f89eaa20..50b3fd75c32 100644 --- a/accel/tcg/tcg-all.c +++ b/accel/tcg/tcg-all.c @@ -41,6 +41,7 @@ #include "hw/boards.h" #include "system/tcg.h" #endif +#include "accel/tcg/cpu-ops.h" #include "internal-common.h" #include "cpu-param.h" @@ -91,11 +92,7 @@ static int tcg_init_machine(MachineState *ms) #else unsigned max_cpus = ms->smp.max_cpus; #endif -#ifdef TARGET_SUPPORTS_MTTCG - bool mttcg_supported = true; -#else - bool mttcg_supported = false; -#endif + bool mttcg_supported = first_cpu->cc->tcg_ops->mttcg_supported; /* FIXME avoid first_cpu */ tcg_allowed = true; mttcg_enabled = s->mttcg_enabled; diff --git a/target/alpha/cpu.c b/target/alpha/cpu.c index e5e14976f51..2bad59a48a4 100644 --- a/target/alpha/cpu.c +++ b/target/alpha/cpu.c @@ -239,6 +239,7 @@ static const TCGCPUOps alpha_tcg_ops = { .synchronize_from_tb = alpha_cpu_synchronize_from_tb, .restore_state_to_opc = alpha_restore_state_to_opc, + .mttcg_supported = true, /* Alpha processors have a weak memory model */ .guest_default_memory_order = 0, diff --git a/target/arm/cpu.c b/target/arm/cpu.c index 8b9f2acf82b..a332d9a5148 100644 --- a/target/arm/cpu.c +++ b/target/arm/cpu.c @@ -2675,6 +2675,7 @@ static const TCGCPUOps arm_tcg_ops = { .debug_excp_handler = arm_debug_excp_handler, .restore_state_to_opc = arm_restore_state_to_opc, + .mttcg_supported = true, /* ARM processors have a weak memory model */ .guest_default_memory_order = 0, diff --git a/target/arm/tcg/cpu-v7m.c b/target/arm/tcg/cpu-v7m.c index df6b7198944..7069a7a2ca8 100644 --- a/target/arm/tcg/cpu-v7m.c +++ b/target/arm/tcg/cpu-v7m.c @@ -238,6 +238,7 @@ static const TCGCPUOps arm_v7m_tcg_ops = { .debug_excp_handler = arm_debug_excp_handler, .restore_state_to_opc = arm_restore_state_to_opc, + .mttcg_supported = true, /* ARM processors have a weak memory model */ .guest_default_memory_order = 0, diff --git a/target/avr/cpu.c b/target/avr/cpu.c index 24e52e28f44..9bc921c1cb2 100644 --- a/target/avr/cpu.c +++ b/target/avr/cpu.c @@ -216,6 +216,7 @@ static const TCGCPUOps avr_tcg_ops = { .cpu_exec_halt = avr_cpu_has_work, .tlb_fill = avr_cpu_tlb_fill, .do_interrupt = avr_cpu_do_interrupt, + .mttcg_supported = false, .guest_default_memory_order = 0, }; diff --git a/target/hexagon/cpu.c b/target/hexagon/cpu.c index 34734b0edb0..7bcf297998f 100644 --- a/target/hexagon/cpu.c +++ b/target/hexagon/cpu.c @@ -324,6 +324,7 @@ static const TCGCPUOps hexagon_tcg_ops = { .translate_code = hexagon_translate_code, .synchronize_from_tb = hexagon_cpu_synchronize_from_tb, .restore_state_to_opc = hexagon_restore_state_to_opc, + .mttcg_supported = false, /* MTTCG not yet supported: require strict ordering */ .guest_default_memory_order = TCG_MO_ALL, }; diff --git a/target/hppa/cpu.c b/target/hppa/cpu.c index 997bd69db19..31f29a95ac0 100644 --- a/target/hppa/cpu.c +++ b/target/hppa/cpu.c @@ -257,6 +257,7 @@ static const TCGCPUOps hppa_tcg_ops = { .synchronize_from_tb = hppa_cpu_synchronize_from_tb, .restore_state_to_opc = hppa_restore_state_to_opc, + .mttcg_supported = true, /* PA-RISC 1.x processors have a strong memory model. */ /* * ??? While we do not yet implement PA-RISC 2.0, those processors have diff --git a/target/i386/tcg/tcg-cpu.c b/target/i386/tcg/tcg-cpu.c index 4a76c475971..62d36880ceb 100644 --- a/target/i386/tcg/tcg-cpu.c +++ b/target/i386/tcg/tcg-cpu.c @@ -129,6 +129,7 @@ static const TCGCPUOps x86_tcg_ops = { .need_replay_interrupt = x86_need_replay_interrupt, #endif /* !CONFIG_USER_ONLY */ + .mttcg_supported = true, /* * The x86 has a strong memory model with some store-after-load re-ordering */ diff --git a/target/loongarch/cpu.c b/target/loongarch/cpu.c index c39ff056157..460d05b1ee5 100644 --- a/target/loongarch/cpu.c +++ b/target/loongarch/cpu.c @@ -869,6 +869,7 @@ static const TCGCPUOps loongarch_tcg_ops = { .synchronize_from_tb = loongarch_cpu_synchronize_from_tb, .restore_state_to_opc = loongarch_restore_state_to_opc, + .mttcg_supported = true, .guest_default_memory_order = 0, #ifndef CONFIG_USER_ONLY diff --git a/target/m68k/cpu.c b/target/m68k/cpu.c index e96b379e266..4c94f031b13 100644 --- a/target/m68k/cpu.c +++ b/target/m68k/cpu.c @@ -593,6 +593,7 @@ static const TCGCPUOps m68k_tcg_ops = { .translate_code = m68k_translate_code, .restore_state_to_opc = m68k_restore_state_to_opc, + .mttcg_supported = false, /* MTTCG not yet supported: require strict ordering */ .guest_default_memory_order = TCG_MO_ALL, diff --git a/target/microblaze/cpu.c b/target/microblaze/cpu.c index 4b9ef6e52c4..5604c2a34a0 100644 --- a/target/microblaze/cpu.c +++ b/target/microblaze/cpu.c @@ -432,6 +432,7 @@ static const TCGCPUOps mb_tcg_ops = { .synchronize_from_tb = mb_cpu_synchronize_from_tb, .restore_state_to_opc = mb_restore_state_to_opc, + .mttcg_supported = true, /* MicroBlaze is always in-order. */ .guest_default_memory_order = TCG_MO_ALL, diff --git a/target/mips/cpu.c b/target/mips/cpu.c index 5ddc9bbb829..eee604e9254 100644 --- a/target/mips/cpu.c +++ b/target/mips/cpu.c @@ -554,6 +554,7 @@ static const TCGCPUOps mips_tcg_ops = { .synchronize_from_tb = mips_cpu_synchronize_from_tb, .restore_state_to_opc = mips_restore_state_to_opc, + .mttcg_supported = TARGET_LONG_BITS == 32, .guest_default_memory_order = 0, #if !defined(CONFIG_USER_ONLY) diff --git a/target/openrisc/cpu.c b/target/openrisc/cpu.c index 6a878aaadd8..1a6ca405a0c 100644 --- a/target/openrisc/cpu.c +++ b/target/openrisc/cpu.c @@ -248,6 +248,7 @@ static const TCGCPUOps openrisc_tcg_ops = { .synchronize_from_tb = openrisc_cpu_synchronize_from_tb, .restore_state_to_opc = openrisc_restore_state_to_opc, + .mttcg_supported = true, .guest_default_memory_order = 0, #ifndef CONFIG_USER_ONLY diff --git a/target/ppc/cpu_init.c b/target/ppc/cpu_init.c index 28fbbb8d3c1..ed79cc1a6b7 100644 --- a/target/ppc/cpu_init.c +++ b/target/ppc/cpu_init.c @@ -7490,6 +7490,7 @@ static const TCGCPUOps ppc_tcg_ops = { .translate_code = ppc_translate_code, .restore_state_to_opc = ppc_restore_state_to_opc, + .mttcg_supported = TARGET_LONG_BITS == 64, .guest_default_memory_order = 0, #ifdef CONFIG_USER_ONLY diff --git a/target/riscv/tcg/tcg-cpu.c b/target/riscv/tcg/tcg-cpu.c index 5ccd7b9dc07..f26cfae6cdb 100644 --- a/target/riscv/tcg/tcg-cpu.c +++ b/target/riscv/tcg/tcg-cpu.c @@ -140,6 +140,7 @@ static const TCGCPUOps riscv_tcg_ops = { .synchronize_from_tb = riscv_cpu_synchronize_from_tb, .restore_state_to_opc = riscv_restore_state_to_opc, + .mttcg_supported = true, .guest_default_memory_order = 0, #ifndef CONFIG_USER_ONLY diff --git a/target/rx/cpu.c b/target/rx/cpu.c index 6a24e7e9136..4bcbc22d3ad 100644 --- a/target/rx/cpu.c +++ b/target/rx/cpu.c @@ -213,6 +213,7 @@ static const TCGCPUOps rx_tcg_ops = { .cpu_exec_halt = rx_cpu_has_work, .do_interrupt = rx_cpu_do_interrupt, + .mttcg_supported = false, /* MTTCG not yet supported: require strict ordering */ .guest_default_memory_order = TCG_MO_ALL, }; diff --git a/target/s390x/cpu.c b/target/s390x/cpu.c index 12fd853c00a..7ca34002d37 100644 --- a/target/s390x/cpu.c +++ b/target/s390x/cpu.c @@ -361,6 +361,7 @@ static const TCGCPUOps s390_tcg_ops = { .do_unaligned_access = s390x_cpu_do_unaligned_access, #endif /* !CONFIG_USER_ONLY */ + .mttcg_supported = true, /* * The z/Architecture has a strong memory model with some * store-after-load re-ordering. diff --git a/target/sh4/cpu.c b/target/sh4/cpu.c index ce9ed75107a..b796bac8afd 100644 --- a/target/sh4/cpu.c +++ b/target/sh4/cpu.c @@ -267,6 +267,7 @@ static const TCGCPUOps superh_tcg_ops = { .synchronize_from_tb = superh_cpu_synchronize_from_tb, .restore_state_to_opc = superh_restore_state_to_opc, + .mttcg_supported = false, /* MTTCG not yet supported: require strict ordering */ .guest_default_memory_order = TCG_MO_ALL, diff --git a/target/sparc/cpu.c b/target/sparc/cpu.c index 39bd0c42855..2ae7173c0bc 100644 --- a/target/sparc/cpu.c +++ b/target/sparc/cpu.c @@ -1005,6 +1005,7 @@ static const TCGCPUOps sparc_tcg_ops = { .synchronize_from_tb = sparc_cpu_synchronize_from_tb, .restore_state_to_opc = sparc_restore_state_to_opc, + .mttcg_supported = true, /* * From Oracle SPARC Architecture 2015: * diff --git a/target/tricore/cpu.c b/target/tricore/cpu.c index e0a48065948..aea1f211516 100644 --- a/target/tricore/cpu.c +++ b/target/tricore/cpu.c @@ -179,6 +179,7 @@ static const TCGCPUOps tricore_tcg_ops = { .tlb_fill = tricore_cpu_tlb_fill, .cpu_exec_interrupt = tricore_cpu_exec_interrupt, .cpu_exec_halt = tricore_cpu_has_work, + .mttcg_supported = false, /* MTTCG not yet supported: require strict ordering */ .guest_default_memory_order = TCG_MO_ALL, }; diff --git a/target/xtensa/cpu.c b/target/xtensa/cpu.c index dd9061ba469..8cc987f8408 100644 --- a/target/xtensa/cpu.c +++ b/target/xtensa/cpu.c @@ -237,6 +237,7 @@ static const TCGCPUOps xtensa_tcg_ops = { .debug_excp_handler = xtensa_breakpoint_handler, .restore_state_to_opc = xtensa_restore_state_to_opc, + .mttcg_supported = true, /* Xtensa processors have a weak memory model */ .guest_default_memory_order = 0,