From patchwork Fri Mar 21 16:06:17 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Nemesa Garg X-Patchwork-Id: 14025702 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 4895FC36002 for ; Fri, 21 Mar 2025 16:11:45 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id AA87110E7F4; Fri, 21 Mar 2025 16:11:44 +0000 (UTC) Authentication-Results: gabe.freedesktop.org; dkim=pass (2048-bit key; unprotected) header.d=intel.com header.i=@intel.com header.b="FyiF0Cqa"; dkim-atps=neutral Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.9]) by gabe.freedesktop.org (Postfix) with ESMTPS id 0762D10E7F2; Fri, 21 Mar 2025 16:11:43 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1742573503; x=1774109503; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=qwwz1qzQ9G3py7ZJBGnaicQBH35pPzuVyDrfr7IJNfs=; b=FyiF0CqaNdyqREjULnMsJgF2K9EE0yETOmS7Zyus2UaASsYXqZfJhf6t JPr/kzYd5spdJkExxIVmaaCLXu//u+9YCcmu8PBeYOQ3PBl8NSdqniuFP IBBUMoYXiKkR7yKviwY+df9U8Sd+gLR/jCnBuSXhRMKoVCAytYXFt3lqH 3sC5NNhwtWW0XsTnnSx8hhVqssKSv8pGoWeXE1aJFbNKYIlsQW4HoZKeN zQcYsUWN0KsToJKQ7f28kNH68wurrZEzGMu4vlaWCy+jyJLI6qTeN3DBJ VhMJ60DQgnO7ALblImaum/oFpr94xrQfy3n2vrc+ywSKjEXHPbNJL8Wxk Q==; X-CSE-ConnectionGUID: puphwiV5QomI7X4lcpbyDQ== X-CSE-MsgGUID: 21YS5EkYQyuuGxLuLVCa/A== X-IronPort-AV: E=McAfee;i="6700,10204,11380"; a="66308456" X-IronPort-AV: E=Sophos;i="6.14,264,1736841600"; d="scan'208";a="66308456" Received: from fmviesa004.fm.intel.com ([10.60.135.144]) by orvoesa101.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 21 Mar 2025 09:11:42 -0700 X-CSE-ConnectionGUID: gENlT830Q9CkCMex/D0IKw== X-CSE-MsgGUID: XYi4fdP6SBeb7AS4zqD0zA== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.14,264,1736841600"; d="scan'208";a="128554921" Received: from nemesa.iind.intel.com ([10.190.239.22]) by fmviesa004.fm.intel.com with ESMTP; 21 Mar 2025 09:11:41 -0700 From: Nemesa Garg To: intel-gfx@lists.freedesktop.org, intel-xe@lists.freedesktop.org, dri-devel@lists.freedesktop.org Cc: Nemesa Garg Subject: [PATCH 01/12] drm/i915/display: Introduce sharpness strength property Date: Fri, 21 Mar 2025 21:36:17 +0530 Message-Id: <20250321160628.2663912-2-nemesa.garg@intel.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20250321160628.2663912-1-nemesa.garg@intel.com> References: <20250321160628.2663912-1-nemesa.garg@intel.com> MIME-Version: 1.0 X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" Introduces the new crtc property "SHARPNESS_STRENGTH" that allows the user to set the intensity so as to get the sharpness effect. The value of this property can be set from 0-255. It is useful in scenario when the output is blurry and user want to sharpen the pixels. User can increase/decrease the sharpness level depending on the content displayed. v2: Rename crtc property variable [Arun] Add modeset detail in uapi doc[Uma] v3: Fix build issue Signed-off-by: Nemesa Garg --- drivers/gpu/drm/drm_atomic_uapi.c | 4 ++++ drivers/gpu/drm/drm_crtc.c | 35 +++++++++++++++++++++++++++++++ include/drm/drm_crtc.h | 17 +++++++++++++++ 3 files changed, 56 insertions(+) diff --git a/drivers/gpu/drm/drm_atomic_uapi.c b/drivers/gpu/drm/drm_atomic_uapi.c index c2726af6698e..5c1297bcc920 100644 --- a/drivers/gpu/drm/drm_atomic_uapi.c +++ b/drivers/gpu/drm/drm_atomic_uapi.c @@ -418,6 +418,8 @@ static int drm_atomic_crtc_set_property(struct drm_crtc *crtc, set_out_fence_for_crtc(state->state, crtc, fence_ptr); } else if (property == crtc->scaling_filter_property) { state->scaling_filter = val; + } else if (property == crtc->sharpness_strength_property) { + state->sharpness_strength = val; } else if (crtc->funcs->atomic_set_property) { return crtc->funcs->atomic_set_property(crtc, state, property, val); } else { @@ -455,6 +457,8 @@ drm_atomic_crtc_get_property(struct drm_crtc *crtc, *val = 0; else if (property == crtc->scaling_filter_property) *val = state->scaling_filter; + else if (property == crtc->sharpness_strength_property) + *val = state->sharpness_strength; else if (crtc->funcs->atomic_get_property) return crtc->funcs->atomic_get_property(crtc, state, property, val); else { diff --git a/drivers/gpu/drm/drm_crtc.c b/drivers/gpu/drm/drm_crtc.c index 46655339003d..1b7ce99cea5e 100644 --- a/drivers/gpu/drm/drm_crtc.c +++ b/drivers/gpu/drm/drm_crtc.c @@ -229,6 +229,25 @@ struct dma_fence *drm_crtc_create_fence(struct drm_crtc *crtc) * Driver's default scaling filter * Nearest Neighbor: * Nearest Neighbor scaling filter + * SHARPNESS_STRENGTH: + * Atomic property for setting the sharpness strength/intensity by userspace. + * + * The value of this property is set as an integer value ranging + * from 0 - 255 where: + * + * 0 means feature is disabled. + * + * 1 means minimum sharpness. + * + * 255 means maximum sharpness. + * + * User can gradually increase or decrease the sharpness level and can + * set the optimum value depending on content and this value will be + * passed to kernel through the Uapi. + * The setting of this property does not require modeset. + * The sharpness effect takes place post blending on the final composed output. + * If the feature is disabled, the content remains same without any sharpening effect + * and when this feature is applied, it enhances the clarity of the content. */ __printf(6, 0) @@ -940,6 +959,22 @@ int drm_crtc_create_scaling_filter_property(struct drm_crtc *crtc, } EXPORT_SYMBOL(drm_crtc_create_scaling_filter_property); +int drm_crtc_create_sharpness_strength_property(struct drm_crtc *crtc) +{ + struct drm_device *dev = crtc->dev; + struct drm_property *prop = + drm_property_create_range(dev, 0, "SHARPNESS_STRENGTH", 0, 255); + + if (!prop) + return -ENOMEM; + + crtc->sharpness_strength_property = prop; + drm_object_attach_property(&crtc->base, prop, 0); + + return 0; +} +EXPORT_SYMBOL(drm_crtc_create_sharpness_strength_property); + /** * drm_crtc_in_clone_mode - check if the given CRTC state is in clone mode * diff --git a/include/drm/drm_crtc.h b/include/drm/drm_crtc.h index caa56e039da2..2b26b90e82e6 100644 --- a/include/drm/drm_crtc.h +++ b/include/drm/drm_crtc.h @@ -317,6 +317,16 @@ struct drm_crtc_state { */ enum drm_scaling_filter scaling_filter; + /** + * @sharpness_strength: + * + * Used by the user to set the sharpness intensity. + * The value ranges from 0-255. + * Any value greater than 0 means enabling the featuring + * along with setting the value for sharpness. + */ + u8 sharpness_strength; + /** * @event: * @@ -1088,6 +1098,12 @@ struct drm_crtc { */ struct drm_property *scaling_filter_property; + /** + * @sharpness_strength_property: property to apply + * the intensity of the sharpness requested. + */ + struct drm_property *sharpness_strength_property; + /** * @state: * @@ -1324,4 +1340,5 @@ static inline struct drm_crtc *drm_crtc_find(struct drm_device *dev, int drm_crtc_create_scaling_filter_property(struct drm_crtc *crtc, unsigned int supported_filters); bool drm_crtc_in_clone_mode(struct drm_crtc_state *crtc_state); +int drm_crtc_create_sharpness_strength_property(struct drm_crtc *crtc); #endif /* __DRM_CRTC_H__ */ From patchwork Fri Mar 21 16:06:18 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Nemesa Garg X-Patchwork-Id: 14025703 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 14D23C36000 for ; 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X-CSE-ConnectionGUID: XCJotvGFRp6jcarTvpPfhw== X-CSE-MsgGUID: bdgZm7DPSyqXjo53jXJ8WQ== X-IronPort-AV: E=McAfee;i="6700,10204,11380"; a="66308458" X-IronPort-AV: E=Sophos;i="6.14,264,1736841600"; d="scan'208";a="66308458" Received: from fmviesa004.fm.intel.com ([10.60.135.144]) by orvoesa101.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 21 Mar 2025 09:11:44 -0700 X-CSE-ConnectionGUID: fPfyxlCrQeSXf5ROrN6Thw== X-CSE-MsgGUID: AD1tCUtdT06ZTkNajqWfbg== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.14,264,1736841600"; d="scan'208";a="128554926" Received: from nemesa.iind.intel.com ([10.190.239.22]) by fmviesa004.fm.intel.com with ESMTP; 21 Mar 2025 09:11:43 -0700 From: Nemesa Garg To: intel-gfx@lists.freedesktop.org, intel-xe@lists.freedesktop.org, dri-devel@lists.freedesktop.org Cc: Nemesa Garg Subject: [PATCH 02/12] drm/i915/display: Introduce HAS_CASF for sharpness support Date: Fri, 21 Mar 2025 21:36:18 +0530 Message-Id: <20250321160628.2663912-3-nemesa.garg@intel.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20250321160628.2663912-1-nemesa.garg@intel.com> References: <20250321160628.2663912-1-nemesa.garg@intel.com> MIME-Version: 1.0 X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" HAS_CASF macro will be used to check whether platform support the content adaptive sharpness capability or not. v2: Update commit message[Ankit] Signed-off-by: Nemesa Garg --- drivers/gpu/drm/i915/display/intel_display_device.h | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/gpu/drm/i915/display/intel_display_device.h b/drivers/gpu/drm/i915/display/intel_display_device.h index 368b0d3417c2..09b9991beffa 100644 --- a/drivers/gpu/drm/i915/display/intel_display_device.h +++ b/drivers/gpu/drm/i915/display/intel_display_device.h @@ -145,6 +145,7 @@ struct intel_display_platforms { #define HAS_ASYNC_FLIPS(__display) (DISPLAY_VER(__display) >= 5) #define HAS_AS_SDP(__display) (DISPLAY_VER(__display) >= 13) #define HAS_BIGJOINER(__display) (DISPLAY_VER(__display) >= 11 && HAS_DSC(__display)) +#define HAS_CASF(__display) (DISPLAY_VER(__display) >= 20) #define HAS_CDCLK_CRAWL(__display) (DISPLAY_INFO(__display)->has_cdclk_crawl) #define HAS_CDCLK_SQUASH(__display) (DISPLAY_INFO(__display)->has_cdclk_squash) #define HAS_CMRR(__display) (DISPLAY_VER(__display) >= 20) From patchwork Fri Mar 21 16:06:19 2025 Content-Type: text/plain; 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d="scan'208";a="128554931" Received: from nemesa.iind.intel.com ([10.190.239.22]) by fmviesa004.fm.intel.com with ESMTP; 21 Mar 2025 09:11:44 -0700 From: Nemesa Garg To: intel-gfx@lists.freedesktop.org, intel-xe@lists.freedesktop.org, dri-devel@lists.freedesktop.org Cc: Nemesa Garg Subject: [PATCH 03/12] drm/i915/display: Add sharpness strength and winsize Date: Fri, 21 Mar 2025 21:36:19 +0530 Message-Id: <20250321160628.2663912-4-nemesa.garg@intel.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20250321160628.2663912-1-nemesa.garg@intel.com> References: <20250321160628.2663912-1-nemesa.garg@intel.com> MIME-Version: 1.0 X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" register The strength value for sharpness is based on user input and the winsize is based on resolution. Set the casf_enable flag if there is a platform support and uapi strength is not zero. Once the sharpness is enabled then just update the strength bit of the register everytime whenever user changes the strength as enable bit and winsize bit remains constant. v2: Introduce get_config for casf[Ankit] Signed-off-by: Nemesa Garg --- drivers/gpu/drm/i915/Makefile | 1 + drivers/gpu/drm/i915/display/intel_casf.c | 99 +++++++++++++++++++ drivers/gpu/drm/i915/display/intel_casf.h | 17 ++++ .../gpu/drm/i915/display/intel_casf_regs.h | 22 +++++ .../drm/i915/display/intel_crtc_state_dump.c | 7 ++ .../drm/i915/display/intel_display_types.h | 7 ++ drivers/gpu/drm/i915/display/skl_scaler.c | 1 + drivers/gpu/drm/xe/Makefile | 1 + 8 files changed, 155 insertions(+) create mode 100644 drivers/gpu/drm/i915/display/intel_casf.c create mode 100644 drivers/gpu/drm/i915/display/intel_casf.h create mode 100644 drivers/gpu/drm/i915/display/intel_casf_regs.h diff --git a/drivers/gpu/drm/i915/Makefile b/drivers/gpu/drm/i915/Makefile index c8fc271b33b7..a955960d09ec 100644 --- a/drivers/gpu/drm/i915/Makefile +++ b/drivers/gpu/drm/i915/Makefile @@ -230,6 +230,7 @@ i915-y += \ display/intel_bios.o \ display/intel_bo.o \ display/intel_bw.o \ + display/intel_casf.o \ display/intel_cdclk.o \ display/intel_cmtg.o \ display/intel_color.o \ diff --git a/drivers/gpu/drm/i915/display/intel_casf.c b/drivers/gpu/drm/i915/display/intel_casf.c new file mode 100644 index 000000000000..28f76b06fd8f --- /dev/null +++ b/drivers/gpu/drm/i915/display/intel_casf.c @@ -0,0 +1,99 @@ +// SPDX-License-Identifier: MIT +/* + * Copyright © 2025 Intel Corporation + * + */ +#include "i915_reg.h" +#include "intel_casf.h" +#include "intel_casf_regs.h" +#include "intel_de.h" +#include "intel_display_types.h" + +#define MAX_PIXELS_FOR_3_TAP_FILTER (1920 * 1080) +#define MAX_PIXELS_FOR_5_TAP_FILTER (3840 * 2160) + +/** + * DOC: Content Adaptive Sharpness Filter (CASF) + * + * From LNL onwards the display engine based adaptive + * sharpening filter is supported. This helps in + * improving the image quality. The display hardware + * uses one of the pipe scaler for implementing casf. + * It works on a region of pixels depending on the + * tap size. The coefficients are used to generate an + * alpha value which is used to blend the sharpened image + * to original image. + */ + +void intel_casf_update_strength(struct intel_crtc_state *crtc_state) +{ + struct intel_display *display = to_intel_display(crtc_state); + struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); + + intel_de_rmw(display, SHARPNESS_CTL(crtc->pipe), 0, + FILTER_STRENGTH(crtc_state->hw.casf_params.strength)); +} + +static void intel_casf_compute_win_size(struct intel_crtc_state *crtc_state) +{ + const struct drm_display_mode *mode = &crtc_state->hw.adjusted_mode; + u16 total_pixels = mode->hdisplay * mode->vdisplay; + + if (total_pixels <= MAX_PIXELS_FOR_3_TAP_FILTER) + crtc_state->hw.casf_params.win_size = SHARPNESS_FILTER_SIZE_3X3; + else if (total_pixels <= MAX_PIXELS_FOR_5_TAP_FILTER) + crtc_state->hw.casf_params.win_size = SHARPNESS_FILTER_SIZE_5X5; + else + crtc_state->hw.casf_params.win_size = SHARPNESS_FILTER_SIZE_7X7; +} + +int intel_casf_compute_config(struct intel_crtc_state *crtc_state) +{ + struct intel_display *display = to_intel_display(crtc_state); + + if (!HAS_CASF(display)) + return 0; + + if (crtc_state->uapi.sharpness_strength == 0) { + crtc_state->hw.casf_params.casf_enable = false; + crtc_state->hw.casf_params.strength = 0; + return 0; + } + + crtc_state->hw.casf_params.casf_enable = true; + + /* + * HW takes a value in form (1.0 + strength) in 4.4 fixed format. + * Strength is from 0.0-14.9375 ie from 0-239. + * User can give value from 0-255 but is clamped to 239. + * Ex. User gives 85 which is 5.3125 and adding 1.0 gives 6.3125. + * 6.3125 in 4.4 format is b01100101 which is equal to 101. + * Also 85 + 16 = 101. + */ + crtc_state->hw.casf_params.strength = + min(crtc_state->uapi.sharpness_strength, 0xEF) + 0x10; + + intel_casf_compute_win_size(crtc_state); + + return 0; +} + +void intel_casf_sharpness_get_config(struct intel_crtc_state *crtc_state) +{ + struct intel_display *display = to_intel_display(crtc_state); + struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); + u32 sharp; + + sharp = intel_de_read(display, SHARPNESS_CTL(crtc->pipe)); + if (sharp & FILTER_EN) { + if (drm_WARN_ON(display->drm, + REG_FIELD_GET(FILTER_STRENGTH_MASK, sharp) < 16)) + crtc_state->hw.casf_params.strength = 0; + else + crtc_state->hw.casf_params.strength = + REG_FIELD_GET(FILTER_STRENGTH_MASK, sharp); + crtc_state->hw.casf_params.casf_enable = true; + crtc_state->hw.casf_params.win_size = + REG_FIELD_GET(FILTER_SIZE_MASK, sharp); + } +} diff --git a/drivers/gpu/drm/i915/display/intel_casf.h b/drivers/gpu/drm/i915/display/intel_casf.h new file mode 100644 index 000000000000..83523fe66c48 --- /dev/null +++ b/drivers/gpu/drm/i915/display/intel_casf.h @@ -0,0 +1,17 @@ +/* SPDX-License-Identifier: MIT */ +/* + * Copyright © 2025 Intel Corporation + */ + +#ifndef __INTEL_CASF_H__ +#define __INTEL_CASF_H__ + +#include + +struct intel_crtc_state; + +int intel_casf_compute_config(struct intel_crtc_state *crtc_state); +void intel_casf_update_strength(struct intel_crtc_state *new_crtc_state); +void intel_casf_sharpness_get_config(struct intel_crtc_state *crtc_state); + +#endif /* __INTEL_CASF_H__ */ diff --git a/drivers/gpu/drm/i915/display/intel_casf_regs.h b/drivers/gpu/drm/i915/display/intel_casf_regs.h new file mode 100644 index 000000000000..c24ba281ae37 --- /dev/null +++ b/drivers/gpu/drm/i915/display/intel_casf_regs.h @@ -0,0 +1,22 @@ +/* SPDX-License-Identifier: MIT */ +/* + * Copyright © 2025 Intel Corporation + */ + +#ifndef __INTEL_CASF_REGS_H__ +#define __INTEL_CASF_REGS_H__ + +#include "intel_display_reg_defs.h" + +#define _SHARPNESS_CTL_A 0x682B0 +#define _SHARPNESS_CTL_B 0x68AB0 +#define SHARPNESS_CTL(pipe) _MMIO_PIPE(pipe, _SHARPNESS_CTL_A, _SHARPNESS_CTL_B) +#define FILTER_EN REG_BIT(31) +#define FILTER_STRENGTH_MASK REG_GENMASK(15, 8) +#define FILTER_STRENGTH(x) REG_FIELD_PREP(FILTER_STRENGTH_MASK, (x)) +#define FILTER_SIZE_MASK REG_GENMASK(1, 0) +#define SHARPNESS_FILTER_SIZE_3X3 REG_FIELD_PREP(FILTER_SIZE_MASK, 0) +#define SHARPNESS_FILTER_SIZE_5X5 REG_FIELD_PREP(FILTER_SIZE_MASK, 1) +#define SHARPNESS_FILTER_SIZE_7X7 REG_FIELD_PREP(FILTER_SIZE_MASK, 2) + +#endif /* __INTEL_CASF_REGS__ */ diff --git a/drivers/gpu/drm/i915/display/intel_crtc_state_dump.c b/drivers/gpu/drm/i915/display/intel_crtc_state_dump.c index 599ddce96371..66b6fbae8294 100644 --- a/drivers/gpu/drm/i915/display/intel_crtc_state_dump.c +++ b/drivers/gpu/drm/i915/display/intel_crtc_state_dump.c @@ -372,6 +372,13 @@ void intel_crtc_state_dump(const struct intel_crtc_state *pipe_config, intel_vdsc_state_dump(&p, 0, pipe_config); + if (HAS_CASF(i915)) { + drm_printf(&p, "sharpness strength: %d, sharpness tap size :%d\n sharpness enable :%d\n", + pipe_config->hw.casf_params.strength, + pipe_config->hw.casf_params.win_size, + pipe_config->hw.casf_params.casf_enable); + } + dump_planes: if (!state) return; diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h b/drivers/gpu/drm/i915/display/intel_display_types.h index 7d9cc430a6b8..2540a2a1a0e0 100644 --- a/drivers/gpu/drm/i915/display/intel_display_types.h +++ b/drivers/gpu/drm/i915/display/intel_display_types.h @@ -931,6 +931,12 @@ struct intel_csc_matrix { u16 postoff[3]; }; +struct intel_casf { + u8 strength; + u8 win_size; + bool casf_enable; +}; + void intel_io_mmio_fw_write(void *ctx, i915_reg_t reg, u32 val); typedef void (*intel_io_reg_write)(void *ctx, i915_reg_t reg, u32 val); @@ -971,6 +977,7 @@ struct intel_crtc_state { struct drm_property_blob *degamma_lut, *gamma_lut, *ctm; struct drm_display_mode mode, pipe_mode, adjusted_mode; enum drm_scaling_filter scaling_filter; + struct intel_casf casf_params; } hw; /* actual state of LUTs */ diff --git a/drivers/gpu/drm/i915/display/skl_scaler.c b/drivers/gpu/drm/i915/display/skl_scaler.c index ee81220a7c88..f0cf966211c9 100644 --- a/drivers/gpu/drm/i915/display/skl_scaler.c +++ b/drivers/gpu/drm/i915/display/skl_scaler.c @@ -5,6 +5,7 @@ #include "i915_drv.h" #include "i915_reg.h" +#include "intel_casf_regs.h" #include "intel_de.h" #include "intel_display_trace.h" #include "intel_display_types.h" diff --git a/drivers/gpu/drm/xe/Makefile b/drivers/gpu/drm/xe/Makefile index cd464fe26eb8..785bda98973d 100644 --- a/drivers/gpu/drm/xe/Makefile +++ b/drivers/gpu/drm/xe/Makefile @@ -210,6 +210,7 @@ xe-$(CONFIG_DRM_XE_DISPLAY) += \ i915-display/intel_backlight.o \ i915-display/intel_bios.o \ i915-display/intel_bw.o \ + i915-display/intel_casf.o \ i915-display/intel_cdclk.o \ i915-display/intel_cmtg.o \ i915-display/intel_color.o \ From patchwork Fri Mar 21 16:06:20 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Nemesa Garg X-Patchwork-Id: 14025705 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 4A5B9C36005 for ; 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These values are golden values and these value has to be loaded one time while enabling the casf. v2: update commit message[Ankit] Signed-off-by: Nemesa Garg Reviewed-by: Ankit Nautiyal --- drivers/gpu/drm/i915/display/intel_casf.c | 22 +++++++++++++++++++ drivers/gpu/drm/i915/display/intel_casf.h | 3 +++ .../gpu/drm/i915/display/intel_casf_regs.h | 11 ++++++++++ 3 files changed, 36 insertions(+) diff --git a/drivers/gpu/drm/i915/display/intel_casf.c b/drivers/gpu/drm/i915/display/intel_casf.c index 28f76b06fd8f..d0bb51cd4b54 100644 --- a/drivers/gpu/drm/i915/display/intel_casf.c +++ b/drivers/gpu/drm/i915/display/intel_casf.c @@ -25,6 +25,28 @@ * to original image. */ +/* Default LUT values to be loaded one time. */ +static const u16 sharpness_lut[] = { + 4095, 2047, 1364, 1022, 816, 678, 579, + 504, 444, 397, 357, 323, 293, 268, 244, 224, + 204, 187, 170, 154, 139, 125, 111, 98, 85, + 73, 60, 48, 36, 24, 12, 0 +}; + +void intel_filter_lut_load(struct intel_crtc *crtc, + const struct intel_crtc_state *crtc_state) +{ + struct intel_display *display = to_intel_display(crtc_state); + int i; + + intel_de_write(display, SHRPLUT_INDEX(crtc->pipe), + INDEX_AUTO_INCR | INDEX_VALUE(0)); + + for (i = 0; i < ARRAY_SIZE(sharpness_lut); i++) + intel_de_write(display, SHRPLUT_DATA(crtc->pipe), + sharpness_lut[i]); +} + void intel_casf_update_strength(struct intel_crtc_state *crtc_state) { struct intel_display *display = to_intel_display(crtc_state); diff --git a/drivers/gpu/drm/i915/display/intel_casf.h b/drivers/gpu/drm/i915/display/intel_casf.h index 83523fe66c48..80642809c08b 100644 --- a/drivers/gpu/drm/i915/display/intel_casf.h +++ b/drivers/gpu/drm/i915/display/intel_casf.h @@ -9,9 +9,12 @@ #include struct intel_crtc_state; +struct intel_crtc; int intel_casf_compute_config(struct intel_crtc_state *crtc_state); void intel_casf_update_strength(struct intel_crtc_state *new_crtc_state); void intel_casf_sharpness_get_config(struct intel_crtc_state *crtc_state); +void intel_filter_lut_load(struct intel_crtc *crtc, + const struct intel_crtc_state *crtc_state); #endif /* __INTEL_CASF_H__ */ diff --git a/drivers/gpu/drm/i915/display/intel_casf_regs.h b/drivers/gpu/drm/i915/display/intel_casf_regs.h index c24ba281ae37..b96950a48335 100644 --- a/drivers/gpu/drm/i915/display/intel_casf_regs.h +++ b/drivers/gpu/drm/i915/display/intel_casf_regs.h @@ -19,4 +19,15 @@ #define SHARPNESS_FILTER_SIZE_5X5 REG_FIELD_PREP(FILTER_SIZE_MASK, 1) #define SHARPNESS_FILTER_SIZE_7X7 REG_FIELD_PREP(FILTER_SIZE_MASK, 2) +#define _SHRPLUT_DATA_A 0x682B8 +#define _SHRPLUT_DATA_B 0x68AB8 +#define SHRPLUT_DATA(pipe) _MMIO_PIPE(pipe, _SHRPLUT_DATA_A, _SHRPLUT_DATA_B) + +#define _SHRPLUT_INDEX_A 0x682B4 +#define _SHRPLUT_INDEX_B 0x68AB4 +#define SHRPLUT_INDEX(pipe) _MMIO_PIPE(pipe, _SHRPLUT_INDEX_A, _SHRPLUT_INDEX_B) +#define INDEX_AUTO_INCR REG_BIT(10) +#define INDEX_VALUE_MASK REG_GENMASK(4, 0) +#define INDEX_VALUE(x) REG_FIELD_PREP(INDEX_VALUE_MASK, (x)) + #endif /* __INTEL_CASF_REGS__ */ From patchwork Fri Mar 21 16:06:21 2025 Content-Type: text/plain; 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d="scan'208";a="128554954" Received: from nemesa.iind.intel.com ([10.190.239.22]) by fmviesa004.fm.intel.com with ESMTP; 21 Mar 2025 09:11:48 -0700 From: Nemesa Garg To: intel-gfx@lists.freedesktop.org, intel-xe@lists.freedesktop.org, dri-devel@lists.freedesktop.org Cc: Nemesa Garg , Ankit Nautiyal Subject: [PATCH 05/12] drm/i915/display: Compute the scaler filter Date: Fri, 21 Mar 2025 21:36:21 +0530 Message-Id: <20250321160628.2663912-6-nemesa.garg@intel.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20250321160628.2663912-1-nemesa.garg@intel.com> References: <20250321160628.2663912-1-nemesa.garg@intel.com> MIME-Version: 1.0 X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" coefficients The sharpness property requires the use of one of the scaler so need to set the sharpness scaler coefficient values. These values are based on experiments and vary for different tap value/win size. These values are normalized by taking the sum of all values and then dividing each value with a sum. v2: Fix ifndef header naming issue reported by kernel test robot v3: Rename file name[Arun] Replace array size number with macro[Arun] v4: Correct the register format[Jani] Add brief comment and expalin about file[Jani] Remove coefficient value from crtc_state[Jani] v5: Fix build issue v6: Add new function for writing coefficients[Ankit] v7: Add cooments and add a scaler id check [Ankit] v8: Remove casf_enable from here[Ankit] Signed-off-by: Nemesa Garg Reviewed-by: Ankit Nautiyal --- drivers/gpu/drm/i915/display/intel_casf.c | 120 ++++++++++++++++++ drivers/gpu/drm/i915/display/intel_casf.h | 1 + .../gpu/drm/i915/display/intel_casf_regs.h | 7 + .../drm/i915/display/intel_display_types.h | 8 ++ 4 files changed, 136 insertions(+) diff --git a/drivers/gpu/drm/i915/display/intel_casf.c b/drivers/gpu/drm/i915/display/intel_casf.c index d0bb51cd4b54..eb69c449a2f5 100644 --- a/drivers/gpu/drm/i915/display/intel_casf.c +++ b/drivers/gpu/drm/i915/display/intel_casf.c @@ -12,6 +12,13 @@ #define MAX_PIXELS_FOR_3_TAP_FILTER (1920 * 1080) #define MAX_PIXELS_FOR_5_TAP_FILTER (3840 * 2160) +#define FILTER_COEFF_0_125 125 +#define FILTER_COEFF_0_25 250 +#define FILTER_COEFF_0_5 500 +#define FILTER_COEFF_1_0 1000 +#define FILTER_COEFF_0_0 0 +#define SET_POSITIVE_SIGN(x) ((x) & (~SIGN)) + /** * DOC: Content Adaptive Sharpness Filter (CASF) * @@ -33,6 +40,24 @@ static const u16 sharpness_lut[] = { 73, 60, 48, 36, 24, 12, 0 }; +const u16 filtercoeff_1[] = { + FILTER_COEFF_0_0, FILTER_COEFF_0_0, FILTER_COEFF_0_5, + FILTER_COEFF_1_0, FILTER_COEFF_0_5, FILTER_COEFF_0_0, + FILTER_COEFF_0_0, +}; + +const u16 filtercoeff_2[] = { + FILTER_COEFF_0_0, FILTER_COEFF_0_25, FILTER_COEFF_0_5, + FILTER_COEFF_1_0, FILTER_COEFF_0_5, FILTER_COEFF_0_25, + FILTER_COEFF_0_0, +}; + +const u16 filtercoeff_3[] = { + FILTER_COEFF_0_125, FILTER_COEFF_0_25, FILTER_COEFF_0_5, + FILTER_COEFF_1_0, FILTER_COEFF_0_5, FILTER_COEFF_0_25, + FILTER_COEFF_0_125, +}; + void intel_filter_lut_load(struct intel_crtc *crtc, const struct intel_crtc_state *crtc_state) { @@ -97,6 +122,8 @@ int intel_casf_compute_config(struct intel_crtc_state *crtc_state) intel_casf_compute_win_size(crtc_state); + intel_casf_scaler_compute_config(crtc_state); + return 0; } @@ -119,3 +146,96 @@ void intel_casf_sharpness_get_config(struct intel_crtc_state *crtc_state) REG_FIELD_GET(FILTER_SIZE_MASK, sharp); } } + +static int casf_coeff_tap(int i) +{ + return i % SCALER_FILTER_NUM_TAPS; +} + +static u16 casf_coeff(struct intel_crtc_state *crtc_state, int t) +{ + struct scaler_filter_coeff value; + u16 coeff; + + value = crtc_state->hw.casf_params.coeff[t]; + coeff = SET_POSITIVE_SIGN(0) | EXPONENT(value.exp) | MANTISSA(value.mantissa); + return coeff; +} + +/* + * 17 phase of 7 taps requires 119 coefficients in 60 dwords per set. + * To enable casf: program scaler coefficients with the coeffients + * that are calculated and stored in hw.casf_params.coeff as per + * SCALER_COEFFICIENT_FORMAT + */ +static void intel_casf_write_coeff(struct intel_crtc_state *crtc_state) +{ + struct intel_display *display = to_intel_display(crtc_state); + struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); + int id = crtc_state->scaler_state.scaler_id; + int i; + + if (id != 1) { + drm_WARN(display->drm, 0, "Second scaler not enabled\n"); + return; + } + + intel_de_write_fw(display, GLK_PS_COEF_INDEX_SET(crtc->pipe, id, 0), + PS_COEF_INDEX_AUTO_INC); + + for (i = 0; i < 17 * SCALER_FILTER_NUM_TAPS; i += 2) { + u32 tmp; + int t; + + t = casf_coeff_tap(i); + tmp = casf_coeff(crtc_state, t); + + t = casf_coeff_tap(i + 1); + tmp |= casf_coeff(crtc_state, t) << 16; + + intel_de_write_fw(display, GLK_PS_COEF_DATA_SET(crtc->pipe, id, 0), + tmp); + } +} + +static void convert_sharpness_coef_binary(struct scaler_filter_coeff *coeff, + u16 coefficient) +{ + if (coefficient < 25) { + coeff->mantissa = (coefficient * 2048) / 100; + coeff->exp = 3; + } else if (coefficient < 50) { + coeff->mantissa = (coefficient * 1024) / 100; + coeff->exp = 2; + } else if (coefficient < 100) { + coeff->mantissa = (coefficient * 512) / 100; + coeff->exp = 1; + } else { + coeff->mantissa = (coefficient * 256) / 100; + coeff->exp = 0; + } +} + +void intel_casf_scaler_compute_config(struct intel_crtc_state *crtc_state) +{ + const u16 *filtercoeff; + u16 filter_coeff[SCALER_FILTER_NUM_TAPS]; + u16 sumcoeff = 0; + u8 i; + + if (crtc_state->hw.casf_params.win_size == 0) + filtercoeff = filtercoeff_1; + else if (crtc_state->hw.casf_params.win_size == 1) + filtercoeff = filtercoeff_2; + else + filtercoeff = filtercoeff_3; + + for (i = 0; i < SCALER_FILTER_NUM_TAPS; i++) + sumcoeff += *(filtercoeff + i); + + for (i = 0; i < SCALER_FILTER_NUM_TAPS; i++) { + filter_coeff[i] = (*(filtercoeff + i) * 100 / sumcoeff); + convert_sharpness_coef_binary(&crtc_state->hw.casf_params.coeff[i], + filter_coeff[i]); + } +} diff --git a/drivers/gpu/drm/i915/display/intel_casf.h b/drivers/gpu/drm/i915/display/intel_casf.h index 80642809c08b..381d5e10c70d 100644 --- a/drivers/gpu/drm/i915/display/intel_casf.h +++ b/drivers/gpu/drm/i915/display/intel_casf.h @@ -16,5 +16,6 @@ void intel_casf_update_strength(struct intel_crtc_state *new_crtc_state); void intel_casf_sharpness_get_config(struct intel_crtc_state *crtc_state); void intel_filter_lut_load(struct intel_crtc *crtc, const struct intel_crtc_state *crtc_state); +void intel_casf_scaler_compute_config(struct intel_crtc_state *crtc_state); #endif /* __INTEL_CASF_H__ */ diff --git a/drivers/gpu/drm/i915/display/intel_casf_regs.h b/drivers/gpu/drm/i915/display/intel_casf_regs.h index b96950a48335..f8c3c86f2949 100644 --- a/drivers/gpu/drm/i915/display/intel_casf_regs.h +++ b/drivers/gpu/drm/i915/display/intel_casf_regs.h @@ -30,4 +30,11 @@ #define INDEX_VALUE_MASK REG_GENMASK(4, 0) #define INDEX_VALUE(x) REG_FIELD_PREP(INDEX_VALUE_MASK, (x)) +/* Scaler Coefficient structure */ +#define SIGN REG_BIT(15) +#define EXPONENT_MASK REG_GENMASK(13, 12) +#define EXPONENT(x) REG_FIELD_PREP(EXPONENT_MASK, (x)) +#define MANTISSA_MASK REG_GENMASK(11, 3) +#define MANTISSA(x) REG_FIELD_PREP(MANTISSA_MASK, (x)) + #endif /* __INTEL_CASF_REGS__ */ diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h b/drivers/gpu/drm/i915/display/intel_display_types.h index 2540a2a1a0e0..b2dcdbc6b81c 100644 --- a/drivers/gpu/drm/i915/display/intel_display_types.h +++ b/drivers/gpu/drm/i915/display/intel_display_types.h @@ -931,7 +931,15 @@ struct intel_csc_matrix { u16 postoff[3]; }; +struct scaler_filter_coeff { + u16 sign; + u16 exp; + u16 mantissa; +}; + struct intel_casf { +#define SCALER_FILTER_NUM_TAPS 7 + struct scaler_filter_coeff coeff[SCALER_FILTER_NUM_TAPS]; u8 strength; u8 win_size; bool casf_enable; From patchwork Fri Mar 21 16:06:22 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Nemesa Garg X-Patchwork-Id: 14025706 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id E6D3CC36000 for ; Fri, 21 Mar 2025 16:11:53 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 4E49310E804; Fri, 21 Mar 2025 16:11:53 +0000 (UTC) Authentication-Results: gabe.freedesktop.org; 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a="66308473" X-IronPort-AV: E=Sophos;i="6.14,264,1736841600"; d="scan'208";a="66308473" Received: from fmviesa004.fm.intel.com ([10.60.135.144]) by orvoesa101.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 21 Mar 2025 09:11:51 -0700 X-CSE-ConnectionGUID: mUoMCsFBQ3aWX9UcLqMsdA== X-CSE-MsgGUID: aAYN7Z04TgSvwH6yNMl94Q== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.14,264,1736841600"; d="scan'208";a="128554958" Received: from nemesa.iind.intel.com ([10.190.239.22]) by fmviesa004.fm.intel.com with ESMTP; 21 Mar 2025 09:11:50 -0700 From: Nemesa Garg To: intel-gfx@lists.freedesktop.org, intel-xe@lists.freedesktop.org, dri-devel@lists.freedesktop.org Cc: Nemesa Garg , Ankit Nautiyal Subject: [PATCH 06/12] drm/i915/display: Add and compute scaler parameter Date: Fri, 21 Mar 2025 21:36:22 +0530 Message-Id: <20250321160628.2663912-7-nemesa.garg@intel.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20250321160628.2663912-1-nemesa.garg@intel.com> References: <20250321160628.2663912-1-nemesa.garg@intel.com> MIME-Version: 1.0 X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" Compute the values for second scaler for sharpness. Fill the register bits corresponding to the scaler. v1: Rename the title of patch [Ankit] v2: Remove setup_casf from here[Ankit] Signed-off-by: Nemesa Garg Reviewed-by: Ankit Nautiyal --- drivers/gpu/drm/i915/display/intel_casf.c | 1 + drivers/gpu/drm/i915/display/skl_scaler.c | 46 +++++++++++++++++++++++ drivers/gpu/drm/i915/display/skl_scaler.h | 1 + 3 files changed, 48 insertions(+) diff --git a/drivers/gpu/drm/i915/display/intel_casf.c b/drivers/gpu/drm/i915/display/intel_casf.c index eb69c449a2f5..4c41a41872bd 100644 --- a/drivers/gpu/drm/i915/display/intel_casf.c +++ b/drivers/gpu/drm/i915/display/intel_casf.c @@ -8,6 +8,7 @@ #include "intel_casf_regs.h" #include "intel_de.h" #include "intel_display_types.h" +#include "skl_scaler.h" #define MAX_PIXELS_FOR_3_TAP_FILTER (1920 * 1080) #define MAX_PIXELS_FOR_5_TAP_FILTER (3840 * 2160) diff --git a/drivers/gpu/drm/i915/display/skl_scaler.c b/drivers/gpu/drm/i915/display/skl_scaler.c index f0cf966211c9..39fc537e54f0 100644 --- a/drivers/gpu/drm/i915/display/skl_scaler.c +++ b/drivers/gpu/drm/i915/display/skl_scaler.c @@ -133,6 +133,13 @@ static void skl_scaler_max_dst_size(struct intel_crtc *crtc, } } +#define CASF_SCALER_FILTER_SELECT \ + (PS_FILTER_PROGRAMMED | \ + PS_Y_VERT_FILTER_SELECT(0) | \ + PS_Y_HORZ_FILTER_SELECT(0) | \ + PS_UV_VERT_FILTER_SELECT(0) | \ + PS_UV_HORZ_FILTER_SELECT(0)) + static int skl_update_scaler(struct intel_crtc_state *crtc_state, bool force_detach, unsigned int scaler_user, int *scaler_id, @@ -722,6 +729,45 @@ static void skl_scaler_setup_filter(struct intel_display *display, } } +void skl_scaler_setup_casf(struct intel_crtc_state *crtc_state) +{ + struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); + struct intel_display *display = to_intel_display(crtc); + struct drm_display_mode *adjusted_mode = + &crtc_state->hw.adjusted_mode; + struct intel_crtc_scaler_state *scaler_state = + &crtc_state->scaler_state; + struct drm_rect src, dest; + int id, width, height; + int x = 0, y = 0; + enum pipe pipe = crtc->pipe; + u32 ps_ctrl; + + width = adjusted_mode->crtc_hdisplay; + height = adjusted_mode->crtc_vdisplay; + + drm_rect_init(&dest, x, y, width, height); + + width = drm_rect_width(&dest); + height = drm_rect_height(&dest); + id = scaler_state->scaler_id; + + drm_rect_init(&src, 0, 0, + drm_rect_width(&crtc_state->pipe_src) << 16, + drm_rect_height(&crtc_state->pipe_src) << 16); + + trace_intel_pipe_scaler_update_arm(crtc, id, x, y, width, height); + + ps_ctrl = PS_SCALER_EN | PS_BINDING_PIPE | scaler_state->scalers[id].mode | + CASF_SCALER_FILTER_SELECT; + + intel_de_write_fw(display, SKL_PS_CTRL(pipe, id), ps_ctrl); + intel_de_write_fw(display, SKL_PS_WIN_POS(pipe, id), + PS_WIN_XPOS(x) | PS_WIN_YPOS(y)); + intel_de_write_fw(display, SKL_PS_WIN_SZ(pipe, id), + PS_WIN_XSIZE(width) | PS_WIN_YSIZE(height)); +} + void skl_pfit_enable(const struct intel_crtc_state *crtc_state) { struct intel_display *display = to_intel_display(crtc_state); diff --git a/drivers/gpu/drm/i915/display/skl_scaler.h b/drivers/gpu/drm/i915/display/skl_scaler.h index 355ea15260ca..22fcfe78b506 100644 --- a/drivers/gpu/drm/i915/display/skl_scaler.h +++ b/drivers/gpu/drm/i915/display/skl_scaler.h @@ -31,5 +31,6 @@ void skl_detach_scalers(struct intel_dsb *dsb, void skl_scaler_disable(const struct intel_crtc_state *old_crtc_state); void skl_scaler_get_config(struct intel_crtc_state *crtc_state); +void skl_scaler_setup_casf(struct intel_crtc_state *crtc_state); #endif From patchwork Fri Mar 21 16:06:23 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Nemesa Garg X-Patchwork-Id: 14025708 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id D5CA1C36007 for ; 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X-CSE-ConnectionGUID: z34Y+6wXTFCfHLDrwJZnmw== X-CSE-MsgGUID: dktpiJjqRa6WmuIf0gUVGg== X-IronPort-AV: E=McAfee;i="6700,10204,11380"; a="66308475" X-IronPort-AV: E=Sophos;i="6.14,264,1736841600"; d="scan'208";a="66308475" Received: from fmviesa004.fm.intel.com ([10.60.135.144]) by orvoesa101.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 21 Mar 2025 09:11:53 -0700 X-CSE-ConnectionGUID: 381sktXORU6p2945ti+WQg== X-CSE-MsgGUID: WjIU1sGISnyJYJcyGmZ0Ew== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.14,264,1736841600"; d="scan'208";a="128554962" Received: from nemesa.iind.intel.com ([10.190.239.22]) by fmviesa004.fm.intel.com with ESMTP; 21 Mar 2025 09:11:52 -0700 From: Nemesa Garg To: intel-gfx@lists.freedesktop.org, intel-xe@lists.freedesktop.org, dri-devel@lists.freedesktop.org Cc: Nemesa Garg Subject: [PATCH 07/12] drm/i915/display: Configure the second scaler for Date: Fri, 21 Mar 2025 21:36:23 +0530 Message-Id: <20250321160628.2663912-8-nemesa.garg@intel.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20250321160628.2663912-1-nemesa.garg@intel.com> References: <20250321160628.2663912-1-nemesa.garg@intel.com> MIME-Version: 1.0 X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" sharpness As only second scaler can be used for sharpness check if it is available and also check if panel fitting is not enabled, then set the sharpness as both uses pipe scaler so only one can be enabled at a time. v2: Add the panel fitting check before enabling sharpness v3: Reframe commit message[Arun] v4: Replace string based comparison with plane_state[Jani] v5: Rebase v6: Fix build issue v7: Remove scaler id from verify_crtc_state[Ankit] v8: Change the patch title. Add code comment. Move the config part in patch#6. [Ankit] v9: Refactor the patch[Ankit] Signed-off-by: Nemesa Garg --- drivers/gpu/drm/i915/display/intel_casf.c | 8 +++++++ drivers/gpu/drm/i915/display/intel_casf.h | 1 + drivers/gpu/drm/i915/display/intel_display.c | 4 +++- drivers/gpu/drm/i915/display/skl_scaler.c | 25 +++++++++++++++----- 4 files changed, 31 insertions(+), 7 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_casf.c b/drivers/gpu/drm/i915/display/intel_casf.c index 4c41a41872bd..367a73a91ae6 100644 --- a/drivers/gpu/drm/i915/display/intel_casf.c +++ b/drivers/gpu/drm/i915/display/intel_casf.c @@ -148,6 +148,14 @@ void intel_casf_sharpness_get_config(struct intel_crtc_state *crtc_state) } } +bool intel_casf_needs_scaler(const struct intel_crtc_state *crtc_state) +{ + if (crtc_state->hw.casf_params.casf_enable) + return true; + + return false; +} + static int casf_coeff_tap(int i) { return i % SCALER_FILTER_NUM_TAPS; diff --git a/drivers/gpu/drm/i915/display/intel_casf.h b/drivers/gpu/drm/i915/display/intel_casf.h index 381d5e10c70d..026a2b8348df 100644 --- a/drivers/gpu/drm/i915/display/intel_casf.h +++ b/drivers/gpu/drm/i915/display/intel_casf.h @@ -17,5 +17,6 @@ void intel_casf_sharpness_get_config(struct intel_crtc_state *crtc_state); void intel_filter_lut_load(struct intel_crtc *crtc, const struct intel_crtc_state *crtc_state); void intel_casf_scaler_compute_config(struct intel_crtc_state *crtc_state); +bool intel_casf_needs_scaler(const struct intel_crtc_state *crtc_state); #endif /* __INTEL_CASF_H__ */ diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c index b852ffe94a10..4ffe738ad725 100644 --- a/drivers/gpu/drm/i915/display/intel_display.c +++ b/drivers/gpu/drm/i915/display/intel_display.c @@ -60,6 +60,7 @@ #include "intel_audio.h" #include "intel_bo.h" #include "intel_bw.h" +#include "intel_casf.h" #include "intel_cdclk.h" #include "intel_clock_gating.h" #include "intel_color.h" @@ -4225,7 +4226,8 @@ static int intel_crtc_atomic_check(struct intel_atomic_state *state, if (DISPLAY_VER(display) >= 9) { if (intel_crtc_needs_modeset(crtc_state) || - intel_crtc_needs_fastset(crtc_state)) { + intel_crtc_needs_fastset(crtc_state) || + intel_casf_needs_scaler(crtc_state)) { ret = skl_update_scaler_crtc(crtc_state); if (ret) return ret; diff --git a/drivers/gpu/drm/i915/display/skl_scaler.c b/drivers/gpu/drm/i915/display/skl_scaler.c index 39fc537e54f0..d816dae9cec4 100644 --- a/drivers/gpu/drm/i915/display/skl_scaler.c +++ b/drivers/gpu/drm/i915/display/skl_scaler.c @@ -5,6 +5,7 @@ #include "i915_drv.h" #include "i915_reg.h" +#include "intel_casf.h" #include "intel_casf_regs.h" #include "intel_de.h" #include "intel_display_trace.h" @@ -272,7 +273,8 @@ int skl_update_scaler_crtc(struct intel_crtc_state *crtc_state) drm_rect_width(&crtc_state->pipe_src), drm_rect_height(&crtc_state->pipe_src), width, height, NULL, 0, - crtc_state->pch_pfit.enabled); + crtc_state->pch_pfit.enabled || + intel_casf_needs_scaler(crtc_state)); } /** @@ -311,7 +313,9 @@ int skl_update_scaler_plane(struct intel_crtc_state *crtc_state, } static int intel_allocate_scaler(struct intel_crtc_scaler_state *scaler_state, - struct intel_crtc *crtc) + struct intel_crtc *crtc, + struct intel_plane_state *plane_state, + bool casf_scaler) { int i; @@ -319,6 +323,10 @@ static int intel_allocate_scaler(struct intel_crtc_scaler_state *scaler_state, if (scaler_state->scalers[i].in_use) continue; + /* CASF needs second scaler */ + if (!plane_state && casf_scaler && i != 1) + continue; + scaler_state->scalers[i].in_use = true; return i; @@ -369,7 +377,7 @@ static int intel_atomic_setup_scaler(struct intel_crtc_state *crtc_state, int num_scalers_need, struct intel_crtc *crtc, const char *name, int idx, struct intel_plane_state *plane_state, - int *scaler_id) + int *scaler_id, bool casf_scaler) { struct intel_display *display = to_intel_display(crtc); struct intel_crtc_scaler_state *scaler_state = &crtc_state->scaler_state; @@ -378,7 +386,7 @@ static int intel_atomic_setup_scaler(struct intel_crtc_state *crtc_state, int vscale = 0; if (*scaler_id < 0) - *scaler_id = intel_allocate_scaler(scaler_state, crtc); + *scaler_id = intel_allocate_scaler(scaler_state, crtc, plane_state, casf_scaler); if (drm_WARN(display->drm, *scaler_id < 0, "Cannot find scaler for %s:%d\n", name, idx)) @@ -510,10 +518,14 @@ static int setup_crtc_scaler(struct intel_atomic_state *state, struct intel_crtc_scaler_state *scaler_state = &crtc_state->scaler_state; + if (intel_casf_needs_scaler(crtc_state) && crtc_state->pch_pfit.enabled) + return -EINVAL; + return intel_atomic_setup_scaler(crtc_state, hweight32(scaler_state->scaler_users), crtc, "CRTC", crtc->base.base.id, - NULL, &scaler_state->scaler_id); + NULL, &scaler_state->scaler_id, + intel_casf_needs_scaler(crtc_state)); } static int setup_plane_scaler(struct intel_atomic_state *state, @@ -548,7 +560,8 @@ static int setup_plane_scaler(struct intel_atomic_state *state, return intel_atomic_setup_scaler(crtc_state, hweight32(scaler_state->scaler_users), crtc, "PLANE", plane->base.base.id, - plane_state, &plane_state->scaler_id); + plane_state, &plane_state->scaler_id, + false); } /** From patchwork Fri Mar 21 16:06:24 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Nemesa Garg X-Patchwork-Id: 14025709 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 29624C3600D for ; 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X-CSE-ConnectionGUID: CQrwKmCpQC+oZYINjg4zjQ== X-CSE-MsgGUID: lVvlOmhFQPugQQX6djy5vQ== X-IronPort-AV: E=McAfee;i="6700,10204,11380"; a="66308477" X-IronPort-AV: E=Sophos;i="6.14,264,1736841600"; d="scan'208";a="66308477" Received: from fmviesa004.fm.intel.com ([10.60.135.144]) by orvoesa101.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 21 Mar 2025 09:11:55 -0700 X-CSE-ConnectionGUID: GjpxnUbbQNOxeAzkPYbPZA== X-CSE-MsgGUID: dPAWOGFkS22SeP6Gb+7Xtg== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.14,264,1736841600"; d="scan'208";a="128554975" Received: from nemesa.iind.intel.com ([10.190.239.22]) by fmviesa004.fm.intel.com with ESMTP; 21 Mar 2025 09:11:54 -0700 From: Nemesa Garg To: intel-gfx@lists.freedesktop.org, intel-xe@lists.freedesktop.org, dri-devel@lists.freedesktop.org Cc: Nemesa Garg Subject: [PATCH 08/12] drm/i915/display: Compare the sharpness state Date: Fri, 21 Mar 2025 21:36:24 +0530 Message-Id: <20250321160628.2663912-9-nemesa.garg@intel.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20250321160628.2663912-1-nemesa.garg@intel.com> References: <20250321160628.2663912-1-nemesa.garg@intel.com> MIME-Version: 1.0 X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" Compare the sharpness win_size, strength and enable bits Signed-off-by: Nemesa Garg --- drivers/gpu/drm/i915/display/intel_display.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c index 4ffe738ad725..f807915e0fee 100644 --- a/drivers/gpu/drm/i915/display/intel_display.c +++ b/drivers/gpu/drm/i915/display/intel_display.c @@ -5276,6 +5276,9 @@ intel_pipe_config_compare(const struct intel_crtc_state *current_config, PIPE_CONF_CHECK_I(scaler_state.scaler_id); PIPE_CONF_CHECK_I(pixel_rate); + PIPE_CONF_CHECK_BOOL(hw.casf_params.casf_enable); + PIPE_CONF_CHECK_I(hw.casf_params.win_size); + PIPE_CONF_CHECK_I(hw.casf_params.strength); PIPE_CONF_CHECK_X(gamma_mode); if (display->platform.cherryview) From patchwork Fri Mar 21 16:06:25 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Nemesa Garg X-Patchwork-Id: 14025710 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 7023EC36000 for ; Fri, 21 Mar 2025 16:12:00 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 9240510E80C; Fri, 21 Mar 2025 16:11:58 +0000 (UTC) Authentication-Results: gabe.freedesktop.org; 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a="66308479" X-IronPort-AV: E=Sophos;i="6.14,264,1736841600"; d="scan'208";a="66308479" Received: from fmviesa004.fm.intel.com ([10.60.135.144]) by orvoesa101.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 21 Mar 2025 09:11:56 -0700 X-CSE-ConnectionGUID: 9d4/uSdBQKWNnpWOWDsJ1w== X-CSE-MsgGUID: 0sWmz0iUTfuCmfBfTma6iA== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.14,264,1736841600"; d="scan'208";a="128554988" Received: from nemesa.iind.intel.com ([10.190.239.22]) by fmviesa004.fm.intel.com with ESMTP; 21 Mar 2025 09:11:55 -0700 From: Nemesa Garg To: intel-gfx@lists.freedesktop.org, intel-xe@lists.freedesktop.org, dri-devel@lists.freedesktop.org Cc: Nemesa Garg Subject: [PATCH 09/12] drm/i915/display: Set a scaler mode Date: Fri, 21 Mar 2025 21:36:25 +0530 Message-Id: <20250321160628.2663912-10-nemesa.garg@intel.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20250321160628.2663912-1-nemesa.garg@intel.com> References: <20250321160628.2663912-1-nemesa.garg@intel.com> MIME-Version: 1.0 X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" Set the mode of scaler to HQ for casf. Signed-off-by: Nemesa Garg --- drivers/gpu/drm/i915/display/skl_scaler.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/drivers/gpu/drm/i915/display/skl_scaler.c b/drivers/gpu/drm/i915/display/skl_scaler.c index d816dae9cec4..93a847c05535 100644 --- a/drivers/gpu/drm/i915/display/skl_scaler.c +++ b/drivers/gpu/drm/i915/display/skl_scaler.c @@ -392,6 +392,9 @@ static int intel_atomic_setup_scaler(struct intel_crtc_state *crtc_state, "Cannot find scaler for %s:%d\n", name, idx)) return -EINVAL; + if (casf_scaler) + mode = SKL_PS_SCALER_MODE_HQ; + /* set scaler mode */ if (plane_state && plane_state->hw.fb && plane_state->hw.fb->format->is_yuv && From patchwork Fri Mar 21 16:06:26 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Nemesa Garg X-Patchwork-Id: 14025711 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id EDD59C36007 for ; Fri, 21 Mar 2025 16:12:00 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 102A510E813; Fri, 21 Mar 2025 16:11:59 +0000 (UTC) Authentication-Results: gabe.freedesktop.org; dkim=pass (2048-bit key; unprotected) header.d=intel.com header.i=@intel.com header.b="bfKCaKs7"; dkim-atps=neutral Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.9]) by gabe.freedesktop.org (Postfix) with ESMTPS id 58CC510E80F; Fri, 21 Mar 2025 16:11:58 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1742573518; x=1774109518; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=e8+S6DI7rbwbylk84oUC7wm45fpSaE4R6d3QUi98Th0=; b=bfKCaKs7YQoPrEJ9R2D73p/untlgM8ewwRlLU4vEO5SlyLwUOrXl5vyn ynOUfLGfFwuKkG9KgZeLYjcDIDXpL/JQTdeR16VVgCMfehEODOUtVDXRW IL6UM+GAnTLj1UJv8PmCbnDr95MNVZ7gNKNt9pI92W+vVstvKvDKWM6DH pZcH+1wZicmC+OUbAxJ69/Pp5BpaeWZxb1e3YFt247B/1n6NBlwgKwGgu qG9dt77aOTqu7o8+B0nRV+TQRMIhAVIRdFVPzdCCnrHFmRcRe7N/+cVUY 2uGAiH3usgps3tnYjFV161JX5GRHyCey5sf2s6D5NsMXKcjs9EUNRg3XH Q==; X-CSE-ConnectionGUID: kbnA/HLSQC+gmXKHsTM8KQ== X-CSE-MsgGUID: 4YZbhfq6SC2gAIABaj5Dsw== X-IronPort-AV: E=McAfee;i="6700,10204,11380"; a="66308481" X-IronPort-AV: E=Sophos;i="6.14,264,1736841600"; d="scan'208";a="66308481" Received: from fmviesa004.fm.intel.com ([10.60.135.144]) by orvoesa101.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 21 Mar 2025 09:11:58 -0700 X-CSE-ConnectionGUID: OzoK11kIS1Cwc4jo8LnCVw== X-CSE-MsgGUID: 8GWzYWFVRn+etnhExcyGVQ== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.14,264,1736841600"; d="scan'208";a="128555003" Received: from nemesa.iind.intel.com ([10.190.239.22]) by fmviesa004.fm.intel.com with ESMTP; 21 Mar 2025 09:11:57 -0700 From: Nemesa Garg To: intel-gfx@lists.freedesktop.org, intel-xe@lists.freedesktop.org, dri-devel@lists.freedesktop.org Cc: Nemesa Garg Subject: [PATCH 10/12] drm/i915/display: Write and read back the casf registers Date: Fri, 21 Mar 2025 21:36:26 +0530 Message-Id: <20250321160628.2663912-11-nemesa.garg@intel.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20250321160628.2663912-1-nemesa.garg@intel.com> References: <20250321160628.2663912-1-nemesa.garg@intel.com> MIME-Version: 1.0 X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" Write the casf registers bits to enable the sharpness and to compute the strength of casf using casf_compute_config. Also verify whether the enable bit is set or not and strength value is correctly updated. v2: Update subject[Ankit] Signed-off-by: Nemesa Garg --- drivers/gpu/drm/i915/display/intel_display.c | 4 ++++ drivers/gpu/drm/i915/display/skl_scaler.c | 18 ++++++++++++------ 2 files changed, 16 insertions(+), 6 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c index f807915e0fee..d6691cb07173 100644 --- a/drivers/gpu/drm/i915/display/intel_display.c +++ b/drivers/gpu/drm/i915/display/intel_display.c @@ -4224,6 +4224,10 @@ static int intel_crtc_atomic_check(struct intel_atomic_state *state, return ret; } + ret = intel_casf_compute_config(crtc_state); + if (ret) + return ret; + if (DISPLAY_VER(display) >= 9) { if (intel_crtc_needs_modeset(crtc_state) || intel_crtc_needs_fastset(crtc_state) || diff --git a/drivers/gpu/drm/i915/display/skl_scaler.c b/drivers/gpu/drm/i915/display/skl_scaler.c index 93a847c05535..6ddc111d5c29 100644 --- a/drivers/gpu/drm/i915/display/skl_scaler.c +++ b/drivers/gpu/drm/i915/display/skl_scaler.c @@ -964,16 +964,22 @@ void skl_scaler_get_config(struct intel_crtc_state *crtc_state) continue; id = i; - crtc_state->pch_pfit.enabled = true; + + if (HAS_CASF(display) && id == 1) + intel_casf_sharpness_get_config(crtc_state); + + if (!crtc_state->hw.casf_params.casf_enable) + crtc_state->pch_pfit.enabled = true; pos = intel_de_read(display, SKL_PS_WIN_POS(crtc->pipe, i)); size = intel_de_read(display, SKL_PS_WIN_SZ(crtc->pipe, i)); - drm_rect_init(&crtc_state->pch_pfit.dst, - REG_FIELD_GET(PS_WIN_XPOS_MASK, pos), - REG_FIELD_GET(PS_WIN_YPOS_MASK, pos), - REG_FIELD_GET(PS_WIN_XSIZE_MASK, size), - REG_FIELD_GET(PS_WIN_YSIZE_MASK, size)); + if (!crtc_state->hw.casf_params.casf_enable) + drm_rect_init(&crtc_state->pch_pfit.dst, + REG_FIELD_GET(PS_WIN_XPOS_MASK, pos), + REG_FIELD_GET(PS_WIN_YPOS_MASK, pos), + REG_FIELD_GET(PS_WIN_XSIZE_MASK, size), + REG_FIELD_GET(PS_WIN_YSIZE_MASK, size)); scaler_state->scalers[i].in_use = true; break; From patchwork Fri Mar 21 16:06:27 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Nemesa Garg X-Patchwork-Id: 14025713 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 336ADC3600A for ; Fri, 21 Mar 2025 16:12:05 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 51F9410E818; Fri, 21 Mar 2025 16:12:04 +0000 (UTC) Authentication-Results: gabe.freedesktop.org; dkim=pass (2048-bit key; unprotected) header.d=intel.com header.i=@intel.com header.b="Yl9KHaLj"; dkim-atps=neutral Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.9]) by gabe.freedesktop.org (Postfix) with ESMTPS id 6588A10E808; Fri, 21 Mar 2025 16:12:00 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1742573520; x=1774109520; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=A7NiCHKwlqak0QUysfKKFCPJgllQ6uAWCs4MaPR82bY=; b=Yl9KHaLj4s4AVpPisDyeyi7H1lay3i8P0BQ34qMrRSIKncvjHE1eRiIg z03qZvUfmd19VVXq8HRFmHiacFl8KMPLc5PSj2Raff0lg0UlbsUvr6exd EHdmXxxBZ7bn9cwpI080kSMjWMllA4RPccRGvpQTw8YKT8dSybfuI7UI6 HtOaIVY9VFDzKM5pd3oDfTBtQMVS/FX6LDcOGmbVn70KNAnI1wHjfyjOM s6gM66I8Jhp2CbGAsRY50FpHRTl7mP+qTAE5NgLY6+Lkpk+xbXji52V3k qNlPbVcDxZZDY+2Pce4YoIIszC0GZi9WzijbPM6Qzz/tir8wON4MIrGzj A==; X-CSE-ConnectionGUID: igGBiUFUSMWRMj2JRKTTnw== X-CSE-MsgGUID: QoxP5mqZQDaI0FfJoP733A== X-IronPort-AV: E=McAfee;i="6700,10204,11380"; a="66308484" X-IronPort-AV: E=Sophos;i="6.14,264,1736841600"; d="scan'208";a="66308484" Received: from fmviesa004.fm.intel.com ([10.60.135.144]) by orvoesa101.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 21 Mar 2025 09:12:00 -0700 X-CSE-ConnectionGUID: AH/b0IsTQXeK2Th8Gf2Fyg== X-CSE-MsgGUID: mopYiPPUSAC5aWtxerOu/Q== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.14,264,1736841600"; d="scan'208";a="128555040" Received: from nemesa.iind.intel.com ([10.190.239.22]) by fmviesa004.fm.intel.com with ESMTP; 21 Mar 2025 09:11:58 -0700 From: Nemesa Garg To: intel-gfx@lists.freedesktop.org, intel-xe@lists.freedesktop.org, dri-devel@lists.freedesktop.org Cc: Nemesa Garg Subject: [PATCH 11/12] drm/i915/display: Enable/disable casf Date: Fri, 21 Mar 2025 21:36:27 +0530 Message-Id: <20250321160628.2663912-12-nemesa.garg@intel.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20250321160628.2663912-1-nemesa.garg@intel.com> References: <20250321160628.2663912-1-nemesa.garg@intel.com> MIME-Version: 1.0 X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" To enable or disable the sharpness check the casf_enable flag. While enabling the sharpness write the programmable coefficients, sharpness register bits and also enable the scaler. Load the filter lut value which needs to be done one time while enabling the sharpness. v2: Introduce casf_enable here[Ankit] Signed-off-by: Nemesa Garg --- drivers/gpu/drm/i915/display/intel_casf.c | 27 ++++++++++++++++++++ drivers/gpu/drm/i915/display/intel_casf.h | 2 ++ drivers/gpu/drm/i915/display/intel_display.c | 27 ++++++++++++++++++++ 3 files changed, 56 insertions(+) diff --git a/drivers/gpu/drm/i915/display/intel_casf.c b/drivers/gpu/drm/i915/display/intel_casf.c index 367a73a91ae6..58fa57596457 100644 --- a/drivers/gpu/drm/i915/display/intel_casf.c +++ b/drivers/gpu/drm/i915/display/intel_casf.c @@ -248,3 +248,30 @@ void intel_casf_scaler_compute_config(struct intel_crtc_state *crtc_state) filter_coeff[i]); } } + +void intel_casf_enable(struct intel_crtc_state *crtc_state) +{ + struct intel_display *display = to_intel_display(crtc_state); + struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); + u32 sharpness_ctl; + + intel_filter_lut_load(crtc, crtc_state); + + intel_casf_write_coeff(crtc_state); + + sharpness_ctl = FILTER_EN | FILTER_STRENGTH(crtc_state->hw.casf_params.strength); + + sharpness_ctl |= crtc_state->hw.casf_params.win_size; + + intel_de_write(display, SHARPNESS_CTL(crtc->pipe), sharpness_ctl); + + skl_scaler_setup_casf(crtc_state); +} + +void intel_casf_disable(const struct intel_crtc_state *crtc_state) +{ + struct intel_display *display = to_intel_display(crtc_state); + struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); + + intel_de_write(display, SHARPNESS_CTL(crtc->pipe), 0); +} diff --git a/drivers/gpu/drm/i915/display/intel_casf.h b/drivers/gpu/drm/i915/display/intel_casf.h index 026a2b8348df..301a9fbd930f 100644 --- a/drivers/gpu/drm/i915/display/intel_casf.h +++ b/drivers/gpu/drm/i915/display/intel_casf.h @@ -18,5 +18,7 @@ void intel_filter_lut_load(struct intel_crtc *crtc, const struct intel_crtc_state *crtc_state); void intel_casf_scaler_compute_config(struct intel_crtc_state *crtc_state); bool intel_casf_needs_scaler(const struct intel_crtc_state *crtc_state); +void intel_casf_enable(struct intel_crtc_state *crtc_state); +void intel_casf_disable(const struct intel_crtc_state *crtc_state); #endif /* __INTEL_CASF_H__ */ diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c index d6691cb07173..cda8a4fed7bc 100644 --- a/drivers/gpu/drm/i915/display/intel_display.c +++ b/drivers/gpu/drm/i915/display/intel_display.c @@ -1036,6 +1036,25 @@ static bool audio_disabling(const struct intel_crtc_state *old_crtc_state, memcmp(old_crtc_state->eld, new_crtc_state->eld, MAX_ELD_BYTES) != 0); } +static bool intel_casf_enabling(const struct intel_crtc_state *new_crtc_state, + const struct intel_crtc_state *old_crtc_state) +{ + if (!new_crtc_state->hw.active) + return false; + + return is_enabling(hw.casf_params.casf_enable, old_crtc_state, new_crtc_state); +} + +static bool intel_casf_disabling(const struct intel_crtc_state *new_crtc_state, + const struct intel_crtc_state *old_crtc_state) +{ + if (!new_crtc_state->hw.active) + return false; + + return (old_crtc_state->hw.casf_params.casf_enable && + !new_crtc_state->hw.casf_params.casf_enable); +} + #undef is_disabling #undef is_enabling @@ -1183,6 +1202,9 @@ static void intel_pre_plane_update(struct intel_atomic_state *state, if (audio_disabling(old_crtc_state, new_crtc_state)) intel_encoders_audio_disable(state, crtc); + if (intel_casf_disabling(old_crtc_state, new_crtc_state)) + intel_casf_disable(new_crtc_state); + intel_drrs_deactivate(old_crtc_state); intel_psr_pre_plane_update(state, crtc); @@ -6699,6 +6721,11 @@ static void intel_pre_update_crtc(struct intel_atomic_state *state, intel_vrr_set_transcoder_timings(new_crtc_state); } + if (intel_casf_enabling(new_crtc_state, old_crtc_state)) + intel_casf_enable(new_crtc_state); + else if (new_crtc_state->hw.casf_params.strength != old_crtc_state->hw.casf_params.strength) + intel_casf_update_strength(new_crtc_state); + intel_fbc_update(state, crtc); drm_WARN_ON(display->drm, !intel_display_power_is_enabled(display, POWER_DOMAIN_DC_OFF)); From patchwork Fri Mar 21 16:06:28 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Nemesa Garg X-Patchwork-Id: 14025712 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id E4FF7C36005 for ; Fri, 21 Mar 2025 16:12:04 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 2E82D10E81B; Fri, 21 Mar 2025 16:12:04 +0000 (UTC) Authentication-Results: gabe.freedesktop.org; dkim=pass (2048-bit key; unprotected) header.d=intel.com header.i=@intel.com header.b="aiAiwW2m"; dkim-atps=neutral Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.9]) by gabe.freedesktop.org (Postfix) with ESMTPS id E594C10E7FD; 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21 Mar 2025 09:12:01 -0700 X-CSE-ConnectionGUID: jwAZ164ZTXyn3BvfDLgc/w== X-CSE-MsgGUID: GrPEv/pGQ+mSlk8/DV2uHA== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.14,264,1736841600"; d="scan'208";a="128555064" Received: from nemesa.iind.intel.com ([10.190.239.22]) by fmviesa004.fm.intel.com with ESMTP; 21 Mar 2025 09:12:00 -0700 From: Nemesa Garg To: intel-gfx@lists.freedesktop.org, intel-xe@lists.freedesktop.org, dri-devel@lists.freedesktop.org Cc: Nemesa Garg Subject: [PATCH 12/12] drm/i915/display: Expose sharpness strength property Date: Fri, 21 Mar 2025 21:36:28 +0530 Message-Id: <20250321160628.2663912-13-nemesa.garg@intel.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20250321160628.2663912-1-nemesa.garg@intel.com> References: <20250321160628.2663912-1-nemesa.garg@intel.com> MIME-Version: 1.0 X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" Expose the drm crtc sharpness strength property which will enable or disable the sharpness/casf based on user input. With this user can set/update the strength of the sharpness or casf filter. v2: Update subject[Ankit] Signed-off-by: Nemesa Garg --- drivers/gpu/drm/i915/display/intel_crtc.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/drivers/gpu/drm/i915/display/intel_crtc.c b/drivers/gpu/drm/i915/display/intel_crtc.c index 5b2603ef2ff7..b8bd255e9555 100644 --- a/drivers/gpu/drm/i915/display/intel_crtc.c +++ b/drivers/gpu/drm/i915/display/intel_crtc.c @@ -391,6 +391,9 @@ int intel_crtc_init(struct intel_display *display, enum pipe pipe) drm_WARN_ON(display->drm, drm_crtc_index(&crtc->base) != crtc->pipe); + if (HAS_CASF(dev_priv)) + drm_crtc_create_sharpness_strength_property(&crtc->base); + return 0; fail: