From patchwork Fri Mar 21 20:05:51 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Marek Vasut X-Patchwork-Id: 14025994 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 8ADF6C36000 for ; Fri, 21 Mar 2025 20:07:15 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id B095B10E09A; Fri, 21 Mar 2025 20:07:14 +0000 (UTC) Authentication-Results: gabe.freedesktop.org; dkim=pass (2048-bit key; unprotected) header.d=denx.de header.i=@denx.de header.b="DfXAd422"; dkim-atps=neutral Received: from mx.denx.de (mx.denx.de [89.58.32.78]) by gabe.freedesktop.org (Postfix) with ESMTPS id 312F010E056 for ; Fri, 21 Mar 2025 20:07:08 +0000 (UTC) Received: from [127.0.0.1] (localhost [127.0.0.1]) by localhost (Mailerdaemon) with ESMTPSA id EEFDE101E90A8; Fri, 21 Mar 2025 21:07:04 +0100 (CET) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=denx.de; s=mx-20241105; t=1742587626; h=from:subject:date:message-id:to:cc:mime-version: content-transfer-encoding:in-reply-to:references; bh=+sSLDnAdQaaRh1ug3/9steXZw1JYzt1ToQ27dvMkXSk=; b=DfXAd422TEJJklzGEddbwWU/OeKgZww3A3cYngRWzDYNyrTTbHl7JC5IXsa9Qkq9vmb8Q4 kP0GxhPzzlaj+gYSu4507wgC/zWzgL5WeKWdSQTNcmQG5yJkhTBuZw2GneDpLImkWcNHz3 wylB1+zTksd57JqSTE/wgS5MnmSH3cCPwAn/Lg11muqeiIjyvv1Dm7uZMe6QsmFi5t+92G D7AvpAlbnKxL+EzT8wDYQdlgwJANhnY5TVaNLeDs9RrsT0GWnWFtjqle9ajLuieDrlJmz+ x3bsE+yL1Fwl49kFeUBHt+OZ5G2aM0aVZwMrcZRswxvwmwjja51uKhnIt6ubvw== From: Marek Vasut To: linux-arm-kernel@lists.infradead.org Cc: Marek Vasut , Boris Brezillon , Conor Dooley , David Airlie , Fabio Estevam , Krzysztof Kozlowski , Liviu Dudau , Maarten Lankhorst , Maxime Ripard , Pengutronix Kernel Team , Philipp Zabel , Rob Herring , Sascha Hauer , Sebastian Reichel , Shawn Guo , Simona Vetter , Steven Price , Thomas Zimmermann , devicetree@vger.kernel.org, dri-devel@lists.freedesktop.org, imx@lists.linux.dev Subject: [PATCH v2 1/9] dt-bindings: reset: imx95-gpu-blk-ctrl: Document Freescale i.MX95 GPU reset Date: Fri, 21 Mar 2025 21:05:51 +0100 Message-ID: <20250321200625.132494-2-marex@denx.de> X-Mailer: git-send-email 2.47.2 In-Reply-To: <20250321200625.132494-1-marex@denx.de> References: <20250321200625.132494-1-marex@denx.de> MIME-Version: 1.0 X-Last-TLS-Session-Version: TLSv1.3 X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" The instance of the GPU populated in Freescale i.MX95 does require release from reset by writing into a single GPUMIX block controller GPURESET register bit 0. Document support for this reset register. Signed-off-by: Marek Vasut Reviewed-by: Rob Herring (Arm) --- Cc: Boris Brezillon Cc: Conor Dooley Cc: David Airlie Cc: Fabio Estevam Cc: Krzysztof Kozlowski Cc: Liviu Dudau Cc: Maarten Lankhorst Cc: Maxime Ripard Cc: Pengutronix Kernel Team Cc: Philipp Zabel Cc: Rob Herring Cc: Sascha Hauer Cc: Sebastian Reichel Cc: Shawn Guo Cc: Simona Vetter Cc: Steven Price Cc: Thomas Zimmermann Cc: devicetree@vger.kernel.org Cc: dri-devel@lists.freedesktop.org Cc: imx@lists.linux.dev Cc: linux-arm-kernel@lists.infradead.org --- V2: - Fix dt_binding_check errors in example, temporarily use fixed numbers to refer to IMX95_CLK_GPUAPB clock and IMX95_PD_GPU power-domain - Drop trailing pipe after description: - Drop leading dash before const in compatible: - Switch from fsl, to nxp, vendor prefix --- .../reset/nxp,imx95-gpu-blk-ctrl.yaml | 49 +++++++++++++++++++ 1 file changed, 49 insertions(+) create mode 100644 Documentation/devicetree/bindings/reset/nxp,imx95-gpu-blk-ctrl.yaml diff --git a/Documentation/devicetree/bindings/reset/nxp,imx95-gpu-blk-ctrl.yaml b/Documentation/devicetree/bindings/reset/nxp,imx95-gpu-blk-ctrl.yaml new file mode 100644 index 0000000000000..ca841db20d35b --- /dev/null +++ b/Documentation/devicetree/bindings/reset/nxp,imx95-gpu-blk-ctrl.yaml @@ -0,0 +1,49 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/reset/nxp,imx95-gpu-blk-ctrl.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Freescale i.MX95 GPU Block Controller + +maintainers: + - Marek Vasut + +description: + This reset controller is a block of ad-hoc debug registers, one of + which is a single-bit GPU reset. + +properties: + compatible: + const: nxp,imx95-gpu-blk-ctrl + + reg: + maxItems: 1 + + clocks: + maxItems: 1 + + power-domains: + maxItems: 1 + + '#reset-cells': + const: 1 + +required: + - compatible + - reg + - clocks + - power-domains + - '#reset-cells' + +additionalProperties: false + +examples: + - | + reset-controller@4d810000 { + compatible = "nxp,imx95-gpu-blk-ctrl"; + reg = <0x4d810000 0xc>; + clocks = <&clk 83>; + power-domains = <&scmi_devpd 14>; + #reset-cells = <1>; + }; From patchwork Fri Mar 21 20:05:52 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Marek Vasut X-Patchwork-Id: 14025993 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 74B7AC36002 for ; Fri, 21 Mar 2025 20:07:12 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id DBD1910E1FD; Fri, 21 Mar 2025 20:07:11 +0000 (UTC) Authentication-Results: gabe.freedesktop.org; dkim=pass (2048-bit key; unprotected) header.d=denx.de header.i=@denx.de header.b="HPjNgGMI"; dkim-atps=neutral Received: from mx.denx.de (mx.denx.de [89.58.32.78]) by gabe.freedesktop.org (Postfix) with ESMTPS id C735410E09A for ; Fri, 21 Mar 2025 20:07:09 +0000 (UTC) Received: from [127.0.0.1] (localhost [127.0.0.1]) by localhost (Mailerdaemon) with ESMTPSA id A9E98101E8FE7; Fri, 21 Mar 2025 21:07:06 +0100 (CET) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=denx.de; s=mx-20241105; t=1742587628; h=from:subject:date:message-id:to:cc:mime-version: content-transfer-encoding:in-reply-to:references; bh=T+aW3YqrWtyb+HJrv0NdBuH13F+b2T4tSgjYxeo3bk0=; b=HPjNgGMIOobFRLkbtZOxz8dZlyaVxNxU64iSONjzGGOv7RG5JKJnnmnov6KAqY69h9uPII M23mjnU2HDHEQRcchu/mGaePSbsLWE31IykDvLPiW4v2UrRdL40KVLDSqPWl2vev9IwruW 5qR0dIDDjk9NYET/N9rMl/YeoVmuKZqc/+RZGvrOpZabzECShlg/fTL2Yp/eVdxG26rB99 3gHUPXDBygq08VWoOmoSnKuDoFpAJT+QFvRGIWgDeymj5WvN3jov+3IgUqZOupfSYxRx6z OsV9AY94J053dyoBoEm9c0gtozsCtTrcOWSyMSlm7Ylr1L1eAWLY/AnaAS7Ojw== From: Marek Vasut To: linux-arm-kernel@lists.infradead.org Cc: Marek Vasut , Boris Brezillon , Conor Dooley , David Airlie , Fabio Estevam , Krzysztof Kozlowski , Liviu Dudau , Maarten Lankhorst , Maxime Ripard , Pengutronix Kernel Team , Philipp Zabel , Rob Herring , Sascha Hauer , Sebastian Reichel , Shawn Guo , Simona Vetter , Steven Price , Thomas Zimmermann , devicetree@vger.kernel.org, dri-devel@lists.freedesktop.org, imx@lists.linux.dev Subject: [PATCH v2 2/9] reset: simple: Add support for Freescale i.MX95 GPU reset Date: Fri, 21 Mar 2025 21:05:52 +0100 Message-ID: <20250321200625.132494-3-marex@denx.de> X-Mailer: git-send-email 2.47.2 In-Reply-To: <20250321200625.132494-1-marex@denx.de> References: <20250321200625.132494-1-marex@denx.de> MIME-Version: 1.0 X-Last-TLS-Session-Version: TLSv1.3 X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" The instance of the GPU populated in Freescale i.MX95 does require release from reset by writing into a single GPUMIX block controller GPURESET register bit 0. Implement support for this reset register. Signed-off-by: Marek Vasut --- Cc: Boris Brezillon Cc: Conor Dooley Cc: David Airlie Cc: Fabio Estevam Cc: Krzysztof Kozlowski Cc: Liviu Dudau Cc: Maarten Lankhorst Cc: Maxime Ripard Cc: Pengutronix Kernel Team Cc: Philipp Zabel Cc: Rob Herring Cc: Sascha Hauer Cc: Sebastian Reichel Cc: Shawn Guo Cc: Simona Vetter Cc: Steven Price Cc: Thomas Zimmermann Cc: devicetree@vger.kernel.org Cc: dri-devel@lists.freedesktop.org Cc: imx@lists.linux.dev Cc: linux-arm-kernel@lists.infradead.org --- V2: - Set nr_resets=1 to limit the amount of resets to single bit - Switch from fsl, to nxp, vendor prefix - Add RESET_IMX95_GPU Kconfig symbol to select this reset driver on MX9 --- drivers/reset/Kconfig | 8 ++++++++ drivers/reset/reset-simple.c | 9 +++++++++ 2 files changed, 17 insertions(+) diff --git a/drivers/reset/Kconfig b/drivers/reset/Kconfig index 99f6f9784e686..0b48e76fd0aab 100644 --- a/drivers/reset/Kconfig +++ b/drivers/reset/Kconfig @@ -249,12 +249,20 @@ config RESET_SIMPLE - Altera SoCFPGAs - ASPEED BMC SoCs - Bitmain BM1880 SoC + - NXP i.MX95 GPU - Realtek SoCs - RCC reset controller in STM32 MCUs - Allwinner SoCs - SiFive FU740 SoCs - Sophgo SoCs +config RESET_IMX95_GPU + bool "NXP i.MX95 GPU Reset Driver" if COMPILE_TEST && !SOC_IMX9 + default SOC_IMX9 + select RESET_SIMPLE + help + This enables the reset driver for i.MX95 GPU. + config RESET_SOCFPGA bool "SoCFPGA Reset Driver" if COMPILE_TEST && (!ARM || !ARCH_INTEL_SOCFPGA) default ARM && ARCH_INTEL_SOCFPGA diff --git a/drivers/reset/reset-simple.c b/drivers/reset/reset-simple.c index 2760678398308..64aeda8f76b75 100644 --- a/drivers/reset/reset-simple.c +++ b/drivers/reset/reset-simple.c @@ -133,9 +133,18 @@ static const struct reset_simple_devdata reset_simple_active_low = { .status_active_low = true, }; +static const struct reset_simple_devdata reset_simple_fsl_imx95_gpu_blk_ctrl = { + .reg_offset = 0x8, + .active_low = true, + .nr_resets = 1, + .status_active_low = true, +}; + static const struct of_device_id reset_simple_dt_ids[] = { { .compatible = "altr,stratix10-rst-mgr", .data = &reset_simple_socfpga }, + { .compatible = "nxp,imx95-gpu-blk-ctrl", + .data = &reset_simple_fsl_imx95_gpu_blk_ctrl }, { .compatible = "st,stm32-rcc", }, { .compatible = "allwinner,sun6i-a31-clock-reset", .data = &reset_simple_active_low }, From patchwork Fri Mar 21 20:05:53 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Marek Vasut X-Patchwork-Id: 14025996 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id B65FDC36008 for ; Fri, 21 Mar 2025 20:07:17 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id B50C210E1EE; Fri, 21 Mar 2025 20:07:14 +0000 (UTC) Authentication-Results: gabe.freedesktop.org; dkim=pass (2048-bit key; unprotected) header.d=denx.de header.i=@denx.de header.b="Nn4K6Weu"; dkim-atps=neutral Received: from mx.denx.de (mx.denx.de [89.58.32.78]) by gabe.freedesktop.org (Postfix) with ESMTPS id A561110E09A for ; Fri, 21 Mar 2025 20:07:11 +0000 (UTC) Received: from [127.0.0.1] (localhost [127.0.0.1]) by localhost (Mailerdaemon) with ESMTPSA id 53656101E8FE9; Fri, 21 Mar 2025 21:07:08 +0100 (CET) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=denx.de; s=mx-20241105; t=1742587629; h=from:subject:date:message-id:to:cc:mime-version: content-transfer-encoding:in-reply-to:references; bh=/QjT7PtVWPkoRPUHyfCfzMI+lVd5Zx3OIJsUBq2pBDI=; b=Nn4K6WeuDlELvisXql4OpZVGGp9NE+QVqa0IrHuTGC1z8zSVUKEdkdPhaGbpvWlNdeVR/G 6/vl9gvs7mPL2cN3yuq9N80FNtHwRrmhUEU3Mh3zmgSBa9aqXW4TAzNpxA8fFdKDUe8Hqw 5IuhoR3wxTFmxQm/FN3w+m2pDBuqG4rL2XMD/CUbEZP0wSRbRUAmKKBjN5VtaXdjnSJDY1 xpD6vqF0aClV4p9c7uCQMRNlAIXMnazbjWhPC/HbDOqaC5oe4AvMnVi85va6tsqqiAvnvX r0htcX7Ndd6NN1baiQDu2MuXVQIRG4kIvoAop+MxVT3wXbtrbXP1skg5hHOW9A== From: Marek Vasut To: linux-arm-kernel@lists.infradead.org Cc: Marek Vasut , "Rob Herring (Arm)" , Frank Li , Boris Brezillon , Conor Dooley , David Airlie , Fabio Estevam , Krzysztof Kozlowski , Liviu Dudau , Maarten Lankhorst , Maxime Ripard , Pengutronix Kernel Team , Philipp Zabel , Sascha Hauer , Sebastian Reichel , Shawn Guo , Simona Vetter , Steven Price , Thomas Zimmermann , devicetree@vger.kernel.org, dri-devel@lists.freedesktop.org, imx@lists.linux.dev Subject: [PATCH v2 3/9] dt-bindings: gpu: mali-valhall-csf: Document optional reset Date: Fri, 21 Mar 2025 21:05:53 +0100 Message-ID: <20250321200625.132494-4-marex@denx.de> X-Mailer: git-send-email 2.47.2 In-Reply-To: <20250321200625.132494-1-marex@denx.de> References: <20250321200625.132494-1-marex@denx.de> MIME-Version: 1.0 X-Last-TLS-Session-Version: TLSv1.3 X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" The instance of the GPU populated in Freescale i.MX95 does require release from reset by writing into a single GPUMIX block controller GPURESET register bit 0. Document support for one optional reset. Acked-by: Rob Herring (Arm) Reviewed-by: Frank Li Signed-off-by: Marek Vasut --- Cc: Boris Brezillon Cc: Conor Dooley Cc: David Airlie Cc: Fabio Estevam Cc: Krzysztof Kozlowski Cc: Liviu Dudau Cc: Maarten Lankhorst Cc: Maxime Ripard Cc: Pengutronix Kernel Team Cc: Philipp Zabel Cc: Rob Herring Cc: Sascha Hauer Cc: Sebastian Reichel Cc: Shawn Guo Cc: Simona Vetter Cc: Steven Price Cc: Thomas Zimmermann Cc: devicetree@vger.kernel.org Cc: dri-devel@lists.freedesktop.org Cc: imx@lists.linux.dev Cc: linux-arm-kernel@lists.infradead.org --- V2: - Add RB from Frank - Add AB from Rob --- .../devicetree/bindings/gpu/arm,mali-valhall-csf.yaml | 3 +++ 1 file changed, 3 insertions(+) diff --git a/Documentation/devicetree/bindings/gpu/arm,mali-valhall-csf.yaml b/Documentation/devicetree/bindings/gpu/arm,mali-valhall-csf.yaml index a5b4e00217587..0efa06822a543 100644 --- a/Documentation/devicetree/bindings/gpu/arm,mali-valhall-csf.yaml +++ b/Documentation/devicetree/bindings/gpu/arm,mali-valhall-csf.yaml @@ -61,6 +61,9 @@ properties: minItems: 1 maxItems: 5 + resets: + maxItems: 1 + sram-supply: true "#cooling-cells": From patchwork Fri Mar 21 20:05:54 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Marek Vasut X-Patchwork-Id: 14025995 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 57C1CC36007 for ; Fri, 21 Mar 2025 20:07:16 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id BC44010E20F; Fri, 21 Mar 2025 20:07:14 +0000 (UTC) Authentication-Results: gabe.freedesktop.org; dkim=pass (2048-bit key; unprotected) header.d=denx.de header.i=@denx.de header.b="Ujh3YbJp"; dkim-atps=neutral Received: from mx.denx.de (mx.denx.de [89.58.32.78]) by gabe.freedesktop.org (Postfix) with ESMTPS id 715A810E09A for ; Fri, 21 Mar 2025 20:07:13 +0000 (UTC) Received: from [127.0.0.1] (localhost [127.0.0.1]) by localhost (Mailerdaemon) with ESMTPSA id 46EF310206773; Fri, 21 Mar 2025 21:07:10 +0100 (CET) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=denx.de; s=mx-20241105; t=1742587631; h=from:subject:date:message-id:to:cc:mime-version: content-transfer-encoding:in-reply-to:references; bh=tbl1bzwd72WBMUHQVUL0sGP9LINKYez4xzgILWcrQd0=; b=Ujh3YbJpP0w6d7Vq3HH9Q30e9e0u1qTMHdtq9Vyg79Vb6a4W2PuiLeQJ7PDrgp0QIRoBYn hqoNE1AGZ3HPtUgaGbGXHzJM/LZfXFqVRQPSMH59yZurKeJQ1p6ClZGURG8can0C36aQJi I4VyO8rBrbPYSAUPosCoJ6rKTRmxtzGi15XRyfEUG0Kkwg11l8BFjTEFkzmD8xz3gy7TVN Mg8/V70meiqDVRvhoSsIaqmF75S4kjGVipBKH9b7w5wG0DxyqzhYVW0o5NX/a0eNa1iXIr pMfEogdxrjt6VOXYT6rEpn2rq/svVdni5lsfJbddgnL0lsXE9Yw6UfoPhbXqFA== From: Marek Vasut To: linux-arm-kernel@lists.infradead.org Cc: Marek Vasut , Boris Brezillon , Conor Dooley , David Airlie , Fabio Estevam , Krzysztof Kozlowski , Liviu Dudau , Maarten Lankhorst , Maxime Ripard , Pengutronix Kernel Team , Philipp Zabel , Rob Herring , Sascha Hauer , Sebastian Reichel , Shawn Guo , Simona Vetter , Steven Price , Thomas Zimmermann , devicetree@vger.kernel.org, dri-devel@lists.freedesktop.org, imx@lists.linux.dev Subject: [PATCH v2 4/9] drm/panthor: Implement optional reset Date: Fri, 21 Mar 2025 21:05:54 +0100 Message-ID: <20250321200625.132494-5-marex@denx.de> X-Mailer: git-send-email 2.47.2 In-Reply-To: <20250321200625.132494-1-marex@denx.de> References: <20250321200625.132494-1-marex@denx.de> MIME-Version: 1.0 X-Last-TLS-Session-Version: TLSv1.3 X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" The instance of the GPU populated in Freescale i.MX95 does require release from reset by writing into a single GPUMIX block controller GPURESET register bit 0. Implement support for one optional reset. Signed-off-by: Marek Vasut --- Cc: Boris Brezillon Cc: Conor Dooley Cc: David Airlie Cc: Fabio Estevam Cc: Krzysztof Kozlowski Cc: Liviu Dudau Cc: Maarten Lankhorst Cc: Maxime Ripard Cc: Pengutronix Kernel Team Cc: Philipp Zabel Cc: Rob Herring Cc: Sascha Hauer Cc: Sebastian Reichel Cc: Shawn Guo Cc: Simona Vetter Cc: Steven Price Cc: Thomas Zimmermann Cc: devicetree@vger.kernel.org Cc: dri-devel@lists.freedesktop.org Cc: imx@lists.linux.dev Cc: linux-arm-kernel@lists.infradead.org --- V2: Drop the select RESET_SIMPLE from Kconfig --- drivers/gpu/drm/panthor/panthor_device.c | 23 +++++++++++++++++++++++ drivers/gpu/drm/panthor/panthor_device.h | 3 +++ 2 files changed, 26 insertions(+) diff --git a/drivers/gpu/drm/panthor/panthor_device.c b/drivers/gpu/drm/panthor/panthor_device.c index a9da1d1eeb707..51ee9cae94504 100644 --- a/drivers/gpu/drm/panthor/panthor_device.c +++ b/drivers/gpu/drm/panthor/panthor_device.c @@ -64,6 +64,17 @@ static int panthor_clk_init(struct panthor_device *ptdev) return 0; } +static int panthor_reset_init(struct panthor_device *ptdev) +{ + ptdev->resets = devm_reset_control_get_optional_exclusive_deasserted(ptdev->base.dev, NULL); + if (IS_ERR(ptdev->resets)) + return dev_err_probe(ptdev->base.dev, + PTR_ERR(ptdev->resets), + "get reset failed"); + + return 0; +} + void panthor_device_unplug(struct panthor_device *ptdev) { /* This function can be called from two different path: the reset work @@ -217,6 +228,10 @@ int panthor_device_init(struct panthor_device *ptdev) if (ret) return ret; + ret = panthor_reset_init(ptdev); + if (ret) + return ret; + ret = panthor_devfreq_init(ptdev); if (ret) return ret; @@ -470,6 +485,10 @@ int panthor_device_resume(struct device *dev) if (ret) goto err_disable_stacks_clk; + ret = reset_control_deassert(ptdev->resets); + if (ret) + goto err_disable_coregroup_clk; + panthor_devfreq_resume(ptdev); if (panthor_device_is_initialized(ptdev) && @@ -512,6 +531,9 @@ int panthor_device_resume(struct device *dev) err_suspend_devfreq: panthor_devfreq_suspend(ptdev); + reset_control_assert(ptdev->resets); + +err_disable_coregroup_clk: clk_disable_unprepare(ptdev->clks.coregroup); err_disable_stacks_clk: @@ -563,6 +585,7 @@ int panthor_device_suspend(struct device *dev) panthor_devfreq_suspend(ptdev); + reset_control_assert(ptdev->resets); clk_disable_unprepare(ptdev->clks.coregroup); clk_disable_unprepare(ptdev->clks.stacks); clk_disable_unprepare(ptdev->clks.core); diff --git a/drivers/gpu/drm/panthor/panthor_device.h b/drivers/gpu/drm/panthor/panthor_device.h index da6574021664b..fea3a05778e2e 100644 --- a/drivers/gpu/drm/panthor/panthor_device.h +++ b/drivers/gpu/drm/panthor/panthor_device.h @@ -111,6 +111,9 @@ struct panthor_device { struct clk *coregroup; } clks; + /** @resets: GPU reset. */ + struct reset_control *resets; + /** @coherent: True if the CPU/GPU are memory coherent. */ bool coherent; From patchwork Fri Mar 21 20:05:55 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Marek Vasut X-Patchwork-Id: 14025998 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 5F5B6C36007 for ; Fri, 21 Mar 2025 20:07:22 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id BED6C10E832; Fri, 21 Mar 2025 20:07:21 +0000 (UTC) Authentication-Results: gabe.freedesktop.org; dkim=pass (2048-bit key; unprotected) header.d=denx.de header.i=@denx.de header.b="iQXdB06y"; dkim-atps=neutral Received: from mx.denx.de (mx.denx.de [89.58.32.78]) by gabe.freedesktop.org (Postfix) with ESMTPS id 31BBB10E832 for ; Fri, 21 Mar 2025 20:07:15 +0000 (UTC) Received: from [127.0.0.1] (localhost [127.0.0.1]) by localhost (Mailerdaemon) with ESMTPSA id 05FF4101E8FEB; Fri, 21 Mar 2025 21:07:11 +0100 (CET) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=denx.de; s=mx-20241105; t=1742587633; h=from:subject:date:message-id:to:cc:mime-version: content-transfer-encoding:in-reply-to:references; bh=z4RQQIr4ZFU6Esl1yW2CHyR2/BWf3qsLICtii4ahl3Q=; b=iQXdB06yKDMUsIJvi63/gPlGNXOFWoV8gbkZ+RXpFA2TWdP0p/RGwFTaTFw8jxgRySF7Fv lUoBT6MAWjo9aXnemjGI0bkQQfu2PNGXvu1EqtnPRsvGL/dLtrGHNIxl6N5LGT2xjPHhIG CxK643CaukO+yJleMsJz/HdnKNBS+TtmrnubBGPERV9XaLgoD6W3indUj7mU6GMqqfyOSe SwrpV1hDIX0siexbMHc4EwyIT5wqxOG92JYQFm002WJ8LbOuB+j7Pv3vCIZW9nBnydqTvP SZFszmUrPXwnhPsGXtkmpyDk8KZtScydbXs0k/W8QtD/rrYuPxgM6wNoKZebTA== From: Marek Vasut To: linux-arm-kernel@lists.infradead.org Cc: Marek Vasut , Boris Brezillon , Conor Dooley , David Airlie , Fabio Estevam , Krzysztof Kozlowski , Liviu Dudau , Maarten Lankhorst , Maxime Ripard , Pengutronix Kernel Team , Philipp Zabel , Rob Herring , Sascha Hauer , Sebastian Reichel , Shawn Guo , Simona Vetter , Steven Price , Thomas Zimmermann , devicetree@vger.kernel.org, dri-devel@lists.freedesktop.org, imx@lists.linux.dev Subject: [PATCH v2 5/9] drm/panthor: Implement support for multiple power domains Date: Fri, 21 Mar 2025 21:05:55 +0100 Message-ID: <20250321200625.132494-6-marex@denx.de> X-Mailer: git-send-email 2.47.2 In-Reply-To: <20250321200625.132494-1-marex@denx.de> References: <20250321200625.132494-1-marex@denx.de> MIME-Version: 1.0 X-Last-TLS-Session-Version: TLSv1.3 X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" The driver code power domain binding to driver instances only works for single power domain, in case there are multiple power domains, it is necessary to explicitly attach via dev_pm_domain_attach*(). As DT bindings list support for up to 5 power domains, add support for attaching them all. This is useful on Freescale i.MX95 which does have two power domains. Signed-off-by: Marek Vasut --- Cc: Boris Brezillon Cc: Conor Dooley Cc: David Airlie Cc: Fabio Estevam Cc: Krzysztof Kozlowski Cc: Liviu Dudau Cc: Maarten Lankhorst Cc: Maxime Ripard Cc: Pengutronix Kernel Team Cc: Philipp Zabel Cc: Rob Herring Cc: Sascha Hauer Cc: Sebastian Reichel Cc: Shawn Guo Cc: Simona Vetter Cc: Steven Price Cc: Thomas Zimmermann Cc: devicetree@vger.kernel.org Cc: dri-devel@lists.freedesktop.org Cc: imx@lists.linux.dev Cc: linux-arm-kernel@lists.infradead.org --- V2: Exit from panthor_genpd_init() on any pm_domain_attach_by_id() failure --- drivers/gpu/drm/panthor/panthor_device.c | 52 ++++++++++++++++++++++++ drivers/gpu/drm/panthor/panthor_device.h | 5 +++ 2 files changed, 57 insertions(+) diff --git a/drivers/gpu/drm/panthor/panthor_device.c b/drivers/gpu/drm/panthor/panthor_device.c index 51ee9cae94504..8aa79c6d157e1 100644 --- a/drivers/gpu/drm/panthor/panthor_device.c +++ b/drivers/gpu/drm/panthor/panthor_device.c @@ -75,6 +75,54 @@ static int panthor_reset_init(struct panthor_device *ptdev) return 0; } +/* Generic power domain handling code, see drivers/gpu/drm/tiny/simpledrm.c */ +static void panthor_detach_genpd(void *res) +{ + struct panthor_device *ptdev = res; + int i; + + if (ptdev->pwr_dom_count <= 1) + return; + + for (i = ptdev->pwr_dom_count - 1; i >= 0; i--) + dev_pm_domain_detach(ptdev->pwr_dom_devs[i], true); +} + +static int panthor_genpd_init(struct panthor_device *ptdev) +{ + struct device *dev = ptdev->base.dev; + int i; + + ptdev->pwr_dom_count = of_count_phandle_with_args(dev->of_node, "power-domains", + "#power-domain-cells"); + /* + * Single power-domain devices are handled by driver core nothing to do + * here. The same for device nodes without "power-domains" property. + */ + if (ptdev->pwr_dom_count <= 1) + return 0; + + if (ptdev->pwr_dom_count > ARRAY_SIZE(ptdev->pwr_dom_devs)) { + drm_warn(&ptdev->base, "Too many power domains (%d) for this device\n", + ptdev->pwr_dom_count); + return -EINVAL; + } + + for (i = 0; i < ptdev->pwr_dom_count; i++) { + ptdev->pwr_dom_devs[i] = dev_pm_domain_attach_by_id(dev, i); + if (!IS_ERR(ptdev->pwr_dom_devs[i])) + continue; + + /* Missing dependency, try again. */ + panthor_detach_genpd(ptdev); + return dev_err_probe(ptdev->base.dev, + PTR_ERR(ptdev->pwr_dom_devs[i]), + "pm_domain_attach_by_id(%u) failed\n", i); + } + + return devm_add_action_or_reset(dev, panthor_detach_genpd, ptdev); +} + void panthor_device_unplug(struct panthor_device *ptdev) { /* This function can be called from two different path: the reset work @@ -232,6 +280,10 @@ int panthor_device_init(struct panthor_device *ptdev) if (ret) return ret; + ret = panthor_genpd_init(ptdev); + if (ret) + return ret; + ret = panthor_devfreq_init(ptdev); if (ret) return ret; diff --git a/drivers/gpu/drm/panthor/panthor_device.h b/drivers/gpu/drm/panthor/panthor_device.h index fea3a05778e2e..7fb65447253e9 100644 --- a/drivers/gpu/drm/panthor/panthor_device.h +++ b/drivers/gpu/drm/panthor/panthor_device.h @@ -114,6 +114,11 @@ struct panthor_device { /** @resets: GPU reset. */ struct reset_control *resets; + /** @pwr_dom_count: Power domain count */ + int pwr_dom_count; + /** @pwr_dom_dev: Power domain devices */ + struct device *pwr_dom_devs[5]; + /** @coherent: True if the CPU/GPU are memory coherent. */ bool coherent; From patchwork Fri Mar 21 20:05:56 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Marek Vasut X-Patchwork-Id: 14026000 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 1F89DC36000 for ; Fri, 21 Mar 2025 20:07:30 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 7D57810E836; Fri, 21 Mar 2025 20:07:29 +0000 (UTC) Authentication-Results: gabe.freedesktop.org; dkim=pass (2048-bit key; unprotected) header.d=denx.de header.i=@denx.de header.b="dbkJVkNr"; dkim-atps=neutral Received: from mx.denx.de (mx.denx.de [89.58.32.78]) by gabe.freedesktop.org (Postfix) with ESMTPS id 0C3EE10E832 for ; Fri, 21 Mar 2025 20:07:17 +0000 (UTC) Received: from [127.0.0.1] (localhost [127.0.0.1]) by localhost (Mailerdaemon) with ESMTPSA id C7E5D101E8FE7; Fri, 21 Mar 2025 21:07:13 +0100 (CET) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=denx.de; s=mx-20241105; t=1742587635; h=from:subject:date:message-id:to:cc:mime-version: content-transfer-encoding:in-reply-to:references; bh=O8iECVKqUngmbLKesdAXdxuc21AF1mv3PVk149t7akU=; b=dbkJVkNrAiPA1y2flaykkwgNtX4AnewryWHqt5l/Jmoaw6Rwx0rMnsDXHOlEHmWHlDHHlQ kA1TiweR3QTmtoSMyfYo5B/pghhZnm24wn/bT/5ogob2FiFAQL8uVlT47avHBNP1PsaS9H v6UhNwzQ+eBXsTb+H3TigCcr/jK7g/cuXzb7lCrVnT8AHQdC4S5Wrd7aaqbO9hVv2bLsab QNJyixNjnHnTHfuBzNEYcItV0h+7tVXaELiv38kwsvH9Gya72u07w6MQAK9BpHYa2GfNdQ IsU7AlUuBi0Rg5eYyPQ7clJYJPC1iXpQik3JyOMyGDjyZG3SwQGgPgn8QFahtw== From: Marek Vasut To: linux-arm-kernel@lists.infradead.org Cc: Marek Vasut , Boris Brezillon , Conor Dooley , David Airlie , Fabio Estevam , Krzysztof Kozlowski , Liviu Dudau , Maarten Lankhorst , Maxime Ripard , Pengutronix Kernel Team , Philipp Zabel , Rob Herring , Sascha Hauer , Sebastian Reichel , Shawn Guo , Simona Vetter , Steven Price , Thomas Zimmermann , devicetree@vger.kernel.org, dri-devel@lists.freedesktop.org, imx@lists.linux.dev Subject: [PATCH v2 6/9] drm/panthor: Reset GPU after L2 cache power off Date: Fri, 21 Mar 2025 21:05:56 +0100 Message-ID: <20250321200625.132494-7-marex@denx.de> X-Mailer: git-send-email 2.47.2 In-Reply-To: <20250321200625.132494-1-marex@denx.de> References: <20250321200625.132494-1-marex@denx.de> MIME-Version: 1.0 X-Last-TLS-Session-Version: TLSv1.3 X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" This seems necessary on Freescale i.MX95 Mali G310 to reliably resume from runtime PM suspend. Without this, if only the L2 is powered down on RPM entry, the GPU gets stuck and does not indicate the firmware is booted after RPM resume. Signed-off-by: Marek Vasut --- Cc: Boris Brezillon Cc: Conor Dooley Cc: David Airlie Cc: Fabio Estevam Cc: Krzysztof Kozlowski Cc: Liviu Dudau Cc: Maarten Lankhorst Cc: Maxime Ripard Cc: Pengutronix Kernel Team Cc: Philipp Zabel Cc: Rob Herring Cc: Sascha Hauer Cc: Sebastian Reichel Cc: Shawn Guo Cc: Simona Vetter Cc: Steven Price Cc: Thomas Zimmermann Cc: devicetree@vger.kernel.org Cc: dri-devel@lists.freedesktop.org Cc: imx@lists.linux.dev Cc: linux-arm-kernel@lists.infradead.org --- V2: No change --- drivers/gpu/drm/panthor/panthor_gpu.c | 11 ++++++----- 1 file changed, 6 insertions(+), 5 deletions(-) diff --git a/drivers/gpu/drm/panthor/panthor_gpu.c b/drivers/gpu/drm/panthor/panthor_gpu.c index 671049020afaa..0f07ef7d9aea7 100644 --- a/drivers/gpu/drm/panthor/panthor_gpu.c +++ b/drivers/gpu/drm/panthor/panthor_gpu.c @@ -470,11 +470,12 @@ int panthor_gpu_soft_reset(struct panthor_device *ptdev) */ void panthor_gpu_suspend(struct panthor_device *ptdev) { - /* On a fast reset, simply power down the L2. */ - if (!ptdev->reset.fast) - panthor_gpu_soft_reset(ptdev); - else - panthor_gpu_power_off(ptdev, L2, 1, 20000); + /* + * Power off the L2 and soft reset the GPU, that makes + * iMX95 Mali G310 resume without firmware boot timeout. + */ + panthor_gpu_power_off(ptdev, L2, 1, 20000); + panthor_gpu_soft_reset(ptdev); panthor_gpu_irq_suspend(&ptdev->gpu->irq); } From patchwork Fri Mar 21 20:05:57 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Marek Vasut X-Patchwork-Id: 14025999 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 6A93FC36002 for ; Fri, 21 Mar 2025 20:07:23 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 2BE3110E834; Fri, 21 Mar 2025 20:07:22 +0000 (UTC) Authentication-Results: gabe.freedesktop.org; dkim=pass (2048-bit key; unprotected) header.d=denx.de header.i=@denx.de header.b="A9XBJ1i6"; dkim-atps=neutral Received: from mx.denx.de (mx.denx.de [89.58.32.78]) by gabe.freedesktop.org (Postfix) with ESMTPS id 3375510E833 for ; Fri, 21 Mar 2025 20:07:19 +0000 (UTC) Received: from [127.0.0.1] (localhost [127.0.0.1]) by localhost (Mailerdaemon) with ESMTPSA id 9C2CC101E8FEE; Fri, 21 Mar 2025 21:07:15 +0100 (CET) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=denx.de; s=mx-20241105; t=1742587637; h=from:subject:date:message-id:to:cc:mime-version: content-transfer-encoding:in-reply-to:references; bh=ZzRD5QOdeWfzwL+D5t37uF2dpRk29SkQGyL53eKSa5Q=; b=A9XBJ1i68wOzhkEqzV2QKFTy3CrsFNhwqsvwx/iHoBcJ17IYmByaRzeVVyZZDMc68iHzL8 1kNoYtbMnKvGc9r2c+M+ZY/nm+9h+h0o1lEtcSKgN6IERjiqkbwmoMz0+jFSHef9hb5Ovl z5Mc0+TSFxo0oBz2tfUCx/vRyHsSa50w5nYbn+ZBo3SKb7Hf6DQ0DTdO/ypccB4ZkSZwWK A77u7gOvzlVzSapAIJCMR5CdgAqY9sLb6KzIsN4sv+5rN+tceWeYyvHk0MfyP/rjuKehih vNIjHFlgR/wV/53HwUSMEFD8XeH1vlC+iZVvezWZPqy0hQI4Hyj74NdXsOXm8g== From: Marek Vasut To: linux-arm-kernel@lists.infradead.org Cc: Marek Vasut , Alexander Stein , Frank Li , Boris Brezillon , Conor Dooley , David Airlie , Fabio Estevam , Krzysztof Kozlowski , Liviu Dudau , Maarten Lankhorst , Maxime Ripard , Pengutronix Kernel Team , Philipp Zabel , Rob Herring , Sascha Hauer , Sebastian Reichel , Shawn Guo , Simona Vetter , Steven Price , Thomas Zimmermann , devicetree@vger.kernel.org, dri-devel@lists.freedesktop.org, imx@lists.linux.dev Subject: [PATCH v2 7/9] dt-bindings: gpu: mali-valhall-csf: Document i.MX95 support Date: Fri, 21 Mar 2025 21:05:57 +0100 Message-ID: <20250321200625.132494-8-marex@denx.de> X-Mailer: git-send-email 2.47.2 In-Reply-To: <20250321200625.132494-1-marex@denx.de> References: <20250321200625.132494-1-marex@denx.de> MIME-Version: 1.0 X-Last-TLS-Session-Version: TLSv1.3 X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" The instance of the GPU populated in Freescale i.MX95 is the Mali G310, document support for this variant. Reviewed-by: Alexander Stein Reviewed-by: Frank Li Signed-off-by: Marek Vasut Reviewed-by: Rob Herring (Arm) --- Cc: Boris Brezillon Cc: Conor Dooley Cc: David Airlie Cc: Fabio Estevam Cc: Krzysztof Kozlowski Cc: Liviu Dudau Cc: Maarten Lankhorst Cc: Maxime Ripard Cc: Pengutronix Kernel Team Cc: Philipp Zabel Cc: Rob Herring Cc: Sascha Hauer Cc: Sebastian Reichel Cc: Shawn Guo Cc: Simona Vetter Cc: Steven Price Cc: Thomas Zimmermann Cc: devicetree@vger.kernel.org Cc: dri-devel@lists.freedesktop.org Cc: imx@lists.linux.dev Cc: linux-arm-kernel@lists.infradead.org --- V2: - Add RB from Frank and Alexander - Make resets: mandatory on i.MX95 - Switch from fsl, to nxp, vendor prefix --- .../devicetree/bindings/gpu/arm,mali-valhall-csf.yaml | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/Documentation/devicetree/bindings/gpu/arm,mali-valhall-csf.yaml b/Documentation/devicetree/bindings/gpu/arm,mali-valhall-csf.yaml index 0efa06822a543..485609de54eac 100644 --- a/Documentation/devicetree/bindings/gpu/arm,mali-valhall-csf.yaml +++ b/Documentation/devicetree/bindings/gpu/arm,mali-valhall-csf.yaml @@ -18,6 +18,7 @@ properties: oneOf: - items: - enum: + - nxp,imx95-mali # G310 - rockchip,rk3588-mali - const: arm,mali-valhall-csf # Mali Valhall GPU model/revision is fully discoverable @@ -111,6 +112,14 @@ allOf: power-domains: maxItems: 1 power-domain-names: false + - if: + properties: + compatible: + contains: + const: nxp,imx95-mali + then: + required: + - resets examples: - | From patchwork Fri Mar 21 20:05:58 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Marek Vasut X-Patchwork-Id: 14025997 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 844D8C36000 for ; Fri, 21 Mar 2025 20:07:22 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id C4B1310E833; Fri, 21 Mar 2025 20:07:21 +0000 (UTC) Authentication-Results: gabe.freedesktop.org; dkim=pass (2048-bit key; unprotected) header.d=denx.de header.i=@denx.de header.b="ZTaqmbiV"; dkim-atps=neutral Received: from mx.denx.de (mx.denx.de [89.58.32.78]) by gabe.freedesktop.org (Postfix) with ESMTPS id 017CB10E832 for ; Fri, 21 Mar 2025 20:07:20 +0000 (UTC) Received: from [127.0.0.1] (localhost [127.0.0.1]) by localhost (Mailerdaemon) with ESMTPSA id CA41810206773; Fri, 21 Mar 2025 21:07:17 +0100 (CET) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=denx.de; s=mx-20241105; t=1742587639; h=from:subject:date:message-id:to:cc:mime-version: content-transfer-encoding:in-reply-to:references; bh=GS0DTW8urIe1mVBYAFT1ILELcujA8A8LqLBoIuElaRI=; b=ZTaqmbiV6GWUzLqpmKiQCW+8deNpU3TNxYAvqgUb7GivfibYqRoLRFU7PmdpUX76XNtTK5 SsibKYYtGFj43qbQFVnk0uXJyKU9CvCpK+v3dVs4Mo/4qAwjrjl8ksdLqU2gc5J1AywDNu 5uk8lCJX1YrocnlB8JiVOY8Sx9V0jsCqytMNWA2gvowfl2tOJf2JAk43csHcflGkVdsBGE JmTS3mAZN7uC9Abcer6W4v2467gw1c7FPB2z9WbK0PjclcjS6cSDLCJjkl3XNpglOEn96n C7vznTE7eMXWzkUTOekiR4GJhiqfh+UqV+Idw2QiC8TPZni718gVWjwx1L8Z0A== From: Marek Vasut To: linux-arm-kernel@lists.infradead.org Cc: Marek Vasut , Frank Li , Boris Brezillon , Conor Dooley , David Airlie , Fabio Estevam , Krzysztof Kozlowski , Liviu Dudau , Maarten Lankhorst , Maxime Ripard , Pengutronix Kernel Team , Philipp Zabel , Rob Herring , Sascha Hauer , Sebastian Reichel , Shawn Guo , Simona Vetter , Steven Price , Thomas Zimmermann , devicetree@vger.kernel.org, dri-devel@lists.freedesktop.org, imx@lists.linux.dev Subject: [PATCH v2 8/9] drm/panthor: Add i.MX95 support Date: Fri, 21 Mar 2025 21:05:58 +0100 Message-ID: <20250321200625.132494-9-marex@denx.de> X-Mailer: git-send-email 2.47.2 In-Reply-To: <20250321200625.132494-1-marex@denx.de> References: <20250321200625.132494-1-marex@denx.de> MIME-Version: 1.0 X-Last-TLS-Session-Version: TLSv1.3 X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" The instance of the GPU populated in Freescale i.MX95 is the Mali G310, add support for this variant. Reviewed-by: Frank Li Signed-off-by: Marek Vasut --- Cc: Boris Brezillon Cc: Conor Dooley Cc: David Airlie Cc: Fabio Estevam Cc: Krzysztof Kozlowski Cc: Liviu Dudau Cc: Maarten Lankhorst Cc: Maxime Ripard Cc: Pengutronix Kernel Team Cc: Philipp Zabel Cc: Rob Herring Cc: Sascha Hauer Cc: Sebastian Reichel Cc: Shawn Guo Cc: Simona Vetter Cc: Steven Price Cc: Thomas Zimmermann Cc: devicetree@vger.kernel.org Cc: dri-devel@lists.freedesktop.org Cc: imx@lists.linux.dev Cc: linux-arm-kernel@lists.infradead.org --- V2: - Add RB from Frank - Switch from fsl, to nxp, vendor prefix - Fix up GPU_MODEL(g310, 0, 0) to GPU_MODEL(g310, 10, 4) - Remove code comments about MX95 and G310 --- drivers/gpu/drm/panthor/panthor_drv.c | 1 + drivers/gpu/drm/panthor/panthor_gpu.c | 1 + 2 files changed, 2 insertions(+) diff --git a/drivers/gpu/drm/panthor/panthor_drv.c b/drivers/gpu/drm/panthor/panthor_drv.c index 06fe46e320738..299ec8bafdd17 100644 --- a/drivers/gpu/drm/panthor/panthor_drv.c +++ b/drivers/gpu/drm/panthor/panthor_drv.c @@ -1591,6 +1591,7 @@ static struct attribute *panthor_attrs[] = { ATTRIBUTE_GROUPS(panthor); static const struct of_device_id dt_match[] = { + { .compatible = "nxp,imx95-mali" }, { .compatible = "rockchip,rk3588-mali" }, { .compatible = "arm,mali-valhall-csf" }, {} diff --git a/drivers/gpu/drm/panthor/panthor_gpu.c b/drivers/gpu/drm/panthor/panthor_gpu.c index 0f07ef7d9aea7..59fc1cacefcfe 100644 --- a/drivers/gpu/drm/panthor/panthor_gpu.c +++ b/drivers/gpu/drm/panthor/panthor_gpu.c @@ -67,6 +67,7 @@ struct panthor_model { } static const struct panthor_model gpu_models[] = { + GPU_MODEL(g310, 10, 4), GPU_MODEL(g610, 10, 7), {}, }; From patchwork Fri Mar 21 20:05:59 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Marek Vasut X-Patchwork-Id: 14026001 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id D2916C36000 for ; Fri, 21 Mar 2025 20:07:33 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 4A95C10E837; Fri, 21 Mar 2025 20:07:33 +0000 (UTC) Authentication-Results: gabe.freedesktop.org; dkim=pass (2048-bit key; unprotected) header.d=denx.de header.i=@denx.de header.b="X7jesX2i"; dkim-atps=neutral Received: from mx.denx.de (mx.denx.de [89.58.32.78]) by gabe.freedesktop.org (Postfix) with ESMTPS id B666D10E836 for ; Fri, 21 Mar 2025 20:07:22 +0000 (UTC) Received: from [127.0.0.1] (localhost [127.0.0.1]) by localhost (Mailerdaemon) with ESMTPSA id 98AF9101E90A8; Fri, 21 Mar 2025 21:07:19 +0100 (CET) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=denx.de; s=mx-20241105; t=1742587640; h=from:subject:date:message-id:to:cc:mime-version: content-transfer-encoding:in-reply-to:references; bh=5+jyyD01tuaQ9cu3oI1xcyMiNqOwJFt8kuWaEBU5/6M=; b=X7jesX2iMhyumPrNedJv8B7XDjh9wic5AVfGyGcHHjXEGGlmQlyN5IX89SX6MgHKiAQMBR Ct/179I90ZNIfnBvCXwnYO8JjWcvFXj6suKf1XPJsKG2iDb406uTu4IfNxw5kObrfNK38u 0IGcUf3aloiWa3ePtAQ09nGRbH9v8W13NlVg0YSTDLtPUKofPPgbrT7xk6R+1aIfrD7Xpz ZPkmm0ovCje/ouFs6fjxQTxXdwZwYbZMJs9fgY7FBXuelthnbmkdZA8iBNqJqhRIipB/bO UDfOEmH1jI2Ldj1BdeNVv8wIfYtqnA1sY0/4HdEr6EekGeuLolSMHTLNyW3YFA== From: Marek Vasut To: linux-arm-kernel@lists.infradead.org Cc: Marek Vasut , Boris Brezillon , Conor Dooley , David Airlie , Fabio Estevam , Krzysztof Kozlowski , Liviu Dudau , Maarten Lankhorst , Maxime Ripard , Pengutronix Kernel Team , Philipp Zabel , Rob Herring , Sascha Hauer , Sebastian Reichel , Shawn Guo , Simona Vetter , Steven Price , Thomas Zimmermann , devicetree@vger.kernel.org, dri-devel@lists.freedesktop.org, imx@lists.linux.dev Subject: [PATCH v2 9/9] arm64: dts: imx95: Describe Mali G310 GPU Date: Fri, 21 Mar 2025 21:05:59 +0100 Message-ID: <20250321200625.132494-10-marex@denx.de> X-Mailer: git-send-email 2.47.2 In-Reply-To: <20250321200625.132494-1-marex@denx.de> References: <20250321200625.132494-1-marex@denx.de> MIME-Version: 1.0 X-Last-TLS-Session-Version: TLSv1.3 X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" The instance of the GPU populated in i.MX95 is the G310, describe this GPU in the DT. Include description of the GPUMIX block controller, which can be operated as a simple reset. Include dummy GPU voltage regulator and OPP tables. Signed-off-by: Marek Vasut --- Cc: Boris Brezillon Cc: Conor Dooley Cc: David Airlie Cc: Fabio Estevam Cc: Krzysztof Kozlowski Cc: Liviu Dudau Cc: Maarten Lankhorst Cc: Maxime Ripard Cc: Pengutronix Kernel Team Cc: Philipp Zabel Cc: Rob Herring Cc: Sascha Hauer Cc: Sebastian Reichel Cc: Shawn Guo Cc: Simona Vetter Cc: Steven Price Cc: Thomas Zimmermann Cc: devicetree@vger.kernel.org Cc: dri-devel@lists.freedesktop.org Cc: imx@lists.linux.dev Cc: linux-arm-kernel@lists.infradead.org --- V2: - Drop regulator-{always,boot}-on from fixed-gpu-reg regulator - Keep the GPU and GPUMIX always enabled - Switch from fsl, to nxp, vendor prefix - Fix opp_table to opp-table - Describe IMX95_CLK_GPUAPB as coregroup clock - Sort interrupts by their names to match bindings --- arch/arm64/boot/dts/freescale/imx95.dtsi | 58 ++++++++++++++++++++++++ 1 file changed, 58 insertions(+) diff --git a/arch/arm64/boot/dts/freescale/imx95.dtsi b/arch/arm64/boot/dts/freescale/imx95.dtsi index 9bb26b466a061..3acdbd7fd4eee 100644 --- a/arch/arm64/boot/dts/freescale/imx95.dtsi +++ b/arch/arm64/boot/dts/freescale/imx95.dtsi @@ -249,6 +249,35 @@ dummy: clock-dummy { clock-output-names = "dummy"; }; + gpu_fixed_reg: fixed-gpu-reg { + compatible = "regulator-fixed"; + regulator-min-microvolt = <920000>; + regulator-max-microvolt = <920000>; + regulator-name = "vdd_gpu"; + }; + + gpu_opp_table: opp-table { + compatible = "operating-points-v2"; + + opp-500000000 { + opp-hz = /bits/ 64 <500000000>; + opp-hz-real = /bits/ 64 <500000000>; + opp-microvolt = <920000>; + }; + + opp-800000000 { + opp-hz = /bits/ 64 <800000000>; + opp-hz-real = /bits/ 64 <800000000>; + opp-microvolt = <920000>; + }; + + opp-1000000000 { + opp-hz = /bits/ 64 <1000000000>; + opp-hz-real = /bits/ 64 <1000000000>; + opp-microvolt = <920000>; + }; + }; + clk_ext1: clock-ext1 { compatible = "fixed-clock"; #clock-cells = <0>; @@ -1890,6 +1919,35 @@ netc_emdio: mdio@0,0 { }; }; + gpu_blk_ctrl: reset-controller@4d810000 { + compatible = "nxp,imx95-gpu-blk-ctrl"; + reg = <0x0 0x4d810000 0x0 0xc>; + #reset-cells = <1>; + clocks = <&scmi_clk IMX95_CLK_GPUAPB>; + assigned-clocks = <&scmi_clk IMX95_CLK_GPUAPB>; + assigned-clock-parents = <&scmi_clk IMX95_CLK_SYSPLL1_PFD1_DIV2>; + assigned-clock-rates = <133333333>; + power-domains = <&scmi_devpd IMX95_PD_GPU>; + }; + + gpu: gpu@4d900000 { + compatible = "nxp,imx95-mali", "arm,mali-valhall-csf"; + reg = <0 0x4d900000 0 0x480000>; + clocks = <&scmi_clk IMX95_CLK_GPU>, <&scmi_clk IMX95_CLK_GPUAPB>; + clock-names = "core", "coregroup"; + interrupts = , + , + ; + interrupt-names = "job", "mmu", "gpu"; + mali-supply = <&gpu_fixed_reg>; + operating-points-v2 = <&gpu_opp_table>; + power-domains = <&scmi_devpd IMX95_PD_GPU>, <&scmi_perf IMX95_PERF_GPU>; + power-domain-names = "mix", "perf"; + resets = <&gpu_blk_ctrl 0>; + #cooling-cells = <2>; + dynamic-power-coefficient = <1013>; + }; + ddr-pmu@4e090dc0 { compatible = "fsl,imx95-ddr-pmu", "fsl,imx93-ddr-pmu"; reg = <0x0 0x4e090dc0 0x0 0x200>;