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Sun, 23 Mar 2025 05:28:43 -0700 From: Tariq Toukan To: "David S. Miller" , Jakub Kicinski , Paolo Abeni , Eric Dumazet , "Andrew Lunn" CC: Gal Pressman , Leon Romanovsky , "Saeed Mahameed" , Leon Romanovsky , Tariq Toukan , , , , Moshe Shemesh , Mark Bloch , Lama Kayal Subject: [PATCH net] net/mlx5e: SHAMPO, Make reserved size independent of page size Date: Sun, 23 Mar 2025 14:28:26 +0200 Message-ID: <1742732906-166564-1-git-send-email-tariqt@nvidia.com> X-Mailer: git-send-email 2.8.0 Precedence: bulk X-Mailing-List: netdev@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-NV-OnPremToCloud: AnonymousSubmission X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: DS2PEPF0000343E:EE_|IA1PR12MB6305:EE_ X-MS-Office365-Filtering-Correlation-Id: f91d1100-1817-4523-675a-08dd6a0642df X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|376014|1800799024|36860700013|82310400026; X-Microsoft-Antispam-Message-Info: W5BDBqUE9PvOl2j46ATKcuF/v+2g+uneqpk+mS/OY0pr2Bj9PZT/i4eOMubWXXKoQile+avuEZWcM+7EILja4b+RD7yj0wO6qddEP1oMWScET/Z6Rif2Uve+21DzCjFmzSODbVmjHmnjUIH86AXChOVMr62MOPe2SvccdbWjkvZIF2opH9ImrIheyCfBUbIAhwk/uXzQeSTV3slibhbmhXfQt8yYgR8dowYK1SZq1dwFjbQYLR+GIM7NlDMX9bZGE4ZENVgQqajpXoweEhqzucaQH0qiL+BDwUhLm2tA2CmEahb6YWxOEPaL6m5u4lJub7BVxlRUxRVvSKY6QLA0pLUHhavIGYt6wMzv8DXVYajyUnPv5ZExgAVH4/wOYEyUxd4lVGkzqH8fc/mMtLiSGVV7RljcEG+KyKQB91l06gO8y3bOQRmBIkFO5OkqW4Guf36RwCrgIuv/O9Um6oFgHErNCIT8rSoYgJPOBBbqPFbKL1ajqDN+zWkNnySMLCklOJXlugfSgaNm/+cTCQaG2FaLMzIwIacQX1sGdH2OQDAd61dN04gr6OuFxBcIKMAs6pofBy4SnNVhXEU+CVHT7oVEtaSN9oR2ngt31TtQ9YO+9CPtUfv4mr62hUDReZsj4yYoKhJE9GNYjqNDx9xQLJyO9Fy/Da+v2Va7X1551j48OPeFhyJgn10pNX8vXeXZ2+Sz9gPXY7ZAligJNywcb8m28joUhb3goLULdNAP42E3R83GACNDCVXfavt+4MtB/nZgdQ4zM+8mxr8LIb7PHhlH/7B2IyHvg90X7tjDNgD/sPEc3WE4ZjQ7dgNaAkFyKgWDLL1KZJFCt+vy/tWYjFNeEnMFB5BzkD8HUdjTk4ll26SwEd99a7j/GzVhscwrkk320a5RGsKiq+1LtUNSVQPRij9Yf36pvDMUKAtj9AI8eQMkW6FBdWeOs2uY06ISx0aG0JYGOMiIJnwFRNpuFaU0HoZ+SGCaWbhbMuWzUn5OqSe6CYb3a1RidZo+9XsEgFNbMM/O3+3ZG27PunOOru3+Mk6p1ZjluOe9IQZT1B3++F/UEKWGwDjCaYNazbZddOj21GwZ8I0c34A3VQAzPj2hX5+6MnbS0fl06rYkMKVJ4+hkVqIaTOqPnag+IshhphfAywe2Z6FcBAiBMSKBa12EiuGpykJ2HtzB9Va2VOaSIW4t98EuZc2t+nLiCO8vg5brBsxvBPOBvRJxEwh3R2+dtL0p03ALYlfv2NL7xq3tsGBDU0M4+lo9w/WL1RncGPPTXoRwNRNdA4vTBM9KKIFHDnYS/ELXG+DeEXVzKacaupWf03LrRdautPiixy0bdumYwaXKJ2H454uAYtkUVVFIUs6Iq0uJJqYWf4Icp9mdYuJyGdM6KaXU1SKy/iUCQwo8bLOOLUDYj0snQ6/cVtWuxbrOend3Sk4slZQNsL8KBvGQZiZZqFWTbOZcdTn8Oqp8uFcQzp92YTYWtjaUSWMiPZ7B5IVdlJlEsIgYzGo= X-Forefront-Antispam-Report: CIP:216.228.118.232;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:dc7edge1.nvidia.com;CAT:NONE;SFS:(13230040)(376014)(1800799024)(36860700013)(82310400026);DIR:OUT;SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 23 Mar 2025 12:28:47.9357 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: f91d1100-1817-4523-675a-08dd6a0642df X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.118.232];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: DS2PEPF0000343E.namprd02.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: IA1PR12MB6305 X-Patchwork-Delegate: kuba@kernel.org From: Lama Kayal When hw-gro is enabled, the maximum number of header entries that are needed per wqe (hd_per_wqe) is calculated based on the size of the reservations among other parameters. Miscalculation of the size of reservations leads to incorrect calculation of hd_per_wqe as 0, particularly in the case of large page size like in aarch64, this prevents the SHAMPO header from being correctly initialized in the device, ultimately causing the following cqe err that indicates a violation of PD. mlx5_core 0000:00:08.0 eth2: ERR CQE on RQ: 0x1180 mlx5_core 0000:00:08.0 eth2: Error cqe on cqn 0x510, ci 0x0, qn 0x1180, opcode 0xe, syndrome 0x4, vendor syndrome 0x32 00000000: 00 00 00 00 04 4a 00 00 00 00 00 00 20 00 93 32 00000010: 55 00 00 00 fb cc 00 00 00 00 00 00 07 18 00 00 00000020: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 4a 00000030: 00 00 00 9a 93 00 32 04 00 00 00 00 00 00 da e1 Use the correct formula for calculating the size of reservations, precisely it shouldn't be dependent on page size, instead use the correct multiply of MLX5E_SHAMPO_WQ_BASE_RESRV_SIZE. Fixes: e5ca8fb08ab2 ("net/mlx5e: Add control path for SHAMPO feature") Signed-off-by: Lama Kayal Reviewed-by: Dragos Tatulea Signed-off-by: Tariq Toukan --- drivers/net/ethernet/mellanox/mlx5/core/en/params.c | 8 +++++--- 1 file changed, 5 insertions(+), 3 deletions(-) base-commit: ed3ba9b6e280e14cc3148c1b226ba453f02fa76c diff --git a/drivers/net/ethernet/mellanox/mlx5/core/en/params.c b/drivers/net/ethernet/mellanox/mlx5/core/en/params.c index 64b62ed17b07..31eb99f09c63 100644 --- a/drivers/net/ethernet/mellanox/mlx5/core/en/params.c +++ b/drivers/net/ethernet/mellanox/mlx5/core/en/params.c @@ -423,7 +423,7 @@ u8 mlx5e_shampo_get_log_pkt_per_rsrv(struct mlx5_core_dev *mdev, struct mlx5e_params *params) { u32 resrv_size = BIT(mlx5e_shampo_get_log_rsrv_size(mdev, params)) * - PAGE_SIZE; + MLX5E_SHAMPO_WQ_BASE_RESRV_SIZE; return order_base_2(DIV_ROUND_UP(resrv_size, params->sw_mtu)); } @@ -827,7 +827,8 @@ static u32 mlx5e_shampo_get_log_cq_size(struct mlx5_core_dev *mdev, struct mlx5e_params *params, struct mlx5e_xsk_param *xsk) { - int rsrv_size = BIT(mlx5e_shampo_get_log_rsrv_size(mdev, params)) * PAGE_SIZE; + int rsrv_size = BIT(mlx5e_shampo_get_log_rsrv_size(mdev, params)) * + MLX5E_SHAMPO_WQ_BASE_RESRV_SIZE; u16 num_strides = BIT(mlx5e_mpwqe_get_log_num_strides(mdev, params, xsk)); int pkt_per_rsrv = BIT(mlx5e_shampo_get_log_pkt_per_rsrv(mdev, params)); u8 log_stride_sz = mlx5e_mpwqe_get_log_stride_size(mdev, params, xsk); @@ -1036,7 +1037,8 @@ u32 mlx5e_shampo_hd_per_wqe(struct mlx5_core_dev *mdev, struct mlx5e_params *params, struct mlx5e_rq_param *rq_param) { - int resv_size = BIT(mlx5e_shampo_get_log_rsrv_size(mdev, params)) * PAGE_SIZE; + int resv_size = BIT(mlx5e_shampo_get_log_rsrv_size(mdev, params)) * + MLX5E_SHAMPO_WQ_BASE_RESRV_SIZE; u16 num_strides = BIT(mlx5e_mpwqe_get_log_num_strides(mdev, params, NULL)); int pkt_per_resv = BIT(mlx5e_shampo_get_log_pkt_per_rsrv(mdev, params)); u8 log_stride_sz = mlx5e_mpwqe_get_log_stride_size(mdev, params, NULL);