From patchwork Mon Mar 24 12:37:10 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Mi, Dapeng" X-Patchwork-Id: 14026851 Received: from mgamail.intel.com (mgamail.intel.com [192.198.163.16]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 4FC972505C2 for ; Mon, 24 Mar 2025 07:08:44 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=192.198.163.16 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1742800126; cv=none; b=IZgpUtn3+N/7xJXtV/fnK0NLXK63W4QtIsHWkRJHISSkiWMH6gTgkip6J1seV6eK/nex+0dInJmNT2XmH8Dno06VM7ha0dKFiOjX8Y3FCC11zkqhVkvdHaL9uNd6sC1NFVhfRdvB42PmHXfmf7TapC3GQ+UDss7LZBROOlWwX6k= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1742800126; c=relaxed/simple; bh=GkePnjIVwJy2gtvDqRPqWnH+ClNauDcNXM7UqV0aetc=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=oITKsd0D9+S/zissyO3E2kNUMCdwDZ9FU2+OSW5M9BEQSzRjog7+VQeMlpM7rc7iHpB6/vwEOv8XKIWVdNwWwm2pkTTDu2AdEhwftb3wzbBM4GEt+2NZF7Kes8PQJJZ3ho8oJfxQ1CNfo95TDYJwNaD0fdxfs+vLAnGvbe7TXP4= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.intel.com; spf=none smtp.mailfrom=linux.intel.com; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b=NSD7MPZC; arc=none smtp.client-ip=192.198.163.16 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.intel.com Authentication-Results: smtp.subspace.kernel.org; spf=none smtp.mailfrom=linux.intel.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b="NSD7MPZC" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1742800124; x=1774336124; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=GkePnjIVwJy2gtvDqRPqWnH+ClNauDcNXM7UqV0aetc=; b=NSD7MPZCHOatWMXEPbaiZQ4yduZ48oLEzuyqk8zDapO5eTqBxfKFMiqW qXpiU46GwuM36Z+BUz1VZkNblDa0uIsAbIMW4mmbFoN5aKbgcMKlw3Tyq L04Uy5s4IiSIMxILtMPRgT+YiHM3SVxTr/J+wf0JCoWtMs1Ha7ku3OIJX Tu5CP2jrSBaxF0MNn8szW8HmJl8gAFDNswAW93k44+306jkaqULLrcYXg vPIi80IETGfh6lDZkmjcsWckCEfpLyVg1g4GZxhXotjz0kKJt94Mo2DdI 9L1/6bvS+aoYFokjA0nOkWTGq13OWehLagUqNr/fnK8nmi/x6wuY46zbw w==; X-CSE-ConnectionGUID: h9coHqEvQyaL1LeP1Wtizw== X-CSE-MsgGUID: V0FXUkmxTmeaoKmdUgZMJw== X-IronPort-AV: E=McAfee;i="6700,10204,11382"; a="31588457" X-IronPort-AV: E=Sophos;i="6.14,271,1736841600"; d="scan'208";a="31588457" Received: from fmviesa007.fm.intel.com ([10.60.135.147]) by fmvoesa110.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 24 Mar 2025 00:08:44 -0700 X-CSE-ConnectionGUID: C9tRJ6dtTjuTepXb6kbW3Q== X-CSE-MsgGUID: uqJ5HATGRKK6tTeN6Y6cww== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.14,271,1736841600"; d="scan'208";a="123944365" Received: from emr.sh.intel.com ([10.112.229.56]) by fmviesa007.fm.intel.com with ESMTP; 24 Mar 2025 00:08:40 -0700 From: Dapeng Mi To: Paolo Bonzini , Sean Christopherson Cc: qemu-devel@nongnu.org, kvm@vger.kernel.org, Zhao Liu , Zide Chen , Xiaoyao Li , Dongli Zhang , Mingwei Zhang , Das Sandipan , Shukla Manali , Dapeng Mi , Gerd Hoffmann Subject: [PATCH 1/3] kvm: Introduce kvm_arch_pre_create_vcpu() Date: Mon, 24 Mar 2025 12:37:10 +0000 Message-Id: <20250324123712.34096-2-dapeng1.mi@linux.intel.com> X-Mailer: git-send-email 2.40.1 In-Reply-To: <20250324123712.34096-1-dapeng1.mi@linux.intel.com> References: <20250324123712.34096-1-dapeng1.mi@linux.intel.com> Precedence: bulk X-Mailing-List: kvm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 From: Xiaoyao Li Introduce kvm_arch_pre_create_vcpu(), to perform arch-dependent work prior to create any vcpu. This is for i386 TDX because it needs call TDX_INIT_VM before creating any vcpu. The specific implemnet of i386 will be added in the future patch. Signed-off-by: Xiaoyao Li Acked-by: Gerd Hoffmann --- accel/kvm/kvm-all.c | 5 +++++ include/system/kvm.h | 1 + target/arm/kvm.c | 5 +++++ target/i386/kvm/kvm.c | 5 +++++ target/loongarch/kvm/kvm.c | 5 +++++ target/mips/kvm.c | 5 +++++ target/ppc/kvm.c | 5 +++++ target/riscv/kvm/kvm-cpu.c | 5 +++++ target/s390x/kvm/kvm.c | 5 +++++ 9 files changed, 41 insertions(+) diff --git a/accel/kvm/kvm-all.c b/accel/kvm/kvm-all.c index f89568bfa3..df9840e53a 100644 --- a/accel/kvm/kvm-all.c +++ b/accel/kvm/kvm-all.c @@ -540,6 +540,11 @@ int kvm_init_vcpu(CPUState *cpu, Error **errp) trace_kvm_init_vcpu(cpu->cpu_index, kvm_arch_vcpu_id(cpu)); + ret = kvm_arch_pre_create_vcpu(cpu, errp); + if (ret < 0) { + goto err; + } + ret = kvm_create_vcpu(cpu); if (ret < 0) { error_setg_errno(errp, -ret, diff --git a/include/system/kvm.h b/include/system/kvm.h index ab17c09a55..d7dfa25493 100644 --- a/include/system/kvm.h +++ b/include/system/kvm.h @@ -374,6 +374,7 @@ int kvm_arch_get_default_type(MachineState *ms); int kvm_arch_init(MachineState *ms, KVMState *s); +int kvm_arch_pre_create_vcpu(CPUState *cpu, Error **errp); int kvm_arch_init_vcpu(CPUState *cpu); int kvm_arch_destroy_vcpu(CPUState *cpu); diff --git a/target/arm/kvm.c b/target/arm/kvm.c index da30bdbb23..93f1a7245b 100644 --- a/target/arm/kvm.c +++ b/target/arm/kvm.c @@ -1874,6 +1874,11 @@ static int kvm_arm_sve_set_vls(ARMCPU *cpu) #define ARM_CPU_ID_MPIDR 3, 0, 0, 0, 5 +int kvm_arch_pre_create_vcpu(CPUState *cpu, Error **errp) +{ + return 0; +} + int kvm_arch_init_vcpu(CPUState *cs) { int ret; diff --git a/target/i386/kvm/kvm.c b/target/i386/kvm/kvm.c index 6c749d4ee8..f41e190fb8 100644 --- a/target/i386/kvm/kvm.c +++ b/target/i386/kvm/kvm.c @@ -2051,6 +2051,11 @@ full: abort(); } +int kvm_arch_pre_create_vcpu(CPUState *cpu, Error **errp) +{ + return 0; +} + int kvm_arch_init_vcpu(CPUState *cs) { struct { diff --git a/target/loongarch/kvm/kvm.c b/target/loongarch/kvm/kvm.c index 7f63e7c8fe..ed0ddf1cbf 100644 --- a/target/loongarch/kvm/kvm.c +++ b/target/loongarch/kvm/kvm.c @@ -1075,6 +1075,11 @@ static int kvm_cpu_check_pv_features(CPUState *cs, Error **errp) return 0; } +int kvm_arch_pre_create_vcpu(CPUState *cpu, Error **errp) +{ + return 0; +} + int kvm_arch_init_vcpu(CPUState *cs) { uint64_t val; diff --git a/target/mips/kvm.c b/target/mips/kvm.c index d67b7c1a8e..ec53acb51a 100644 --- a/target/mips/kvm.c +++ b/target/mips/kvm.c @@ -61,6 +61,11 @@ int kvm_arch_irqchip_create(KVMState *s) return 0; } +int kvm_arch_pre_create_vcpu(CPUState *cpu, Error **errp) +{ + return 0; +} + int kvm_arch_init_vcpu(CPUState *cs) { CPUMIPSState *env = cpu_env(cs); diff --git a/target/ppc/kvm.c b/target/ppc/kvm.c index 992356cb75..20fabccecd 100644 --- a/target/ppc/kvm.c +++ b/target/ppc/kvm.c @@ -479,6 +479,11 @@ static void kvmppc_hw_debug_points_init(CPUPPCState *cenv) } } +int kvm_arch_pre_create_vcpu(CPUState *cpu, Error **errp) +{ + return 0; +} + int kvm_arch_init_vcpu(CPUState *cs) { PowerPCCPU *cpu = POWERPC_CPU(cs); diff --git a/target/riscv/kvm/kvm-cpu.c b/target/riscv/kvm/kvm-cpu.c index 4ffeeaa1c9..451c00f17c 100644 --- a/target/riscv/kvm/kvm-cpu.c +++ b/target/riscv/kvm/kvm-cpu.c @@ -1389,6 +1389,11 @@ static int kvm_vcpu_enable_sbi_dbcn(RISCVCPU *cpu, CPUState *cs) return kvm_set_one_reg(cs, kvm_sbi_dbcn.kvm_reg_id, ®); } +int kvm_arch_pre_create_vcpu(CPUState *cpu, Error **errp) +{ + return 0; +} + int kvm_arch_init_vcpu(CPUState *cs) { int ret = 0; diff --git a/target/s390x/kvm/kvm.c b/target/s390x/kvm/kvm.c index 4d56e653dd..1f592733f4 100644 --- a/target/s390x/kvm/kvm.c +++ b/target/s390x/kvm/kvm.c @@ -404,6 +404,11 @@ unsigned long kvm_arch_vcpu_id(CPUState *cpu) return cpu->cpu_index; } +int kvm_arch_pre_create_vcpu(CPUState *cpu, Error **errp) +{ + return 0; +} + int kvm_arch_init_vcpu(CPUState *cs) { unsigned int max_cpus = MACHINE(qdev_get_machine())->smp.max_cpus; From patchwork Mon Mar 24 12:37:11 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Mi, Dapeng" X-Patchwork-Id: 14026852 Received: from mgamail.intel.com (mgamail.intel.com [192.198.163.16]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 62CED2505C3 for ; Mon, 24 Mar 2025 07:08:47 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=192.198.163.16 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1742800128; cv=none; b=RctTmOY2bRSLXj72l8kSrFxuZvC5swDkiR2685GynBRr046f0Yh0ars98NNTgD+6xwri1Pv/haBK+VNO1fk6r0Vj8xQne4eLYe3msHR2wepCGBZ75HwOV1bmerOc4HZBXWvR1HYA20w1PMCud3N+uE/WTKJhQMV8niB+kI9KSnE= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1742800128; c=relaxed/simple; bh=RSPvGIZxsfM4bA/IY36Wq0EbC6TmhSvPF08yfS2Nt4k=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=AYVxAGxQty2283MOA6eb+ud+HvkjRn/QnY4+04IzKdZOZvInEw4cHAxn2noIQBnnzQ1n60V2B4hqVZiwYTxOnPs9eVwCx8gvlB9/gJ2teuyKCw6m/y2FW2ortHluNxKlopbt4D1kUKh+YDY8hRoE7nxZsc0BXb+DkfimEmAthCo= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.intel.com; spf=none smtp.mailfrom=linux.intel.com; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b=MoGwIImQ; arc=none smtp.client-ip=192.198.163.16 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.intel.com Authentication-Results: smtp.subspace.kernel.org; spf=none smtp.mailfrom=linux.intel.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b="MoGwIImQ" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1742800127; x=1774336127; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=RSPvGIZxsfM4bA/IY36Wq0EbC6TmhSvPF08yfS2Nt4k=; b=MoGwIImQ0XhFl5lW6cjo7ROm0Pufu0daxxxsgaT6o1DE+l536+CIbq/o pAbfbsHpN6OLuHuvfQkGbOHoJzW6OeZNttsVbqYnHtHge6k3NE+H50D7D Pkfk1uSW9ogsqb0jxwpzqb6nDXOixR0JWU6qB5+cgpVWXQU3/F0dvlU23 YFhBEUheGMlgL3kdJRfznOYe9BFs9RGiEJZEOPPm+MXY2W2aAAhsWVtxb +hEo7KbLgBuABUtJmTwMN8nEDUKrPIS1xyH3cYT5G4VXvIBqC/uMFBaN0 m8olmH0CrCh5i/7G+22mQWvb2YDvEy+OCPnhr1k6TDXKStajlDeRphM39 w==; X-CSE-ConnectionGUID: Q+prNaCwQUmu9enr+fEsmA== X-CSE-MsgGUID: nLcm9R4TRwyGsrgag9NtVw== X-IronPort-AV: E=McAfee;i="6700,10204,11382"; a="31588465" X-IronPort-AV: E=Sophos;i="6.14,271,1736841600"; d="scan'208";a="31588465" Received: from fmviesa007.fm.intel.com ([10.60.135.147]) by fmvoesa110.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 24 Mar 2025 00:08:47 -0700 X-CSE-ConnectionGUID: h7j1ukYCQSqoT6dryF50Bw== X-CSE-MsgGUID: 6xu+B54JQaiEpUbobTY1pw== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.14,271,1736841600"; d="scan'208";a="123944393" Received: from emr.sh.intel.com ([10.112.229.56]) by fmviesa007.fm.intel.com with ESMTP; 24 Mar 2025 00:08:44 -0700 From: Dapeng Mi To: Paolo Bonzini , Sean Christopherson Cc: qemu-devel@nongnu.org, kvm@vger.kernel.org, Zhao Liu , Zide Chen , Xiaoyao Li , Dongli Zhang , Mingwei Zhang , Das Sandipan , Shukla Manali , Dapeng Mi , Dapeng Mi Subject: [PATCH 2/3] target/i386: Call KVM_CAP_PMU_CAPABILITY iotcl to enable/disable PMU Date: Mon, 24 Mar 2025 12:37:11 +0000 Message-Id: <20250324123712.34096-3-dapeng1.mi@linux.intel.com> X-Mailer: git-send-email 2.40.1 In-Reply-To: <20250324123712.34096-1-dapeng1.mi@linux.intel.com> References: <20250324123712.34096-1-dapeng1.mi@linux.intel.com> Precedence: bulk X-Mailing-List: kvm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 After introducing mediated vPMU, mediated vPMU must be enabled by explicitly calling KVM_CAP_PMU_CAPABILITY to enable. Thus call KVM_CAP_PMU_CAPABILITY to enable/disable PMU base on user configuration. Suggested-by: Zhao Liu Signed-off-by: Dapeng Mi --- target/i386/kvm/kvm.c | 17 +++++++++++++++++ 1 file changed, 17 insertions(+) diff --git a/target/i386/kvm/kvm.c b/target/i386/kvm/kvm.c index f41e190fb8..d3e6984844 100644 --- a/target/i386/kvm/kvm.c +++ b/target/i386/kvm/kvm.c @@ -2051,8 +2051,25 @@ full: abort(); } +static bool pmu_cap_set = false; int kvm_arch_pre_create_vcpu(CPUState *cpu, Error **errp) { + KVMState *s = kvm_state; + X86CPU *x86_cpu = X86_CPU(cpu); + + if (!pmu_cap_set && kvm_check_extension(s, KVM_CAP_PMU_CAPABILITY)) { + int r = kvm_vm_enable_cap(s, KVM_CAP_PMU_CAPABILITY, 0, + KVM_PMU_CAP_DISABLE & !x86_cpu->enable_pmu); + if (r < 0) { + error_report("kvm: Failed to %s pmu cap: %s", + x86_cpu->enable_pmu ? "enable" : "disable", + strerror(-r)); + return r; + } + + pmu_cap_set = true; + } + return 0; } From patchwork Mon Mar 24 12:37:12 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Mi, Dapeng" X-Patchwork-Id: 14026853 Received: from mgamail.intel.com (mgamail.intel.com [192.198.163.16]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 0FC54250BE8 for ; Mon, 24 Mar 2025 07:08:50 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=192.198.163.16 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1742800131; cv=none; b=SsMHsUuf00OZBeWZqQaq7jg1fdIuiE51RfU64DzZyfqxs7l4Xcmy5Obgn4MuO7AyBQz8o8dEP8iZkoDIbxzC7PHuEgPhV27SDvvSMDVsbCkJ+bTiVBYToPSMmfBEufHQ2D5T6H7/zYyujJNUDszISyXhaj2vJJU2RoyxRjUrjvY= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1742800131; c=relaxed/simple; bh=bcLIsmrOKPi83DhR2wgRbrkYxT7RJ0kVGYi7GuXJLOQ=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=IkKr0CaI9qiQKP8EH4HLwE/lPye0+CYZmkPh8M8Ds+op8sXAQr0ta9LhyyiEbd4IiipPpqHQzcFDNcZubVKhXDsH4Vcda0nEmnSly4AhChfLpOhKh37V4LnsnGZv6KO7vbR4B3A3mjRC5nSgGkpII/m0O+GDOumnZJWy39cUWZ4= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.intel.com; spf=none smtp.mailfrom=linux.intel.com; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b=H58ZqUp5; arc=none smtp.client-ip=192.198.163.16 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.intel.com Authentication-Results: smtp.subspace.kernel.org; spf=none smtp.mailfrom=linux.intel.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b="H58ZqUp5" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1742800130; x=1774336130; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=bcLIsmrOKPi83DhR2wgRbrkYxT7RJ0kVGYi7GuXJLOQ=; b=H58ZqUp5H5o7F4CysD639lKhtmJCmjHnn3eU7fXnWRA0JGEM3HIN0C9x m6TTjx2pVTEf0m+wggKbSon8toCIRz/88TPuVKcWo/iH4eQqnKlU0Iahu 6CBtjrxdvgIfhXEwGRB+PC43ztd/RQ10RMQLo4MU80fsigHvLvKeyNa8i TcX27y4Xu1asX1IJCpJb4MP8/SlMSLy+hJXr4H66nZhX1XnxmLIepRsqg LyAjuo+MFv1uS2c7ppGHDtoo376lnitPsBBCEv1AhF6vpAMyKJE8JGUIX H5RURN0d+se20Er24hgjRSrQqvsKM+v4hLoJe3uSwIzthSyn5w0x32gIA w==; X-CSE-ConnectionGUID: AAbSt+AHSqOvX+hphiWlBg== X-CSE-MsgGUID: xOkhPNAiQma/9XTMsGFkgg== X-IronPort-AV: E=McAfee;i="6700,10204,11382"; a="31588479" X-IronPort-AV: E=Sophos;i="6.14,271,1736841600"; d="scan'208";a="31588479" Received: from fmviesa007.fm.intel.com ([10.60.135.147]) by fmvoesa110.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 24 Mar 2025 00:08:50 -0700 X-CSE-ConnectionGUID: N3YfX5fhRDWeGrJegQyyAw== X-CSE-MsgGUID: Gqadn5AZR9ejQjmgIv0XLA== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.14,271,1736841600"; d="scan'208";a="123944422" Received: from emr.sh.intel.com ([10.112.229.56]) by fmviesa007.fm.intel.com with ESMTP; 24 Mar 2025 00:08:47 -0700 From: Dapeng Mi To: Paolo Bonzini , Sean Christopherson Cc: qemu-devel@nongnu.org, kvm@vger.kernel.org, Zhao Liu , Zide Chen , Xiaoyao Li , Dongli Zhang , Mingwei Zhang , Das Sandipan , Shukla Manali , Dapeng Mi , Dapeng Mi Subject: [PATCH 3/3] target/i386: Support VMX_VM_EXIT_SAVE_IA32_PERF_GLOBAL_CTRL Date: Mon, 24 Mar 2025 12:37:12 +0000 Message-Id: <20250324123712.34096-4-dapeng1.mi@linux.intel.com> X-Mailer: git-send-email 2.40.1 In-Reply-To: <20250324123712.34096-1-dapeng1.mi@linux.intel.com> References: <20250324123712.34096-1-dapeng1.mi@linux.intel.com> Precedence: bulk X-Mailing-List: kvm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Since Sapphire Rapids starts, VMX instrocude a new bit SAVE_IA32_PERF_GLOBAL_CTRL in VMCS VM-EXIT control field to manage if vmx can save guest PERF_GLOBAL_CTRL MSR. This patch enables this feature. Signed-off-by: Dapeng Mi --- target/i386/cpu.c | 12 ++++++++---- target/i386/cpu.h | 1 + 2 files changed, 9 insertions(+), 4 deletions(-) diff --git a/target/i386/cpu.c b/target/i386/cpu.c index 1b64ceaaba..317ccc8b0a 100644 --- a/target/i386/cpu.c +++ b/target/i386/cpu.c @@ -1481,7 +1481,8 @@ FeatureWordInfo feature_word_info[FEATURE_WORDS] = { "vmx-exit-save-efer", "vmx-exit-load-efer", "vmx-exit-save-preemption-timer", "vmx-exit-clear-bndcfgs", NULL, "vmx-exit-clear-rtit-ctl", NULL, NULL, - NULL, "vmx-exit-load-pkrs", NULL, "vmx-exit-secondary-ctls", + NULL, "vmx-exit-load-pkrs", "vmx-exit-save-perf-global-ctrl", + "vmx-exit-secondary-ctls", }, .msr = { .index = MSR_IA32_VMX_TRUE_EXIT_CTLS, @@ -4212,7 +4213,8 @@ static const X86CPUDefinition builtin_x86_defs[] = { VMX_VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL | VMX_VM_EXIT_ACK_INTR_ON_EXIT | VMX_VM_EXIT_SAVE_IA32_PAT | VMX_VM_EXIT_LOAD_IA32_PAT | VMX_VM_EXIT_SAVE_IA32_EFER | - VMX_VM_EXIT_LOAD_IA32_EFER | VMX_VM_EXIT_SAVE_VMX_PREEMPTION_TIMER, + VMX_VM_EXIT_LOAD_IA32_EFER | VMX_VM_EXIT_SAVE_VMX_PREEMPTION_TIMER | + VMX_VM_EXIT_SAVE_IA32_PERF_GLOBAL_CTRL, .features[FEAT_VMX_MISC] = MSR_VMX_MISC_STORE_LMA | MSR_VMX_MISC_ACTIVITY_HLT | MSR_VMX_MISC_VMWRITE_VMEXIT, @@ -4368,7 +4370,8 @@ static const X86CPUDefinition builtin_x86_defs[] = { VMX_VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL | VMX_VM_EXIT_ACK_INTR_ON_EXIT | VMX_VM_EXIT_SAVE_IA32_PAT | VMX_VM_EXIT_LOAD_IA32_PAT | VMX_VM_EXIT_SAVE_IA32_EFER | - VMX_VM_EXIT_LOAD_IA32_EFER | VMX_VM_EXIT_SAVE_VMX_PREEMPTION_TIMER, + VMX_VM_EXIT_LOAD_IA32_EFER | VMX_VM_EXIT_SAVE_VMX_PREEMPTION_TIMER | + VMX_VM_EXIT_SAVE_IA32_PERF_GLOBAL_CTRL, .features[FEAT_VMX_MISC] = MSR_VMX_MISC_STORE_LMA | MSR_VMX_MISC_ACTIVITY_HLT | MSR_VMX_MISC_VMWRITE_VMEXIT, @@ -4511,7 +4514,8 @@ static const X86CPUDefinition builtin_x86_defs[] = { VMX_VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL | VMX_VM_EXIT_ACK_INTR_ON_EXIT | VMX_VM_EXIT_SAVE_IA32_PAT | VMX_VM_EXIT_LOAD_IA32_PAT | VMX_VM_EXIT_SAVE_IA32_EFER | - VMX_VM_EXIT_LOAD_IA32_EFER | VMX_VM_EXIT_SAVE_VMX_PREEMPTION_TIMER, + VMX_VM_EXIT_LOAD_IA32_EFER | VMX_VM_EXIT_SAVE_VMX_PREEMPTION_TIMER | + VMX_VM_EXIT_SAVE_IA32_PERF_GLOBAL_CTRL, .features[FEAT_VMX_MISC] = MSR_VMX_MISC_STORE_LMA | MSR_VMX_MISC_ACTIVITY_HLT | MSR_VMX_MISC_VMWRITE_VMEXIT, diff --git a/target/i386/cpu.h b/target/i386/cpu.h index 76f24446a5..ad387e6ee7 100644 --- a/target/i386/cpu.h +++ b/target/i386/cpu.h @@ -1312,6 +1312,7 @@ uint64_t x86_cpu_get_supported_feature_word(X86CPU *cpu, FeatureWord w); #define VMX_VM_EXIT_PT_CONCEAL_PIP 0x01000000 #define VMX_VM_EXIT_CLEAR_IA32_RTIT_CTL 0x02000000 #define VMX_VM_EXIT_LOAD_IA32_PKRS 0x20000000 +#define VMX_VM_EXIT_SAVE_IA32_PERF_GLOBAL_CTRL 0x40000000 #define VMX_VM_EXIT_ACTIVATE_SECONDARY_CONTROLS 0x80000000 #define VMX_VM_ENTRY_LOAD_DEBUG_CONTROLS 0x00000004