From patchwork Mon Mar 24 13:32:33 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Nautiyal, Ankit K" X-Patchwork-Id: 14027359 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 968B5C3600C for ; Mon, 24 Mar 2025 13:44:41 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 2790A10E356; Mon, 24 Mar 2025 13:44:41 +0000 (UTC) Authentication-Results: gabe.freedesktop.org; dkim=pass (2048-bit key; unprotected) header.d=intel.com header.i=@intel.com header.b="YmhqIZ4m"; dkim-atps=neutral Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.21]) by gabe.freedesktop.org (Postfix) with ESMTPS id 3540810E26E; Mon, 24 Mar 2025 13:44:40 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1742823880; x=1774359880; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=wTrBq0rmVsGk9LwWbSeVbEPwVwTPlUS/aQDJWPq0ILA=; b=YmhqIZ4mHOMS8fU799zPwd3cqQMyDOU8IEI6qJ7GnsuIacjVdOPkwdpS qwnN/WQEejxZgCNzx/hYTB7ym70gU6T/VpsvMSkekLeVaCWeveDulXM6A nHRR/tYwTT3WIDrmP0K2OvCoGpliNjMNDtcJPjJ5fI6k6uvzdyN3C+iLo mHLpeJV3MojyriHbGaRebp7hftvX/RMIKfnS62NAtfPAN/BocgRy0SOg2 zNzv+mmBcprSYy3lTgxxTdhyI8fMuRZGykxN8u5MHdwQprN59Ruwue7QM V1FiSb2M0Yo9ov60YqzSV/PQrZb1afn+NBJlgCaY8HfPCp7CfYww/vgtX A==; X-CSE-ConnectionGUID: 1MXBqPERS66H6dG/Hq/RZg== X-CSE-MsgGUID: ckJbrC8ySxuuSBGy3yjQ8A== X-IronPort-AV: E=McAfee;i="6700,10204,11383"; a="43955691" X-IronPort-AV: E=Sophos;i="6.14,272,1736841600"; d="scan'208";a="43955691" Received: from fmviesa007.fm.intel.com ([10.60.135.147]) by orvoesa113.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 24 Mar 2025 06:44:39 -0700 X-CSE-ConnectionGUID: SRdC0U93Q+qPscvjr0m1pw== X-CSE-MsgGUID: FEdTTfLdR6+W7U3ExvmbSA== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.14,272,1736841600"; d="scan'208";a="124040466" Received: from srr4-3-linux-103-aknautiy.iind.intel.com ([10.223.34.160]) by fmviesa007-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 24 Mar 2025 06:44:38 -0700 From: Ankit Nautiyal To: intel-gfx@lists.freedesktop.org Cc: intel-xe@lists.freedesktop.org, jani.nikula@linux.intel.com, ville.syrjala@linux.intel.com, mitulkumar.ajitkumar.golani@intel.com Subject: [PATCH 01/16] drm/i915/hdmi: Use VRR Timing generator for HDMI for fixed_rr Date: Mon, 24 Mar 2025 19:02:33 +0530 Message-ID: <20250324133248.4071909-2-ankit.k.nautiyal@intel.com> X-Mailer: git-send-email 2.45.2 In-Reply-To: <20250324133248.4071909-1-ankit.k.nautiyal@intel.com> References: <20250324133248.4071909-1-ankit.k.nautiyal@intel.com> MIME-Version: 1.0 X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" Currently VRR is not supported with HDMI, but we can still leverage the VRR Timing Generator to achieve a fixed refresh rate. Call intel_vrr_compute_config() for HDMI which will handle the vrr timings to have fixed refresh rate with VRR Timing Generator. v2: Improve commit message. (Ville). Signed-off-by: Ankit Nautiyal Reviewed-by: Mitul Golani (#v1) --- drivers/gpu/drm/i915/display/intel_hdmi.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/drivers/gpu/drm/i915/display/intel_hdmi.c b/drivers/gpu/drm/i915/display/intel_hdmi.c index 33b8d5229db0..f9fa17e1f584 100644 --- a/drivers/gpu/drm/i915/display/intel_hdmi.c +++ b/drivers/gpu/drm/i915/display/intel_hdmi.c @@ -64,6 +64,7 @@ #include "intel_panel.h" #include "intel_pfit.h" #include "intel_snps_phy.h" +#include "intel_vrr.h" static void assert_hdmi_port_disabled(struct intel_hdmi *intel_hdmi) @@ -2384,6 +2385,8 @@ int intel_hdmi_compute_config(struct intel_encoder *encoder, } } + intel_vrr_compute_config(pipe_config, conn_state); + intel_hdmi_compute_gcp_infoframe(encoder, pipe_config, conn_state); From patchwork Mon Mar 24 13:32:34 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: "Nautiyal, Ankit K" X-Patchwork-Id: 14027361 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 11E47C3600B for ; Mon, 24 Mar 2025 13:44:44 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 9C68610E424; Mon, 24 Mar 2025 13:44:43 +0000 (UTC) Authentication-Results: gabe.freedesktop.org; dkim=pass (2048-bit key; unprotected) header.d=intel.com header.i=@intel.com header.b="oBO5KypP"; dkim-atps=neutral Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.21]) by gabe.freedesktop.org (Postfix) with ESMTPS id A0BF310E370; Mon, 24 Mar 2025 13:44:41 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1742823881; x=1774359881; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=hVJIFQdLHIiP6ZhdCug458wLcrbsZhSrjy2QAINTdjU=; b=oBO5KypPPF9p27cmNr6Ux5uY7qKy4mRR+r/99rbjnfLiAr2wbxsXudHZ g90z7vofenBuW4QcpFuWk6STUVg3RR3yXQu9wbOphpByArWjnq1ZMV1FY aoUGyowlVEXikVUGrIlk3PeLQA0UvrfGHZhgNJ2CSLA422JlHRWh3vWQn 40pD8TtfGLx1OhT42lNKLyus+GmJj86fyjbAJhydLJHk90zDdzrw2iRfF Qa7j1vwuK/rsG0FIjfHZmepEhePzaynWII8M0zJA9AkWVe8rqmNAdSpW6 6SSj1TvM2JWLDpyULmyg7QHNLrGNndhdH2lOs5quLOvuf4o8WtgX3GeqC A==; X-CSE-ConnectionGUID: N8ysYAT7R7yOQHfLpwoKlg== X-CSE-MsgGUID: xPh4WoE/SVyA7aMQoTQupg== X-IronPort-AV: E=McAfee;i="6700,10204,11383"; a="43955698" X-IronPort-AV: E=Sophos;i="6.14,272,1736841600"; d="scan'208";a="43955698" Received: from fmviesa007.fm.intel.com ([10.60.135.147]) by orvoesa113.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 24 Mar 2025 06:44:41 -0700 X-CSE-ConnectionGUID: 1fUJkFRyTYaokAVOFPHQDw== X-CSE-MsgGUID: nMrRmptTQcGcSayE0zkV5Q== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.14,272,1736841600"; d="scan'208";a="124040496" Received: from srr4-3-linux-103-aknautiy.iind.intel.com ([10.223.34.160]) by fmviesa007-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 24 Mar 2025 06:44:40 -0700 From: Ankit Nautiyal To: intel-gfx@lists.freedesktop.org Cc: intel-xe@lists.freedesktop.org, jani.nikula@linux.intel.com, ville.syrjala@linux.intel.com, mitulkumar.ajitkumar.golani@intel.com Subject: [PATCH 02/16] drm/i915/dp_mst: Use VRR Timing generator for DP MST for fixed_rr Date: Mon, 24 Mar 2025 19:02:34 +0530 Message-ID: <20250324133248.4071909-3-ankit.k.nautiyal@intel.com> X-Mailer: git-send-email 2.45.2 In-Reply-To: <20250324133248.4071909-1-ankit.k.nautiyal@intel.com> References: <20250324133248.4071909-1-ankit.k.nautiyal@intel.com> MIME-Version: 1.0 X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" Currently the variable timings are supported only for DP and eDP and not for DP MST. Call intel_vrr_compute_config() for MST which will configure fixed refresh rate timings irrespective of whether VRR is supported or not. Since vrr_capable still doesn't have support for DP MST this will be just treated as non VRR case and vrr.vmin/vmax/flipline will be all set to adjusted_mode->crtc_vtotal. This will help to move away from the legacy timing generator and always use VRR timing generator by default. With this change, we need to exclude MST in intel_vrr_is_capable for now, to avoid having LRR with MST. v2: Exclude MST in intel_vrr_is_capable() for now. (Ville) Signed-off-by: Ankit Nautiyal Reviewed-by: Ville Syrjälä --- drivers/gpu/drm/i915/display/intel_dp_mst.c | 3 +++ drivers/gpu/drm/i915/display/intel_vrr.c | 2 ++ 2 files changed, 5 insertions(+) diff --git a/drivers/gpu/drm/i915/display/intel_dp_mst.c b/drivers/gpu/drm/i915/display/intel_dp_mst.c index 02f95108c637..bd47cf127b4c 100644 --- a/drivers/gpu/drm/i915/display/intel_dp_mst.c +++ b/drivers/gpu/drm/i915/display/intel_dp_mst.c @@ -52,6 +52,7 @@ #include "intel_pfit.h" #include "intel_psr.h" #include "intel_vdsc.h" +#include "intel_vrr.h" #include "skl_scaler.h" /* @@ -710,6 +711,8 @@ static int mst_stream_compute_config(struct intel_encoder *encoder, pipe_config->lane_lat_optim_mask = bxt_dpio_phy_calc_lane_lat_optim_mask(pipe_config->lane_count); + intel_vrr_compute_config(pipe_config, conn_state); + intel_dp_audio_compute_config(encoder, pipe_config, conn_state); intel_ddi_compute_min_voltage_level(pipe_config); diff --git a/drivers/gpu/drm/i915/display/intel_vrr.c b/drivers/gpu/drm/i915/display/intel_vrr.c index 6bdcdfed4b9b..c682c487eb25 100644 --- a/drivers/gpu/drm/i915/display/intel_vrr.c +++ b/drivers/gpu/drm/i915/display/intel_vrr.c @@ -32,6 +32,8 @@ bool intel_vrr_is_capable(struct intel_connector *connector) return false; fallthrough; case DRM_MODE_CONNECTOR_DisplayPort: + if (connector->mst.dp) + return false; intel_dp = intel_attached_dp(connector); if (!drm_dp_sink_can_do_video_without_timing_msa(intel_dp->dpcd)) From patchwork Mon Mar 24 13:32:35 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: "Nautiyal, Ankit K" X-Patchwork-Id: 14027362 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 010F6C3600B for ; Mon, 24 Mar 2025 13:44:46 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 85C8D10E42F; Mon, 24 Mar 2025 13:44:46 +0000 (UTC) Authentication-Results: gabe.freedesktop.org; dkim=pass (2048-bit key; unprotected) header.d=intel.com header.i=@intel.com header.b="TcMusYp2"; dkim-atps=neutral Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.21]) by gabe.freedesktop.org (Postfix) with ESMTPS id 9C11510E423; Mon, 24 Mar 2025 13:44:43 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1742823883; x=1774359883; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=9/TWZFKuWG+gt0R6/mloNA/cyFOiardj1cZ6DwP/RNA=; b=TcMusYp21C5QtLjAn1L9d/aMixCRNv+tkC4t8DA7nvcsKguQe6D6yx9H H+BB2WY4htt63mJlwMGV8IUR12tiDRrHFx5UAGQD+uFtkJM//m+yIXuJq E6whhmNaYBUGYJP+Doy2Ps2WTKdXD9QMaPM6JfDZA/L8O6Lb13zSegoBc Cqni9wkH6Wz2QXH1JQwn8M+6jQzcnsbGlDdJpoLPIJPYDygqMHX150Dko 0SljHHU36AwE4d3rTgp155lio5hmFTYu8URD/sjSYfBWt9/oCoqoXiaQo JSjo5jYTpxKF5qRBkGGjxNqXcHuc54QTuXMykAnhaeUXoPPF627j+06vM Q==; X-CSE-ConnectionGUID: ee2iP7XPSo2zwv5HWB8mnQ== X-CSE-MsgGUID: fdKpyMEuRTSiB2gYashufw== X-IronPort-AV: E=McAfee;i="6700,10204,11383"; a="43955703" X-IronPort-AV: E=Sophos;i="6.14,272,1736841600"; d="scan'208";a="43955703" Received: from fmviesa007.fm.intel.com ([10.60.135.147]) by orvoesa113.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 24 Mar 2025 06:44:43 -0700 X-CSE-ConnectionGUID: gQwg9dq2R5e54B3D73mnpw== X-CSE-MsgGUID: NmKqhDQkT+ek9k2Hkd38mQ== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.14,272,1736841600"; d="scan'208";a="124040525" Received: from srr4-3-linux-103-aknautiy.iind.intel.com ([10.223.34.160]) by fmviesa007-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 24 Mar 2025 06:44:41 -0700 From: Ankit Nautiyal To: intel-gfx@lists.freedesktop.org Cc: intel-xe@lists.freedesktop.org, jani.nikula@linux.intel.com, ville.syrjala@linux.intel.com, mitulkumar.ajitkumar.golani@intel.com Subject: [PATCH 03/16] drm/i915/display: Disable PSR before disabling VRR Date: Mon, 24 Mar 2025 19:02:35 +0530 Message-ID: <20250324133248.4071909-4-ankit.k.nautiyal@intel.com> X-Mailer: git-send-email 2.45.2 In-Reply-To: <20250324133248.4071909-1-ankit.k.nautiyal@intel.com> References: <20250324133248.4071909-1-ankit.k.nautiyal@intel.com> MIME-Version: 1.0 X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" As per bspec 49268: Disable PSR before disabling VRR. Signed-off-by: Ankit Nautiyal Reviewed-by: Ville Syrjälä --- drivers/gpu/drm/i915/display/intel_display.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c index b852ffe94a10..53675a92bbf5 100644 --- a/drivers/gpu/drm/i915/display/intel_display.c +++ b/drivers/gpu/drm/i915/display/intel_display.c @@ -1174,6 +1174,8 @@ static void intel_pre_plane_update(struct intel_atomic_state *state, intel_atomic_get_new_crtc_state(state, crtc); enum pipe pipe = crtc->pipe; + intel_psr_pre_plane_update(state, crtc); + if (intel_crtc_vrr_disabling(state, crtc)) { intel_vrr_disable(old_crtc_state); intel_crtc_update_active_timings(old_crtc_state, false); @@ -1184,8 +1186,6 @@ static void intel_pre_plane_update(struct intel_atomic_state *state, intel_drrs_deactivate(old_crtc_state); - intel_psr_pre_plane_update(state, crtc); - if (hsw_ips_pre_update(state, crtc)) intel_crtc_wait_for_next_vblank(crtc); From patchwork Mon Mar 24 13:32:36 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: "Nautiyal, Ankit K" X-Patchwork-Id: 14027363 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id EBD0AC36002 for ; Mon, 24 Mar 2025 13:44:46 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 7FC3D10E42D; Mon, 24 Mar 2025 13:44:46 +0000 (UTC) Authentication-Results: gabe.freedesktop.org; dkim=pass (2048-bit key; unprotected) header.d=intel.com header.i=@intel.com header.b="Dv/bySHz"; dkim-atps=neutral Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.21]) by gabe.freedesktop.org (Postfix) with ESMTPS id 8374C10E42D; Mon, 24 Mar 2025 13:44:45 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1742823885; x=1774359885; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=ttCaFfGJTG2Zy1yk4o2+VJGV+zdof9UtvNaTboXsMTs=; b=Dv/bySHz0fffbPVv0jbVzC8gnGHYGjTpY2MJ4xIcSgh2hIcq7f2p8qC6 EARlrHFJ4ZN1rZROkYl/tijAUUnEDhBEgdeIw6NjVfGk0Z9PFiD+zuJMP PF87PUHmEpR6GPSI/rpMpBqvUdWOcqgCXV5wGqOudjirL+qKurbCwQWNN QuTGsUgRwQsKqhbSypiibKirpT1US6Coi0k+5yMBH25KhEz1NAsoaH9lP JlimTtjZpU7SM/J5MOA6D2FU4khu4vDy7dfObmYRl9RkS0IThtRYo4o6g 0jlUNe7MEjRjEXgquFMJwCD8WZ/vrH7jX3GEo4ZXeMawADttnGcqXeA+b A==; X-CSE-ConnectionGUID: n7JznBIbQEKWkFA+95xBqw== X-CSE-MsgGUID: sVYE0IwCRyWvyCrvdgBL3w== X-IronPort-AV: E=McAfee;i="6700,10204,11383"; a="43955707" X-IronPort-AV: E=Sophos;i="6.14,272,1736841600"; d="scan'208";a="43955707" Received: from fmviesa007.fm.intel.com ([10.60.135.147]) by orvoesa113.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 24 Mar 2025 06:44:45 -0700 X-CSE-ConnectionGUID: 4/Ia61YRQsuiSZBhLBBasg== X-CSE-MsgGUID: dBVVUnGpQ9+CQbN96pW68Q== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.14,272,1736841600"; d="scan'208";a="124040544" Received: from srr4-3-linux-103-aknautiy.iind.intel.com ([10.223.34.160]) by fmviesa007-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 24 Mar 2025 06:44:43 -0700 From: Ankit Nautiyal To: intel-gfx@lists.freedesktop.org Cc: intel-xe@lists.freedesktop.org, jani.nikula@linux.intel.com, ville.syrjala@linux.intel.com, mitulkumar.ajitkumar.golani@intel.com Subject: [PATCH 04/16] drm/i915/display: Move intel_psr_post_plane_update() at the later Date: Mon, 24 Mar 2025 19:02:36 +0530 Message-ID: <20250324133248.4071909-5-ankit.k.nautiyal@intel.com> X-Mailer: git-send-email 2.45.2 In-Reply-To: <20250324133248.4071909-1-ankit.k.nautiyal@intel.com> References: <20250324133248.4071909-1-ankit.k.nautiyal@intel.com> MIME-Version: 1.0 X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" In intel_post_plane_update() there are things which might need to do vblank waits, so enabling PSR as early as we do now is simply counter-productive. Therefore move intel_psr_post_plane_update() at the last of intel_post_plane_update(). Signed-off-by: Ankit Nautiyal Suggested-by: Ville Syrjälä --- drivers/gpu/drm/i915/display/intel_display.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c index 53675a92bbf5..b68b86923dca 100644 --- a/drivers/gpu/drm/i915/display/intel_display.c +++ b/drivers/gpu/drm/i915/display/intel_display.c @@ -1049,8 +1049,6 @@ static void intel_post_plane_update(struct intel_atomic_state *state, intel_atomic_get_new_crtc_state(state, crtc); enum pipe pipe = crtc->pipe; - intel_psr_post_plane_update(state, crtc); - intel_frontbuffer_flip(dev_priv, new_crtc_state->fb_bits); if (new_crtc_state->update_wm_post && new_crtc_state->hw.active) @@ -1079,6 +1077,8 @@ static void intel_post_plane_update(struct intel_atomic_state *state, if (audio_enabling(old_crtc_state, new_crtc_state)) intel_encoders_audio_enable(state, crtc); + + intel_psr_post_plane_update(state, crtc); } static void intel_post_plane_update_after_readout(struct intel_atomic_state *state, From patchwork Mon Mar 24 13:32:37 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: "Nautiyal, Ankit K" X-Patchwork-Id: 14027364 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id A93C7C3600C for ; Mon, 24 Mar 2025 13:44:50 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 417E010E431; Mon, 24 Mar 2025 13:44:50 +0000 (UTC) Authentication-Results: gabe.freedesktop.org; dkim=pass (2048-bit key; unprotected) header.d=intel.com header.i=@intel.com header.b="EtML/ux6"; dkim-atps=neutral Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.21]) by gabe.freedesktop.org (Postfix) with ESMTPS id 9114710E427; Mon, 24 Mar 2025 13:44:47 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1742823887; x=1774359887; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=xwKr3JPf2XJN07/QRIxfIL4iTXbxAB5p90+O6zkCV1c=; b=EtML/ux6LzOMoCMXbnoUOO6Vs08jlyRijz34THnralPhGOtsBs9WrzZE ggac60eknt2aRQDId4OZwORaGGKdum2kJaDqoCbenp29CE5YDMqRMy/4F nGowCpJD/2Iv/IQlV9RjjrHkZC+MXemP2BceTDzb7wMOiR+DzLEVLyatG xd+CR9zF4Pj32r929/h1HxJ8dIrvpecFTvgkpYM7BqZktWUoh4XG4xdLh YDnhHzN12oHCRY+E1fbU8OqFGiU95L92/Zu+jVVgq0p574wURh/w/t6mP G/TVPqmDMeXOMAPjN1BrhjkVp8d/G6Jb+dd/3Rbn/WHxRSYKp0m0/Ijjy A==; X-CSE-ConnectionGUID: 5mumeb5ESZCdWkgT9aatnA== X-CSE-MsgGUID: 5T2RZs0FQlWoayk24ff4Gg== X-IronPort-AV: E=McAfee;i="6700,10204,11383"; a="43955715" X-IronPort-AV: E=Sophos;i="6.14,272,1736841600"; d="scan'208";a="43955715" Received: from fmviesa007.fm.intel.com ([10.60.135.147]) by orvoesa113.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 24 Mar 2025 06:44:47 -0700 X-CSE-ConnectionGUID: wgzk0m4LR32GyZ0LhBcSCg== X-CSE-MsgGUID: YHxUMOjETTWQuzxviuwaBg== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.14,272,1736841600"; d="scan'208";a="124040564" Received: from srr4-3-linux-103-aknautiy.iind.intel.com ([10.223.34.160]) by fmviesa007-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 24 Mar 2025 06:44:45 -0700 From: Ankit Nautiyal To: intel-gfx@lists.freedesktop.org Cc: intel-xe@lists.freedesktop.org, jani.nikula@linux.intel.com, ville.syrjala@linux.intel.com, mitulkumar.ajitkumar.golani@intel.com Subject: [PATCH 05/16] drm/i915/vrr: Refactor condition for computing vmax and LRR Date: Mon, 24 Mar 2025 19:02:37 +0530 Message-ID: <20250324133248.4071909-6-ankit.k.nautiyal@intel.com> X-Mailer: git-send-email 2.45.2 In-Reply-To: <20250324133248.4071909-1-ankit.k.nautiyal@intel.com> References: <20250324133248.4071909-1-ankit.k.nautiyal@intel.com> MIME-Version: 1.0 X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" LRR and Vmax can be computed only if VRR is supported and vrr.in_range is set. Currently we proceed with vrr timings only for VRR supporting panels and return otherwise. For using VRR TG with fix timings, need to continue even for panels that do not support VRR. To achieve this, refactor the condition for computing vmax and update_lrr so that we can continue for fixed timings for panels that do not support VRR. v2: Set vmax = vmin for non VRR panels. (Ville) Signed-off-by: Ankit Nautiyal Reviewed-by: Ville Syrjälä --- drivers/gpu/drm/i915/display/intel_vrr.c | 14 ++++++++------ 1 file changed, 8 insertions(+), 6 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_vrr.c b/drivers/gpu/drm/i915/display/intel_vrr.c index c682c487eb25..e68c13ae21b3 100644 --- a/drivers/gpu/drm/i915/display/intel_vrr.c +++ b/drivers/gpu/drm/i915/display/intel_vrr.c @@ -365,14 +365,16 @@ intel_vrr_compute_config(struct intel_crtc_state *crtc_state, crtc_state->vrr.in_range = intel_vrr_is_in_range(connector, drm_mode_vrefresh(adjusted_mode)); - if (!crtc_state->vrr.in_range) - return; - - if (HAS_LRR(display)) - crtc_state->update_lrr = true; vmin = intel_vrr_compute_vmin(crtc_state); - vmax = intel_vrr_compute_vmax(connector, adjusted_mode); + + if (crtc_state->vrr.in_range) { + if (HAS_LRR(display)) + crtc_state->update_lrr = true; + vmax = intel_vrr_compute_vmax(connector, adjusted_mode); + } else { + vmax = vmin; + } if (vmin >= vmax) return; From patchwork Mon Mar 24 13:32:38 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: "Nautiyal, Ankit K" X-Patchwork-Id: 14027365 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 04A21C3600B for ; Mon, 24 Mar 2025 13:44:51 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 86D7310E433; Mon, 24 Mar 2025 13:44:50 +0000 (UTC) Authentication-Results: gabe.freedesktop.org; dkim=pass (2048-bit key; unprotected) header.d=intel.com header.i=@intel.com header.b="idCBq8pG"; dkim-atps=neutral Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.21]) by gabe.freedesktop.org (Postfix) with ESMTPS id 86B3E10E433; Mon, 24 Mar 2025 13:44:49 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1742823889; x=1774359889; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=l9lhqX9X5DPP3EmmQXz4r/1BesaJTao62iK2w1hzAP8=; b=idCBq8pGrZ7XCbHCIquscjV2+FVHU8ykkKcowV/d6WvVh+bDtzXvslpZ oO42thX9nwpqI3rJa7QickPVa+70z9aTl9QDVSNKAYU/qghh+3F8oJEMT F0xvdnUjdbRx0r1EcsWuqzKfSpngeDkghNGODKqhmKvU/XbKxJGBgvOl9 F1GvUfd3zu0EQjj5Ki246Fx7i7TlJ76xrJA1Lpo93hyjPkRCr7oKCT5/j 1QeMPz2IjKIHzrfHmaungqloxhwa6z5A24UODpo8TgJnso+aeFc1Jket5 tw2IbkqbKWnpof5GWVbRltFvPEjhNuX6SiGqPm+ZAFPTd4Rg+ui0y1lnx g==; X-CSE-ConnectionGUID: IMAYEsOTT3advY44mppwhw== X-CSE-MsgGUID: bduDRHkwSImtooqUvMBWTA== X-IronPort-AV: E=McAfee;i="6700,10204,11383"; a="43955720" X-IronPort-AV: E=Sophos;i="6.14,272,1736841600"; d="scan'208";a="43955720" Received: from fmviesa007.fm.intel.com ([10.60.135.147]) by orvoesa113.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 24 Mar 2025 06:44:49 -0700 X-CSE-ConnectionGUID: bxeSTF1gQ9umuhnJxqG+Sw== X-CSE-MsgGUID: PQVLlIRaRZ6mWs3osQwutg== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.14,272,1736841600"; d="scan'208";a="124040583" Received: from srr4-3-linux-103-aknautiy.iind.intel.com ([10.223.34.160]) by fmviesa007-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 24 Mar 2025 06:44:47 -0700 From: Ankit Nautiyal To: intel-gfx@lists.freedesktop.org Cc: intel-xe@lists.freedesktop.org, jani.nikula@linux.intel.com, ville.syrjala@linux.intel.com, mitulkumar.ajitkumar.golani@intel.com Subject: [PATCH 06/16] drm/i915/vrr: Always set vrr vmax/vmin/flipline in vrr_{enable/disable} Date: Mon, 24 Mar 2025 19:02:38 +0530 Message-ID: <20250324133248.4071909-7-ankit.k.nautiyal@intel.com> X-Mailer: git-send-email 2.45.2 In-Reply-To: <20250324133248.4071909-1-ankit.k.nautiyal@intel.com> References: <20250324133248.4071909-1-ankit.k.nautiyal@intel.com> MIME-Version: 1.0 X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" For platforms for which vrr timing generator is always set, VRR_CTL enable bit does not need to toggle, so modify the vrr_{enable/disable} for this. At the moment the helper intel_vrr_always_use_vrr_tg() return false for all cases. This will be set later when all other bits are in place. Signed-off-by: Ankit Nautiyal Reviewed-by: Ville Syrjälä --- drivers/gpu/drm/i915/display/intel_vrr.c | 40 ++++++++++++++++-------- 1 file changed, 27 insertions(+), 13 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_vrr.c b/drivers/gpu/drm/i915/display/intel_vrr.c index e68c13ae21b3..8ae279f132fd 100644 --- a/drivers/gpu/drm/i915/display/intel_vrr.c +++ b/drivers/gpu/drm/i915/display/intel_vrr.c @@ -560,6 +560,16 @@ bool intel_vrr_is_push_sent(const struct intel_crtc_state *crtc_state) return intel_de_read(display, TRANS_PUSH(display, cpu_transcoder)) & TRANS_PUSH_SEND; } +static +bool intel_vrr_always_use_vrr_tg(struct intel_display *display) +{ + if (!HAS_VRR(display)) + return false; + + /* #TODO return true for platforms supporting fixed_rr */ + return false; +} + void intel_vrr_enable(const struct intel_crtc_state *crtc_state) { struct intel_display *display = to_intel_display(crtc_state); @@ -578,13 +588,15 @@ void intel_vrr_enable(const struct intel_crtc_state *crtc_state) intel_de_write(display, TRANS_PUSH(display, cpu_transcoder), TRANS_PUSH_EN); - if (crtc_state->cmrr.enable) { - intel_de_write(display, TRANS_VRR_CTL(display, cpu_transcoder), - VRR_CTL_VRR_ENABLE | VRR_CTL_CMRR_ENABLE | - trans_vrr_ctl(crtc_state)); - } else { - intel_de_write(display, TRANS_VRR_CTL(display, cpu_transcoder), - VRR_CTL_VRR_ENABLE | trans_vrr_ctl(crtc_state)); + if (!intel_vrr_always_use_vrr_tg(display)) { + if (crtc_state->cmrr.enable) { + intel_de_write(display, TRANS_VRR_CTL(display, cpu_transcoder), + VRR_CTL_VRR_ENABLE | VRR_CTL_CMRR_ENABLE | + trans_vrr_ctl(crtc_state)); + } else { + intel_de_write(display, TRANS_VRR_CTL(display, cpu_transcoder), + VRR_CTL_VRR_ENABLE | trans_vrr_ctl(crtc_state)); + } } } @@ -596,12 +608,14 @@ void intel_vrr_disable(const struct intel_crtc_state *old_crtc_state) if (!old_crtc_state->vrr.enable) return; - intel_de_write(display, TRANS_VRR_CTL(display, cpu_transcoder), - trans_vrr_ctl(old_crtc_state)); - intel_de_wait_for_clear(display, - TRANS_VRR_STATUS(display, cpu_transcoder), - VRR_STATUS_VRR_EN_LIVE, 1000); - intel_de_write(display, TRANS_PUSH(display, cpu_transcoder), 0); + if (!intel_vrr_always_use_vrr_tg(display)) { + intel_de_write(display, TRANS_VRR_CTL(display, cpu_transcoder), + trans_vrr_ctl(old_crtc_state)); + intel_de_wait_for_clear(display, + TRANS_VRR_STATUS(display, cpu_transcoder), + VRR_STATUS_VRR_EN_LIVE, 1000); + intel_de_write(display, TRANS_PUSH(display, cpu_transcoder), 0); + } intel_vrr_set_fixed_rr_timings(old_crtc_state); } From patchwork Mon Mar 24 13:32:39 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: "Nautiyal, Ankit K" X-Patchwork-Id: 14027366 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 02499C36002 for ; Mon, 24 Mar 2025 13:44:52 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 90A0D10E438; Mon, 24 Mar 2025 13:44:52 +0000 (UTC) Authentication-Results: gabe.freedesktop.org; dkim=pass (2048-bit key; unprotected) header.d=intel.com header.i=@intel.com header.b="Z6aDCCuH"; dkim-atps=neutral Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.21]) by gabe.freedesktop.org (Postfix) with ESMTPS id 6F72B10E430; Mon, 24 Mar 2025 13:44:51 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1742823891; x=1774359891; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=xWF6RLEn+R7zaO300QbHsa8dCEQPJu6OoQbAu+O7JvQ=; b=Z6aDCCuHJEA1KDT4SXtVuSc0FWltjwgvQe8nYR6Rgqv0dQqY8H19Tp3F 8yXwoFTNL2Y53j5EvEgDTFIzNYoFu2RGC+/LINeXxeO20ViS/FMFCLWFh f5Vl9bZX3hNiWwgFFzw0euxTCnABKTMLDEErl8R1O9luRRrgeDbzmE8S8 bVBUcX0HNlZ45HqbGqXUg15xQVu2lBNuWWZ3ZoyUfsRH3+GzhUk6dEACY lQHNBYg9nfAuhhzq7l+HhCyat/nVLhxPl1ASwp5RZ53EkMXM5vQV2kmV4 HjkYusV3t2+Z5fbAeE+i931A11OKZEjGOCp2s2/fSWGv30BZoSN1AW2L4 Q==; X-CSE-ConnectionGUID: tHrOAS8uQ1+EvBWZ1bMX2A== X-CSE-MsgGUID: bp3DQ0O/SzOTK0bOe2cIlw== X-IronPort-AV: E=McAfee;i="6700,10204,11383"; a="43955723" X-IronPort-AV: E=Sophos;i="6.14,272,1736841600"; d="scan'208";a="43955723" Received: from fmviesa007.fm.intel.com ([10.60.135.147]) by orvoesa113.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 24 Mar 2025 06:44:51 -0700 X-CSE-ConnectionGUID: sTXQotggTbaOPAXodbCL7g== X-CSE-MsgGUID: Td5BWUowQP26KaGScmQ6Cg== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.14,272,1736841600"; d="scan'208";a="124040598" Received: from srr4-3-linux-103-aknautiy.iind.intel.com ([10.223.34.160]) by fmviesa007-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 24 Mar 2025 06:44:49 -0700 From: Ankit Nautiyal To: intel-gfx@lists.freedesktop.org Cc: intel-xe@lists.freedesktop.org, jani.nikula@linux.intel.com, ville.syrjala@linux.intel.com, mitulkumar.ajitkumar.golani@intel.com Subject: [PATCH 07/16] drm/i915/vrr: Set vrr.enable for VRR TG with fixed_rr Date: Mon, 24 Mar 2025 19:02:39 +0530 Message-ID: <20250324133248.4071909-8-ankit.k.nautiyal@intel.com> X-Mailer: git-send-email 2.45.2 In-Reply-To: <20250324133248.4071909-1-ankit.k.nautiyal@intel.com> References: <20250324133248.4071909-1-ankit.k.nautiyal@intel.com> MIME-Version: 1.0 X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" For platforms that enable VRR TG only for variable timings, the VRR_CTL.VRR_ENABLE bit indicates VRR is active. For platforms that always have VRR TG enabled, the VRR_CTL.VRR_ENABLE bit indicates VRR is active only when not in fixed refresh rate mode. Signed-off-by: Ankit Nautiyal Reviewed-by: Ville Syrjälä --- drivers/gpu/drm/i915/display/intel_vrr.c | 8 +++++++- 1 file changed, 7 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/i915/display/intel_vrr.c b/drivers/gpu/drm/i915/display/intel_vrr.c index 8ae279f132fd..8a0d27666ea7 100644 --- a/drivers/gpu/drm/i915/display/intel_vrr.c +++ b/drivers/gpu/drm/i915/display/intel_vrr.c @@ -632,6 +632,7 @@ void intel_vrr_get_config(struct intel_crtc_state *crtc_state) struct intel_display *display = to_intel_display(crtc_state); enum transcoder cpu_transcoder = crtc_state->cpu_transcoder; u32 trans_vrr_ctl, trans_vrr_vsync; + bool vrr_enable; trans_vrr_ctl = intel_de_read(display, TRANS_VRR_CTL(display, cpu_transcoder)); @@ -675,7 +676,12 @@ void intel_vrr_get_config(struct intel_crtc_state *crtc_state) } } - crtc_state->vrr.enable = trans_vrr_ctl & VRR_CTL_VRR_ENABLE; + vrr_enable = trans_vrr_ctl & VRR_CTL_VRR_ENABLE; + + if (intel_vrr_always_use_vrr_tg(display)) + crtc_state->vrr.enable = vrr_enable && !intel_vrr_is_fixed_rr(crtc_state); + else + crtc_state->vrr.enable = vrr_enable; /* * #TODO: For Both VRR and CMRR the flag I915_MODE_FLAG_VRR is set for mode_flags. From patchwork Mon Mar 24 13:32:40 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: "Nautiyal, Ankit K" X-Patchwork-Id: 14027367 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 84685C3600C for ; Mon, 24 Mar 2025 13:44:54 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 263DF10E437; Mon, 24 Mar 2025 13:44:54 +0000 (UTC) Authentication-Results: gabe.freedesktop.org; dkim=pass (2048-bit key; unprotected) header.d=intel.com header.i=@intel.com header.b="YP5Cru2R"; dkim-atps=neutral Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.21]) by gabe.freedesktop.org (Postfix) with ESMTPS id 62B5D10E437; Mon, 24 Mar 2025 13:44:53 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1742823893; x=1774359893; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=kjIINNc6RFmH2HIVyVxoXsIVz/eQjrQ04KOrkVtoojg=; b=YP5Cru2RzRLaBxMsdy9VlemDIA53Wgif/MyrbBoJmfbDGofuRggN3lIW KFck6xH0YdqyOpiPvWqhtQ0ZS5XE2xxEXmBiu2/WpoCq3MN3XKF3xBIUE ex3n93H7V5rlxNgX6xpAwOYx4zaJpoag+GWl9h2kX/maOD9r0vdS6JSL1 yof2aQZ8ncK0nIuNK/9jZ7ndowz1sA74PjMVKTFw39R05k1paFM0+DOoF 00rhEuiyU55U43n+6v55l++CwgxSE9PoSAWCqLrkVPkFg/7faZZj56co6 KZ5NAvRF+HBGam8bIF/6DKEyyygWE6ns8qNpxy/21o2eepZziW3vK6fhz A==; X-CSE-ConnectionGUID: 8d2EE6OcQRiTOPp+udW6dA== X-CSE-MsgGUID: ZmNAo/F9Sf6aYbVRUl1kyA== X-IronPort-AV: E=McAfee;i="6700,10204,11383"; a="43955724" X-IronPort-AV: E=Sophos;i="6.14,272,1736841600"; d="scan'208";a="43955724" Received: from fmviesa007.fm.intel.com ([10.60.135.147]) by orvoesa113.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 24 Mar 2025 06:44:53 -0700 X-CSE-ConnectionGUID: MVtyWDvJTy+vMXUC4fcygA== X-CSE-MsgGUID: remGklKSS0S8uecokBixtw== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.14,272,1736841600"; d="scan'208";a="124040626" Received: from srr4-3-linux-103-aknautiy.iind.intel.com ([10.223.34.160]) by fmviesa007-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 24 Mar 2025 06:44:51 -0700 From: Ankit Nautiyal To: intel-gfx@lists.freedesktop.org Cc: intel-xe@lists.freedesktop.org, jani.nikula@linux.intel.com, ville.syrjala@linux.intel.com, mitulkumar.ajitkumar.golani@intel.com Subject: [PATCH 08/16] drm/i915/display: Use fixed_rr timings in modeset sequence Date: Mon, 24 Mar 2025 19:02:40 +0530 Message-ID: <20250324133248.4071909-9-ankit.k.nautiyal@intel.com> X-Mailer: git-send-email 2.45.2 In-Reply-To: <20250324133248.4071909-1-ankit.k.nautiyal@intel.com> References: <20250324133248.4071909-1-ankit.k.nautiyal@intel.com> MIME-Version: 1.0 X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" During modeset enable sequence, program the fixed timings, and turn on the VRR Timing Generator (VRR TG) for platforms that always use VRR TG. For this intel_vrr_set_transcoder now always programs fixed timings. Later if vrr timings are required, vrr_enable() will switch to the real VRR timings. For platforms that will always use VRR TG, the VRR_CTL Enable bit is set and reset in the transcoder enable/disable path. v2: Update intel_vrr_set_transcoder_timings for fixed_rr. v3: Update intel_set_transcoder_timings_lrr for fixed_rr. (Ville) v4: Have separate functions to enable/disable VRR CTL v5: -For platforms that do not always have VRRTG on, do write bits other than enable bit and also use write the TRANS_VRR_PUSH register. (Ville) -Avoid writing trans_ctl_vrr if !vrr_possible(). v6: -Disable VRR just before intel_ddi_disable_transcoder_func(). (Ville) -Correct the sequence of configuring PUSH and VRR Enable/Disable. (Ville) v7: Reset trans_vrr_ctl to 0 unconditionally in intel_vrr_transcoder_disable(). (Ville) v8: Reset trans_vrr_ctl if flipline is not set. (Ville) Signed-off-by: Ankit Nautiyal Reviewed-by: Ville Syrjälä --- drivers/gpu/drm/i915/display/intel_ddi.c | 5 ++ drivers/gpu/drm/i915/display/intel_dp_mst.c | 4 ++ drivers/gpu/drm/i915/display/intel_vrr.c | 51 +++++++++++++++++---- drivers/gpu/drm/i915/display/intel_vrr.h | 2 + 4 files changed, 54 insertions(+), 8 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c b/drivers/gpu/drm/i915/display/intel_ddi.c index f38c998935b9..44f4465c27e2 100644 --- a/drivers/gpu/drm/i915/display/intel_ddi.c +++ b/drivers/gpu/drm/i915/display/intel_ddi.c @@ -78,6 +78,7 @@ #include "intel_tc.h" #include "intel_vdsc.h" #include "intel_vdsc_regs.h" +#include "intel_vrr.h" #include "skl_scaler.h" #include "skl_universal_plane.h" @@ -3249,6 +3250,8 @@ static void intel_ddi_post_disable_hdmi_or_sst(struct intel_atomic_state *state, drm_dp_dpcd_poll_act_handled(&intel_dp->aux, 0); } + intel_vrr_transcoder_disable(old_crtc_state); + intel_ddi_disable_transcoder_func(old_crtc_state); for_each_pipe_crtc_modeset_disable(display, pipe_crtc, old_crtc_state, i) { @@ -3522,6 +3525,8 @@ static void intel_ddi_enable(struct intel_atomic_state *state, intel_ddi_enable_transcoder_func(encoder, crtc_state); + intel_vrr_transcoder_enable(crtc_state); + /* Enable/Disable DP2.0 SDP split config before transcoder */ intel_audio_sdp_split_update(crtc_state); diff --git a/drivers/gpu/drm/i915/display/intel_dp_mst.c b/drivers/gpu/drm/i915/display/intel_dp_mst.c index bd47cf127b4c..d2988b9a6e7b 100644 --- a/drivers/gpu/drm/i915/display/intel_dp_mst.c +++ b/drivers/gpu/drm/i915/display/intel_dp_mst.c @@ -1065,6 +1065,8 @@ static void mst_stream_post_disable(struct intel_atomic_state *state, drm_dp_remove_payload_part2(&intel_dp->mst.mgr, new_mst_state, old_payload, new_payload); + intel_vrr_transcoder_disable(old_crtc_state); + intel_ddi_disable_transcoder_func(old_crtc_state); for_each_pipe_crtc_modeset_disable(display, pipe_crtc, old_crtc_state, i) { @@ -1326,6 +1328,8 @@ static void mst_stream_enable(struct intel_atomic_state *state, intel_ddi_enable_transcoder_func(encoder, pipe_config); + intel_vrr_transcoder_enable(pipe_config); + intel_ddi_clear_act_sent(encoder, pipe_config); intel_de_rmw(display, TRANS_DDI_FUNC_CTL(display, trans), 0, diff --git a/drivers/gpu/drm/i915/display/intel_vrr.c b/drivers/gpu/drm/i915/display/intel_vrr.c index 8a0d27666ea7..96b6b730bea4 100644 --- a/drivers/gpu/drm/i915/display/intel_vrr.c +++ b/drivers/gpu/drm/i915/display/intel_vrr.c @@ -479,14 +479,7 @@ void intel_vrr_set_transcoder_timings(const struct intel_crtc_state *crtc_state) lower_32_bits(crtc_state->cmrr.cmrr_n)); } - intel_de_write(display, TRANS_VRR_VMIN(display, cpu_transcoder), - crtc_state->vrr.vmin - 1); - intel_de_write(display, TRANS_VRR_VMAX(display, cpu_transcoder), - crtc_state->vrr.vmax - 1); - intel_de_write(display, TRANS_VRR_CTL(display, cpu_transcoder), - trans_vrr_ctl(crtc_state)); - intel_de_write(display, TRANS_VRR_FLIPLINE(display, cpu_transcoder), - crtc_state->vrr.flipline - 1); + intel_vrr_set_fixed_rr_timings(crtc_state); if (HAS_AS_SDP(display)) intel_de_write(display, @@ -620,6 +613,48 @@ void intel_vrr_disable(const struct intel_crtc_state *old_crtc_state) intel_vrr_set_fixed_rr_timings(old_crtc_state); } +void intel_vrr_transcoder_enable(const struct intel_crtc_state *crtc_state) +{ + struct intel_display *display = to_intel_display(crtc_state); + enum transcoder cpu_transcoder = crtc_state->cpu_transcoder; + + if (!HAS_VRR(display)) + return; + + if (!intel_vrr_possible(crtc_state)) + return; + + if (!intel_vrr_always_use_vrr_tg(display)) { + intel_de_write(display, TRANS_VRR_CTL(display, cpu_transcoder), + trans_vrr_ctl(crtc_state)); + return; + } + + intel_de_write(display, TRANS_PUSH(display, cpu_transcoder), + TRANS_PUSH_EN); + + intel_de_write(display, TRANS_VRR_CTL(display, cpu_transcoder), + VRR_CTL_VRR_ENABLE | trans_vrr_ctl(crtc_state)); +} + +void intel_vrr_transcoder_disable(const struct intel_crtc_state *crtc_state) +{ + struct intel_display *display = to_intel_display(crtc_state); + enum transcoder cpu_transcoder = crtc_state->cpu_transcoder; + + if (!HAS_VRR(display)) + return; + + if (!intel_vrr_possible(crtc_state)) + return; + + intel_de_write(display, TRANS_VRR_CTL(display, cpu_transcoder), 0); + + intel_de_wait_for_clear(display, TRANS_VRR_STATUS(display, cpu_transcoder), + VRR_STATUS_VRR_EN_LIVE, 1000); + intel_de_write(display, TRANS_PUSH(display, cpu_transcoder), 0); +} + bool intel_vrr_is_fixed_rr(const struct intel_crtc_state *crtc_state) { return crtc_state->vrr.flipline && diff --git a/drivers/gpu/drm/i915/display/intel_vrr.h b/drivers/gpu/drm/i915/display/intel_vrr.h index 65d2b0eead51..859f1dc8a6d7 100644 --- a/drivers/gpu/drm/i915/display/intel_vrr.h +++ b/drivers/gpu/drm/i915/display/intel_vrr.h @@ -36,5 +36,7 @@ int intel_vrr_vmax_vblank_start(const struct intel_crtc_state *crtc_state); int intel_vrr_vmin_vblank_start(const struct intel_crtc_state *crtc_state); int intel_vrr_vblank_delay(const struct intel_crtc_state *crtc_state); bool intel_vrr_is_fixed_rr(const struct intel_crtc_state *crtc_state); +void intel_vrr_transcoder_enable(const struct intel_crtc_state *crtc_state); +void intel_vrr_transcoder_disable(const struct intel_crtc_state *crtc_state); #endif /* __INTEL_VRR_H__ */ From patchwork Mon Mar 24 13:32:41 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: "Nautiyal, Ankit K" X-Patchwork-Id: 14027368 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 0585DC36010 for ; Mon, 24 Mar 2025 13:44:59 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 9875810E43A; Mon, 24 Mar 2025 13:44:58 +0000 (UTC) Authentication-Results: gabe.freedesktop.org; dkim=pass (2048-bit key; unprotected) header.d=intel.com header.i=@intel.com header.b="WKk//hTZ"; dkim-atps=neutral Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.21]) by gabe.freedesktop.org (Postfix) with ESMTPS id 41ECF10E43A; Mon, 24 Mar 2025 13:44:55 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1742823895; x=1774359895; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=owCoZKr/IzZGH2U2LhkX4VSXET85s8rmkSA4rymgUls=; b=WKk//hTZDvC03eB20vPcaZwkoXfRd7WTDkIWpiPbrMIQcItqsILRZM5D zqGZkOLaDi2tH6U1wgIypnyNQjt2H7GIrs50osMzk0/ugas5IlMtecyYR n5RnZ+51PyxUR5fDeYNxeKUs++TlI3BCXpYbOIXIA+YRFHM5cXWwEcbCE Dp9eO5k4tr3vU2hKKkTusOqDtxcAgyalm7maAePKN2hnQ47mZdi1A4hj1 dqwpvk0EjtGLJoZPGa3fTJmHQRnNouCOVdYtPWsrt9SGx7ly/hVuRCmy2 ZjXp30m5J1V1mWKVJuSiCDvoAi9Jfh+DiJjhknZ6XpbryrKZmqxUTrwVW w==; X-CSE-ConnectionGUID: NcjQG2i8R9CkFX2NmbH/Zw== X-CSE-MsgGUID: ncKyODwXSVCmGwLyEVMTqw== X-IronPort-AV: E=McAfee;i="6700,10204,11383"; a="43955727" X-IronPort-AV: E=Sophos;i="6.14,272,1736841600"; d="scan'208";a="43955727" Received: from fmviesa007.fm.intel.com ([10.60.135.147]) by orvoesa113.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 24 Mar 2025 06:44:55 -0700 X-CSE-ConnectionGUID: Zk/ajZmqTv29fe48Qe3tgg== X-CSE-MsgGUID: PSnbo9zYQxqAZeiSS//Edw== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.14,272,1736841600"; d="scan'208";a="124040646" Received: from srr4-3-linux-103-aknautiy.iind.intel.com ([10.223.34.160]) by fmviesa007-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 24 Mar 2025 06:44:53 -0700 From: Ankit Nautiyal To: intel-gfx@lists.freedesktop.org Cc: intel-xe@lists.freedesktop.org, jani.nikula@linux.intel.com, ville.syrjala@linux.intel.com, mitulkumar.ajitkumar.golani@intel.com Subject: [PATCH 09/16] drm/i915/vrr: Use fixed timings for platforms that support VRR Date: Mon, 24 Mar 2025 19:02:41 +0530 Message-ID: <20250324133248.4071909-10-ankit.k.nautiyal@intel.com> X-Mailer: git-send-email 2.45.2 In-Reply-To: <20250324133248.4071909-1-ankit.k.nautiyal@intel.com> References: <20250324133248.4071909-1-ankit.k.nautiyal@intel.com> MIME-Version: 1.0 X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" For fixed refresh rate use fixed timings for all platforms that support VRR. For this add checks to avoid computing and reading VRR for platforms that do not support VRR. v2: Avoid touching check for VRR_CTL_FLIP_LINE_EN. (Ville) v3: Avoid redundant statements in vrr_{compute/get}_config. (Ville) Signed-off-by: Ankit Nautiyal Reviewed-by: Ville Syrjälä --- drivers/gpu/drm/i915/display/intel_vrr.c | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_vrr.c b/drivers/gpu/drm/i915/display/intel_vrr.c index 96b6b730bea4..f225fd7f34ff 100644 --- a/drivers/gpu/drm/i915/display/intel_vrr.c +++ b/drivers/gpu/drm/i915/display/intel_vrr.c @@ -353,6 +353,9 @@ intel_vrr_compute_config(struct intel_crtc_state *crtc_state, struct drm_display_mode *adjusted_mode = &crtc_state->hw.adjusted_mode; int vmin, vmax; + if (!HAS_VRR(display)) + return; + /* * FIXME all joined pipes share the same transcoder. * Need to account for that during VRR toggle/push/etc. @@ -376,15 +379,12 @@ intel_vrr_compute_config(struct intel_crtc_state *crtc_state, vmax = vmin; } - if (vmin >= vmax) - return; - crtc_state->vrr.vmin = vmin; crtc_state->vrr.vmax = vmax; crtc_state->vrr.flipline = crtc_state->vrr.vmin; - if (crtc_state->uapi.vrr_enabled) + if (crtc_state->uapi.vrr_enabled && vmin < vmax) intel_vrr_compute_vrr_timings(crtc_state); else if (is_cmrr_frac_required(crtc_state) && is_edp) intel_vrr_compute_cmrr_timings(crtc_state); From patchwork Mon Mar 24 13:32:42 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: "Nautiyal, Ankit K" X-Patchwork-Id: 14027369 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 7032AC3600C for ; Mon, 24 Mar 2025 13:44:58 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 1275F10E43F; Mon, 24 Mar 2025 13:44:58 +0000 (UTC) Authentication-Results: gabe.freedesktop.org; dkim=pass (2048-bit key; unprotected) header.d=intel.com header.i=@intel.com header.b="Ox6obM8N"; dkim-atps=neutral Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.21]) by gabe.freedesktop.org (Postfix) with ESMTPS id 482B110E440; Mon, 24 Mar 2025 13:44:57 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1742823897; x=1774359897; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=+onqxst8+HEmQgmlX20rZBtY8zJwfYVAOnIx7F/cWQc=; b=Ox6obM8NFlGClsrX4whbqD7WJsdorC+nWVlEr+V+brCaS7wiIkF+GEkP eD/YwWslcSFpdsjXnOWw6GADhJhrhDVgCCoWmyS1TWVxDBVI9RMsTw6di z3kPIVrGXHkcwy3FLG0Puz+I1alQ5hyjKylkh+owNOHXGxfO1uYL2gecH LxLr3PYfNhBMI2BcjOO3E/fQzrZA98qAptofBoXubwixxmGY1qr7oXw3Y h59iFXJ48BWEZPidKKJ18HvtPrzMpVJjmlB1WyAzHRjg7AeXgA0poFMdc +1gEneg2GpMndUihbMSIfuW9YTIXiiWcdETK6G2cX9VaSJp8rBHUI2W4X A==; X-CSE-ConnectionGUID: U8T2RM4zRaC1IEjX4Z1Owg== X-CSE-MsgGUID: g3MICvdFRcmxw8QettMADQ== X-IronPort-AV: E=McAfee;i="6700,10204,11383"; a="43955730" X-IronPort-AV: E=Sophos;i="6.14,272,1736841600"; d="scan'208";a="43955730" Received: from fmviesa007.fm.intel.com ([10.60.135.147]) by orvoesa113.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 24 Mar 2025 06:44:57 -0700 X-CSE-ConnectionGUID: ds2D+cGrRuOtX61EiHDsvg== X-CSE-MsgGUID: J5DNIjcnQJ+oAlgR8gCz8A== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.14,272,1736841600"; d="scan'208";a="124040666" Received: from srr4-3-linux-103-aknautiy.iind.intel.com ([10.223.34.160]) by fmviesa007-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 24 Mar 2025 06:44:55 -0700 From: Ankit Nautiyal To: intel-gfx@lists.freedesktop.org Cc: intel-xe@lists.freedesktop.org, jani.nikula@linux.intel.com, ville.syrjala@linux.intel.com, mitulkumar.ajitkumar.golani@intel.com Subject: [PATCH 10/16] drm/i915/display: Use fixed rr timings in intel_set_transcoder_timings_lrr() Date: Mon, 24 Mar 2025 19:02:42 +0530 Message-ID: <20250324133248.4071909-11-ankit.k.nautiyal@intel.com> X-Mailer: git-send-email 2.45.2 In-Reply-To: <20250324133248.4071909-1-ankit.k.nautiyal@intel.com> References: <20250324133248.4071909-1-ankit.k.nautiyal@intel.com> MIME-Version: 1.0 X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" Update the intel_set_transcoder_timings_lrr() function to use fixed refresh rate timings. Signed-off-by: Ankit Nautiyal Reviewed-by: Ville Syrjälä --- drivers/gpu/drm/i915/display/intel_display.c | 3 +++ drivers/gpu/drm/i915/display/intel_vrr.c | 1 - drivers/gpu/drm/i915/display/intel_vrr.h | 1 + 3 files changed, 4 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c index b68b86923dca..d26e696ec037 100644 --- a/drivers/gpu/drm/i915/display/intel_display.c +++ b/drivers/gpu/drm/i915/display/intel_display.c @@ -2769,6 +2769,9 @@ static void intel_set_transcoder_timings_lrr(const struct intel_crtc_state *crtc intel_de_write(display, TRANS_VTOTAL(display, cpu_transcoder), VACTIVE(crtc_vdisplay - 1) | VTOTAL(crtc_vtotal - 1)); + + intel_vrr_set_fixed_rr_timings(crtc_state); + intel_vrr_transcoder_enable(crtc_state); } static void intel_set_pipe_src_size(const struct intel_crtc_state *crtc_state) diff --git a/drivers/gpu/drm/i915/display/intel_vrr.c b/drivers/gpu/drm/i915/display/intel_vrr.c index f225fd7f34ff..352b853c10eb 100644 --- a/drivers/gpu/drm/i915/display/intel_vrr.c +++ b/drivers/gpu/drm/i915/display/intel_vrr.c @@ -286,7 +286,6 @@ int intel_vrr_fixed_rr_flipline(const struct intel_crtc_state *crtc_state) return intel_vrr_fixed_rr_vtotal(crtc_state); } -static void intel_vrr_set_fixed_rr_timings(const struct intel_crtc_state *crtc_state) { struct intel_display *display = to_intel_display(crtc_state); diff --git a/drivers/gpu/drm/i915/display/intel_vrr.h b/drivers/gpu/drm/i915/display/intel_vrr.h index 859f1dc8a6d7..c95acf1ad238 100644 --- a/drivers/gpu/drm/i915/display/intel_vrr.h +++ b/drivers/gpu/drm/i915/display/intel_vrr.h @@ -38,5 +38,6 @@ int intel_vrr_vblank_delay(const struct intel_crtc_state *crtc_state); bool intel_vrr_is_fixed_rr(const struct intel_crtc_state *crtc_state); void intel_vrr_transcoder_enable(const struct intel_crtc_state *crtc_state); void intel_vrr_transcoder_disable(const struct intel_crtc_state *crtc_state); +void intel_vrr_set_fixed_rr_timings(const struct intel_crtc_state *crtc_state); #endif /* __INTEL_VRR_H__ */ From patchwork Mon Mar 24 13:32:43 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: "Nautiyal, Ankit K" X-Patchwork-Id: 14027370 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 79BA3C3600D for ; Mon, 24 Mar 2025 13:45:05 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 05DF210E447; Mon, 24 Mar 2025 13:45:05 +0000 (UTC) Authentication-Results: gabe.freedesktop.org; dkim=pass (2048-bit key; unprotected) header.d=intel.com header.i=@intel.com header.b="TACRcIFa"; dkim-atps=neutral Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.21]) by gabe.freedesktop.org (Postfix) with ESMTPS id 5EF1C10E440; Mon, 24 Mar 2025 13:44:59 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1742823899; x=1774359899; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=Jco2h2vwWWkiXDef5QmHb3I8amLSZJkVAG8HTmA7UXc=; b=TACRcIFaEvQbasabQ8lLkGChdMNcMLZXlFMVdJXOCGKGis+qhhCUUkyg n5xn3FBLd3ny3Cftqu27+RS9NNemKZntYF4ctF9yr1S+WTAXerozPrAr7 e6RlvTRW/smR0y1U1OAlVThJK6vqXpQzAKolhPodZFARh2UxHv3jCdHFP /yMY/LMp+vNRuEfiz8w9NFsnf4V0Lfkw9PGeEtj3c8zLhc/V0m7pBJKSy PgO3BD4EkpDs9VhzBYMH64O9DUDrPlCjY5F93alTKp8pCUvscwhydD9y1 VU/dMaMhnfRYJgPCLLTHV1vALw3/QzgNgvkSuwwhszfSYyuS419eLtUps w==; X-CSE-ConnectionGUID: O1Yjnf/7ToSxdmPd2KRoBw== X-CSE-MsgGUID: ZwBgKkbKTD24geYJMiOuiw== X-IronPort-AV: E=McAfee;i="6700,10204,11383"; a="43955733" X-IronPort-AV: E=Sophos;i="6.14,272,1736841600"; d="scan'208";a="43955733" Received: from fmviesa007.fm.intel.com ([10.60.135.147]) by orvoesa113.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 24 Mar 2025 06:44:59 -0700 X-CSE-ConnectionGUID: q+uNlehpTomskVI41DqWgw== X-CSE-MsgGUID: pTotd6PUSn2V34rQ3Rsh8w== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.14,272,1736841600"; d="scan'208";a="124040688" Received: from srr4-3-linux-103-aknautiy.iind.intel.com ([10.223.34.160]) by fmviesa007-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 24 Mar 2025 06:44:57 -0700 From: Ankit Nautiyal To: intel-gfx@lists.freedesktop.org Cc: intel-xe@lists.freedesktop.org, jani.nikula@linux.intel.com, ville.syrjala@linux.intel.com, mitulkumar.ajitkumar.golani@intel.com Subject: [PATCH 11/16] drm/i915/display: Move vrr.guardband/pipeline_full out of !fastset block Date: Mon, 24 Mar 2025 19:02:43 +0530 Message-ID: <20250324133248.4071909-12-ankit.k.nautiyal@intel.com> X-Mailer: git-send-email 2.45.2 In-Reply-To: <20250324133248.4071909-1-ankit.k.nautiyal@intel.com> References: <20250324133248.4071909-1-ankit.k.nautiyal@intel.com> MIME-Version: 1.0 X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" Since the vrr.guardband can now change for platforms that always use the VRR Timing Generator, and it is unsafe to reprogram the guardband on the fly, move the guardband and pipeline_full checks from the pure !fastboot path and add a check for intel_vrr_always_use_vrr_tg(). For older platforms the vrr.guardband change happens when VRR Timing generator is off. For the platforms that always use the VRR Timing Generator, this will prevent reprogramming the vrr.guardband without a full modeset. However, this will disrupt LRR functionality for these platforms. v2: Modify the check to avoid breaking the LRR on older platform. (Ville) v3: Correct the oversight of not removing the lines from the original location. (Ville) Signed-off-by: Ankit Nautiyal Reviewed-by: Ville Syrjälä --- drivers/gpu/drm/i915/display/intel_display.c | 7 +++++-- drivers/gpu/drm/i915/display/intel_vrr.c | 1 - drivers/gpu/drm/i915/display/intel_vrr.h | 2 ++ 3 files changed, 7 insertions(+), 3 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c index d26e696ec037..ae1dc32044fb 100644 --- a/drivers/gpu/drm/i915/display/intel_display.c +++ b/drivers/gpu/drm/i915/display/intel_display.c @@ -5389,8 +5389,6 @@ intel_pipe_config_compare(const struct intel_crtc_state *current_config, PIPE_CONF_CHECK_I(vrr.vmin); PIPE_CONF_CHECK_I(vrr.vmax); PIPE_CONF_CHECK_I(vrr.flipline); - PIPE_CONF_CHECK_I(vrr.pipeline_full); - PIPE_CONF_CHECK_I(vrr.guardband); PIPE_CONF_CHECK_I(vrr.vsync_start); PIPE_CONF_CHECK_I(vrr.vsync_end); PIPE_CONF_CHECK_LLI(cmrr.cmrr_m); @@ -5398,6 +5396,11 @@ intel_pipe_config_compare(const struct intel_crtc_state *current_config, PIPE_CONF_CHECK_BOOL(cmrr.enable); } + if (!fastset || intel_vrr_always_use_vrr_tg(display)) { + PIPE_CONF_CHECK_I(vrr.pipeline_full); + PIPE_CONF_CHECK_I(vrr.guardband); + } + #undef PIPE_CONF_CHECK_X #undef PIPE_CONF_CHECK_I #undef PIPE_CONF_CHECK_LLI diff --git a/drivers/gpu/drm/i915/display/intel_vrr.c b/drivers/gpu/drm/i915/display/intel_vrr.c index 352b853c10eb..c57e0319d83c 100644 --- a/drivers/gpu/drm/i915/display/intel_vrr.c +++ b/drivers/gpu/drm/i915/display/intel_vrr.c @@ -552,7 +552,6 @@ bool intel_vrr_is_push_sent(const struct intel_crtc_state *crtc_state) return intel_de_read(display, TRANS_PUSH(display, cpu_transcoder)) & TRANS_PUSH_SEND; } -static bool intel_vrr_always_use_vrr_tg(struct intel_display *display) { if (!HAS_VRR(display)) diff --git a/drivers/gpu/drm/i915/display/intel_vrr.h b/drivers/gpu/drm/i915/display/intel_vrr.h index c95acf1ad238..38bf9996b883 100644 --- a/drivers/gpu/drm/i915/display/intel_vrr.h +++ b/drivers/gpu/drm/i915/display/intel_vrr.h @@ -13,6 +13,7 @@ struct intel_atomic_state; struct intel_connector; struct intel_crtc_state; struct intel_dsb; +struct intel_display; bool intel_vrr_is_capable(struct intel_connector *connector); bool intel_vrr_is_in_range(struct intel_connector *connector, int vrefresh); @@ -39,5 +40,6 @@ bool intel_vrr_is_fixed_rr(const struct intel_crtc_state *crtc_state); void intel_vrr_transcoder_enable(const struct intel_crtc_state *crtc_state); void intel_vrr_transcoder_disable(const struct intel_crtc_state *crtc_state); void intel_vrr_set_fixed_rr_timings(const struct intel_crtc_state *crtc_state); +bool intel_vrr_always_use_vrr_tg(struct intel_display *display); #endif /* __INTEL_VRR_H__ */ From patchwork Mon Mar 24 13:32:44 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: "Nautiyal, Ankit K" X-Patchwork-Id: 14027374 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 98D5CC3600C for ; Mon, 24 Mar 2025 13:45:11 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 36A2510E44E; Mon, 24 Mar 2025 13:45:11 +0000 (UTC) Authentication-Results: gabe.freedesktop.org; dkim=pass (2048-bit key; unprotected) header.d=intel.com header.i=@intel.com header.b="LME5zA02"; dkim-atps=neutral Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.21]) by gabe.freedesktop.org (Postfix) with ESMTPS id 85D8710E442; Mon, 24 Mar 2025 13:45:01 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1742823901; x=1774359901; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=tZHQxC8ZaHKB46FaN4CY31F4VpeLO667r3/RMy7ARSc=; b=LME5zA02QijkcGh28+EpazMso/d08a5I2Dfk5CS8CFO03WpbX1JlHQEq Bu8QUTYSUx0r4tY4FXriPtWR8QACpC0QAnHrNEmv3S0K8OLOpvYjmGZdi NJcFEAPWiwqh/L8zaPBSV1Tvh0uV8Dy1T0lv+CN6dIjgYq35/8yzDEvzB gp6TWSPVi7p4cpe379VsESp2VxGq22fs2Z5oIS9lHeArqEHYFLmg6frq6 JgfSf8IGfZHLJ4+lSzfjVuTVYc7fPtWGGF6zf4NQTiBbizHEpTx/h7X88 3K44uEvroi0sKyP7rA8h79astGLPVqdP8YTehS1P7Ox3Ck6NF++nxVH6u A==; X-CSE-ConnectionGUID: YKsD+CdlQhqBlTunS1NsoQ== X-CSE-MsgGUID: ZpPrHmayS9SB+S4Mrtp9qg== X-IronPort-AV: E=McAfee;i="6700,10204,11383"; a="43955736" X-IronPort-AV: E=Sophos;i="6.14,272,1736841600"; d="scan'208";a="43955736" Received: from fmviesa007.fm.intel.com ([10.60.135.147]) by orvoesa113.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 24 Mar 2025 06:45:01 -0700 X-CSE-ConnectionGUID: drToeZDySRSavqC1akmGDQ== X-CSE-MsgGUID: 1BYDkkBpTX+F8iL18dSrRA== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.14,272,1736841600"; d="scan'208";a="124040711" Received: from srr4-3-linux-103-aknautiy.iind.intel.com ([10.223.34.160]) by fmviesa007-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 24 Mar 2025 06:44:59 -0700 From: Ankit Nautiyal To: intel-gfx@lists.freedesktop.org Cc: intel-xe@lists.freedesktop.org, jani.nikula@linux.intel.com, ville.syrjala@linux.intel.com, mitulkumar.ajitkumar.golani@intel.com Subject: [PATCH 12/16] drm/i915/vrr: Allow fixed_rr with pipe joiner Date: Mon, 24 Mar 2025 19:02:44 +0530 Message-ID: <20250324133248.4071909-13-ankit.k.nautiyal@intel.com> X-Mailer: git-send-email 2.45.2 In-Reply-To: <20250324133248.4071909-1-ankit.k.nautiyal@intel.com> References: <20250324133248.4071909-1-ankit.k.nautiyal@intel.com> MIME-Version: 1.0 X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" VRR with joiner is currently disabled as it still needs some work to correctly sequence the primary and secondary transcoders. However, we can still use VRR Timing generator in fixed refresh rate for joiner and since it just need to program vrr timings once and does not involve changing timings on the fly. We still need to skip the VRR and LRR for joiner. To achieve this set vrr.in_range to 0 for joiner case, so that we do not try VRR and LRR for the joiner case. v2: Avoid checks for secondary pipes, where not required. (Ville) v3: Remove a redundant check and reset vrr.in_range to false. (Ville) Signed-off-by: Ankit Nautiyal Reviewed-by: Ville Syrjälä --- drivers/gpu/drm/i915/display/intel_vrr.c | 18 +++++++++++------- 1 file changed, 11 insertions(+), 7 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_vrr.c b/drivers/gpu/drm/i915/display/intel_vrr.c index c57e0319d83c..dda42522f461 100644 --- a/drivers/gpu/drm/i915/display/intel_vrr.c +++ b/drivers/gpu/drm/i915/display/intel_vrr.c @@ -355,19 +355,23 @@ intel_vrr_compute_config(struct intel_crtc_state *crtc_state, if (!HAS_VRR(display)) return; - /* - * FIXME all joined pipes share the same transcoder. - * Need to account for that during VRR toggle/push/etc. - */ - if (crtc_state->joiner_pipes) - return; - if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) return; crtc_state->vrr.in_range = intel_vrr_is_in_range(connector, drm_mode_vrefresh(adjusted_mode)); + /* + * Allow fixed refresh rate with VRR Timing Generator. + * For now set the vrr.in_range to 0, to allow fixed_rr but skip actual + * VRR and LRR. + * #TODO For actual VRR with joiner, we need to figure out how to + * correctly sequence transcoder level stuff vs. pipe level stuff + * in the commit. + */ + if (crtc_state->joiner_pipes) + crtc_state->vrr.in_range = false; + vmin = intel_vrr_compute_vmin(crtc_state); if (crtc_state->vrr.in_range) { From patchwork Mon Mar 24 13:32:45 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: "Nautiyal, Ankit K" X-Patchwork-Id: 14027373 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 00317C3600D for ; Mon, 24 Mar 2025 13:45:11 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 8A70910E450; Mon, 24 Mar 2025 13:45:11 +0000 (UTC) Authentication-Results: gabe.freedesktop.org; dkim=pass (2048-bit key; unprotected) header.d=intel.com header.i=@intel.com header.b="Ei9hsDvZ"; dkim-atps=neutral Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.21]) by gabe.freedesktop.org (Postfix) with ESMTPS id D443A10E442; Mon, 24 Mar 2025 13:45:03 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1742823904; x=1774359904; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=ZSYEFdR3p4jiZ4YeiONbG6vOnWHVd1yPOOQwl9o6bMI=; b=Ei9hsDvZekSe/AoOdhQo7KAnbHcUgQjBZvwpTB6N/PeILQ0tsMi/dEYh ajrrYOsO4mS7puRMy2TrvYjMUCMoFgy+K7IjF6ZeZgXGYtHxZwv+DNFgz u8quTJwqSj8ACI45jecMhXsabenApyC8UoAyf7iPPIfVdUsbwqrdWrkT9 jfU6QVcghuQxPAYRwHBDjGdu2tmlytweZxEjAaZ+tESbfNp88vYCXoIys qpPYtMd/3zfqxyH4c7dBFNFf1rYaRL4Ds6g3sr2wEaXb/5GZ/jShPT2nr Xe39I+8L9Hc64PcsxHOh0Bpp7ENqUx1yVvWyd4069nTn4pBH4gwvkyFUA Q==; X-CSE-ConnectionGUID: 9s29dCSCRT2xoGbefUEv2w== X-CSE-MsgGUID: q16D/5pSRVGaCVwQVAg38w== X-IronPort-AV: E=McAfee;i="6700,10204,11383"; a="43955738" X-IronPort-AV: E=Sophos;i="6.14,272,1736841600"; d="scan'208";a="43955738" Received: from fmviesa007.fm.intel.com ([10.60.135.147]) by orvoesa113.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 24 Mar 2025 06:45:03 -0700 X-CSE-ConnectionGUID: AoMyMQWRTcaRHFdb1SdsZw== X-CSE-MsgGUID: WfDP42RUSu2NOLER1KwOfw== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.14,272,1736841600"; d="scan'208";a="124040743" Received: from srr4-3-linux-103-aknautiy.iind.intel.com ([10.223.34.160]) by fmviesa007-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 24 Mar 2025 06:45:01 -0700 From: Ankit Nautiyal To: intel-gfx@lists.freedesktop.org Cc: intel-xe@lists.freedesktop.org, jani.nikula@linux.intel.com, ville.syrjala@linux.intel.com, mitulkumar.ajitkumar.golani@intel.com Subject: [PATCH 13/16] drm/i915/vrr: Always use VRR timing generator for PTL+ Date: Mon, 24 Mar 2025 19:02:45 +0530 Message-ID: <20250324133248.4071909-14-ankit.k.nautiyal@intel.com> X-Mailer: git-send-email 2.45.2 In-Reply-To: <20250324133248.4071909-1-ankit.k.nautiyal@intel.com> References: <20250324133248.4071909-1-ankit.k.nautiyal@intel.com> MIME-Version: 1.0 X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" Currently, the VRR timing generator is used only when VRR is enabled by userspace for sinks that support VRR. Starting with PTL+, gradually move away from the legacy timing generator and use the VRR timing generator for both variable and fixed timings. Note: For platforms where we always enable the VRR timing generator, the LRR fastset is not allowed to avoid live programming of vrr.guardband with VRR TG enabled. This effectively breaks the LRR fastset functionality for these platforms and needs to be addressed. v2: Use this for PTL for now to avoid losing LRR fastset for older platforms. (Ville) Signed-off-by: Ankit Nautiyal Reviewed-by: Ville Syrjälä --- drivers/gpu/drm/i915/display/intel_vrr.c | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/i915/display/intel_vrr.c b/drivers/gpu/drm/i915/display/intel_vrr.c index dda42522f461..5e60da2bb0c3 100644 --- a/drivers/gpu/drm/i915/display/intel_vrr.c +++ b/drivers/gpu/drm/i915/display/intel_vrr.c @@ -561,7 +561,9 @@ bool intel_vrr_always_use_vrr_tg(struct intel_display *display) if (!HAS_VRR(display)) return false; - /* #TODO return true for platforms supporting fixed_rr */ + if (DISPLAY_VER(display) >= 30) + return true; + return false; } From patchwork Mon Mar 24 13:32:46 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: "Nautiyal, Ankit K" X-Patchwork-Id: 14027371 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 49CACC36002 for ; Mon, 24 Mar 2025 13:45:07 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id D8C9F10E443; Mon, 24 Mar 2025 13:45:06 +0000 (UTC) Authentication-Results: gabe.freedesktop.org; dkim=pass (2048-bit key; unprotected) header.d=intel.com header.i=@intel.com header.b="FKRopMFo"; dkim-atps=neutral Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.21]) by gabe.freedesktop.org (Postfix) with ESMTPS id 5A3DF10E443; Mon, 24 Mar 2025 13:45:05 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1742823905; x=1774359905; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=v2fY03Yh+n2qvHhlAFCgaOdRZuuVM7TXNDi1wSegm4c=; b=FKRopMFo8HKW7gGvdi9VZ78P4fAwEcwPqBXTxZ1HepJ6upmTYeKpYI5V bEkXNCDMaQ5ebP4xjs+ujcEtBbm8TdY/ngjmug6FPdz0ZmYIKV2/JBe8e 6UbIJ1qE6iDpIJzEpNnYHpsZ+/OK7yoFypqUp67/JOi9qJLrDmfMgepGr n34EWgU3Q8kSjujTx4yc8qlyrSY0iUb0gyuVtiWk7DFii9sNLpNlbt0jx QCtKowXmO0f9xYvZgg+2ixwob732R1k8JbWl1TgHZBYVAe7faVRz/ELkt yYb80xyySKGwqP8Qq3iDkLnT1RCdiom1ylt+dcVDhhAaJRXpxokyjMx/d A==; X-CSE-ConnectionGUID: ymgdDDgHSbuCgoKv0gvo6w== X-CSE-MsgGUID: J6rdrglARiGR/ZndnfvXPw== X-IronPort-AV: E=McAfee;i="6700,10204,11383"; a="43955755" X-IronPort-AV: E=Sophos;i="6.14,272,1736841600"; d="scan'208";a="43955755" Received: from fmviesa007.fm.intel.com ([10.60.135.147]) by orvoesa113.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 24 Mar 2025 06:45:05 -0700 X-CSE-ConnectionGUID: zF7ZiMVYQnCJ9qnDLHYxSg== X-CSE-MsgGUID: Fgyd5NrGQvmA3surPwrggw== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.14,272,1736841600"; d="scan'208";a="124040771" Received: from srr4-3-linux-103-aknautiy.iind.intel.com ([10.223.34.160]) by fmviesa007-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 24 Mar 2025 06:45:03 -0700 From: Ankit Nautiyal To: intel-gfx@lists.freedesktop.org Cc: intel-xe@lists.freedesktop.org, jani.nikula@linux.intel.com, ville.syrjala@linux.intel.com, mitulkumar.ajitkumar.golani@intel.com Subject: [PATCH 14/16] drm/i915/vrr: Set trans_vrr_ctl in intel_vrr_set_transcoder_timings() Date: Mon, 24 Mar 2025 19:02:46 +0530 Message-ID: <20250324133248.4071909-15-ankit.k.nautiyal@intel.com> X-Mailer: git-send-email 2.45.2 In-Reply-To: <20250324133248.4071909-1-ankit.k.nautiyal@intel.com> References: <20250324133248.4071909-1-ankit.k.nautiyal@intel.com> MIME-Version: 1.0 X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" We now always set vrr.flipline, vmin, and vmax for all platforms that support VRR. Therefore, we should set all TRANS_VRR_CTL bits except VRR_ENABLE. Without this, the readback for these bits will fail because we only read vrr.flipline, vmin, and vmax if TRANS_VRR_CTL has the FLIPLINE_EN bit set. For platforms that always have the VRR Timing Generator enabled, the FLIPLINE_EN bit is always set in TRANS_VRR_CTL during intel_transcoder_vrr_enable(). However, for the remaining platforms (that do not always have the VRR Timing Generator enabled) if a full modeset doesn't occur and VRR is not enabled, the bit is not set. This results in a mismatch between the software state and hardware state because the software state expects VRR timings like flipline, vmin, and vmax to be set, but the readout for these doesn't happen since the FLIPLINE_EN bit is not set in TRANS_VRR_CTL. To avoid this mismatch, write trans_vrr_ctl in intel_vrr_set_transcoder_timings() even when VRR is not enabled for platforms that do not have the VRR Timing Generator always enabled. Signed-off-by: Ankit Nautiyal Reviewed-by: Ville Syrjälä --- drivers/gpu/drm/i915/display/intel_vrr.c | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/drivers/gpu/drm/i915/display/intel_vrr.c b/drivers/gpu/drm/i915/display/intel_vrr.c index 5e60da2bb0c3..414f93851059 100644 --- a/drivers/gpu/drm/i915/display/intel_vrr.c +++ b/drivers/gpu/drm/i915/display/intel_vrr.c @@ -484,6 +484,10 @@ void intel_vrr_set_transcoder_timings(const struct intel_crtc_state *crtc_state) intel_vrr_set_fixed_rr_timings(crtc_state); + if (!intel_vrr_always_use_vrr_tg(display) && !crtc_state->vrr.enable) + intel_de_write(display, TRANS_VRR_CTL(display, cpu_transcoder), + trans_vrr_ctl(crtc_state)); + if (HAS_AS_SDP(display)) intel_de_write(display, TRANS_VRR_VSYNC(display, cpu_transcoder), From patchwork Mon Mar 24 13:32:47 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Nautiyal, Ankit K" X-Patchwork-Id: 14027375 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 6656EC3600B for ; Mon, 24 Mar 2025 13:45:12 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id D588D10E451; Mon, 24 Mar 2025 13:45:11 +0000 (UTC) Authentication-Results: gabe.freedesktop.org; dkim=pass (2048-bit key; unprotected) header.d=intel.com header.i=@intel.com header.b="QjGNo0gc"; dkim-atps=neutral Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.21]) by gabe.freedesktop.org (Postfix) with ESMTPS id 4EA8310E448; Mon, 24 Mar 2025 13:45:07 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1742823907; x=1774359907; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=MJR4VsnGBGG5VxCSBQ/Pd/Hbl6Qxv0VofXFymoRHLcs=; b=QjGNo0gcK4/uknI9efiFKQOjJV8wLwnIcE5wuxcUavjoZQnv0Qi5tcRR bDhl9fIXKLbs6bLHpE0+S35Bec1TisJqyrjlEDXbxTO3b4In8t3IArfJx 50khHETRvGSWiL3MD8CQoPoqiP60OZ67wEZ3yg38Bmc6dfRf/v4Cbgt4Q kTTjKs6LpE7r/gz00WlThKXhzZC3C7iywJJy31gBnMKXQKmwyBULGs+62 TnepdPDMGJGnkv1kl36i6LU+V86hbNlcqk1GEFJWPBU/6tqOpx1gSwLPD xWhrmhyncCzzyiQ0VzhAlnFWJqdMm+Vlx+SAzHJeLNzPG4MNroEhAoEu8 w==; X-CSE-ConnectionGUID: eXD2mIV6R8WrUybEV70khA== X-CSE-MsgGUID: HXSmWgEWSWObUkQwm1k1gA== X-IronPort-AV: E=McAfee;i="6700,10204,11383"; a="43955759" X-IronPort-AV: E=Sophos;i="6.14,272,1736841600"; d="scan'208";a="43955759" Received: from fmviesa007.fm.intel.com ([10.60.135.147]) by orvoesa113.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 24 Mar 2025 06:45:07 -0700 X-CSE-ConnectionGUID: bfC6tqZGQq+iuSrXhkayQQ== X-CSE-MsgGUID: pODP48g2SjKZdXL+T/6huA== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.14,272,1736841600"; d="scan'208";a="124040801" Received: from srr4-3-linux-103-aknautiy.iind.intel.com ([10.223.34.160]) by fmviesa007-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 24 Mar 2025 06:45:05 -0700 From: Ankit Nautiyal To: intel-gfx@lists.freedesktop.org Cc: intel-xe@lists.freedesktop.org, jani.nikula@linux.intel.com, ville.syrjala@linux.intel.com, mitulkumar.ajitkumar.golani@intel.com Subject: [PATCH 15/16] drm/i915/display: Separate out functions to get/set VTOTAL register Date: Mon, 24 Mar 2025 19:02:47 +0530 Message-ID: <20250324133248.4071909-16-ankit.k.nautiyal@intel.com> X-Mailer: git-send-email 2.45.2 In-Reply-To: <20250324133248.4071909-1-ankit.k.nautiyal@intel.com> References: <20250324133248.4071909-1-ankit.k.nautiyal@intel.com> MIME-Version: 1.0 X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" Introduce helpers to get and set TRANS_VTOTAL registers. This will pave way to avoid reading/writing VTOTAL.Vtotal bits for platforms that always use VRR timing generator. Signed-off-by: Ankit Nautiyal --- drivers/gpu/drm/i915/display/intel_display.c | 41 +++++++++++++------- 1 file changed, 27 insertions(+), 14 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c index ae1dc32044fb..fa9c6793357e 100644 --- a/drivers/gpu/drm/i915/display/intel_display.c +++ b/drivers/gpu/drm/i915/display/intel_display.c @@ -2638,6 +2638,15 @@ void intel_cpu_transcoder_set_m2_n2(struct intel_crtc *crtc, PIPE_LINK_N2(display, transcoder)); } +static void intel_crtc_set_vtotal(struct intel_display *display, + enum transcoder cpu_transcoder, + u32 crtc_vdisplay, u32 crtc_vtotal) +{ + intel_de_write(display, TRANS_VTOTAL(display, cpu_transcoder), + VACTIVE(crtc_vdisplay - 1) | + VTOTAL(crtc_vtotal - 1)); +} + static void intel_set_transcoder_timings(const struct intel_crtc_state *crtc_state) { struct intel_display *display = to_intel_display(crtc_state); @@ -2702,9 +2711,8 @@ static void intel_set_transcoder_timings(const struct intel_crtc_state *crtc_sta HSYNC_START(adjusted_mode->crtc_hsync_start - 1) | HSYNC_END(adjusted_mode->crtc_hsync_end - 1)); - intel_de_write(display, TRANS_VTOTAL(display, cpu_transcoder), - VACTIVE(crtc_vdisplay - 1) | - VTOTAL(crtc_vtotal - 1)); + intel_crtc_set_vtotal(display, cpu_transcoder, crtc_vdisplay, crtc_vtotal); + intel_de_write(display, TRANS_VBLANK(display, cpu_transcoder), VBLANK_START(crtc_vblank_start - 1) | VBLANK_END(crtc_vblank_end - 1)); @@ -2718,9 +2726,8 @@ static void intel_set_transcoder_timings(const struct intel_crtc_state *crtc_sta * bits. */ if (display->platform.haswell && cpu_transcoder == TRANSCODER_EDP && (pipe == PIPE_B || pipe == PIPE_C)) - intel_de_write(display, TRANS_VTOTAL(display, pipe), - VACTIVE(crtc_vdisplay - 1) | - VTOTAL(crtc_vtotal - 1)); + intel_crtc_set_vtotal(display, (enum transcoder)pipe, + crtc_vdisplay, crtc_vtotal); } static void intel_set_transcoder_timings_lrr(const struct intel_crtc_state *crtc_state) @@ -2766,9 +2773,7 @@ static void intel_set_transcoder_timings_lrr(const struct intel_crtc_state *crtc * The double buffer latch point for TRANS_VTOTAL * is the transcoder's undelayed vblank. */ - intel_de_write(display, TRANS_VTOTAL(display, cpu_transcoder), - VACTIVE(crtc_vdisplay - 1) | - VTOTAL(crtc_vtotal - 1)); + intel_crtc_set_vtotal(display, cpu_transcoder, crtc_vdisplay, crtc_vtotal); intel_vrr_set_fixed_rr_timings(crtc_state); intel_vrr_transcoder_enable(crtc_state); @@ -2806,6 +2811,17 @@ static bool intel_pipe_is_interlaced(const struct intel_crtc_state *crtc_state) TRANSCONF(display, cpu_transcoder)) & TRANSCONF_INTERLACE_MASK; } +static void intel_crtc_get_vtotal(struct intel_crtc_state *crtc_state) +{ + struct intel_display *display = to_intel_display(crtc_state); + enum transcoder cpu_transcoder = crtc_state->cpu_transcoder; + struct drm_display_mode *adjusted_mode = &crtc_state->hw.adjusted_mode; + u32 tmp = intel_de_read(display, TRANS_VTOTAL(display, cpu_transcoder)); + + adjusted_mode->crtc_vdisplay = REG_FIELD_GET(VACTIVE_MASK, tmp) + 1; + adjusted_mode->crtc_vtotal = REG_FIELD_GET(VTOTAL_MASK, tmp) + 1; +} + static void intel_get_transcoder_timings(struct intel_crtc *crtc, struct intel_crtc_state *pipe_config) { @@ -2829,9 +2845,7 @@ static void intel_get_transcoder_timings(struct intel_crtc *crtc, adjusted_mode->crtc_hsync_start = REG_FIELD_GET(HSYNC_START_MASK, tmp) + 1; adjusted_mode->crtc_hsync_end = REG_FIELD_GET(HSYNC_END_MASK, tmp) + 1; - tmp = intel_de_read(display, TRANS_VTOTAL(display, cpu_transcoder)); - adjusted_mode->crtc_vdisplay = REG_FIELD_GET(VACTIVE_MASK, tmp) + 1; - adjusted_mode->crtc_vtotal = REG_FIELD_GET(VTOTAL_MASK, tmp) + 1; + intel_crtc_get_vtotal(pipe_config); /* FIXME TGL+ DSI transcoders have this! */ if (!transcoder_is_dsi(cpu_transcoder)) { @@ -8168,8 +8182,7 @@ void i830_enable_pipe(struct intel_display *display, enum pipe pipe) HBLANK_START(640 - 1) | HBLANK_END(800 - 1)); intel_de_write(display, TRANS_HSYNC(display, cpu_transcoder), HSYNC_START(656 - 1) | HSYNC_END(752 - 1)); - intel_de_write(display, TRANS_VTOTAL(display, cpu_transcoder), - VACTIVE(480 - 1) | VTOTAL(525 - 1)); + intel_crtc_set_vtotal(display, cpu_transcoder, 480, 525); intel_de_write(display, TRANS_VBLANK(display, cpu_transcoder), VBLANK_START(480 - 1) | VBLANK_END(525 - 1)); intel_de_write(display, TRANS_VSYNC(display, cpu_transcoder), From patchwork Mon Mar 24 13:32:48 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Nautiyal, Ankit K" X-Patchwork-Id: 14027372 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id A0EADC36002 for ; Mon, 24 Mar 2025 13:45:10 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 4133810E44C; Mon, 24 Mar 2025 13:45:10 +0000 (UTC) Authentication-Results: gabe.freedesktop.org; dkim=pass (2048-bit key; unprotected) header.d=intel.com header.i=@intel.com header.b="XfsNsNhi"; dkim-atps=neutral Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.21]) by gabe.freedesktop.org (Postfix) with ESMTPS id 9766B10E44D; Mon, 24 Mar 2025 13:45:09 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1742823909; x=1774359909; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=LfeVp6BhrDU/SuR64FwuyiHJzBAAB4XrKyRr89gLTGs=; b=XfsNsNhiZJPAjR4aJJKnQnS9oNteQ076CVITZ8p/E9gbtIscDj6rZ0SR 63fYU1qxQp3w1bpZcPWrmiKQoWG9x+TRlllkImK3I97/DlfKwrKyLer7a itO830xZ2LofedSCbw0aVtRvYQkqwy0tfkTZ4+xgDY8Zf5sqXL5IzJ1xn BK/u+aiNcaObfiIgHZyK2f+TUH3Xzgz2MO+p8I182PBD7SJVFAq/CUIFk VNWMrdGyZXvdLcaKJqqtSVB5AARLBJRmq1ON/66fT6LUGY3U74WbOwRF5 DvyVKA9vX1Lx9sUuoSsV5rcX1AtZOgHNXC3SDg0nO7+uBt+AoUJ6p6ymS Q==; X-CSE-ConnectionGUID: 1gKybks5RLmbT6voiic+zA== X-CSE-MsgGUID: BMsZr2nLRlCD+/BNow610g== X-IronPort-AV: E=McAfee;i="6700,10204,11383"; a="43955766" X-IronPort-AV: E=Sophos;i="6.14,272,1736841600"; d="scan'208";a="43955766" Received: from fmviesa007.fm.intel.com ([10.60.135.147]) by orvoesa113.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 24 Mar 2025 06:45:09 -0700 X-CSE-ConnectionGUID: 3r6m/6BgRrq8jDtXWrhAsQ== X-CSE-MsgGUID: kNVwQE+aQjWz0EcnHI6ySQ== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.14,272,1736841600"; d="scan'208";a="124040865" Received: from srr4-3-linux-103-aknautiy.iind.intel.com ([10.223.34.160]) by fmviesa007-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 24 Mar 2025 06:45:07 -0700 From: Ankit Nautiyal To: intel-gfx@lists.freedesktop.org Cc: intel-xe@lists.freedesktop.org, jani.nikula@linux.intel.com, ville.syrjala@linux.intel.com, mitulkumar.ajitkumar.golani@intel.com Subject: [PATCH 16/16] drm/i915/display: Avoid use of VTOTAL.Vtotal bits Date: Mon, 24 Mar 2025 19:02:48 +0530 Message-ID: <20250324133248.4071909-17-ankit.k.nautiyal@intel.com> X-Mailer: git-send-email 2.45.2 In-Reply-To: <20250324133248.4071909-1-ankit.k.nautiyal@intel.com> References: <20250324133248.4071909-1-ankit.k.nautiyal@intel.com> MIME-Version: 1.0 X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" For platforms that always use VRR Timing Generator, the VTOTAL.Vtotal bits are not required. Since the support for these bits is going to be deprecated in upcoming platforms, avoid writing these bits for the platforms that do not use legacy Timing Generator. Since for these platforms TRAN_VMIN is always filled with crtc_vtotal, use TRAN_VRR_VMIN to get the vtotal for adjusted_mode. Signed-off-by: Ankit Nautiyal --- drivers/gpu/drm/i915/display/intel_display.c | 29 ++++++++++++++++++-- drivers/gpu/drm/i915/display/intel_vrr.c | 8 ++++++ drivers/gpu/drm/i915/display/intel_vrr.h | 1 + 3 files changed, 35 insertions(+), 3 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c index fa9c6793357e..ddd98037bef8 100644 --- a/drivers/gpu/drm/i915/display/intel_display.c +++ b/drivers/gpu/drm/i915/display/intel_display.c @@ -2642,9 +2642,21 @@ static void intel_crtc_set_vtotal(struct intel_display *display, enum transcoder cpu_transcoder, u32 crtc_vdisplay, u32 crtc_vtotal) { + u32 vtotal_bits; + + /* + * For platforms that always use VRR Timing Generator, the VTOTAL.Vtotal + * bits are not required. Since the support for these bits is going to + * be deprecated in upcoming platforms, avoid writing these bits for the + * platforms that do not use legacy Timing Generator. + */ + if (intel_vrr_always_use_vrr_tg(display)) + vtotal_bits = 0; + else + vtotal_bits = VTOTAL(crtc_vtotal - 1); + intel_de_write(display, TRANS_VTOTAL(display, cpu_transcoder), - VACTIVE(crtc_vdisplay - 1) | - VTOTAL(crtc_vtotal - 1)); + VACTIVE(crtc_vdisplay - 1) | vtotal_bits); } static void intel_set_transcoder_timings(const struct intel_crtc_state *crtc_state) @@ -2819,7 +2831,18 @@ static void intel_crtc_get_vtotal(struct intel_crtc_state *crtc_state) u32 tmp = intel_de_read(display, TRANS_VTOTAL(display, cpu_transcoder)); adjusted_mode->crtc_vdisplay = REG_FIELD_GET(VACTIVE_MASK, tmp) + 1; - adjusted_mode->crtc_vtotal = REG_FIELD_GET(VTOTAL_MASK, tmp) + 1; + + /* + * For platforms that always use VRR Timing Generator, the VTOTAL.Vtotal + * bits are not filled. Since for these platforms TRAN_VMIN is always + * filled with crtc_vtotal, use TRAN_VRR_VMIN to get the vtotal for + * adjusted_mode. + */ + if (intel_vrr_always_use_vrr_tg(display)) { + adjusted_mode->crtc_vtotal = intel_vrr_get_vtotal_vmin(crtc_state); + } else { + adjusted_mode->crtc_vtotal = REG_FIELD_GET(VTOTAL_MASK, tmp) + 1; + } } static void intel_get_transcoder_timings(struct intel_crtc *crtc, diff --git a/drivers/gpu/drm/i915/display/intel_vrr.c b/drivers/gpu/drm/i915/display/intel_vrr.c index 414f93851059..4413c97b3135 100644 --- a/drivers/gpu/drm/i915/display/intel_vrr.c +++ b/drivers/gpu/drm/i915/display/intel_vrr.c @@ -734,3 +734,11 @@ void intel_vrr_get_config(struct intel_crtc_state *crtc_state) if (crtc_state->vrr.enable) crtc_state->mode_flags |= I915_MODE_FLAG_VRR; } + +int intel_vrr_get_vtotal_vmin(struct intel_crtc_state *crtc_state) +{ + struct intel_display *display = to_intel_display(crtc_state); + enum transcoder cpu_transcoder = crtc_state->cpu_transcoder; + + return intel_de_read(display, TRANS_VRR_VMIN(display, cpu_transcoder)) + 1; +} diff --git a/drivers/gpu/drm/i915/display/intel_vrr.h b/drivers/gpu/drm/i915/display/intel_vrr.h index 38bf9996b883..1ad17812a08b 100644 --- a/drivers/gpu/drm/i915/display/intel_vrr.h +++ b/drivers/gpu/drm/i915/display/intel_vrr.h @@ -41,5 +41,6 @@ void intel_vrr_transcoder_enable(const struct intel_crtc_state *crtc_state); void intel_vrr_transcoder_disable(const struct intel_crtc_state *crtc_state); void intel_vrr_set_fixed_rr_timings(const struct intel_crtc_state *crtc_state); bool intel_vrr_always_use_vrr_tg(struct intel_display *display); +int intel_vrr_get_vtotal_vmin(struct intel_crtc_state *crtc_state); #endif /* __INTEL_VRR_H__ */