From patchwork Tue Mar 25 06:59:27 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Christian Bruel X-Patchwork-Id: 14028150 X-Patchwork-Delegate: kw@linux.com Received: from mx08-00178001.pphosted.com (mx08-00178001.pphosted.com [91.207.212.93]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 6E29D207E08; Tue, 25 Mar 2025 07:03:34 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=91.207.212.93 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1742886216; cv=none; b=XZiZ/D34o5ByIJVfDD5napUn+JUx+K7LAHX/EE2itLq3BbWlCla99NDLBVrM8pqFm/RjUHqYfJHjZJlkvG6zb5yWrmLHsDLzdOyC+tgMeeVI8dS1+q+L0cpcpd1jidCMvyrr622RkLAmY7dznVZgXFxqkhrpK65dEE0cazPxJN8= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1742886216; c=relaxed/simple; bh=C4+oUPEN9Noig0K+rNbvHo5kIRMN684zMDXD/FWHi0k=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=oBC9h+WzWPZBJYYrqUnYL75wnzGuQh/V8zVWUEtxKEsQyOmTnWhYyhThTAQ2FLYkc1r5exOmdyZTXXKcZCO8LMITYaWw1Ig8mLmhjBGVh5R4qBwc+CHVXSWhSGgzYXjy73etzzuMzyD+LCehbpgQotPHRCVeP8ZDQAbayLuDBu0= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=foss.st.com; spf=pass smtp.mailfrom=foss.st.com; dkim=pass (2048-bit key) header.d=foss.st.com header.i=@foss.st.com header.b=ZxtJs8TT; arc=none smtp.client-ip=91.207.212.93 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=foss.st.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=foss.st.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=foss.st.com header.i=@foss.st.com header.b="ZxtJs8TT" Received: from pps.filterd (m0369457.ppops.net [127.0.0.1]) by mx07-00178001.pphosted.com (8.18.1.2/8.18.1.2) with ESMTP id 52P5uE2F022015; Tue, 25 Mar 2025 08:03:04 +0100 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=foss.st.com; h= cc:content-transfer-encoding:content-type:date:from:in-reply-to :message-id:mime-version:references:subject:to; s=selector1; bh= qGD73/6Hfje+CHtFjpnoM4cVHsKMuplCC1K3yOtX1GM=; b=ZxtJs8TT1oXDT9Cw czWE5vE+6aancuLHlqYlOCRIBy5eZemUEhQK0Y+VK0U7qwPeQpQZIw5ldD+a9C9m s8ZT21//rbbIte+sjgf/opMuSxt3pZg1PJQnTOoxFs9P8tdpqIJRPthxZKzG/LTB heTHeQjKijhytcaec7MNu9u6oBfgXxPVxh3eydbBzIjLDKqeg1/OStYJd8ICDUXV oZEdFW9VhyKEXje2DCiH9fxCCg1aBdjlxTv9Net6Gp4TCklA/uHdT5d+vv5jfiSD TP6aFuyjE88CNDjmFw0Gl2xtjXEq6PMiiJvhtksXrvwOspel/tKrswJGI6lb8dMu mhkPoA== Received: from beta.dmz-ap.st.com (beta.dmz-ap.st.com [138.198.100.35]) by mx07-00178001.pphosted.com (PPS) with ESMTPS id 45j91s8bvn-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Tue, 25 Mar 2025 08:03:03 +0100 (CET) Received: from euls16034.sgp.st.com (euls16034.sgp.st.com [10.75.44.20]) by beta.dmz-ap.st.com (STMicroelectronics) with ESMTP id 7BC4140078; Tue, 25 Mar 2025 08:01:30 +0100 (CET) Received: from Webmail-eu.st.com (shfdag1node3.st.com [10.75.129.71]) by euls16034.sgp.st.com (STMicroelectronics) with ESMTP id 703F8840457; Tue, 25 Mar 2025 07:59:43 +0100 (CET) Received: from localhost (10.130.77.120) by SHFDAG1NODE3.st.com (10.75.129.71) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.39; Tue, 25 Mar 2025 07:59:43 +0100 From: Christian Bruel To: , , , , , , , , , , , , , CC: , , , , , Subject: [PATCH v5 1/9 RESEND] dt-bindings: PCI: Add STM32MP25 PCIe Root Complex bindings Date: Tue, 25 Mar 2025 07:59:27 +0100 Message-ID: <20250325065935.908886-2-christian.bruel@foss.st.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20250325065935.908886-1-christian.bruel@foss.st.com> References: <20250325065935.908886-1-christian.bruel@foss.st.com> Precedence: bulk X-Mailing-List: linux-pci@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-ClientProxiedBy: EQNCAS1NODE4.st.com (10.75.129.82) To SHFDAG1NODE3.st.com (10.75.129.71) X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1093,Hydra:6.0.680,FMLib:17.12.68.34 definitions=2025-03-25_03,2025-03-21_01,2024-11-22_01 Document the bindings for STM32MP25 PCIe Controller configured in root complex mode with one root port. Supports 4 INTx and MSI interrupts from the ARM GICv2m controller. STM32 PCIe may be in a power domain which is the case for the STM32MP25 based boards. Supports WAKE# from wake-gpios Signed-off-by: Christian Bruel Reviewed-by: Rob Herring (Arm) --- .../bindings/pci/st,stm32-pcie-common.yaml | 33 ++++++ .../bindings/pci/st,stm32-pcie-host.yaml | 112 ++++++++++++++++++ 2 files changed, 145 insertions(+) create mode 100644 Documentation/devicetree/bindings/pci/st,stm32-pcie-common.yaml create mode 100644 Documentation/devicetree/bindings/pci/st,stm32-pcie-host.yaml diff --git a/Documentation/devicetree/bindings/pci/st,stm32-pcie-common.yaml b/Documentation/devicetree/bindings/pci/st,stm32-pcie-common.yaml new file mode 100644 index 000000000000..5adbff259204 --- /dev/null +++ b/Documentation/devicetree/bindings/pci/st,stm32-pcie-common.yaml @@ -0,0 +1,33 @@ +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/pci/st,stm32-pcie-common.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: STM32MP25 PCIe RC/EP controller + +maintainers: + - Christian Bruel + +description: + STM32MP25 PCIe RC/EP common properties + +properties: + clocks: + maxItems: 1 + description: PCIe system clock + + resets: + maxItems: 1 + + power-domains: + maxItems: 1 + + access-controllers: + maxItems: 1 + +required: + - clocks + - resets + +additionalProperties: true diff --git a/Documentation/devicetree/bindings/pci/st,stm32-pcie-host.yaml b/Documentation/devicetree/bindings/pci/st,stm32-pcie-host.yaml new file mode 100644 index 000000000000..26f852e6f5b7 --- /dev/null +++ b/Documentation/devicetree/bindings/pci/st,stm32-pcie-host.yaml @@ -0,0 +1,112 @@ +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/pci/st,stm32-pcie-host.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: STMicroelectronics STM32MP25 PCIe Root Complex + +maintainers: + - Christian Bruel + +description: + PCIe root complex controller based on the Synopsys DesignWare PCIe core. + +allOf: + - $ref: /schemas/pci/snps,dw-pcie.yaml# + - $ref: /schemas/pci/st,stm32-pcie-common.yaml# + +properties: + compatible: + const: st,stm32mp25-pcie-rc + + reg: + items: + - description: Data Bus Interface (DBI) registers. + - description: PCIe configuration registers. + + reg-names: + items: + - const: dbi + - const: config + + msi-parent: + maxItems: 1 + +patternProperties: + '^pcie@[0-2],0$': + type: object + $ref: /schemas/pci/pci-pci-bridge.yaml# + + properties: + reg: + maxItems: 1 + + phys: + maxItems: 1 + + reset-gpios: + description: GPIO controlled connection to PERST# signal + maxItems: 1 + + wake-gpios: + description: GPIO used as WAKE# input signal + maxItems: 1 + + required: + - phys + - ranges + + unevaluatedProperties: false + +required: + - interrupt-map + - interrupt-map-mask + - ranges + - dma-ranges + +unevaluatedProperties: false + +examples: + - | + #include + #include + #include + #include + #include + + pcie@48400000 { + compatible = "st,stm32mp25-pcie-rc"; + device_type = "pci"; + reg = <0x48400000 0x400000>, + <0x10000000 0x10000>; + reg-names = "dbi", "config"; + #interrupt-cells = <1>; + interrupt-map-mask = <0 0 0 7>; + interrupt-map = <0 0 0 1 &intc 0 0 GIC_SPI 264 IRQ_TYPE_LEVEL_HIGH>, + <0 0 0 2 &intc 0 0 GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>, + <0 0 0 3 &intc 0 0 GIC_SPI 266 IRQ_TYPE_LEVEL_HIGH>, + <0 0 0 4 &intc 0 0 GIC_SPI 267 IRQ_TYPE_LEVEL_HIGH>; + #address-cells = <3>; + #size-cells = <2>; + ranges = <0x01000000 0x0 0x00000000 0x10010000 0x0 0x10000>, + <0x02000000 0x0 0x10020000 0x10020000 0x0 0x7fe0000>, + <0x42000000 0x0 0x18000000 0x18000000 0x0 0x8000000>; + dma-ranges = <0x42000000 0x0 0x80000000 0x80000000 0x0 0x80000000>; + clocks = <&rcc CK_BUS_PCIE>; + resets = <&rcc PCIE_R>; + msi-parent = <&v2m0>; + access-controllers = <&rifsc 68>; + power-domains = <&CLUSTER_PD>; + + pcie@0,0 { + device_type = "pci"; + reg = <0x0 0x0 0x0 0x0 0x0>; + phys = <&combophy PHY_TYPE_PCIE>; + wake-gpios = <&gpioh 5 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>; + reset-gpios = <&gpioj 8 GPIO_ACTIVE_LOW>; + #address-cells = <3>; + #size-cells = <2>; + ranges; + }; + }; From patchwork Tue Mar 25 06:59:28 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Christian Bruel X-Patchwork-Id: 14028156 X-Patchwork-Delegate: kw@linux.com Received: from mx07-00178001.pphosted.com (mx07-00178001.pphosted.com [185.132.182.106]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id B635C79F5; Tue, 25 Mar 2025 07:03:56 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=185.132.182.106 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1742886238; cv=none; b=H7uvrb+Jp/wzsXWo3B4sLvtWAB3lx7KJ5FLnBp8pVVuUHq+pn7vwpI3nouIqpeT9lCs9MLo5vkgVKbpFBwGPK7MUch2fna5GoYLNfdEn5p0+XHJSGEBHybS43FWDaIxjkdMahD3r/F3AZp0i44GGeBDZjs13CCmqraoSX0F2hqk= ARC-Message-Signature: i=1; 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Tue, 25 Mar 2025 08:02:14 +0100 (CET) Received: from Webmail-eu.st.com (shfdag1node3.st.com [10.75.129.71]) by euls16034.sgp.st.com (STMicroelectronics) with ESMTP id ACB5E84046F; Tue, 25 Mar 2025 07:59:46 +0100 (CET) Received: from localhost (10.130.77.120) by SHFDAG1NODE3.st.com (10.75.129.71) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.39; Tue, 25 Mar 2025 07:59:46 +0100 From: Christian Bruel To: , , , , , , , , , , , , , CC: , , , , , Subject: [PATCH v5 2/9 RESEND] PCI: stm32: Add PCIe host support for STM32MP25 Date: Tue, 25 Mar 2025 07:59:28 +0100 Message-ID: <20250325065935.908886-3-christian.bruel@foss.st.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20250325065935.908886-1-christian.bruel@foss.st.com> References: <20250325065935.908886-1-christian.bruel@foss.st.com> Precedence: bulk X-Mailing-List: linux-pci@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-ClientProxiedBy: EQNCAS1NODE4.st.com (10.75.129.82) To SHFDAG1NODE3.st.com (10.75.129.71) X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1093,Hydra:6.0.680,FMLib:17.12.68.34 definitions=2025-03-25_03,2025-03-21_01,2024-11-22_01 Add driver for the STM32MP25 SoC PCIe Gen1 2.5 GT/s and Gen2 5GT/s controller based on the DesignWare PCIe core. Supports MSI via GICv2m, Single Virtual Channel, Single Function Supports WAKE# GPIO. Signed-off-by: Christian Bruel --- drivers/pci/controller/dwc/Kconfig | 12 + drivers/pci/controller/dwc/Makefile | 1 + drivers/pci/controller/dwc/pcie-stm32.c | 367 ++++++++++++++++++++++++ drivers/pci/controller/dwc/pcie-stm32.h | 15 + 4 files changed, 395 insertions(+) create mode 100644 drivers/pci/controller/dwc/pcie-stm32.c create mode 100644 drivers/pci/controller/dwc/pcie-stm32.h diff --git a/drivers/pci/controller/dwc/Kconfig b/drivers/pci/controller/dwc/Kconfig index b6d6778b0698..0c18879b604c 100644 --- a/drivers/pci/controller/dwc/Kconfig +++ b/drivers/pci/controller/dwc/Kconfig @@ -389,6 +389,18 @@ config PCIE_SPEAR13XX help Say Y here if you want PCIe support on SPEAr13XX SoCs. +config PCIE_STM32 + tristate "STMicroelectronics STM32MP25 PCIe Controller (host mode)" + depends on ARCH_STM32 || COMPILE_TEST + depends on PCI_MSI + select PCIE_DW_HOST + help + Enables support for the DesignWare core based PCIe host controller + found in STM32MP25 SoC. + + This driver can also be built as a module. If so, the module + will be called pcie-stm32. + config PCI_DRA7XX tristate diff --git a/drivers/pci/controller/dwc/Makefile b/drivers/pci/controller/dwc/Makefile index a8308d9ea986..576d99cb3bc5 100644 --- a/drivers/pci/controller/dwc/Makefile +++ b/drivers/pci/controller/dwc/Makefile @@ -28,6 +28,7 @@ obj-$(CONFIG_PCIE_UNIPHIER) += pcie-uniphier.o obj-$(CONFIG_PCIE_UNIPHIER_EP) += pcie-uniphier-ep.o obj-$(CONFIG_PCIE_VISCONTI_HOST) += pcie-visconti.o obj-$(CONFIG_PCIE_RCAR_GEN4) += pcie-rcar-gen4.o +obj-$(CONFIG_PCIE_STM32) += pcie-stm32.o # The following drivers are for devices that use the generic ACPI # pci_root.c driver but don't support standard ECAM config access. diff --git a/drivers/pci/controller/dwc/pcie-stm32.c b/drivers/pci/controller/dwc/pcie-stm32.c new file mode 100644 index 000000000000..3937777d9eb9 --- /dev/null +++ b/drivers/pci/controller/dwc/pcie-stm32.c @@ -0,0 +1,367 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * STMicroelectronics STM32MP25 PCIe root complex driver. + * + * Copyright (C) 2025 STMicroelectronics + * Author: Christian Bruel + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include "pcie-designware.h" +#include "pcie-stm32.h" +#include "../../pci.h" + +struct stm32_pcie { + struct dw_pcie pci; + struct regmap *regmap; + struct reset_control *rst; + struct phy *phy; + struct clk *clk; + struct gpio_desc *perst_gpio; + struct gpio_desc *wake_gpio; +}; + +static void stm32_pcie_deassert_perst(struct stm32_pcie *stm32_pcie) +{ + gpiod_set_value(stm32_pcie->perst_gpio, 0); + + if (stm32_pcie->perst_gpio) + msleep(PCIE_T_RRS_READY_MS); +} + +static void stm32_pcie_assert_perst(struct stm32_pcie *stm32_pcie) +{ + gpiod_set_value(stm32_pcie->perst_gpio, 1); +} + +static int stm32_pcie_start_link(struct dw_pcie *pci) +{ + struct stm32_pcie *stm32_pcie = to_stm32_pcie(pci); + + return regmap_update_bits(stm32_pcie->regmap, SYSCFG_PCIECR, + STM32MP25_PCIECR_LTSSM_EN, + STM32MP25_PCIECR_LTSSM_EN); +} + +static void stm32_pcie_stop_link(struct dw_pcie *pci) +{ + struct stm32_pcie *stm32_pcie = to_stm32_pcie(pci); + + regmap_update_bits(stm32_pcie->regmap, SYSCFG_PCIECR, + STM32MP25_PCIECR_LTSSM_EN, 0); +} + +static int stm32_pcie_suspend_noirq(struct device *dev) +{ + struct stm32_pcie *stm32_pcie = dev_get_drvdata(dev); + int ret; + + ret = dw_pcie_suspend_noirq(&stm32_pcie->pci); + if (ret) { + stm32_pcie_deassert_perst(stm32_pcie); + return ret; + } + + stm32_pcie_assert_perst(stm32_pcie); + + clk_disable_unprepare(stm32_pcie->clk); + + if (!device_wakeup_path(dev)) + phy_exit(stm32_pcie->phy); + + return pinctrl_pm_select_sleep_state(dev); +} + +static int stm32_pcie_resume_noirq(struct device *dev) +{ + struct stm32_pcie *stm32_pcie = dev_get_drvdata(dev); + int ret; + + /* + * The core clock is gated with CLKREQ# from the COMBOPHY REFCLK, + * thus if no device is present, must force it low with an init pinmux + * to be able to access the DBI registers. + */ + if (!IS_ERR(dev->pins->init_state)) + ret = pinctrl_select_state(dev->pins->p, dev->pins->init_state); + else + ret = pinctrl_pm_select_default_state(dev); + + if (ret) { + dev_err(dev, "Failed to activate pinctrl pm state: %d\n", ret); + return ret; + } + + if (!device_wakeup_path(dev)) { + ret = phy_init(stm32_pcie->phy); + if (ret) { + pinctrl_pm_select_default_state(dev); + return ret; + } + } + + ret = clk_prepare_enable(stm32_pcie->clk); + if (ret) + goto err_phy_exit; + + stm32_pcie_deassert_perst(stm32_pcie); + + ret = dw_pcie_resume_noirq(&stm32_pcie->pci); + if (ret) + goto err_disable_clk; + + pinctrl_pm_select_default_state(dev); + + return 0; + +err_disable_clk: + stm32_pcie_assert_perst(stm32_pcie); + clk_disable_unprepare(stm32_pcie->clk); + +err_phy_exit: + phy_exit(stm32_pcie->phy); + pinctrl_pm_select_default_state(dev); + + return ret; +} + +static const struct dev_pm_ops stm32_pcie_pm_ops = { + NOIRQ_SYSTEM_SLEEP_PM_OPS(stm32_pcie_suspend_noirq, + stm32_pcie_resume_noirq) +}; + +static const struct dw_pcie_host_ops stm32_pcie_host_ops = { +}; + +static const struct dw_pcie_ops dw_pcie_ops = { + .start_link = stm32_pcie_start_link, + .stop_link = stm32_pcie_stop_link +}; + +static int stm32_add_pcie_port(struct stm32_pcie *stm32_pcie, + struct platform_device *pdev) +{ + struct device *dev = stm32_pcie->pci.dev; + unsigned int wake_irq; + int ret; + + /* Start to enable resources with PERST# asserted from GPIO */ + + ret = phy_set_mode(stm32_pcie->phy, PHY_MODE_PCIE); + if (ret) + return ret; + + ret = phy_init(stm32_pcie->phy); + if (ret) + return ret; + + ret = regmap_update_bits(stm32_pcie->regmap, SYSCFG_PCIECR, + STM32MP25_PCIECR_TYPE_MASK, + STM32MP25_PCIECR_RC); + if (ret) + goto err_phy_exit; + + stm32_pcie_deassert_perst(stm32_pcie); + + if (stm32_pcie->wake_gpio) { + wake_irq = gpiod_to_irq(stm32_pcie->wake_gpio); + ret = dev_pm_set_dedicated_wake_irq(dev, wake_irq); + if (ret) { + dev_info(dev, "Failed to enable wake# %d\n", ret); + goto err_disable_clk; + } + irq_set_irq_type(wake_irq, IRQ_TYPE_EDGE_FALLING); + } + + return 0; + +err_disable_clk: + stm32_pcie_assert_perst(stm32_pcie); + clk_disable_unprepare(stm32_pcie->clk); + +err_phy_exit: + phy_exit(stm32_pcie->phy); + + return ret; +} + +static void stm32_remove_pcie_port(struct stm32_pcie *stm32_pcie) +{ + stm32_pcie_assert_perst(stm32_pcie); + + phy_exit(stm32_pcie->phy); +} + +static int stm32_pcie_parse_port(struct stm32_pcie *stm32_pcie) +{ + struct device *dev = stm32_pcie->pci.dev; + struct device_node *root_port; + + root_port = of_get_next_available_child(dev->of_node, NULL); + + stm32_pcie->phy = devm_of_phy_get(dev, root_port, NULL); + if (IS_ERR(stm32_pcie->phy)) { + of_node_put(root_port); + return dev_err_probe(dev, PTR_ERR(stm32_pcie->phy), + "Failed to get pcie-phy\n"); + } + + stm32_pcie->perst_gpio = devm_fwnode_gpiod_get(dev, of_fwnode_handle(root_port), + "reset", GPIOD_OUT_HIGH, NULL); + if (IS_ERR(stm32_pcie->perst_gpio)) { + if (PTR_ERR(stm32_pcie->perst_gpio) != -ENOENT) { + of_node_put(root_port); + return dev_err_probe(dev, PTR_ERR(stm32_pcie->perst_gpio), + "Failed to get reset GPIO\n"); + } + stm32_pcie->perst_gpio = NULL; + } + + stm32_pcie->wake_gpio = devm_fwnode_gpiod_get(dev, of_fwnode_handle(root_port), + "wake", GPIOD_IN, NULL); + + if (IS_ERR(stm32_pcie->wake_gpio)) { + if (PTR_ERR(stm32_pcie->wake_gpio) != -ENOENT) { + of_node_put(root_port); + return dev_err_probe(dev, PTR_ERR(stm32_pcie->wake_gpio), + "Failed to get wake GPIO\n"); + } + stm32_pcie->wake_gpio = NULL; + } + + of_node_put(root_port); + + return 0; +} + +static int stm32_pcie_probe(struct platform_device *pdev) +{ + struct stm32_pcie *stm32_pcie; + struct device *dev = &pdev->dev; + int ret; + + stm32_pcie = devm_kzalloc(dev, sizeof(*stm32_pcie), GFP_KERNEL); + if (!stm32_pcie) + return -ENOMEM; + + stm32_pcie->pci.dev = dev; + stm32_pcie->pci.ops = &dw_pcie_ops; + stm32_pcie->pci.pp.ops = &stm32_pcie_host_ops; + + stm32_pcie->regmap = syscon_regmap_lookup_by_compatible("st,stm32mp25-syscfg"); + if (IS_ERR(stm32_pcie->regmap)) + return dev_err_probe(dev, PTR_ERR(stm32_pcie->regmap), + "No syscfg specified\n"); + + stm32_pcie->clk = devm_clk_get(dev, NULL); + if (IS_ERR(stm32_pcie->clk)) + return dev_err_probe(dev, PTR_ERR(stm32_pcie->clk), + "Failed to get PCIe clock source\n"); + + stm32_pcie->rst = devm_reset_control_get_exclusive(dev, NULL); + if (IS_ERR(stm32_pcie->rst)) + return dev_err_probe(dev, PTR_ERR(stm32_pcie->rst), + "Failed to get PCIe reset\n"); + + ret = stm32_pcie_parse_port(stm32_pcie); + if (ret) + return ret; + + platform_set_drvdata(pdev, stm32_pcie); + + ret = pm_runtime_set_active(dev); + if (ret < 0) { + dev_err(dev, "Failed to activate runtime PM %d\n", ret); + return ret; + } + + ret = devm_pm_runtime_enable(dev); + if (ret < 0) { + dev_err(dev, "Failed to enable runtime PM %d\n", ret); + return ret; + } + + pm_runtime_get_noresume(dev); + + ret = stm32_add_pcie_port(stm32_pcie, pdev); + if (ret) { + pm_runtime_put_noidle(&pdev->dev); + return ret; + } + + reset_control_assert(stm32_pcie->rst); + reset_control_deassert(stm32_pcie->rst); + + ret = clk_prepare_enable(stm32_pcie->clk); + if (ret) { + dev_err(dev, "Core clock enable failed %d\n", ret); + goto err_remove_port; + } + + ret = dw_pcie_host_init(&stm32_pcie->pci.pp); + if (ret) + goto err_disable_clk; + + if (stm32_pcie->wake_gpio) + device_set_wakeup_capable(dev, true); + + return 0; + +err_disable_clk: + clk_disable_unprepare(stm32_pcie->clk); + +err_remove_port: + stm32_remove_pcie_port(stm32_pcie); + pm_runtime_put_noidle(&pdev->dev); + + return ret; +} + +static void stm32_pcie_remove(struct platform_device *pdev) +{ + struct stm32_pcie *stm32_pcie = platform_get_drvdata(pdev); + struct dw_pcie_rp *pp = &stm32_pcie->pci.pp; + + if (stm32_pcie->wake_gpio) + device_init_wakeup(&pdev->dev, false); + + dw_pcie_host_deinit(pp); + + clk_disable_unprepare(stm32_pcie->clk); + + stm32_remove_pcie_port(stm32_pcie); + + pm_runtime_put_noidle(&pdev->dev); +} + +static const struct of_device_id stm32_pcie_of_match[] = { + { .compatible = "st,stm32mp25-pcie-rc" }, + {}, +}; + +static struct platform_driver stm32_pcie_driver = { + .probe = stm32_pcie_probe, + .remove = stm32_pcie_remove, + .driver = { + .name = "stm32-pcie", + .of_match_table = stm32_pcie_of_match, + .pm = &stm32_pcie_pm_ops, + .probe_type = PROBE_PREFER_ASYNCHRONOUS, + }, +}; + +module_platform_driver(stm32_pcie_driver); + +MODULE_AUTHOR("Christian Bruel "); +MODULE_DESCRIPTION("STM32MP25 PCIe Controller driver"); +MODULE_LICENSE("GPL"); +MODULE_DEVICE_TABLE(of, stm32_pcie_of_match); diff --git a/drivers/pci/controller/dwc/pcie-stm32.h b/drivers/pci/controller/dwc/pcie-stm32.h new file mode 100644 index 000000000000..387112c4e42c --- /dev/null +++ b/drivers/pci/controller/dwc/pcie-stm32.h @@ -0,0 +1,15 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * ST PCIe driver definitions for STM32-MP25 SoC + * + * Copyright (C) 2025 STMicroelectronics - All Rights Reserved + * Author: Christian Bruel + */ + +#define to_stm32_pcie(x) dev_get_drvdata((x)->dev) + +#define STM32MP25_PCIECR_TYPE_MASK GENMASK(11, 8) +#define STM32MP25_PCIECR_LTSSM_EN BIT(2) +#define STM32MP25_PCIECR_RC BIT(10) + +#define SYSCFG_PCIECR 0x6000 From patchwork Tue Mar 25 06:59:29 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Christian Bruel X-Patchwork-Id: 14028153 X-Patchwork-Delegate: kw@linux.com Received: from mx08-00178001.pphosted.com (mx08-00178001.pphosted.com [91.207.212.93]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 19F062F3B; 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Signed-off-by: Christian Bruel Reviewed-by: Rob Herring (Arm) Acked-by: Manivannan Sadhasivam --- .../bindings/pci/st,stm32-pcie-ep.yaml | 67 +++++++++++++++++++ 1 file changed, 67 insertions(+) create mode 100644 Documentation/devicetree/bindings/pci/st,stm32-pcie-ep.yaml diff --git a/Documentation/devicetree/bindings/pci/st,stm32-pcie-ep.yaml b/Documentation/devicetree/bindings/pci/st,stm32-pcie-ep.yaml new file mode 100644 index 000000000000..fc1bbe19e616 --- /dev/null +++ b/Documentation/devicetree/bindings/pci/st,stm32-pcie-ep.yaml @@ -0,0 +1,67 @@ +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/pci/st,stm32-pcie-ep.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: STMicroelectronics STM32MP25 PCIe Endpoint + +maintainers: + - Christian Bruel + +description: + PCIe endpoint controller based on the Synopsys DesignWare PCIe core. + +allOf: + - $ref: /schemas/pci/snps,dw-pcie-ep.yaml# + - $ref: /schemas/pci/st,stm32-pcie-common.yaml# + +properties: + compatible: + const: st,stm32mp25-pcie-ep + + reg: + items: + - description: Data Bus Interface (DBI) registers. + - description: PCIe configuration registers. + + reg-names: + items: + - const: dbi + - const: addr_space + + reset-gpios: + description: GPIO controlled connection to PERST# signal + maxItems: 1 + + phys: + maxItems: 1 + +required: + - phys + - reset-gpios + +unevaluatedProperties: false + +examples: + - | + #include + #include + #include + #include + + pcie-ep@48400000 { + compatible = "st,stm32mp25-pcie-ep"; + reg = <0x48400000 0x400000>, + <0x10000000 0x8000000>; + reg-names = "dbi", "addr_space"; + clocks = <&rcc CK_BUS_PCIE>; + phys = <&combophy PHY_TYPE_PCIE>; + resets = <&rcc PCIE_R>; + pinctrl-names = "default", "init"; + pinctrl-0 = <&pcie_pins_a>; + pinctrl-1 = <&pcie_init_pins_a>; + reset-gpios = <&gpioj 8 GPIO_ACTIVE_LOW>; + access-controllers = <&rifsc 68>; + power-domains = <&CLUSTER_PD>; + }; From patchwork Tue Mar 25 06:59:30 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Christian Bruel X-Patchwork-Id: 14028155 X-Patchwork-Delegate: kw@linux.com Received: from mx07-00178001.pphosted.com (mx07-00178001.pphosted.com [185.132.182.106]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 6E06D253B73; Tue, 25 Mar 2025 07:03:55 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=185.132.182.106 ARC-Seal: i=1; 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Tue, 25 Mar 2025 08:03:30 +0100 (CET) Received: from euls16034.sgp.st.com (euls16034.sgp.st.com [10.75.44.20]) by beta.dmz-ap.st.com (STMicroelectronics) with ESMTP id 826E64005C; Tue, 25 Mar 2025 08:02:06 +0100 (CET) Received: from Webmail-eu.st.com (shfdag1node3.st.com [10.75.129.71]) by euls16034.sgp.st.com (STMicroelectronics) with ESMTP id 5A79F844ECD; Tue, 25 Mar 2025 07:59:51 +0100 (CET) Received: from localhost (10.130.77.120) by SHFDAG1NODE3.st.com (10.75.129.71) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.39; Tue, 25 Mar 2025 07:59:51 +0100 From: Christian Bruel To: , , , , , , , , , , , , , CC: , , , , , Subject: [PATCH v5 4/9 RESEND] PCI: stm32: Add PCIe Endpoint support for STM32MP25 Date: Tue, 25 Mar 2025 07:59:30 +0100 Message-ID: <20250325065935.908886-5-christian.bruel@foss.st.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20250325065935.908886-1-christian.bruel@foss.st.com> References: <20250325065935.908886-1-christian.bruel@foss.st.com> Precedence: bulk X-Mailing-List: linux-pci@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-ClientProxiedBy: EQNCAS1NODE4.st.com (10.75.129.82) To SHFDAG1NODE3.st.com (10.75.129.71) X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1093,Hydra:6.0.680,FMLib:17.12.68.34 definitions=2025-03-25_03,2025-03-21_01,2024-11-22_01 Add driver to configure the STM32MP25 SoC PCIe Gen1 2.5GT/s or Gen2 5GT/s controller based on the DesignWare PCIe core in endpoint mode. Uses the common reference clock provided by the host. The PCIe core_clk receives the pipe0_clk from the ComboPHY as input, and the ComboPHY PLL must be locked for pipe0_clk to be ready. Consequently, PCIe core registers cannot be accessed until the ComboPHY is fully initialised and refclk is enabled and ready. Signed-off-by: Christian Bruel --- drivers/pci/controller/dwc/Kconfig | 12 + drivers/pci/controller/dwc/Makefile | 1 + drivers/pci/controller/dwc/pcie-stm32-ep.c | 420 +++++++++++++++++++++ drivers/pci/controller/dwc/pcie-stm32.h | 1 + 4 files changed, 434 insertions(+) create mode 100644 drivers/pci/controller/dwc/pcie-stm32-ep.c diff --git a/drivers/pci/controller/dwc/Kconfig b/drivers/pci/controller/dwc/Kconfig index 0c18879b604c..4a3eb838557c 100644 --- a/drivers/pci/controller/dwc/Kconfig +++ b/drivers/pci/controller/dwc/Kconfig @@ -401,6 +401,18 @@ config PCIE_STM32 This driver can also be built as a module. If so, the module will be called pcie-stm32. +config PCIE_STM32_EP + tristate "STMicroelectronics STM32MP25 PCIe Controller (endpoint mode)" + depends on ARCH_STM32 || COMPILE_TEST + depends on PCI_ENDPOINT + select PCIE_DW_EP + help + Enables endpoint support for DesignWare core based PCIe controller + found in STM32MP25 SoC. + + This driver can also be built as a module. If so, the module + will be called pcie-stm32-ep. + config PCI_DRA7XX tristate diff --git a/drivers/pci/controller/dwc/Makefile b/drivers/pci/controller/dwc/Makefile index 576d99cb3bc5..caebd98f6dd3 100644 --- a/drivers/pci/controller/dwc/Makefile +++ b/drivers/pci/controller/dwc/Makefile @@ -29,6 +29,7 @@ obj-$(CONFIG_PCIE_UNIPHIER_EP) += pcie-uniphier-ep.o obj-$(CONFIG_PCIE_VISCONTI_HOST) += pcie-visconti.o obj-$(CONFIG_PCIE_RCAR_GEN4) += pcie-rcar-gen4.o obj-$(CONFIG_PCIE_STM32) += pcie-stm32.o +obj-$(CONFIG_PCIE_STM32_EP) += pcie-stm32-ep.o # The following drivers are for devices that use the generic ACPI # pci_root.c driver but don't support standard ECAM config access. diff --git a/drivers/pci/controller/dwc/pcie-stm32-ep.c b/drivers/pci/controller/dwc/pcie-stm32-ep.c new file mode 100644 index 000000000000..a8e9c5a9b127 --- /dev/null +++ b/drivers/pci/controller/dwc/pcie-stm32-ep.c @@ -0,0 +1,420 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * STMicroelectronics STM32MP25 PCIe endpoint driver. + * + * Copyright (C) 2025 STMicroelectronics + * Author: Christian Bruel + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include "pcie-designware.h" +#include "pcie-stm32.h" + +enum stm32_pcie_ep_link_status { + STM32_PCIE_EP_LINK_DISABLED, + STM32_PCIE_EP_LINK_ENABLED, +}; + +struct stm32_pcie { + struct dw_pcie pci; + struct regmap *regmap; + struct reset_control *rst; + struct phy *phy; + struct clk *clk; + struct gpio_desc *perst_gpio; + enum stm32_pcie_ep_link_status link_status; + unsigned int perst_irq; +}; + +static void stm32_pcie_ep_init(struct dw_pcie_ep *ep) +{ + struct dw_pcie *pci = to_dw_pcie_from_ep(ep); + enum pci_barno bar; + + for (bar = 0; bar < PCI_STD_NUM_BARS; bar++) + dw_pcie_ep_reset_bar(pci, bar); +} + +static int stm32_pcie_enable_link(struct dw_pcie *pci) +{ + struct stm32_pcie *stm32_pcie = to_stm32_pcie(pci); + + regmap_update_bits(stm32_pcie->regmap, SYSCFG_PCIECR, + STM32MP25_PCIECR_LTSSM_EN, + STM32MP25_PCIECR_LTSSM_EN); + + return dw_pcie_wait_for_link(pci); +} + +static void stm32_pcie_disable_link(struct dw_pcie *pci) +{ + struct stm32_pcie *stm32_pcie = to_stm32_pcie(pci); + + regmap_update_bits(stm32_pcie->regmap, SYSCFG_PCIECR, STM32MP25_PCIECR_LTSSM_EN, 0); +} + +static int stm32_pcie_start_link(struct dw_pcie *pci) +{ + struct stm32_pcie *stm32_pcie = to_stm32_pcie(pci); + struct dw_pcie_ep *ep = &pci->ep; + int ret; + + if (stm32_pcie->link_status == STM32_PCIE_EP_LINK_ENABLED) { + dev_dbg(pci->dev, "Link is already enabled\n"); + return 0; + } + + ret = stm32_pcie_enable_link(pci); + if (ret) { + dev_err(pci->dev, "PCIe cannot establish link: %d\n", ret); + return ret; + } + + dw_pcie_ep_linkup(ep); + + stm32_pcie->link_status = STM32_PCIE_EP_LINK_ENABLED; + + enable_irq(stm32_pcie->perst_irq); + + return 0; +} + +static void stm32_pcie_stop_link(struct dw_pcie *pci) +{ + struct stm32_pcie *stm32_pcie = to_stm32_pcie(pci); + + if (stm32_pcie->link_status == STM32_PCIE_EP_LINK_DISABLED) { + dev_dbg(pci->dev, "Link is already disabled\n"); + return; + } + + disable_irq(stm32_pcie->perst_irq); + + stm32_pcie_disable_link(pci); + + stm32_pcie->link_status = STM32_PCIE_EP_LINK_DISABLED; +} + +static int stm32_pcie_raise_irq(struct dw_pcie_ep *ep, u8 func_no, + unsigned int type, u16 interrupt_num) +{ + struct dw_pcie *pci = to_dw_pcie_from_ep(ep); + + switch (type) { + case PCI_IRQ_INTX: + return dw_pcie_ep_raise_intx_irq(ep, func_no); + case PCI_IRQ_MSI: + return dw_pcie_ep_raise_msi_irq(ep, func_no, interrupt_num); + default: + dev_err(pci->dev, "UNKNOWN IRQ type\n"); + return -EINVAL; + } +} + +static const struct pci_epc_features stm32_pcie_epc_features = { + .msi_capable = true, + .align = SZ_64K, +}; + +static const struct pci_epc_features* +stm32_pcie_get_features(struct dw_pcie_ep *ep) +{ + return &stm32_pcie_epc_features; +} + +static const struct dw_pcie_ep_ops stm32_pcie_ep_ops = { + .init = stm32_pcie_ep_init, + .raise_irq = stm32_pcie_raise_irq, + .get_features = stm32_pcie_get_features, +}; + +static const struct dw_pcie_ops dw_pcie_ops = { + .start_link = stm32_pcie_start_link, + .stop_link = stm32_pcie_stop_link, +}; + +static int stm32_pcie_enable_resources(struct stm32_pcie *stm32_pcie) +{ + int ret; + + ret = phy_init(stm32_pcie->phy); + if (ret) + return ret; + + ret = clk_prepare_enable(stm32_pcie->clk); + if (ret) + phy_exit(stm32_pcie->phy); + + return ret; +} + +static void stm32_pcie_disable_resources(struct stm32_pcie *stm32_pcie) +{ + clk_disable_unprepare(stm32_pcie->clk); + + phy_exit(stm32_pcie->phy); +} + +static void stm32_pcie_perst_assert(struct dw_pcie *pci) +{ + struct stm32_pcie *stm32_pcie = to_stm32_pcie(pci); + struct device *dev = pci->dev; + + dev_dbg(dev, "PERST asserted by host. Shutting down the PCIe link\n"); + + /* + * Do not try to release resources if the PERST# is + * asserted before the link is started. + */ + if (stm32_pcie->link_status == STM32_PCIE_EP_LINK_DISABLED) { + dev_dbg(pci->dev, "Link is already disabled\n"); + return; + } + + stm32_pcie_disable_link(pci); + + stm32_pcie_disable_resources(stm32_pcie); + + pm_runtime_put_sync(dev); + + stm32_pcie->link_status = STM32_PCIE_EP_LINK_DISABLED; +} + +static void stm32_pcie_perst_deassert(struct dw_pcie *pci) +{ + struct stm32_pcie *stm32_pcie = to_stm32_pcie(pci); + struct device *dev = pci->dev; + struct dw_pcie_ep *ep = &pci->ep; + int ret; + + if (stm32_pcie->link_status == STM32_PCIE_EP_LINK_ENABLED) { + dev_dbg(pci->dev, "Link is already enabled\n"); + return; + } + + dev_dbg(dev, "PERST de-asserted by host. Starting link training\n"); + + ret = pm_runtime_resume_and_get(dev); + if (ret < 0) { + dev_err(dev, "pm runtime resume failed: %d\n", ret); + return; + } + + ret = stm32_pcie_enable_resources(stm32_pcie); + if (ret) { + dev_err(dev, "Failed to enable resources: %d\n", ret); + goto err_pm_put_sync; + } + + ret = dw_pcie_ep_init_registers(ep); + if (ret) { + dev_err(dev, "Failed to complete initialization: %d\n", ret); + goto err_disable_resources; + } + + pci_epc_init_notify(ep->epc); + + ret = stm32_pcie_enable_link(pci); + if (ret) { + dev_err(dev, "PCIe Cannot establish link: %d\n", ret); + goto err_deinit_notify; + } + + stm32_pcie->link_status = STM32_PCIE_EP_LINK_ENABLED; + + return; + +err_deinit_notify: + pci_epc_deinit_notify(ep->epc); + +err_disable_resources: + stm32_pcie_disable_resources(stm32_pcie); + +err_pm_put_sync: + pm_runtime_put_sync(dev); +} + +static irqreturn_t stm32_pcie_ep_perst_irq_thread(int irq, void *data) +{ + struct stm32_pcie *stm32_pcie = data; + struct dw_pcie *pci = &stm32_pcie->pci; + u32 perst; + + perst = gpiod_get_value(stm32_pcie->perst_gpio); + if (perst) + stm32_pcie_perst_assert(pci); + else + stm32_pcie_perst_deassert(pci); + + return IRQ_HANDLED; +} + +static int stm32_add_pcie_ep(struct stm32_pcie *stm32_pcie, + struct platform_device *pdev) +{ + struct dw_pcie_ep *ep = &stm32_pcie->pci.ep; + struct device *dev = &pdev->dev; + int ret; + + ret = pm_runtime_resume_and_get(dev); + if (ret < 0) { + dev_err(dev, "pm runtime resume failed: %d\n", ret); + return ret; + } + + ret = regmap_update_bits(stm32_pcie->regmap, SYSCFG_PCIECR, + STM32MP25_PCIECR_TYPE_MASK, + STM32MP25_PCIECR_EP); + if (ret) { + goto err_pm_put_sync; + return ret; + } + + reset_control_assert(stm32_pcie->rst); + reset_control_deassert(stm32_pcie->rst); + + ep->ops = &stm32_pcie_ep_ops; + + ret = dw_pcie_ep_init(ep); + if (ret) { + dev_err(dev, "failed to initialize ep: %d\n", ret); + goto err_pm_put_sync; + } + + ret = stm32_pcie_enable_resources(stm32_pcie); + if (ret) { + dev_err(dev, "failed to enable resources: %d\n", ret); + goto err_ep_deinit; + } + + ret = dw_pcie_ep_init_registers(ep); + if (ret) { + dev_err(dev, "Failed to initialize DWC endpoint registers\n"); + goto err_disable_resources; + } + + pci_epc_init_notify(ep->epc); + + return 0; + +err_disable_resources: + stm32_pcie_disable_resources(stm32_pcie); + +err_ep_deinit: + dw_pcie_ep_deinit(ep); + +err_pm_put_sync: + pm_runtime_put_sync(dev); + return ret; +} + +static int stm32_pcie_probe(struct platform_device *pdev) +{ + struct stm32_pcie *stm32_pcie; + struct device *dev = &pdev->dev; + int ret; + + stm32_pcie = devm_kzalloc(dev, sizeof(*stm32_pcie), GFP_KERNEL); + if (!stm32_pcie) + return -ENOMEM; + + stm32_pcie->pci.dev = dev; + stm32_pcie->pci.ops = &dw_pcie_ops; + + stm32_pcie->regmap = syscon_regmap_lookup_by_compatible("st,stm32mp25-syscfg"); + if (IS_ERR(stm32_pcie->regmap)) + return dev_err_probe(dev, PTR_ERR(stm32_pcie->regmap), + "No syscfg specified\n"); + + stm32_pcie->phy = devm_phy_get(dev, NULL); + if (IS_ERR(stm32_pcie->phy)) + return dev_err_probe(dev, PTR_ERR(stm32_pcie->phy), + "failed to get pcie-phy\n"); + + stm32_pcie->clk = devm_clk_get(dev, NULL); + if (IS_ERR(stm32_pcie->clk)) + return dev_err_probe(dev, PTR_ERR(stm32_pcie->clk), + "Failed to get PCIe clock source\n"); + + stm32_pcie->rst = devm_reset_control_get_exclusive(dev, NULL); + if (IS_ERR(stm32_pcie->rst)) + return dev_err_probe(dev, PTR_ERR(stm32_pcie->rst), + "Failed to get PCIe reset\n"); + + stm32_pcie->perst_gpio = devm_gpiod_get(dev, "reset", GPIOD_IN); + if (IS_ERR(stm32_pcie->perst_gpio)) + return dev_err_probe(dev, PTR_ERR(stm32_pcie->perst_gpio), + "Failed to get reset GPIO\n"); + + ret = phy_set_mode(stm32_pcie->phy, PHY_MODE_PCIE); + if (ret) + return ret; + + platform_set_drvdata(pdev, stm32_pcie); + + ret = devm_pm_runtime_enable(dev); + if (ret < 0) { + dev_err(dev, "Failed to enable pm runtime %d\n", ret); + return ret; + } + + stm32_pcie->perst_irq = gpiod_to_irq(stm32_pcie->perst_gpio); + + /* Will be enabled in start_link when device is initialized. */ + irq_set_status_flags(stm32_pcie->perst_irq, IRQ_NOAUTOEN); + + ret = devm_request_threaded_irq(dev, stm32_pcie->perst_irq, NULL, + stm32_pcie_ep_perst_irq_thread, + IRQF_TRIGGER_RISING | + IRQF_TRIGGER_FALLING | IRQF_ONESHOT, + "perst_irq", stm32_pcie); + if (ret) { + dev_err(dev, "Failed to request PERST IRQ: %d\n", ret); + return ret; + } + + return stm32_add_pcie_ep(stm32_pcie, pdev); +} + +static void stm32_pcie_remove(struct platform_device *pdev) +{ + struct stm32_pcie *stm32_pcie = platform_get_drvdata(pdev); + struct dw_pcie_ep *ep = &stm32_pcie->pci.ep; + + disable_irq(stm32_pcie->perst_irq); + + dw_pcie_ep_deinit(ep); + + stm32_pcie_disable_resources(stm32_pcie); + + pm_runtime_put_sync(&pdev->dev); +} + +static const struct of_device_id stm32_pcie_ep_of_match[] = { + { .compatible = "st,stm32mp25-pcie-ep" }, + {}, +}; + +static struct platform_driver stm32_pcie_ep_driver = { + .probe = stm32_pcie_probe, + .remove = stm32_pcie_remove, + .driver = { + .name = "stm32-ep-pcie", + .of_match_table = stm32_pcie_ep_of_match, + }, +}; + +module_platform_driver(stm32_pcie_ep_driver); + +MODULE_AUTHOR("Christian Bruel "); +MODULE_DESCRIPTION("STM32MP25 PCIe Endpoint Controller driver"); +MODULE_LICENSE("GPL"); +MODULE_DEVICE_TABLE(of, stm32_pcie_ep_of_match); diff --git a/drivers/pci/controller/dwc/pcie-stm32.h b/drivers/pci/controller/dwc/pcie-stm32.h index 387112c4e42c..09d39f04e469 100644 --- a/drivers/pci/controller/dwc/pcie-stm32.h +++ b/drivers/pci/controller/dwc/pcie-stm32.h @@ -9,6 +9,7 @@ #define to_stm32_pcie(x) dev_get_drvdata((x)->dev) #define STM32MP25_PCIECR_TYPE_MASK GENMASK(11, 8) +#define STM32MP25_PCIECR_EP 0 #define STM32MP25_PCIECR_LTSSM_EN BIT(2) #define STM32MP25_PCIECR_RC BIT(10) From patchwork Tue Mar 25 06:59:31 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Christian Bruel X-Patchwork-Id: 14028152 X-Patchwork-Delegate: kw@linux.com Received: from mx08-00178001.pphosted.com (mx08-00178001.pphosted.com [91.207.212.93]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 8462B21A455; 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Tue, 25 Mar 2025 08:03:03 +0100 (CET) Received: from euls16034.sgp.st.com (euls16034.sgp.st.com [10.75.44.20]) by beta.dmz-ap.st.com (STMicroelectronics) with ESMTP id 7BB9040077; Tue, 25 Mar 2025 08:01:30 +0100 (CET) Received: from Webmail-eu.st.com (shfdag1node3.st.com [10.75.129.71]) by euls16034.sgp.st.com (STMicroelectronics) with ESMTP id A04818518B2; Tue, 25 Mar 2025 08:01:09 +0100 (CET) Received: from localhost (10.130.77.120) by SHFDAG1NODE3.st.com (10.75.129.71) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.39; Tue, 25 Mar 2025 08:01:09 +0100 From: Christian Bruel To: , , , , , , , , , , , , , CC: , , , , , Subject: [PATCH v5 5/9 RESEND] MAINTAINERS: add entry for ST STM32MP25 PCIe drivers Date: Tue, 25 Mar 2025 07:59:31 +0100 Message-ID: <20250325065935.908886-6-christian.bruel@foss.st.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20250325065935.908886-1-christian.bruel@foss.st.com> References: <20250325065935.908886-1-christian.bruel@foss.st.com> Precedence: bulk X-Mailing-List: linux-pci@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-ClientProxiedBy: EQNCAS1NODE4.st.com (10.75.129.82) To SHFDAG1NODE3.st.com (10.75.129.71) X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1093,Hydra:6.0.680,FMLib:17.12.68.34 definitions=2025-03-25_03,2025-03-21_01,2024-11-22_01 Add myself as maintainer of STM32MP25 PCIe host and PCIe endpoint drivers Signed-off-by: Christian Bruel --- MAINTAINERS | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/MAINTAINERS b/MAINTAINERS index 33b9cd11a3a4..d8f2de1a3543 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -18108,6 +18108,13 @@ L: linux-samsung-soc@vger.kernel.org S: Maintained F: drivers/pci/controller/dwc/pci-exynos.c +PCI DRIVER FOR STM32MP25 +M: Christian Bruel +L: linux-pci@vger.kernel.org +S: Maintained +F: Documentation/devicetree/bindings/pci/st,stm32-pcie-*.yaml +F: drivers/pci/controller/dwc/*stm32* + PCI DRIVER FOR SYNOPSYS DESIGNWARE M: Jingoo Han M: Manivannan Sadhasivam From patchwork Tue Mar 25 06:59:32 2025 Content-Type: text/plain; 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}; + pcie_pins_a: pcie-0 { + pins { + pinmux = ; + bias-disable; + }; + }; + + pcie_init_pins_a: pcie-init-0 { + pins { + pinmux = ; + output-low; + }; + }; + + pcie_sleep_pins_a: pcie-sleep-0 { + pins { + pinmux = ; + }; + }; + sdmmc1_b4_pins_a: sdmmc1-b4-0 { pins1 { pinmux = , /* SDMMC1_D0 */ From patchwork Tue Mar 25 06:59:33 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Christian Bruel X-Patchwork-Id: 14028149 X-Patchwork-Delegate: kw@linux.com Received: from mx07-00178001.pphosted.com (mx07-00178001.pphosted.com [185.132.182.106]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id E565B2528E3; Tue, 25 Mar 2025 07:03:25 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=185.132.182.106 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1742886207; cv=none; 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Tue, 25 Mar 2025 08:03:03 +0100 (CET) Received: from euls16034.sgp.st.com (euls16034.sgp.st.com [10.75.44.20]) by beta.dmz-ap.st.com (STMicroelectronics) with ESMTP id 7BD5540079; Tue, 25 Mar 2025 08:01:30 +0100 (CET) Received: from Webmail-eu.st.com (shfdag1node3.st.com [10.75.129.71]) by euls16034.sgp.st.com (STMicroelectronics) with ESMTP id C989E8518B8; Tue, 25 Mar 2025 08:01:13 +0100 (CET) Received: from localhost (10.130.77.120) by SHFDAG1NODE3.st.com (10.75.129.71) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.39; Tue, 25 Mar 2025 08:01:13 +0100 From: Christian Bruel To: , , , , , , , , , , , , , CC: , , , , , Subject: [PATCH v5 7/9 RESEND] arm64: dts: st: Add PCIe Rootcomplex mode on stm32mp251 Date: Tue, 25 Mar 2025 07:59:33 +0100 Message-ID: <20250325065935.908886-8-christian.bruel@foss.st.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20250325065935.908886-1-christian.bruel@foss.st.com> References: <20250325065935.908886-1-christian.bruel@foss.st.com> Precedence: bulk X-Mailing-List: linux-pci@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-ClientProxiedBy: EQNCAS1NODE4.st.com (10.75.129.82) To SHFDAG1NODE3.st.com (10.75.129.71) X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1093,Hydra:6.0.680,FMLib:17.12.68.34 definitions=2025-03-25_03,2025-03-21_01,2024-11-22_01 Add pcie_rc node to support STM32 MP25 PCIe driver based on the DesignWare PCIe core configured as Rootcomplex mode Supports Gen1/Gen2, single lane, MSI interrupts using the ARM GICv2m Signed-off-by: Christian Bruel --- arch/arm64/boot/dts/st/stm32mp251.dtsi | 45 +++++++++++++++++++++++++- 1 file changed, 44 insertions(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/st/stm32mp251.dtsi b/arch/arm64/boot/dts/st/stm32mp251.dtsi index f3c6cdfd7008..a8abb13ab663 100644 --- a/arch/arm64/boot/dts/st/stm32mp251.dtsi +++ b/arch/arm64/boot/dts/st/stm32mp251.dtsi @@ -117,12 +117,20 @@ scmi_vdda18adc: regulator@7 { intc: interrupt-controller@4ac00000 { compatible = "arm,cortex-a7-gic"; #interrupt-cells = <3>; - #address-cells = <1>; + #address-cells = <2>; + #size-cells = <2>; interrupt-controller; reg = <0x0 0x4ac10000 0x0 0x1000>, <0x0 0x4ac20000 0x0 0x2000>, <0x0 0x4ac40000 0x0 0x2000>, <0x0 0x4ac60000 0x0 0x2000>; + ranges; + + v2m0: v2m@48090000 { + compatible = "arm,gic-v2m-frame"; + reg = <0x0 0x48090000 0x0 0x1000>; + msi-controller; + }; }; psci { @@ -900,6 +908,41 @@ stmmac_axi_config_1: stmmac-axi-config { snps,wr_osr_lmt = <0x7>; }; }; + + pcie_rc: pcie@48400000 { + compatible = "st,stm32mp25-pcie-rc"; + device_type = "pci"; + reg = <0x48400000 0x400000>, + <0x10000000 0x10000>; + reg-names = "dbi", "config"; + #interrupt-cells = <1>; + interrupt-map-mask = <0 0 0 7>; + interrupt-map = <0 0 0 1 &intc 0 0 GIC_SPI 264 IRQ_TYPE_LEVEL_HIGH>, + <0 0 0 2 &intc 0 0 GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>, + <0 0 0 3 &intc 0 0 GIC_SPI 266 IRQ_TYPE_LEVEL_HIGH>, + <0 0 0 4 &intc 0 0 GIC_SPI 267 IRQ_TYPE_LEVEL_HIGH>; + #address-cells = <3>; + #size-cells = <2>; + ranges = <0x01000000 0x0 0x00000000 0x10010000 0x0 0x10000>, + <0x02000000 0x0 0x10020000 0x10020000 0x0 0x7fe0000>, + <0x42000000 0x0 0x18000000 0x18000000 0x0 0x8000000>; + dma-ranges = <0x42000000 0x0 0x80000000 0x80000000 0x0 0x80000000>; + clocks = <&rcc CK_BUS_PCIE>; + resets = <&rcc PCIE_R>; + msi-parent = <&v2m0>; + access-controllers = <&rifsc 68>; + power-domains = <&CLUSTER_PD>; + status = "disabled"; + + pcie@0,0 { + device_type = "pci"; + reg = <0x0 0x0 0x0 0x0 0x0>; + phys = <&combophy PHY_TYPE_PCIE>; + #address-cells = <3>; + #size-cells = <2>; + ranges; + }; + }; }; bsec: efuse@44000000 { From patchwork Tue Mar 25 06:59:34 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Christian Bruel X-Patchwork-Id: 14028157 X-Patchwork-Delegate: kw@linux.com Received: from mx07-00178001.pphosted.com (mx07-00178001.pphosted.com [185.132.182.106]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id DFA30253F0E; Tue, 25 Mar 2025 07:04:10 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; 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Tue, 25 Mar 2025 08:03:49 +0100 (CET) Received: from euls16034.sgp.st.com (euls16034.sgp.st.com [10.75.44.20]) by beta.dmz-ap.st.com (STMicroelectronics) with ESMTP id 469A540069; Tue, 25 Mar 2025 08:02:29 +0100 (CET) Received: from Webmail-eu.st.com (shfdag1node3.st.com [10.75.129.71]) by euls16034.sgp.st.com (STMicroelectronics) with ESMTP id B57D482D10A; Tue, 25 Mar 2025 08:01:16 +0100 (CET) Received: from localhost (10.130.77.120) by SHFDAG1NODE3.st.com (10.75.129.71) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.39; Tue, 25 Mar 2025 08:01:16 +0100 From: Christian Bruel To: , , , , , , , , , , , , , CC: , , , , , Subject: [PATCH v5 8/9 RESEND] arm64: dts: st: Add PCIe Endpoint mode on stm32mp251 Date: Tue, 25 Mar 2025 07:59:34 +0100 Message-ID: <20250325065935.908886-9-christian.bruel@foss.st.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20250325065935.908886-1-christian.bruel@foss.st.com> References: <20250325065935.908886-1-christian.bruel@foss.st.com> Precedence: bulk X-Mailing-List: linux-pci@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-ClientProxiedBy: EQNCAS1NODE4.st.com (10.75.129.82) To SHFDAG1NODE3.st.com (10.75.129.71) X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1093,Hydra:6.0.680,FMLib:17.12.68.34 definitions=2025-03-25_03,2025-03-21_01,2024-11-22_01 Add pcie_ep node to support STM32 MP25 PCIe driver based on the DesignWare PCIe core configured as Endpoint mode Signed-off-by: Christian Bruel --- arch/arm64/boot/dts/st/stm32mp251.dtsi | 13 +++++++++++++ 1 file changed, 13 insertions(+) diff --git a/arch/arm64/boot/dts/st/stm32mp251.dtsi b/arch/arm64/boot/dts/st/stm32mp251.dtsi index a8abb13ab663..fe73161ed0d4 100644 --- a/arch/arm64/boot/dts/st/stm32mp251.dtsi +++ b/arch/arm64/boot/dts/st/stm32mp251.dtsi @@ -909,6 +909,19 @@ stmmac_axi_config_1: stmmac-axi-config { }; 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Tue, 25 Mar 2025 08:03:30 +0100 (CET) Received: from euls16034.sgp.st.com (euls16034.sgp.st.com [10.75.44.20]) by beta.dmz-ap.st.com (STMicroelectronics) with ESMTP id 8217540067; Tue, 25 Mar 2025 08:02:14 +0100 (CET) Received: from Webmail-eu.st.com (shfdag1node3.st.com [10.75.129.71]) by euls16034.sgp.st.com (STMicroelectronics) with ESMTP id 134FD846556; Tue, 25 Mar 2025 08:01:19 +0100 (CET) Received: from localhost (10.130.77.120) by SHFDAG1NODE3.st.com (10.75.129.71) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.39; Tue, 25 Mar 2025 08:01:18 +0100 From: Christian Bruel To: , , , , , , , , , , , , , CC: , , , , , Subject: [PATCH v5 9/9 RESEND] arm64: dts: st: Enable PCIe on the stm32mp257f-ev1 board Date: Tue, 25 Mar 2025 07:59:35 +0100 Message-ID: <20250325065935.908886-10-christian.bruel@foss.st.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20250325065935.908886-1-christian.bruel@foss.st.com> References: <20250325065935.908886-1-christian.bruel@foss.st.com> Precedence: bulk X-Mailing-List: linux-pci@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-ClientProxiedBy: EQNCAS1NODE4.st.com (10.75.129.82) To SHFDAG1NODE3.st.com (10.75.129.71) X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1093,Hydra:6.0.680,FMLib:17.12.68.34 definitions=2025-03-25_03,2025-03-21_01,2024-11-22_01 Add PCIe RC and EP support on stm32mp257f-ev1 board. Default to RC mode. Signed-off-by: Christian Bruel --- arch/arm64/boot/dts/st/stm32mp257f-ev1.dts | 21 +++++++++++++++++++++ 1 file changed, 21 insertions(+) diff --git a/arch/arm64/boot/dts/st/stm32mp257f-ev1.dts b/arch/arm64/boot/dts/st/stm32mp257f-ev1.dts index 1b88485a62a1..a7646503d6b2 100644 --- a/arch/arm64/boot/dts/st/stm32mp257f-ev1.dts +++ b/arch/arm64/boot/dts/st/stm32mp257f-ev1.dts @@ -225,6 +225,27 @@ scmi_vdd_sdcard: regulator@23 { }; }; +&pcie_ep { + pinctrl-names = "default", "init"; + pinctrl-0 = <&pcie_pins_a>; + pinctrl-1 = <&pcie_init_pins_a>; + reset-gpios = <&gpioj 8 GPIO_ACTIVE_LOW>; + status = "disabled"; +}; + +&pcie_rc { + pinctrl-names = "default", "init", "sleep"; + pinctrl-0 = <&pcie_pins_a>; + pinctrl-1 = <&pcie_init_pins_a>; + pinctrl-2 = <&pcie_sleep_pins_a>; + status = "okay"; + + pcie@0,0 { + reset-gpios = <&gpioj 8 GPIO_ACTIVE_LOW>; + wake-gpios = <&gpioh 5 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>; + }; +}; + &sdmmc1 { pinctrl-names = "default", "opendrain", "sleep"; pinctrl-0 = <&sdmmc1_b4_pins_a>;