From patchwork Wed Mar 26 17:59:07 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Alexandre Ghiti X-Patchwork-Id: 14030438 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 3ECA4C3600E for ; Wed, 26 Mar 2025 18:00:34 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender:Content-Type: Content-Transfer-Encoding:List-Subscribe:List-Help:List-Post:List-Archive: List-Unsubscribe:List-Id:Subject:From:To:MIME-Version:Date:Message-ID: Reply-To:Cc:Content-ID:Content-Description:Resent-Date:Resent-From: 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+0000 (UTC) Message-ID: Date: Wed, 26 Mar 2025 18:59:07 +0100 MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Content-Language: en-US To: Palmer Dabbelt , "linux-riscv@lists.infradead.org" From: Alexandre Ghiti Subject: [GIT PULL] RISC-V Patches for the 6.15 Merge Window, Part 1 X-GND-State: clean X-GND-Score: -100 X-GND-Cause: gggruggvucftvghtrhhoucdtuddrgeefvddrtddtgdduieeiudelucetufdoteggodetrfdotffvucfrrhhofhhilhgvmecuifetpfffkfdpucggtfgfnhhsuhgsshgtrhhisggvnecuuegrihhlohhuthemuceftddunecusecvtfgvtghiphhivghnthhsucdlqddutddtmdenucfjughrpefkffggfgfvhffutgfgsehtkeertddtvdejnecuhfhrohhmpeetlhgvgigrnhgurhgvucfihhhithhiuceorghlvgigsehghhhithhirdhfrheqnecuggftrfgrthhtvghrnhepvdelveekvdfhgeelieejhfetgeduteekhfeuheffjeduiefgtdfgtdeltdeftddunecuffhomhgrihhnpehkvghrnhgvlhdrohhrghdpghhithhhuhgsrdgtohhmpdhtshdrnhgvthenucfkphepvddttddumeekiedumeeffeekvdemvghfledtmegvlehfugemfedvkeelmegsuddufhemjeefleenucevlhhushhtvghrufhiiigvpedtnecurfgrrhgrmhepihhnvghtpedvtddtudemkeeiudemfeefkedvmegvfheltdemvgelfhgumeefvdekleemsgduudhfmeejfeelpdhhvghloheplgfkrfggieemvddttddumeekiedumeeffeekvdemvghfledtmegvlehfugemfedvkeelmegsuddufhemjeeflegnpdhmrghilhhfrhhomheprghlvgigsehghhhithhirdhfrhdpnhgspghrtghpthhtohepvddprhgtphhtthhopehprghlmhgvrhesuggrsggsvghlthdrtghomhdprhgtphhtthhopehlihhnuhigqdhrihhstghvsehlihhsthhsrdhinhhfr hgruggvrggurdhorhhg X-GND-Sasl: alex@ghiti.fr X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20250326_105914_265850_CD615243 X-CRM114-Status: GOOD ( 15.15 ) X-BeenThere: linux-riscv@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-riscv" Errors-To: linux-riscv-bounces+linux-riscv=archiver.kernel.org@lists.infradead.org The following changes since commit 4701f33a10702d5fc577c32434eb62adde0a1ae1:   Linux 6.14-rc7 (2025-03-16 12:55:17 -1000) are available in the Git repository at:   git://git.kernel.org/pub/scm/linux/kernel/git/alexghiti/linux tags/riscv-mw1-6.15-rc1 for you to fetch changes up to 74f4bf9d15ad1d6862b828d486ed10ea0e874a23:   Merge patch series "riscv: Add runtime constant support" (2025-03-20 09:15:04 +0000) ---------------------------------------------------------------- riscv patches for 6.15-rc1 * A bunch of fixes:   - We were missing a secondary mmu notifier call when flushing the tlb which is required for IOMMU   - Fix ftrace panics by saving the registers as expected by ftrace   - Fix a couple of stimecmp usage related to cpu hotplug   - Fix a bunch of issues in the misaligned probing handling * Perf improvements:   - Introduce support for runtime constant improving perf of d_hash()   - Add support for huge pfnmaps to improve tlb utilization   - Use Zawrs to improve smp_cond_load8/16() used by the queued spinlocks * Hwprobe additions:   - Add support for Zicntr and Zihpm   - Add support for Zaamo and Zalrsc   - Add support for bfloat16 extensiosn   - Add support for Zicbom (only enabling clean and flush, not inval for security reasons) * Misc:   - Add a kernel parameter to bypass the misaligned speed probing since we can't rely on Zicclsm ---------------------------------------------------------------- All the patches have been tested on our github CI and no regressions were found against 6.14-rc7 (https://github.com/linux-riscv/linux/pull/198/checks whose results can be seen here https://mazarinen.tail1c623.ts.net/riscv-linux/linux-all/build/riscv-mw1-6.15-rc1/). ---------------------------------------------------------------- Alexandre Ghiti (8):       Merge patch series "RISC-V: clarify what some RISCV_ISA* config options do & redo Zbb toolchain dependency"       riscv: Call secondary mmu notifier when flushing the tlb       Merge patch series "riscv: Add bfloat16 instruction support"       Merge patch series "Support SSTC while PM operations"       riscv: Fix missing __free_pages() in check_vector_unaligned_access()       Merge patch series "riscv: add support for Zaamo and Zalrsc extensions"       Merge patch series "riscv: Unaligned access speed probing fixes and skipping"       Merge patch series "riscv: Add runtime constant support" Andrew Bresticker (1):       riscv: Support huge pfnmaps Andrew Jones (8):       riscv: Annotate unaligned access init functions       riscv: Fix riscv_online_cpu_vec       riscv: Fix check_unaligned_access_all_cpus       riscv: Change check_unaligned_access_speed_all_cpus to void       riscv: Fix set up of cpu hotplug callbacks       riscv: Fix set up of vector cpu hotplug callback       riscv: Add parameter for skipping access speed tests       Documentation/kernel-parameters: Add riscv unaligned speed parameters Charlie Jenkins (3):       riscv: tracing: Fix __write_overflow_field in ftrace_partial_regs()       riscv: Move nop definition to insn-def.h       riscv: Add runtime constant support Chin Yik Ming (2):       riscv: Simplify base extension checks and direct boolean return       riscv: Fix a comment typo in set_mm_asid() Clément Léger (6):       riscv: remove useless pc check in stacktrace handling       dt-bindings: riscv: add Zaamo and Zalrsc ISA extension description       riscv: add parsing for Zaamo and Zalrsc extensions       riscv: hwprobe: export Zaamo and Zalrsc extensions       RISC-V: KVM: Allow Zaamo/Zalrsc extensions for Guest/VM       KVM: riscv: selftests: Add Zaamo/Zalrsc extensions to get-reg-list test Conor Dooley (2):       RISC-V: clarify what some RISCV_ISA* config options do       RISC-V: separate Zbb optimisations requiring and not requiring toolchain support Geert Uytterhoeven (2):       riscv: defconfig: Disable Renesas SoC support       riscv: Remove duplicate CLINT_TIMER selections Guo Ren (1):       riscv: Implement smp_cond_load8/16() with Zawrs Inochi Amaoto (3):       dt-bindings: riscv: add bfloat16 ISA extension description       riscv: add ISA extension parsing for bfloat16 ISA extension       riscv: hwprobe: export bfloat16 ISA extension Jinjie Ruan (1):       riscv: Remove unused TASK_TI_FLAGS Juhan Jin (1):       riscv: ftrace: Add parentheses in macro definitions of make_call_t0 and make_call_ra Masahiro Yamada (1):       riscv: migrate to the generic rule for built-in DTB Miquel Sabaté Solà (1):       riscv: hwprobe: export Zicntr and Zihpm extensions Nick Hu (2):       riscv: Add stimecmp save and restore       clocksource/drivers/timer-riscv: Stop stimecmp when cpu hotplug Pu Lehui (2):       riscv: fgraph: Select HAVE_FUNCTION_GRAPH_TRACER depends on HAVE_DYNAMIC_FTRACE_WITH_ARGS       riscv: fgraph: Fix stack layout to match __arch_ftrace_regs argument of ftrace_return_to_handler Thomas Weißschuh (1):       riscv: mm: Don't use %pK through printk Tingbo Liao (1):       riscv: Fix the __riscv_copy_vec_words_unaligned implementation Yunhui Cui (3):       RISC-V: Enable cbo.clean/flush in usermode       RISC-V: hwprobe: Expose Zicbom extension and its block size       RISC-V: selftests: Add TEST_ZICBOM into CBO tests Zixian Zeng (1):       riscv: remove redundant CMDLINE_FORCE check  Documentation/admin-guide/kernel-parameters.txt         |  16 ++++  Documentation/arch/riscv/hwprobe.rst                    |  32 +++++++  Documentation/devicetree/bindings/riscv/extensions.yaml |  64 ++++++++++++++  arch/riscv/Kbuild                                       |   1 -  arch/riscv/Kconfig                                      |  66 +++++++++-----  arch/riscv/Kconfig.socs                                 |   2 -  arch/riscv/boot/dts/Makefile                            |   2 -  arch/riscv/configs/defconfig                            |   2 -  arch/riscv/configs/nommu_k210_defconfig                 |   2 +-  arch/riscv/configs/nommu_k210_sdcard_defconfig          |   2 +-  arch/riscv/include/asm/arch_hweight.h                   |   6 +-  arch/riscv/include/asm/asm.h                            |   1 +  arch/riscv/include/asm/bitops.h                         |   4 +-  arch/riscv/include/asm/checksum.h                       |   3 +-  arch/riscv/include/asm/cmpxchg.h                        |  38 +++++++-  arch/riscv/include/asm/cpufeature.h                     |   4 +-  arch/riscv/include/asm/ftrace.h                         |   7 +-  arch/riscv/include/asm/hwcap.h                          |   5 ++  arch/riscv/include/asm/hwprobe.h                        |   2 +-  arch/riscv/include/asm/insn-def.h                       |   3 +  arch/riscv/include/asm/pgtable.h                        |  49 ++++++++++  arch/riscv/include/asm/ptrace.h                         |  18 ++--  arch/riscv/include/asm/runtime-const.h                  | 265 +++++++++++++++++++++++++++++++++++++++++++++++++++++++  arch/riscv/include/asm/suspend.h                        |   4 +  arch/riscv/include/uapi/asm/hwprobe.h                   |   9 ++  arch/riscv/include/uapi/asm/kvm.h                       |   2 +  arch/riscv/kernel/asm-offsets.c                         |   1 -  arch/riscv/kernel/cpufeature.c                          |  58 ++++++++++--  arch/riscv/kernel/ftrace.c                              |   6 +-  arch/riscv/kernel/jump_label.c                          |   4 +-  arch/riscv/kernel/mcount.S                              |  24 +++--  arch/riscv/kernel/setup.c                               |   5 --  arch/riscv/kernel/stacktrace.c                          |   2 +-  arch/riscv/kernel/suspend.c                             |  14 +++  arch/riscv/kernel/sys_hwprobe.c                         |  15 +++-  arch/riscv/kernel/traps_misaligned.c                    |  14 +--  arch/riscv/kernel/unaligned_access_speed.c              | 242 +++++++++++++++++++++++++++++++-------------------  arch/riscv/kernel/vec-copy-unaligned.S                  |   2 +-  arch/riscv/kernel/vendor_extensions.c                   |   2 +-  arch/riscv/kernel/vmlinux.lds.S                         |   3 +  arch/riscv/kvm/vcpu_onereg.c                            |   4 +  arch/riscv/lib/csum.c                                   |  21 +----  arch/riscv/lib/strcmp.S                                 |   5 +-  arch/riscv/lib/strlen.S                                 |   5 +-  arch/riscv/lib/strncmp.S                                |   5 +-  arch/riscv/mm/context.c                                 |   2 +-  arch/riscv/mm/physaddr.c                                |   2 +-  arch/riscv/mm/tlbflush.c                                |  37 ++++----  drivers/clocksource/timer-riscv.c                       |   6 ++  tools/testing/selftests/kvm/riscv/get-reg-list.c        |   8 ++  tools/testing/selftests/riscv/hwprobe/cbo.c             |  66 +++++++++++---  51 files changed, 921 insertions(+), 241 deletions(-)  create mode 100644 arch/riscv/include/asm/runtime-const.h