From patchwork Fri Mar 28 20:01:00 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Prabhakar X-Patchwork-Id: 14032387 X-Patchwork-Delegate: geert@linux-m68k.org Received: from mail-wm1-f46.google.com (mail-wm1-f46.google.com [209.85.128.46]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 1D1901E4B2; Fri, 28 Mar 2025 20:01:25 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.128.46 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1743192087; cv=none; b=eTKReSp0AxBlq51MpJXTZBJ6F1AoDbPylyQBN/da1WMcJlcMU9uNT9HATokb7b1hzoCnraoIq6OCJsroQEx0g8Lbquh+pzxAFJeAV5zPigZHyLcdG1O4NUmSJjjD1+oD60gQtP4KyOESIuT5ZeRzeiuEr6/7Pje6FvFexnKIt+o= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1743192087; c=relaxed/simple; bh=Eo/kZKrGoIM5TsgQ95VKZ8ZUDiJtVk3sj55ctQ/M2Yw=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=i1CrusQhdI3bxeK4eae5Pgibn+xI7YSxR9n4yFsMXTOpM1hq7cVaQ3Hq+2h5hjUItlvQvryUghOAIaCfdddy7GoNnMg0y5pQAVFUhLBpRMmuUJ5io1OJNGsXgngXjm8tayPfkUCV4qfgbJf7bQZKaYRXvm97kdqR9ewmX+hWc5I= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com; spf=pass smtp.mailfrom=gmail.com; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b=hKcjPVy4; arc=none smtp.client-ip=209.85.128.46 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=gmail.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="hKcjPVy4" Received: by mail-wm1-f46.google.com with SMTP id 5b1f17b1804b1-43948f77f1aso18776845e9.0; Fri, 28 Mar 2025 13:01:25 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20230601; t=1743192084; x=1743796884; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=d+pekbS4NUAwvKZ/B2b86T/+AEj63RVTJfey6aPBmu0=; b=hKcjPVy4d4MYQlTt/veRIlozGPIFnoCfWWiuiUjh9G1kt0A+L1lY0FNn1c7AFwF8Vr w/PtxwaMp6NYnihNo1/ZDyskByVir9Q6Ei5W/Ta6akqzCU19gkbKf45jrAhyyaVNnrlR 6UEuM4/0GuwVlGAQmIH8H4TFztk1nhj/g+nR7sfFQkKedP7FMA/gPwjaNnz2ul/N3VL7 Vs+ML3fC8De/myYTuHJWGVTXBeMO9DkrpyRSFqqSbBSKbq/b60yofztsoKXP+ABk8DCl zDfuClil7L3d2shHzwTvuiVNXy985j538eHp+7h0Ae7DJ1XFO7h+ox7Is5gt88yKL58G iKZQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1743192084; x=1743796884; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=d+pekbS4NUAwvKZ/B2b86T/+AEj63RVTJfey6aPBmu0=; b=qnNVm+vmrtIqTnAqrEaWXMlmzSsTlnf3jJjE7jVI7fHzO2ELcxkOws/L4Y41lDeJrb q8HtxtZfBagHg685g8fKWdEx+atJ5OrGTY5bpsNZY91ajjw8lYmXtLBe60o0amfXWxTO 3KJFEXnUDLUt3H1puMwq89nvqAwg5+lcCpu4Neaa1ubBHWU4shQOQLtuDguznsZMHGeo 7iJ151G8f6kyYfMpSNLXVLinV9hQ5b47yEoK3CCxXyqZNXOZwsKsq4Jp1P9POXjMomrD hBJmED5gjZmHlTKjDd0/rKBBjoItMkDQkXEW6jjzJc7Zoe47TDeTCtMns0zo2xI+U8qH wY0w== X-Forwarded-Encrypted: i=1; AJvYcCUjoE6zvAK/OZbK4PsCA+ouNatyROKxhFYwKJRu0xHCBLFO0b1i5mXfpXktG7KipCJskraXq6LqcQTtMVzK@vger.kernel.org, AJvYcCV19xnAyNMFprUrK2evP19YS/r2RnschBgZ4UY6oJy5iJlmFNtHIF7hF/X+WpfC4ijlJvCevL13W01+@vger.kernel.org, AJvYcCVT5GQ9+C9awtGeh9rM+ENWTkRSw8SJwywUW9+Q1rzilionTO/WxxaA/byo4v99mIP9wytVwPudgoYG@vger.kernel.org X-Gm-Message-State: AOJu0YxNH2tZDnOiEVcRkqzfE+uA3qfcg834P41VefLuw3lacV9F8fO9 2XtVXglRtgEWDIiL5/+X3wK8lSO7QvFpBAS9cvD9NqeL7ecD7u5K X-Gm-Gg: ASbGncu8mniZO6yfafmdMrONzDYTFpBnCGJbCHJGVrB/ojYsQHVhLWpNvoSSt7b4iQX xbGJjPVB7q5xx+chjwKW/8iF/GP8S+6cdHLz+u86PW3a5fgUYjsIxR+CevqQlDCvN11QOBpQAvk fpvMWhKxKyZl+qClKMfaohJ+6D+YeMofcYA7CbpRYsRupsjMn2MgA83VQOQuopmIrm3hcCnNVQe Z24WLf0OB1P6mr+C2KGK3YlGaoEKL3L1X1TDtSwdeWDDt7rJVz3FGRJuvTkR0ZYB9brzRs/njuf TNC/jRg8ENqzvBRMe4giD53fAoqy1vWrWLQ/MB9LsnI/3swrsLR31f3PwKSGqkV0o6g= X-Google-Smtp-Source: AGHT+IGmgizPS2RnWbTyUkoC72rOm6aUF2e0C9ZsoUGNIGl2gGKujUEebhImgal58dcp4kgvf+TWmA== X-Received: by 2002:a05:600c:8718:b0:43c:e8ca:5140 with SMTP id 5b1f17b1804b1-43db62bcfeemr7260845e9.23.1743192084074; Fri, 28 Mar 2025 13:01:24 -0700 (PDT) Received: from iku.Home ([2a06:5906:61b:2d00:b400:d08:873:badd]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-43d8fcceaaasm37930955e9.18.2025.03.28.13.01.22 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 28 Mar 2025 13:01:22 -0700 (PDT) From: Prabhakar X-Google-Original-From: Prabhakar To: Geert Uytterhoeven , Michael Turquette , Stephen Boyd , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Magnus Damm Cc: linux-renesas-soc@vger.kernel.org, linux-clk@vger.kernel.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, Prabhakar , Biju Das , Fabrizio Castro , Lad Prabhakar Subject: [PATCH 1/6] clk: renesas: rzv2h-cpg: Use str_on_off() helper in rzv2h_mod_clock_endisable() Date: Fri, 28 Mar 2025 20:01:00 +0000 Message-ID: <20250328200105.176129-2-prabhakar.mahadev-lad.rj@bp.renesas.com> X-Mailer: git-send-email 2.49.0 In-Reply-To: <20250328200105.176129-1-prabhakar.mahadev-lad.rj@bp.renesas.com> References: <20250328200105.176129-1-prabhakar.mahadev-lad.rj@bp.renesas.com> Precedence: bulk X-Mailing-List: linux-renesas-soc@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 From: Lad Prabhakar Replace hard-coded "ON"/"OFF" strings with the `str_on_off()` helper in `rzv2h_mod_clock_endisable()`. Signed-off-by: Lad Prabhakar --- drivers/clk/renesas/rzv2h-cpg.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/drivers/clk/renesas/rzv2h-cpg.c b/drivers/clk/renesas/rzv2h-cpg.c index 4123c30e8663..817a39a8b852 100644 --- a/drivers/clk/renesas/rzv2h-cpg.c +++ b/drivers/clk/renesas/rzv2h-cpg.c @@ -25,6 +25,7 @@ #include #include #include +#include #include @@ -595,7 +596,7 @@ static int rzv2h_mod_clock_endisable(struct clk_hw *hw, bool enable) int error; dev_dbg(dev, "CLK_ON 0x%x/%pC %s\n", reg, hw->clk, - enable ? "ON" : "OFF"); + str_on_off(enable)); if (enabled == enable) return 0; From patchwork Fri Mar 28 20:01:01 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Prabhakar X-Patchwork-Id: 14032388 X-Patchwork-Delegate: geert@linux-m68k.org Received: from mail-wm1-f44.google.com (mail-wm1-f44.google.com [209.85.128.44]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 812201E5B8A; Fri, 28 Mar 2025 20:01:27 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.128.44 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1743192089; cv=none; b=J9HWfkjWATNiAOvKsJ8Q6iAh+TD3axX10fDpYC3XmMpr+XapfBywTT6lfwe9cuYF+0xu5WagAj0Y7uMCcXZrriZ0Z87xO3Y3IFeNdWnqyTMk9oJkkwvM8Bvzp7r0LgLOYa3+DLhdsOVWpC585sipak6HP0TrzXLQcxpP7Ef0/8I= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1743192089; c=relaxed/simple; bh=EOt9wuuZK6W8vqCix7SORy9aWHy2qg1evhD52MrTK+I=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=dI6Qk4/UCAEpmPoDDYX3XosSw2hDUZR16NT5aUyrLiup8JrXdRFqSsziLOeDOl+M19LYz3AMer3Yy4JBAoCZ1PWRvP3uPLST0iGKXkFt/B9TBkVLSwnm1oGs665O0guhgHNJebdHPosh8o6xFaWnnSfLVT6lDZ/co7K97vBpG58= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com; spf=pass smtp.mailfrom=gmail.com; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b=DdwOutjC; arc=none smtp.client-ip=209.85.128.44 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=gmail.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="DdwOutjC" Received: by mail-wm1-f44.google.com with SMTP id 5b1f17b1804b1-43ce70f9afbso26228625e9.0; Fri, 28 Mar 2025 13:01:27 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20230601; t=1743192086; x=1743796886; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=83yLDflhQJMa0Il0PHNLhFSDSzsmuN8I1PiBktowvoY=; b=DdwOutjCNiAaW/SK62m/kODyO+2onuXPr7Yxr7+TwWUV2IlGEVGTTUgtLYID6AfufS HqVFSaeYvEFeWdHQgeDMKiHAqsiSbmtIvh8pBYML9FWccpZsC2zgyArbSLWxYyuuWdol C2NWkHuNgz/wBtyQ7Za8ealOooLGJyS83sH4dC3kRD52Oscq15K7rMEjDYQALejQrKIk 6NIq0sYFwfNTTYDVPLtAfKjO/Zb5BJbpMsXkAMIfxl1zc04LX5+BKxjePztTCKYBboTI /lFAPM3lajfuuEIngsxVJbmCCqaGtpAD3yh+hYWkQTMZGWMSPwhk02o3ozKfS292HavR JKmA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1743192086; x=1743796886; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=83yLDflhQJMa0Il0PHNLhFSDSzsmuN8I1PiBktowvoY=; b=M0rc6lUuDB3+V+dsQII7UuaoABFOMpkQZbtO6JGVK4jJfwAdRaGIsEcGE0QSnDYpbs KfIvdYf2eL3x/8nBumRsZlqxVXhkJvb8llGh6T7PUhzwfW7gjtQurJWembYbSPYK19LR pRemjwuVO0R0y9JZH2X0ObEBRlRTqlLGk7g+Y76aTLazX8DL0+c6t5f93Fah9JnIVGi4 NlafhACzvqPdS5DYjIhYQrcs9OqxaK/XtIcBDGza0o39ezoEL9NqgwptN1XHEPRE9BQ7 y2kyOBLNTOyuyK2L0FKDlBpN2s6rK3sm3Qs2enL626qbZyrdWuvIj3NRFjHLgqrcHTVf 2f9g== X-Forwarded-Encrypted: i=1; AJvYcCV6SSJvAYUZ/QfEbOo49nf8KFWi3HGD7H5IlvZNsuHydA3kk37xY8ZrFG2ijBPJaDhzQ5eORDxccBHhGeaT@vger.kernel.org, AJvYcCVjb9gv8VhAOq9fF+ovNcJiVHxgtZjZcBlTNX9itEZiKEqH5qKBre49qUAKvp7chTKmtBPSA1TsUNwR@vger.kernel.org, AJvYcCVuOm8G61I6RZ9QnyzpWs5SMCGm5GBInMj7sFOY/uJpHnmquaJ2Ovoye47RXkS9jwDXgpQjoGmSDHAs@vger.kernel.org X-Gm-Message-State: AOJu0YyhFs+HED5evMgfnvtyvQJtvZNcTEK8HLHIlauToB097gAbZM5b aERz931yy6skpooQUMbbq9Y1jv+0YaSXLyfylDXF1fdha8M7Pwcs X-Gm-Gg: ASbGncvENBbCYdgjiJs2MgxXGuGwBNlyd+XylLwq0RXDRG7gtwbT0NzfvMJlq6V4dW3 /6DK/AdepEQOU/L1Hj33QZpcxD8w5r1IrmSflPRY3HI79/WqaUBndXuGx6jXB6qoIlVh3+pCmea G9me+SdINxXmL+PjCxQGnKKeMEU/4rLWpkOS+9/vNXXj94UwdiX+lhQ6onj/MhfYum0OI3UuBDR jFCh8aSItENEhnObKWFUBqT9a8OXnd8qTxS0kEvhCJ7ni5V5bmYRa8xmb2HBA7m6hUOXIS+Tooc +vk3zVec1zwKsA+MTzk7kJ6m+kqgg37+Fd2HWq+eFCYQFOuamJnSRqIsJU3T6QvObs4= X-Google-Smtp-Source: AGHT+IGdvWPjGRRZkpllB0l9l5LllyjpxfzuTntQJdvxYuJ6vO1cowSkPSZcoIxKQkmtIviomxCRYA== X-Received: by 2002:a05:600c:3b9d:b0:43c:ebc4:36a5 with SMTP id 5b1f17b1804b1-43db6222078mr7385835e9.7.1743192085314; Fri, 28 Mar 2025 13:01:25 -0700 (PDT) Received: from iku.Home ([2a06:5906:61b:2d00:b400:d08:873:badd]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-43d8fcceaaasm37930955e9.18.2025.03.28.13.01.24 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 28 Mar 2025 13:01:24 -0700 (PDT) From: Prabhakar X-Google-Original-From: Prabhakar To: Geert Uytterhoeven , Michael Turquette , Stephen Boyd , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Magnus Damm Cc: linux-renesas-soc@vger.kernel.org, linux-clk@vger.kernel.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, Prabhakar , Biju Das , Fabrizio Castro , Lad Prabhakar Subject: [PATCH 2/6] clk: renesas: rzv2h-cpg: Use both CLK_ON and CLK_MON bits for clock state validation Date: Fri, 28 Mar 2025 20:01:01 +0000 Message-ID: <20250328200105.176129-3-prabhakar.mahadev-lad.rj@bp.renesas.com> X-Mailer: git-send-email 2.49.0 In-Reply-To: <20250328200105.176129-1-prabhakar.mahadev-lad.rj@bp.renesas.com> References: <20250328200105.176129-1-prabhakar.mahadev-lad.rj@bp.renesas.com> Precedence: bulk X-Mailing-List: linux-renesas-soc@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 From: Lad Prabhakar Update the clock enable/disable logic to follow the latest hardware manual's guidelines, ensuring that both CLK_ON and CLK_MON bits are used to confirm the clock state. According to the manual, enabling a clock requires setting the CPG_CLK_ON bit and verifying the clock has started using the CPG_CLK_MON bit. Similarly, disabling a clock requires clearing the CPG_CLK_ON bit and confirming the clock has stopped via the CPG_CLK_MON bit. Modify `rzv2h_mod_clock_is_enabled()` to check CLK_MON first and then validate CLK_ON for a more accurate clock status evaluation. Signed-off-by: Lad Prabhakar --- drivers/clk/renesas/rzv2h-cpg.c | 9 ++++++--- 1 file changed, 6 insertions(+), 3 deletions(-) diff --git a/drivers/clk/renesas/rzv2h-cpg.c b/drivers/clk/renesas/rzv2h-cpg.c index 817a39a8b852..dec97f731e3a 100644 --- a/drivers/clk/renesas/rzv2h-cpg.c +++ b/drivers/clk/renesas/rzv2h-cpg.c @@ -576,11 +576,14 @@ static int rzv2h_mod_clock_is_enabled(struct clk_hw *hw) if (clock->mon_index >= 0) { offset = GET_CLK_MON_OFFSET(clock->mon_index); bitmask = BIT(clock->mon_bit); - } else { - offset = GET_CLK_ON_OFFSET(clock->on_index); - bitmask = BIT(clock->on_bit); + + if (!(readl(priv->base + offset) & bitmask)) + return 0; } + offset = GET_CLK_ON_OFFSET(clock->on_index); + bitmask = BIT(clock->on_bit); + return readl(priv->base + offset) & bitmask; } From patchwork Fri Mar 28 20:01:02 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Prabhakar X-Patchwork-Id: 14032389 X-Patchwork-Delegate: geert@linux-m68k.org Received: from mail-wm1-f44.google.com (mail-wm1-f44.google.com [209.85.128.44]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 712B01E98F8; Fri, 28 Mar 2025 20:01:28 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.128.44 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1743192090; cv=none; b=GOws51c3A9I3xpYlb3nVO1eIke+Mj05klIgudZThwA8268sejLzUH9W80EMYdJDaxEoWcxzS5JT6LFAlBwmzBaRFi2XyL/nPNYZwecojcxQxWFHUwzAnlxipi8lNVoOt1nDShZEX1/iacX3dV2OmfxMz61IsQEOdjtkMJBRz5zw= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1743192090; c=relaxed/simple; bh=Jy25g5ku5K05bnFAmVpuZgxFbixeJ/5lwipk6/jdG2k=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=N1HoXGSYvRn0xjJpAGe315R9P/jKZEdnVzHPU4swEIWH0ie7m7pKkw71RbmQfomHx+t5VEKBX/thmyh+/anIwxF1aAWV7oDeOC9TlSSvIrJ7kpdQt+QQcDVNuMCikOH45qpqgRbOOw/PXcGp8XDSln4nmR5bbK0TWJcjQWLO544= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com; spf=pass smtp.mailfrom=gmail.com; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b=QdrjEhcS; arc=none smtp.client-ip=209.85.128.44 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=gmail.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="QdrjEhcS" Received: by mail-wm1-f44.google.com with SMTP id 5b1f17b1804b1-43cf05f0c3eso18455405e9.0; Fri, 28 Mar 2025 13:01:28 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20230601; t=1743192087; x=1743796887; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=V3jeUZRmxaWjIp3nx3IiMr1zlX1ebkwMyBUYGf/OK98=; b=QdrjEhcSS1OiLSXrOlwJSzL3z7Z+tn1xA26sd9LBrIdA6FHHYomFN6MP5hX71yVi6E TiHDwR6iy22gLuveQJY/w+fqZr1qAxgwhPIdQBrV44xNCF2uvl6Mf9QG62UUmwhJwafL ena+wfdlTGijh/uetPF8YPRUejTLSLd4HrXdITus82vTuBpe4IVFhJI1ihyWBeAW3Fna vT1XtBCz7egg2KIE2TnaWgdx6MT7sONjv1IS1RlT88Gs96UzDajQuEPyysicekf/qzbi d0UdmLLhIfSn/vi9DweH2vZ0lkjSF3znRumh2DJuIHJrlgg0DVQ1dL96TANIaV1UaC24 XFlQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1743192087; x=1743796887; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=V3jeUZRmxaWjIp3nx3IiMr1zlX1ebkwMyBUYGf/OK98=; b=lffY7UziT2dfCwH5hxMriunijHYlDNHL3xXCpkN7hqz4yxcDvFrJZodIocMRzNNRtT lyMmW8FhmE7NqYtgPKxwNPWzLBwkAKo9V30bzAEuIXeMiDkoFXXO5VSEvdsyk6XIdjH1 PDkQHWh2fNPVWr3G5gh5/kLxn9A6YPt0bAj/66W5jjFiBKG5Q43C7pBxeHJveFKfDOur 26cj6ptf/Q74qJjsX0w7ZGAuG1+wb09Qr2guwiTj7r67K9vnF1JozLnyASYKne/H25GY ZTEnFQnTUeWKqZEzP+WGBx1MOytx3Ju4mAjkDRqjh+0GtQSQDUWF9GucfbvaeFxiwuYS WR2A== X-Forwarded-Encrypted: i=1; AJvYcCUfo9V677Qg3uGIiIn7ztD6fq7diwZkCozKo0O13xgA/RB3eJEiJkXGzgVOPCXqFvA8abM5NPc545ogvLKF@vger.kernel.org, AJvYcCW6HaGZcFXsXxv+LjKhX31yVw9T7ci9aVvU52qVnUdws3wkTJIkkkO+wHfEfy2CD4GHVfyqqOZ97Yab@vger.kernel.org, AJvYcCWjMo8msS8Y36RT65p1PNDSD4xXpEI0mmtzMqhcZG1G0a1drdv0T+9ml0hKkss0jYSWfvxIVgWiusqk@vger.kernel.org X-Gm-Message-State: AOJu0YxAndK8WkV+Q13Hhrqvu4riUg7m2QBNCas0TU+1SqJNSP2WqfQx qeX5k3nFTFDOInyHFsDtl0nZ9CMzVHcM3U1AZhVAjzapArcLVVwW X-Gm-Gg: ASbGnctomAKOiboiy3KMK9TD0TD6WB+hcfLuluh8Kd0ecDsyJmIyNnYuFOi+Zo/xhZs gi/qYDSI8fQ9u9GRqapy4xJbjtbcvCEA+BLpPD97WDdgBLlfUlcJM/V+eGYmPipdVY5g5LceLea FYUau5I6qFcaWcyEXfEbQfdHhfPfBTHbXl65cPtFTeHkKCYoOpLhqqgCzZ6VQlP/JSvm14bV2FA 5u0gYSy8u4whSUDTvp0Oidw9b9EJqDFWEHjGAF0ca4DB7lLeuYZuJ8k84XOoLuK7yRdB0xgK66R b1NR/0wfklCzHI+dd1ncva03S/rv03ezvvmjU5cfQ3SC7pQD62YeCkpjSnOsW4IYB0S4HK0GW1V 2oA== X-Google-Smtp-Source: AGHT+IHCQXvBKq354MzaMySI3MBLz2GNDpm/cuGn729v2/ipYHeF0Y4wgOzvDvG6z1gtsAfb3H9GfA== X-Received: by 2002:a05:600c:4e07:b0:439:86fb:7340 with SMTP id 5b1f17b1804b1-43db62b70b3mr7884295e9.30.1743192086510; Fri, 28 Mar 2025 13:01:26 -0700 (PDT) Received: from iku.Home ([2a06:5906:61b:2d00:b400:d08:873:badd]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-43d8fcceaaasm37930955e9.18.2025.03.28.13.01.25 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 28 Mar 2025 13:01:25 -0700 (PDT) From: Prabhakar X-Google-Original-From: Prabhakar To: Geert Uytterhoeven , Michael Turquette , Stephen Boyd , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Magnus Damm Cc: linux-renesas-soc@vger.kernel.org, linux-clk@vger.kernel.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, Prabhakar , Biju Das , Fabrizio Castro , Lad Prabhakar Subject: [PATCH 3/6] clk: renesas: rzv2h-cpg: Ignore monitoring CLK_MON bits for external clocks Date: Fri, 28 Mar 2025 20:01:02 +0000 Message-ID: <20250328200105.176129-4-prabhakar.mahadev-lad.rj@bp.renesas.com> X-Mailer: git-send-email 2.49.0 In-Reply-To: <20250328200105.176129-1-prabhakar.mahadev-lad.rj@bp.renesas.com> References: <20250328200105.176129-1-prabhakar.mahadev-lad.rj@bp.renesas.com> Precedence: bulk X-Mailing-List: linux-renesas-soc@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 From: Lad Prabhakar Ignore CLK_MON bits when turning on/off module clocks that use an external clock source, as they cannot be monitored. Introduce the `DEF_MOD_EXTERNAL()` macro for defining module clocks that may have an external clock source. Update `rzv2h_cpg_register_mod_clk()` to update mon_index. Signed-off-by: Lad Prabhakar --- drivers/clk/renesas/rzv2h-cpg.c | 24 ++++++++++++++++++++++++ drivers/clk/renesas/rzv2h-cpg.h | 28 ++++++++++++++++++++++++---- 2 files changed, 48 insertions(+), 4 deletions(-) diff --git a/drivers/clk/renesas/rzv2h-cpg.c b/drivers/clk/renesas/rzv2h-cpg.c index dec97f731e3a..e6a3c673879f 100644 --- a/drivers/clk/renesas/rzv2h-cpg.c +++ b/drivers/clk/renesas/rzv2h-cpg.c @@ -566,6 +566,25 @@ static void rzv2h_mod_clock_mstop_disable(struct rzv2h_cpg_priv *priv, spin_unlock_irqrestore(&priv->rmw_lock, flags); } +static bool rzv2h_mod_clock_is_external(struct rzv2h_cpg_priv *priv, + u16 ext_clk_offset, + u8 ext_clk_bit, + u8 ext_cond) +{ + u32 value; + + if (!ext_clk_offset) + return false; + + value = readl(priv->base + ext_clk_offset) & BIT(ext_clk_bit); + value >>= ext_clk_bit; + + if (value == ext_cond) + return true; + + return false; +} + static int rzv2h_mod_clock_is_enabled(struct clk_hw *hw) { struct mod_clock *clock = to_mod_clock(hw); @@ -688,6 +707,11 @@ rzv2h_cpg_register_mod_clk(const struct rzv2h_mod_clk *mod, clock->on_index = mod->on_index; clock->on_bit = mod->on_bit; clock->mon_index = mod->mon_index; + /* If clock is coming from external source ignore the monitor bit for it */ + if (rzv2h_mod_clock_is_external(priv, mod->external_clk_offset, + mod->external_clk_bit, + mod->external_cond)) + clock->mon_index = -1; clock->mon_bit = mod->mon_bit; clock->no_pm = mod->no_pm; clock->priv = priv; diff --git a/drivers/clk/renesas/rzv2h-cpg.h b/drivers/clk/renesas/rzv2h-cpg.h index cae807aa53ef..0277871e298b 100644 --- a/drivers/clk/renesas/rzv2h-cpg.h +++ b/drivers/clk/renesas/rzv2h-cpg.h @@ -180,6 +180,10 @@ enum clk_types { * @on_bit: ON bit * @mon_index: monitor register index * @mon_bit: monitor bit + * @external_clk_offset: Offset to check to determine if the clock is external + * @external_clk_bit: Bit to check to determine if the clock is external + * @external_cond: Condition to determine whether a given clock source is external; + * it can be either 0 or 1. */ struct rzv2h_mod_clk { const char *name; @@ -191,9 +195,14 @@ struct rzv2h_mod_clk { u8 on_bit; s8 mon_index; u8 mon_bit; + u16 external_clk_offset:10; + u8 external_clk_bit:5; + u8 external_cond:1; }; -#define DEF_MOD_BASE(_name, _mstop, _parent, _critical, _no_pm, _onindex, _onbit, _monindex, _monbit) \ +#define DEF_MOD_BASE(_name, _mstop, _parent, _critical, _no_pm, _onindex, \ + _onbit, _monindex, _monbit, _external_clk_offset, \ + _external_clk_bit, _external_cond) \ { \ .name = (_name), \ .mstop_data = (_mstop), \ @@ -204,16 +213,27 @@ struct rzv2h_mod_clk { .on_bit = (_onbit), \ .mon_index = (_monindex), \ .mon_bit = (_monbit), \ + .external_clk_offset = (_external_clk_offset), \ + .external_clk_bit = (_external_clk_bit), \ + .external_cond = (_external_cond), \ } #define DEF_MOD(_name, _parent, _onindex, _onbit, _monindex, _monbit, _mstop) \ - DEF_MOD_BASE(_name, _mstop, _parent, false, false, _onindex, _onbit, _monindex, _monbit) + DEF_MOD_BASE(_name, _mstop, _parent, false, false, _onindex, _onbit, _monindex, _monbit, \ + 0, 0, 0) #define DEF_MOD_CRITICAL(_name, _parent, _onindex, _onbit, _monindex, _monbit, _mstop) \ - DEF_MOD_BASE(_name, _mstop, _parent, true, false, _onindex, _onbit, _monindex, _monbit) + DEF_MOD_BASE(_name, _mstop, _parent, true, false, _onindex, _onbit, _monindex, _monbit, \ + 0, 0, 0) #define DEF_MOD_NO_PM(_name, _parent, _onindex, _onbit, _monindex, _monbit, _mstop) \ - DEF_MOD_BASE(_name, _mstop, _parent, false, true, _onindex, _onbit, _monindex, _monbit) + DEF_MOD_BASE(_name, _mstop, _parent, false, true, _onindex, _onbit, _monindex, _monbit, \ + 0, 0, 0) + +#define DEF_MOD_EXTERNAL(_name, _parent, _onindex, _onbit, _monindex, _monbit, _mstop, \ + _external_clk_offset, _external_clk_bit, _external_cond) \ + DEF_MOD_BASE(_name, _mstop, _parent, false, false, _onindex, _onbit, _monindex, _monbit, \ + _external_clk_offset, _external_clk_bit, _external_cond) /** * struct rzv2h_reset - Reset definitions From patchwork Fri Mar 28 20:01:03 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Prabhakar X-Patchwork-Id: 14032390 X-Patchwork-Delegate: geert@linux-m68k.org Received: from mail-wm1-f48.google.com (mail-wm1-f48.google.com [209.85.128.48]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id E41431EDA19; Fri, 28 Mar 2025 20:01:29 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.128.48 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1743192091; cv=none; b=Gj+2eJSrHipKlFNqeng5N1l624ZJgmmtU9nSSDiAwjamARwX8i1hKxnkQ46GELcuVLNY2KV0ROYZ6/kFZgsMkA+DZJ6rPC5j/83gkmNk955/6rLE4k8dgluC1YQC7LOZ1MYaCJL32dVKgyJydP1X+bIprCDAVdY8Td9m8OUA1xI= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1743192091; c=relaxed/simple; bh=SmGZmSs0jAN2F9cfo9+ZfJfH0tqEjk7syAbSsAg/elM=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=RQOslK7L4lM8JNehqv95oOCzs/xQFKoC6GW0CuyD5e3t9k5AuT/YBeEmbZXBC/XE5HwIDI6OTlzzd0YdxU96VvhEcrljSnJ1kAbuJ10yzIjckP36UP6MWNhBBXiijanXo3g0uwXW+agS/rmmUZ6hqGJC5Km3FsgeUWVebgZ4KSo= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com; spf=pass smtp.mailfrom=gmail.com; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b=jO11ZxXc; arc=none smtp.client-ip=209.85.128.48 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=gmail.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="jO11ZxXc" Received: by mail-wm1-f48.google.com with SMTP id 5b1f17b1804b1-4394a823036so25136105e9.0; Fri, 28 Mar 2025 13:01:29 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20230601; t=1743192088; x=1743796888; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=hR/ZEJowjkxQ8M2CChvL0ELqlxgAaDnp+KCqaZOS0ak=; b=jO11ZxXc3LE5t34BeLk6N8YAvaRTEstvKhQQ2xcUFQvtLwje4Nf2uij9b6Umru9Ngf NEe8f6G+shufuQrKK/Dla5woz980JmSk8eSmmmIjLp6VP6KT18gS8Uz64S/ON85maxYE TQyv4lNNjjmrdgyohUspH8P9yCEuUUbjK7iOQjPj816WksnuTMZUEKp+w3oi2ONucN1q psNTe3psf0vSnbirWh1dYRzM+b0rXQDU0NO0Dx1+pSW1k4eFVIWmGygmaELk+1Ll/o7T Ofn0CgaNuWaB6eYse9LOGmtgG+uV6AJCm3OV/bJ7lgb7KX5eWwdjeQxiJ1W0EQa9EICG jLGw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1743192088; x=1743796888; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=hR/ZEJowjkxQ8M2CChvL0ELqlxgAaDnp+KCqaZOS0ak=; b=MoPCuDs0KFW43V8i1H/uUcoty0cN5m/JNw8QtIjU98N8eoIqKB+MvkMWazEivP+67L fnsyUeZLSdfUXYc9pyiyo41nMYQy8LIgqzf/tFTrKhEocf4s/Gm51WSk/Rv/fMMa/6Hx T4D5dA43uHR8iFXIxx4IEEoRrM9OObcKV4AD15iJY6W1RqYYKT+3Bqj/koTjrQ+0N6Zv mqYOLQ4zCt0PckypOpFkhzmoJ9++XtnNYL5t9TZ3yPKFvegEs18Hk2E1lIJdCsuxReTh 2JR7f+bjace1NnfeK0IeYpYlFTGIle63UvQIZVr4eazhCUm8763Y5UwCN73BwjK9ADEu fyMw== X-Forwarded-Encrypted: i=1; AJvYcCVYyO5GJRaEc5N8XgeZxMobCmHMIGJq0Knbh6wSv/0rerKKsHryBT8HaK0g1kpigm7os3r7ED40jV1HqeFU@vger.kernel.org, AJvYcCVp+0BKlumnbLvQMgCu8X87z7NiCvuysF/CL506+HUXyNcQHnShhTLp7hC9GNaN+GG9GrsFLKTUGeLt@vger.kernel.org, AJvYcCWpSffN1g15WG7WVCez2H1Rhup7SZ/KnvWxQpEEvmT0ucGZwEZ/7oMwsY1Tvg2oOfuMP2KRFkLKxNaR@vger.kernel.org X-Gm-Message-State: AOJu0Yz1u6Tatc2oS43SM1ah+3YOFvMmdjrKY6Zfiocuk4TtfNNYzDw1 s89Bc2Q0dRrspEJXi4MmR4vsFR9fsId7d5z85QCb+ziBQYz+YhgO X-Gm-Gg: ASbGnctud+Wc0yEyDugoLEP6tR09O0FlbXnHD7+Dw1armeKgTK+lXSE0crxt6I08StB uminFIu7od0tShiHT2O83sBs8/E/Mj8+NKUCLw8959FqtZWyASEa231YBc540w4OjTG22mYxuFs CTc0LVqmZ/OhvJuKfVAunDJOcOwl8OOhLEQvZ7nzW8v6N7ed7OR4ONPHO6olsTE3dWP7EMpPIK4 8478/fiQsLRAeL55TLTDVLF7IXIQYfZB/6Uy4aqw+5p4xmX8x6rAR3SaTPP3pRk1YL6lWwhYd14 hREnlAsYT1VOIqKXG6W+OoiF5jmJX9zV64NC/PTZ+cd13a0gJfnpeshH/NcseY9KcsA= X-Google-Smtp-Source: AGHT+IGDDmIVMuuPmc+T+CvGNrz4n2UjVZR3mhSkkiVSb//PSAUuBcHkCroR36pX9ZXZsp8/M/cRrQ== X-Received: by 2002:a05:600c:3ca6:b0:439:9b2a:1b2f with SMTP id 5b1f17b1804b1-43db61dc71dmr8933545e9.3.1743192088165; Fri, 28 Mar 2025 13:01:28 -0700 (PDT) Received: from iku.Home ([2a06:5906:61b:2d00:b400:d08:873:badd]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-43d8fcceaaasm37930955e9.18.2025.03.28.13.01.26 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 28 Mar 2025 13:01:26 -0700 (PDT) From: Prabhakar X-Google-Original-From: Prabhakar To: Geert Uytterhoeven , Michael Turquette , Stephen Boyd , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Magnus Damm Cc: linux-renesas-soc@vger.kernel.org, linux-clk@vger.kernel.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, Prabhakar , Biju Das , Fabrizio Castro , Lad Prabhakar Subject: [PATCH 4/6] dt-bindings: clock: renesas,r9a09g057-cpg: Add USB2 PHY and GBETH PTP core clocks Date: Fri, 28 Mar 2025 20:01:03 +0000 Message-ID: <20250328200105.176129-5-prabhakar.mahadev-lad.rj@bp.renesas.com> X-Mailer: git-send-email 2.49.0 In-Reply-To: <20250328200105.176129-1-prabhakar.mahadev-lad.rj@bp.renesas.com> References: <20250328200105.176129-1-prabhakar.mahadev-lad.rj@bp.renesas.com> Precedence: bulk X-Mailing-List: linux-renesas-soc@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 From: Lad Prabhakar Add definitions for USB2 PHY core clocks and Gigabit Ethernet PTP reference core clocks in the R9A09G057 CPG bindings header file. Signed-off-by: Lad Prabhakar Acked-by: Krzysztof Kozlowski --- Please note these marcos are used in the clock driver patch 5/6 and patch 6/6. Also these macros will be used in the SoC DTSI when USB2 and GBETH are added. --- include/dt-bindings/clock/renesas,r9a09g057-cpg.h | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/include/dt-bindings/clock/renesas,r9a09g057-cpg.h b/include/dt-bindings/clock/renesas,r9a09g057-cpg.h index 541e6d719bd6..884dbeb1e139 100644 --- a/include/dt-bindings/clock/renesas,r9a09g057-cpg.h +++ b/include/dt-bindings/clock/renesas,r9a09g057-cpg.h @@ -17,5 +17,9 @@ #define R9A09G057_CM33_CLK0 6 #define R9A09G057_CST_0_SWCLKTCK 7 #define R9A09G057_IOTOP_0_SHCLK 8 +#define R9A09G057_USB2_0_CLK_CORE0 9 +#define R9A09G057_USB2_0_CLK_CORE1 10 +#define R9A09G057_GBETH_0_CLK_PTP_REF_I 11 +#define R9A09G057_GBETH_1_CLK_PTP_REF_I 12 #endif /* __DT_BINDINGS_CLOCK_RENESAS_R9A09G057_CPG_H__ */ From patchwork Fri Mar 28 20:01:04 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Prabhakar X-Patchwork-Id: 14032391 X-Patchwork-Delegate: geert@linux-m68k.org Received: from mail-wm1-f43.google.com (mail-wm1-f43.google.com [209.85.128.43]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 4BF501F09A3; Fri, 28 Mar 2025 20:01:31 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.128.43 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1743192094; cv=none; b=vD2cK42TkWQEvS0hQ8AS1GA1zsua40OTNcsqV7Rk42zTGPwI6jUx3MRpPNyMVqYPR0fJX69NJLgyMvSYqzUp6LcJLuXzC6PbBNM1DmEsFH+dax35XEoncI6FBztp2njvYO1EXbq0qMDCFmchN+RTXLaq6yAIfz36Lumj3mu6LLg= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1743192094; c=relaxed/simple; bh=ugyqHTFe5dAIP8w+jtcX3EeXua5/7kTcCP6vhlCOgAQ=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=Bq2f3XtuYnS1JCfCq7YX5nltffQ42nSa2xF0NUaFQbwHLj43Xt0v1KeW+aLEi/M9e0InwNP+1G7FbIab3GxcOguotxVCtjs1QpUvlgyKRx/3H9Cuq3dw7nGGFEEMqnYtRvFEIwrXFtoKLrv1m4/VfmKhmzLnZws3sleqJojPoMs= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com; spf=pass smtp.mailfrom=gmail.com; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b=aNXKDXXJ; arc=none smtp.client-ip=209.85.128.43 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=gmail.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="aNXKDXXJ" Received: by mail-wm1-f43.google.com with SMTP id 5b1f17b1804b1-43948021a45so25320355e9.1; Fri, 28 Mar 2025 13:01:30 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20230601; t=1743192089; x=1743796889; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=pWPeody0yl6K0oerpL14uBR8W8cRKVcUF0FRIWM0S0M=; b=aNXKDXXJtckOAelP7w5zCcShTxMqYFkibOBKRO4fldFuP14qTs3ND500VYCMixLK2Z 8TqWV43m49jhED72ykdTAgRR9mfMJPs83+ghHgFFwNOAKPfHejgB/fnjSSQKCuU2dtGE g1BuAbVHuMTvBe71Kax/MOKInac2iknzRHNU4FjpZA95A364H3wITkSxfnj9GR1IiNf/ UQg7jY5r0/7ZdMUsM4Kij/QevQo0Nn+f2cQq/g7scoWSxKncouxoO7b81pH8l7sKBS4R eD4nhLOrWonDx+fXXWsb/Odt8pXCjV3Gb12GSoxqIl7256gHwCVRmXIoIVRIV9JdcmDA iONw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1743192089; x=1743796889; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=pWPeody0yl6K0oerpL14uBR8W8cRKVcUF0FRIWM0S0M=; b=bpkQo9Iib1HzEsL8nfAJLPPRjws8YEw6cg79G7SKRpzfBZvvpz54OazXQfZutQL8x8 z4DPzj/GG3q/csa+lkd4v5p+mEVyaBW4+6R3Bmfh3lNSKCIEzpyfQ5cDXTZ0oRMQlG6H ZgWLie8rbsO6CUllCjbthzN3AP+7TQaIj4WzSMXfwSC28GoSkLGHcR6EnvsgsChbEey9 CbxSTvxANENXfb/d4R07UJ4kfvXbuEpEwkmjWjW7BJvIHcj7/hPThrbVVzsCgI627+AR pfZItycjvjBsvHyfk4ZXvoaMnMNk5uXnL4KR9wkqNJ8mfbpV4IXv1jSTl8qOUtecp5wY vHFA== X-Forwarded-Encrypted: i=1; AJvYcCVEPXUpOMEl4Y9O0YNj86aevkFipC65NsdVRcpHAhHlwX55TnS3YnvP/STqTJEJJkZmaYdRrIoyWkLb@vger.kernel.org, AJvYcCWOtsnNUrSCjv4ioz78E4sjQgW7dw5if3QyEgMY2xo/idd5uEudore9Za1Pmkd2Z9lSgEpJs5maaAZl2mBL@vger.kernel.org, AJvYcCXp/RybHKkXANWoxsxXU/6iKJ69sby8/zgUie6XytH8/zswDEYlLELRDL2i+FmoBZqtWkfAUidOThdn@vger.kernel.org X-Gm-Message-State: AOJu0YxTTZXtXJgRK07X35vXEEv/uRx/brv+jTqWRwPMYLGw2nC3Vmm9 3uBR7Lf89kSjJwJcYiYj7XW+ct+CukhYhZ78zRQB/97XzLNTMgMW X-Gm-Gg: ASbGncsm0DjRHm3x9ARGouIz9u9R+NgF6xqDHnxyz9dEGRp/3E/zCcfnv17n45Kx5lE 2E3y0hQOeeKmcAcJlMyWQO8x9S7PKqSabTqAqrQljSjkFWe1Ka5B2rWTO/EZc7yvN6YallWqb1g X9v35Er88M5qvyA+pOfvD0+SnSE/RSckp9fIPGWBXJVrU0fK5EvsIWTHK8LFhO1nuxQO2ci9zIA kMqlkIOv87OWN5ZhCb4lxTlahuvUdp3PvF+HfGJalhqFrv+0MzpNdecovqThjpKgOihUgmfwhWk WR+SumthG0Ugo0DepcEE/Vs7jZ+07JoquqGCkr221RneISr/SljFAi2mCiazgs3QlwZjhPWunYf TGw== X-Google-Smtp-Source: AGHT+IF3E3bidKyccmvEGIqdEplM0EWPThAIKx2qf+HjkUECmwqCjSCjc6xm9gm0yxYfaL/mlrZXOw== X-Received: by 2002:a05:6000:184c:b0:39c:e0e:a1d8 with SMTP id ffacd0b85a97d-39c120de325mr349436f8f.21.1743192089310; Fri, 28 Mar 2025 13:01:29 -0700 (PDT) Received: from iku.Home ([2a06:5906:61b:2d00:b400:d08:873:badd]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-43d8fcceaaasm37930955e9.18.2025.03.28.13.01.28 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 28 Mar 2025 13:01:28 -0700 (PDT) From: Prabhakar X-Google-Original-From: Prabhakar To: Geert Uytterhoeven , Michael Turquette , Stephen Boyd , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Magnus Damm Cc: linux-renesas-soc@vger.kernel.org, linux-clk@vger.kernel.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, Prabhakar , Biju Das , Fabrizio Castro , Lad Prabhakar Subject: [PATCH 5/6] clk: renesas: r9a09g057: Add clock and reset entries for USB2 Date: Fri, 28 Mar 2025 20:01:04 +0000 Message-ID: <20250328200105.176129-6-prabhakar.mahadev-lad.rj@bp.renesas.com> X-Mailer: git-send-email 2.49.0 In-Reply-To: <20250328200105.176129-1-prabhakar.mahadev-lad.rj@bp.renesas.com> References: <20250328200105.176129-1-prabhakar.mahadev-lad.rj@bp.renesas.com> Precedence: bulk X-Mailing-List: linux-renesas-soc@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 From: Lad Prabhakar Add clock and reset entries for USB2. Signed-off-by: Lad Prabhakar --- drivers/clk/renesas/r9a09g057-cpg.c | 20 +++++++++++++++++++- 1 file changed, 19 insertions(+), 1 deletion(-) diff --git a/drivers/clk/renesas/r9a09g057-cpg.c b/drivers/clk/renesas/r9a09g057-cpg.c index da20dbaead1f..3c40e36259fe 100644 --- a/drivers/clk/renesas/r9a09g057-cpg.c +++ b/drivers/clk/renesas/r9a09g057-cpg.c @@ -16,7 +16,7 @@ enum clk_ids { /* Core Clock Outputs exported to DT */ - LAST_DT_CORE_CLK = R9A09G057_IOTOP_0_SHCLK, + LAST_DT_CORE_CLK = R9A09G057_GBETH_1_CLK_PTP_REF_I, /* External Input Clocks */ CLK_AUDIO_EXTAL, @@ -41,6 +41,7 @@ enum clk_ids { CLK_PLLDTY_ACPU, CLK_PLLDTY_ACPU_DIV2, CLK_PLLDTY_ACPU_DIV4, + CLK_PLLDTY_DIV8, CLK_PLLDTY_DIV16, CLK_PLLDTY_RCPU, CLK_PLLDTY_RCPU_DIV4, @@ -104,6 +105,7 @@ static const struct cpg_core_clk r9a09g057_core_clks[] __initconst = { DEF_DDIV(".plldty_acpu", CLK_PLLDTY_ACPU, CLK_PLLDTY, CDDIV0_DIVCTL2, dtable_2_64), DEF_FIXED(".plldty_acpu_div2", CLK_PLLDTY_ACPU_DIV2, CLK_PLLDTY_ACPU, 1, 2), DEF_FIXED(".plldty_acpu_div4", CLK_PLLDTY_ACPU_DIV4, CLK_PLLDTY_ACPU, 1, 4), + DEF_FIXED(".plldty_div8", CLK_PLLDTY_DIV8, CLK_PLLDTY, 1, 8), DEF_FIXED(".plldty_div16", CLK_PLLDTY_DIV16, CLK_PLLDTY, 1, 16), DEF_DDIV(".plldty_rcpu", CLK_PLLDTY_RCPU, CLK_PLLDTY, CDDIV3_DIVCTL2, dtable_2_64), DEF_FIXED(".plldty_rcpu_div4", CLK_PLLDTY_RCPU_DIV4, CLK_PLLDTY_RCPU, 1, 4), @@ -126,6 +128,8 @@ static const struct cpg_core_clk r9a09g057_core_clks[] __initconst = { DEF_DDIV("ca55_0_coreclk3", R9A09G057_CA55_0_CORE_CLK3, CLK_PLLCA55, CDDIV1_DIVCTL3, dtable_1_8), DEF_FIXED("iotop_0_shclk", R9A09G057_IOTOP_0_SHCLK, CLK_PLLCM33_DIV16, 1, 1), + DEF_FIXED("usb2_0_clk_core0", R9A09G057_USB2_0_CLK_CORE0, CLK_QEXTAL, 1, 1), + DEF_FIXED("usb2_0_clk_core1", R9A09G057_USB2_0_CLK_CORE1, CLK_QEXTAL, 1, 1), }; static const struct rzv2h_mod_clk r9a09g057_mod_clks[] __initconst = { @@ -219,6 +223,16 @@ static const struct rzv2h_mod_clk r9a09g057_mod_clks[] __initconst = { BUS_MSTOP(8, BIT(4))), DEF_MOD("sdhi_2_aclk", CLK_PLLDTY_ACPU_DIV4, 10, 14, 5, 14, BUS_MSTOP(8, BIT(4))), + DEF_MOD("usb2_0_u2h0_hclk", CLK_PLLDTY_DIV8, 11, 3, 5, 19, + BUS_MSTOP(7, BIT(7))), + DEF_MOD("usb2_0_u2h1_hclk", CLK_PLLDTY_DIV8, 11, 4, 5, 20, + BUS_MSTOP(7, BIT(8))), + DEF_MOD("usb2_0_u2p_exr_cpuclk", CLK_PLLDTY_ACPU_DIV4, 11, 5, 5, 21, + BUS_MSTOP(7, BIT(9))), + DEF_MOD("usb2_0_pclk_usbtst0", CLK_PLLDTY_ACPU_DIV4, 11, 6, 5, 22, + BUS_MSTOP(7, BIT(10))), + DEF_MOD("usb2_0_pclk_usbtst1", CLK_PLLDTY_ACPU_DIV4, 11, 7, 5, 23, + BUS_MSTOP(7, BIT(11))), DEF_MOD("cru_0_aclk", CLK_PLLDTY_ACPU_DIV2, 13, 2, 6, 18, BUS_MSTOP(9, BIT(4))), DEF_MOD_NO_PM("cru_0_vclk", CLK_PLLVDO_CRU0, 13, 3, 6, 19, @@ -286,6 +300,10 @@ static const struct rzv2h_reset r9a09g057_resets[] __initconst = { DEF_RST(10, 7, 4, 24), /* SDHI_0_IXRST */ DEF_RST(10, 8, 4, 25), /* SDHI_1_IXRST */ DEF_RST(10, 9, 4, 26), /* SDHI_2_IXRST */ + DEF_RST(10, 12, 4, 29), /* USB2_0_U2H0_HRESETN */ + DEF_RST(10, 13, 4, 30), /* USB2_0_U2H1_HRESETN */ + DEF_RST(10, 14, 4, 31), /* USB2_0_U2P_EXL_SYSRST */ + DEF_RST(10, 15, 5, 0), /* USB2_0_PRESETN */ DEF_RST(12, 5, 5, 22), /* CRU_0_PRESETN */ DEF_RST(12, 6, 5, 23), /* CRU_0_ARESETN */ DEF_RST(12, 7, 5, 24), /* CRU_0_S_RESETN */ From patchwork Fri Mar 28 20:01:05 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Prabhakar X-Patchwork-Id: 14032392 X-Patchwork-Delegate: geert@linux-m68k.org Received: from mail-wm1-f50.google.com (mail-wm1-f50.google.com [209.85.128.50]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 120CF1F09B9; Fri, 28 Mar 2025 20:01:32 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.128.50 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1743192095; cv=none; b=kX7d+veg8+jQx2SCR/dHTwb1g/w4HuEOs8xQMCQr6mTH1qN96+cCF2MIvhAwuRaVdrnSKp7Pzl4sxxHv2SDDc1fYScelYCxfuS1EHuvpj/NG3CPiU6+0Eu4+SLcSj0ZpH6OkTG1j0KYGpfjXXa60o8aDdbAUZf/CK9YVSalwmP0= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1743192095; c=relaxed/simple; bh=U+t9Q2ALK7lnJq1xvyNquzDJ6+QGuiYORhdXe+k1nFo=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=OcCbzoR9UPSjJHD+HqKlSarSXxixuZ9rCFeCbd7PeHNmq4IBBarK5Y8LHUrr29my28CfSeRgYPloCupPK8zzH/TRtVQa7XQalet6hksqVEPehjPs57uWN8q1R2210SWu0jFm8ApCK2nS7Qxr7LlrJqmPEa+AGfA0ErpwJ8OTJRk= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com; spf=pass smtp.mailfrom=gmail.com; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b=gc6bTIox; arc=none smtp.client-ip=209.85.128.50 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=gmail.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="gc6bTIox" Received: by mail-wm1-f50.google.com with SMTP id 5b1f17b1804b1-43690d4605dso17854535e9.0; Fri, 28 Mar 2025 13:01:32 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20230601; t=1743192091; x=1743796891; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=h1fOeglNqBPsySK9Pv3vXlmCbugVsWq/fJq9OAzmtGo=; b=gc6bTIoxmdQ5RvTuEkFAb8/f8FoMeAA+XlA4GuidwLIBHME7FTpbg3To4HHvv4Tb0z kyzQmpJXeOYgmZb2LI/XVo7rhem8D/DB9zxG+L52oGjw3oOsHN3vLNMuzxOZbLZq6Su0 gFFcbBwyDt9kZBY3+MjHdrDZ3tIrq3wmh7V6AeIsx2o1zUb+4ukehn/DIeuHxj+lOaaz uGfvPf6Z+OTpIgWlu7s9AZBdtfahkPSrBKILoRD95WKliLzwjFXD16Ia2j7+l1DuEwKX oQxApKLXEP7MiaakjpS2wf9DTdPwXqz9S4Z9uItnGBW8pj2NbEvbsbkSPhD+/qiV9dL1 vP6g== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1743192091; x=1743796891; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=h1fOeglNqBPsySK9Pv3vXlmCbugVsWq/fJq9OAzmtGo=; b=q/clfP86sgz/dqnQirhb6XBa7deSJ5RK6CRKYEM709mVA3iOAfkIM9mYV2x0YDOYOP RgYrEEJmcqRQKMi1sAdSDnEsjeL7wHK5I+1i6nzak+M4LEbf1vGsSg5cxhRTrbTYNXTQ 7PkDnCzYL4zU2WYznj78LHTvstnv5uQo6issGVBCQ3JGdYEMT7vDVem4ZR1BOy0cW7D/ ma/Rgh1gOBDvSflfp83kh62MYFnKd017XaFyBEAf91Mm+HlR/qQxGvk9VOyQtNgo3D1o aO/BCVGx4BVM8Ku5Os2b9pLowtln7KAT/Vu0Zzi2wwzuZF/CeEsyZlRLi0Cu67LekNxB +X5A== X-Forwarded-Encrypted: i=1; AJvYcCU3QM92kMZWiuOqDUsHYfEAWu0lMAGjkD2Zk3RNB16Xvfd52v257wSwtUKLr3xP2ctIExRSx5j0i0Oq@vger.kernel.org, AJvYcCX5Tli8cy455RSsHt2BYR6HvxlmNtIK3CIWRXV0w2q+tNwp42+KMak3d4FK2w0RFVXolKZyr2mqfR0m7nMs@vger.kernel.org, AJvYcCXfu/Ki0AkW/F25984kKw4gtj5G0NfqEEzTi3Vg17Bc+uztzHkNWSnlwNWt1WAqlqWW2DoIWwU3yKJf@vger.kernel.org X-Gm-Message-State: AOJu0Yzy5uUalFvW1eldMZLycAXuBH2UW+OuMtRX2W6scLnsgwDxrgfP 4vAQLnaSliHM95kGiFrz4Gq5YCZvBFZvS4fFq1cgrabmLHy/g2S7QxvaE94Z X-Gm-Gg: ASbGncs1QNYfFJ+jEenwSXDBWAE4ThI2jfYLCxZdWZ3hUHmAYeKDrc7wfMvofPDKE9E K43nD8nXgfPUDZUZWsnI4U11eYyM6uSlvNoVZGWZk+jffIdrXWQbg0YW0HHgyoxVV248AbTIKja OmAs5T0qepJN7u4bvva9BayKyIyh7I050ZesWPMjfDOe67uf7Onh37Zg1Aqx0R8i2UYI2dHVBZs JDtwS1qkkHhSxZmqKCTx3xXoACH5wVofkt9+o3va3yQVj57vGKdbVfhpedJaN6LbuLAzkqUkxIC RgBfYts52STiWvmrOnfs3IPZBvL+/mKdklwfbyZ+8F0l5o+eCMWeiWm4cYEpKJuh3I4= X-Google-Smtp-Source: AGHT+IG4w4ACsDcndQ7Upce7oKR1gqjBvl646Cf0+8vYVeyx/0n805sGlP0QgfEMS0tRCN9uqfxV3g== X-Received: by 2002:a05:600c:34ce:b0:43d:9d5:474d with SMTP id 5b1f17b1804b1-43dabe23634mr9218175e9.0.1743192091027; Fri, 28 Mar 2025 13:01:31 -0700 (PDT) Received: from iku.Home ([2a06:5906:61b:2d00:b400:d08:873:badd]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-43d8fcceaaasm37930955e9.18.2025.03.28.13.01.29 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 28 Mar 2025 13:01:29 -0700 (PDT) From: Prabhakar X-Google-Original-From: Prabhakar To: Geert Uytterhoeven , Michael Turquette , Stephen Boyd , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Magnus Damm Cc: linux-renesas-soc@vger.kernel.org, linux-clk@vger.kernel.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, Prabhakar , Biju Das , Fabrizio Castro , Lad Prabhakar Subject: [PATCH 6/6] clk: renesas: r9a09g057: Add clock and reset entries for GBETH0/1 Date: Fri, 28 Mar 2025 20:01:05 +0000 Message-ID: <20250328200105.176129-7-prabhakar.mahadev-lad.rj@bp.renesas.com> X-Mailer: git-send-email 2.49.0 In-Reply-To: <20250328200105.176129-1-prabhakar.mahadev-lad.rj@bp.renesas.com> References: <20250328200105.176129-1-prabhakar.mahadev-lad.rj@bp.renesas.com> Precedence: bulk X-Mailing-List: linux-renesas-soc@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 From: Lad Prabhakar Add clock and reset entries for GBETH instances. Include core clocks for PTP, sourced from PLLETH, and add PLLs, dividers, and static mux clocks used as clock sources for the GBETH IP. Signed-off-by: Lad Prabhakar --- drivers/clk/renesas/r9a09g057-cpg.c | 72 +++++++++++++++++++++++++++++ drivers/clk/renesas/rzv2h-cpg.h | 11 +++++ 2 files changed, 83 insertions(+) diff --git a/drivers/clk/renesas/r9a09g057-cpg.c b/drivers/clk/renesas/r9a09g057-cpg.c index 3c40e36259fe..057bfa0e2a57 100644 --- a/drivers/clk/renesas/r9a09g057-cpg.c +++ b/drivers/clk/renesas/r9a09g057-cpg.c @@ -29,6 +29,7 @@ enum clk_ids { CLK_PLLDTY, CLK_PLLCA55, CLK_PLLVDO, + CLK_PLLETH, CLK_PLLGPU, /* Internal Core Clocks */ @@ -49,6 +50,14 @@ enum clk_ids { CLK_PLLVDO_CRU1, CLK_PLLVDO_CRU2, CLK_PLLVDO_CRU3, + CLK_PLLETH_DIV_250_FIX, + CLK_PLLETH_DIV_125_FIX, + CLK_CSDIV_PLLETH_GBE0, + CLK_CSDIV_PLLETH_GBE1, + CLK_SMUX2_GBE0_TXCLK, + CLK_SMUX2_GBE0_RXCLK, + CLK_SMUX2_GBE1_TXCLK, + CLK_SMUX2_GBE1_RXCLK, CLK_PLLGPU_GEAR, /* Module Clocks */ @@ -78,6 +87,19 @@ static const struct clk_div_table dtable_2_64[] = { {0, 0}, }; +static const struct clk_div_table dtable_2_100[] = { + {0, 2}, + {1, 10}, + {2, 100}, + {0, 0}, +}; + +/* Mux clock tables */ +static const char * const smux2_gbe0_rxclk[] = { ".plleth_gbe0", "et0-rxc-rxclk" }; +static const char * const smux2_gbe0_txclk[] = { ".plleth_gbe0", "et0-txc-txclk" }; +static const char * const smux2_gbe1_rxclk[] = { ".plleth_gbe1", "et1-rxc-rxclk" }; +static const char * const smux2_gbe1_txclk[] = { ".plleth_gbe1", "et1-txc-txclk" }; + static const struct cpg_core_clk r9a09g057_core_clks[] __initconst = { /* External Clock Inputs */ DEF_INPUT("audio_extal", CLK_AUDIO_EXTAL), @@ -90,6 +112,7 @@ static const struct cpg_core_clk r9a09g057_core_clks[] __initconst = { DEF_FIXED(".plldty", CLK_PLLDTY, CLK_QEXTAL, 200, 3), DEF_PLL(".pllca55", CLK_PLLCA55, CLK_QEXTAL, PLLCA55), DEF_FIXED(".pllvdo", CLK_PLLVDO, CLK_QEXTAL, 105, 2), + DEF_FIXED(".plleth", CLK_PLLETH, CLK_QEXTAL, 125, 3), DEF_PLL(".pllgpu", CLK_PLLGPU, CLK_QEXTAL, PLLGPU), /* Internal Core Clocks */ @@ -115,6 +138,17 @@ static const struct cpg_core_clk r9a09g057_core_clks[] __initconst = { DEF_DDIV(".pllvdo_cru2", CLK_PLLVDO_CRU2, CLK_PLLVDO, CDDIV4_DIVCTL1, dtable_2_4), DEF_DDIV(".pllvdo_cru3", CLK_PLLVDO_CRU3, CLK_PLLVDO, CDDIV4_DIVCTL2, dtable_2_4), + DEF_FIXED(".plleth_250_fix", CLK_PLLETH_DIV_250_FIX, CLK_PLLETH, 1, 4), + DEF_FIXED(".plleth_125_fix", CLK_PLLETH_DIV_125_FIX, CLK_PLLETH_DIV_250_FIX, 1, 2), + DEF_CSDIV(".plleth_gbe0", CLK_CSDIV_PLLETH_GBE0, + CLK_PLLETH_DIV_250_FIX, CSDIV0_DIVCTL0, dtable_2_100), + DEF_CSDIV(".plleth_gbe1", CLK_CSDIV_PLLETH_GBE1, + CLK_PLLETH_DIV_250_FIX, CSDIV0_DIVCTL1, dtable_2_100), + DEF_SMUX(".smux2_gbe0_txclk", CLK_SMUX2_GBE0_TXCLK, SSEL0_SELCTL2, smux2_gbe0_txclk), + DEF_SMUX(".smux2_gbe0_rxclk", CLK_SMUX2_GBE0_RXCLK, SSEL0_SELCTL3, smux2_gbe0_rxclk), + DEF_SMUX(".smux2_gbe1_txclk", CLK_SMUX2_GBE1_TXCLK, SSEL1_SELCTL0, smux2_gbe1_txclk), + DEF_SMUX(".smux2_gbe1_rxclk", CLK_SMUX2_GBE1_RXCLK, SSEL1_SELCTL1, smux2_gbe1_rxclk), + DEF_DDIV(".pllgpu_gear", CLK_PLLGPU_GEAR, CLK_PLLGPU, CDDIV3_DIVCTL1, dtable_2_64), /* Core Clocks */ @@ -130,6 +164,10 @@ static const struct cpg_core_clk r9a09g057_core_clks[] __initconst = { DEF_FIXED("iotop_0_shclk", R9A09G057_IOTOP_0_SHCLK, CLK_PLLCM33_DIV16, 1, 1), DEF_FIXED("usb2_0_clk_core0", R9A09G057_USB2_0_CLK_CORE0, CLK_QEXTAL, 1, 1), DEF_FIXED("usb2_0_clk_core1", R9A09G057_USB2_0_CLK_CORE1, CLK_QEXTAL, 1, 1), + DEF_FIXED("gbeth_0_clk_ptp_ref_i", R9A09G057_GBETH_0_CLK_PTP_REF_I, + CLK_PLLETH_DIV_125_FIX, 1, 1), + DEF_FIXED("gbeth_1_clk_ptp_ref_i", R9A09G057_GBETH_1_CLK_PTP_REF_I, + CLK_PLLETH_DIV_125_FIX, 1, 1), }; static const struct rzv2h_mod_clk r9a09g057_mod_clks[] __initconst = { @@ -233,6 +271,38 @@ static const struct rzv2h_mod_clk r9a09g057_mod_clks[] __initconst = { BUS_MSTOP(7, BIT(10))), DEF_MOD("usb2_0_pclk_usbtst1", CLK_PLLDTY_ACPU_DIV4, 11, 7, 5, 23, BUS_MSTOP(7, BIT(11))), + DEF_MOD_EXTERNAL("gbeth_0_clk_tx_i", CLK_SMUX2_GBE0_TXCLK, 11, 8, 5, 24, + BUS_MSTOP(8, BIT(5)), + 0x300, 8, 1), + DEF_MOD_EXTERNAL("gbeth_0_clk_rx_i", CLK_SMUX2_GBE0_RXCLK, 11, 9, 5, 25, + BUS_MSTOP(8, BIT(5)), + 0x300, 12, 1), + DEF_MOD_EXTERNAL("gbeth_0_clk_tx_180_i", CLK_SMUX2_GBE0_TXCLK, 11, 10, 5, 26, + BUS_MSTOP(8, BIT(5)), + 0x300, 8, 1), + DEF_MOD_EXTERNAL("gbeth_0_clk_rx_180_i", CLK_SMUX2_GBE0_RXCLK, 11, 11, 5, 27, + BUS_MSTOP(8, BIT(5)), + 0x300, 12, 1), + DEF_MOD("gbeth_0_aclk_csr_i", CLK_PLLDTY_DIV8, 11, 12, 5, 28, + BUS_MSTOP(8, BIT(5))), + DEF_MOD("gbeth_0_aclk_i", CLK_PLLDTY_DIV8, 11, 13, 5, 29, + BUS_MSTOP(8, BIT(5))), + DEF_MOD_EXTERNAL("gbeth_1_clk_tx_i", CLK_SMUX2_GBE1_TXCLK, 11, 14, 5, 30, + BUS_MSTOP(8, BIT(6)), + 0x304, 8, 1), + DEF_MOD_EXTERNAL("gbeth_1_clk_rx_i", CLK_SMUX2_GBE1_RXCLK, 11, 15, 5, 31, + BUS_MSTOP(8, BIT(6)), + 0x304, 12, 1), + DEF_MOD_EXTERNAL("gbeth_1_clk_tx_180_i", CLK_SMUX2_GBE1_TXCLK, 12, 0, 6, 0, + BUS_MSTOP(8, BIT(6)), + 0x304, 8, 1), + DEF_MOD_EXTERNAL("gbeth_1_clk_rx_180_i", CLK_SMUX2_GBE1_RXCLK, 12, 1, 6, 1, + BUS_MSTOP(8, BIT(6)), + 0x304, 12, 1), + DEF_MOD("gbeth_1_aclk_csr_i", CLK_PLLDTY_DIV8, 12, 2, 6, 2, + BUS_MSTOP(8, BIT(6))), + DEF_MOD("gbeth_1_aclk_i", CLK_PLLDTY_DIV8, 12, 3, 6, 3, + BUS_MSTOP(8, BIT(6))), DEF_MOD("cru_0_aclk", CLK_PLLDTY_ACPU_DIV2, 13, 2, 6, 18, BUS_MSTOP(9, BIT(4))), DEF_MOD_NO_PM("cru_0_vclk", CLK_PLLVDO_CRU0, 13, 3, 6, 19, @@ -304,6 +374,8 @@ static const struct rzv2h_reset r9a09g057_resets[] __initconst = { DEF_RST(10, 13, 4, 30), /* USB2_0_U2H1_HRESETN */ DEF_RST(10, 14, 4, 31), /* USB2_0_U2P_EXL_SYSRST */ DEF_RST(10, 15, 5, 0), /* USB2_0_PRESETN */ + DEF_RST(11, 0, 5, 1), /* GBETH_0_ARESETN_I */ + DEF_RST(11, 1, 5, 2), /* GBETH_1_ARESETN_I */ DEF_RST(12, 5, 5, 22), /* CRU_0_PRESETN */ DEF_RST(12, 6, 5, 23), /* CRU_0_ARESETN */ DEF_RST(12, 7, 5, 24), /* CRU_0_S_RESETN */ diff --git a/drivers/clk/renesas/rzv2h-cpg.h b/drivers/clk/renesas/rzv2h-cpg.h index 0277871e298b..2250436c4c24 100644 --- a/drivers/clk/renesas/rzv2h-cpg.h +++ b/drivers/clk/renesas/rzv2h-cpg.h @@ -81,10 +81,13 @@ struct smuxed { .width = _width, \ }) +#define CPG_SSEL0 (0x300) +#define CPG_SSEL1 (0x304) #define CPG_CDDIV0 (0x400) #define CPG_CDDIV1 (0x404) #define CPG_CDDIV3 (0x40C) #define CPG_CDDIV4 (0x410) +#define CPG_CSDIV0 (0x500) #define CDDIV0_DIVCTL1 DDIV_PACK(CPG_CDDIV0, 4, 3, 1) #define CDDIV0_DIVCTL2 DDIV_PACK(CPG_CDDIV0, 8, 3, 2) @@ -99,6 +102,14 @@ struct smuxed { #define CDDIV4_DIVCTL1 DDIV_PACK(CPG_CDDIV4, 4, 1, 17) #define CDDIV4_DIVCTL2 DDIV_PACK(CPG_CDDIV4, 8, 1, 18) +#define CSDIV0_DIVCTL0 DDIV_PACK(CPG_CSDIV0, 0, 2, CSDIV_NO_MON) +#define CSDIV0_DIVCTL1 DDIV_PACK(CPG_CSDIV0, 4, 2, CSDIV_NO_MON) + +#define SSEL0_SELCTL2 SMUX_PACK(CPG_SSEL0, 8, 1) +#define SSEL0_SELCTL3 SMUX_PACK(CPG_SSEL0, 12, 1) +#define SSEL1_SELCTL0 SMUX_PACK(CPG_SSEL1, 0, 1) +#define SSEL1_SELCTL1 SMUX_PACK(CPG_SSEL1, 4, 1) + #define BUS_MSTOP_IDX_MASK GENMASK(31, 16) #define BUS_MSTOP_BITS_MASK GENMASK(15, 0) #define BUS_MSTOP(idx, mask) (FIELD_PREP_CONST(BUS_MSTOP_IDX_MASK, (idx)) | \