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pr=C From: Ayan Kumar Halder To: CC: Ayan Kumar Halder , Stefano Stabellini , Julien Grall , Bertrand Marquis , Michal Orzel , "Volodymyr Babchuk" Subject: [PATCH v3 1/5] xen/arm32: Move MM specific registers to enable_mmu Date: Sun, 30 Mar 2025 19:03:04 +0100 Message-ID: <20250330180308.2551195-2-ayan.kumar.halder@amd.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20250330180308.2551195-1-ayan.kumar.halder@amd.com> References: <20250330180308.2551195-1-ayan.kumar.halder@amd.com> MIME-Version: 1.0 Received-SPF: None (SATLEXMB04.amd.com: ayan.kumar.halder@amd.com does not designate permitted sender hosts) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: BN2PEPF0000449F:EE_|IA1PR12MB7613:EE_ X-MS-Office365-Filtering-Correlation-Id: ab7244cc-19ba-4514-3b60-08dd6fb5340d X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|1800799024|376014|34020700016|82310400026|36860700013; X-Microsoft-Antispam-Message-Info: FCIx6vYTTxQp9alDw6jTNubJTzB6Y23K+S/oN8U3TS/oqO6OXvzpZAFPkVUvgqDHVUNc4GxmhyBYOMRNRwDjK0sATrWMg75vF9xiOiK44PfA63jPY8WgjbkveJsE48sSGCiRBvrHo57nWVp5C6oN9UiX+PtzoQ7X18hEJAEfNnhfTggRqZ3YeutMmrW7Nl+L70xTH4zOhn86VEDUweFlA4yDYNoCpmiMo44xLd0HqESdCVaSpisESGzbTuAMJqUMgLaD3VaPpkZT8PmG+MBNzNgzI3Peg49ShYQsdeXGNjaEYYoq0Amb3HvMo/H7htG+Q1hdxlUrTAH18Y5In+27qnFfHfuKVSvYq16TA9LmHuW2MdjQCjM1P4tn+yNOArGAJ1eIe99sgtjEYlUIbfvIuv1V1PY0V2FCH4s+hacFRBonmMIo7TEJxXwyfKvWTxW+amZVIIaBCCRY9wb1OUKtJ/IB1vLImU2avf3nqaEyokohOM1PE3uf6KTNqjMhnBr/zF/cK5GKOOzcb4u36nUu+c0pgMCgClHWS5aCB/QzwKZNM+xhqvG2NwQvrW+RiSNkK6SY9/MC6UatNAZZAWjBI3/NjBkligr/vuSg6VqNyto5Ro+QrOzAUTcL3iWwe4PSFXDxF9+eYABjuhce3AvhBnadJ8F3q02vCgm3Tn50X9EMCDT7zsyPmfhscdSNUjXiAkh5EcfcpJCjnxH+Cp0gwYtdHs/uT8PaCBTCVC0NTv2cj83XiY8WZdnz/ODQe7E8MmqLWEEKUTQ7tvus6u7OpcR/IjuZpr1fLecuXxDVoXCfzE/0om1Q+TdHaQ4EjNGxdcp0ym8GQ9DyA1rQOGoSD5xPEUoHfgGv+nPW70pj9eKnZcIAMkLSAlvYsT+4arwZgJuYa6NynlQy+JmqwO3fuFTvl5UhJvu8SjFS0BkiaD0O4WeNF1ZmObYpsSEyBsB24iTHZnBeIXWtfy0GkzqL9cjq1xgs3thejOglZLF1Xhgaob9jn+sHWTCkh6iOpLR3DR2bWwkvDzYl2wEiFQ7k1mDkOXtufgkP3TUXvHOLno7kVh479IGLhEom478CcuX+o17KkCyD/94zlDzXQX+X3+ihxf87Y2A7lLJyRg7F1t2qEtr0W0g3FUDeuc6HzNksJ7K4KtCPyjZHdPlEiohBUHxQMJdewcYPLs4CiSAQc95/3VKCB5Gu2pZkv9e3Xz/KB4xfTOt6HkllR+EDUpYWUYud8EmdYYA7Ahm/74EQhBH7ZRfDR9CWbGHxECZn05w+khUMi2QH7HbFCpEvWYwh7FDurR/4MwUAwv4zo9mHUTIDHu1hJARTRl8m5P13WJlewCW/T5ejLs2K9H7AJHYLNJjIUOwK5hNat0kiAXEilD9jlyk1bYIptT5ZqDnRzR+C3ZWzoYm6jnwV1d69Ue8OC73jgVazHuylrL1ZHG9BCEqpPpRCDmCIH/Htb+WA0VWi65G51ILlD5nkHnoZ+XdKRA== X-Forefront-Antispam-Report: CIP:165.204.84.17;CTRY:US;LANG:en;SCL:1;SRV:;IPV:CAL;SFV:NSPM;H:SATLEXMB04.amd.com;PTR:InfoDomainNonexistent;CAT:NONE;SFS:(13230040)(1800799024)(376014)(34020700016)(82310400026)(36860700013);DIR:OUT;SFP:1101; X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 30 Mar 2025 18:03:40.9055 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: ab7244cc-19ba-4514-3b60-08dd6fb5340d X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: BN2PEPF0000449F.namprd02.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: IA1PR12MB7613 All the memory management specific registers are initialized in enable_mmu. Signed-off-by: Ayan Kumar Halder Reviewed-by: Michal Orzel --- Changes from - v1 - HTCR and HMAIR{0,1} are not set together with the other memory management registers in enable_mmu() Similar changes are to be done in arm64 as well. I prefer to do that in a separate patch so that all the arm32 changes are kept together in this series. v2 - Added Michal's R-b. xen/arch/arm/arm32/head.S | 14 -------------- xen/arch/arm/arm32/mmu/head.S | 15 +++++++++++++++ 2 files changed, 15 insertions(+), 14 deletions(-) diff --git a/xen/arch/arm/arm32/head.S b/xen/arch/arm/arm32/head.S index 4ff5c220bc..50da179f81 100644 --- a/xen/arch/arm/arm32/head.S +++ b/xen/arch/arm/arm32/head.S @@ -218,20 +218,6 @@ cpu_init: add pc, r1, r10 /* Call paddr(init func) */ cpu_init_done: - /* Set up memory attribute type tables */ - mov_w r0, MAIR0VAL - mov_w r1, MAIR1VAL - mcr CP32(r0, HMAIR0) - mcr CP32(r1, HMAIR1) - - /* - * Set up the HTCR: - * PT walks use Inner-Shareable accesses, - * PT walks are write-back, write-allocate in both cache levels, - * Full 32-bit address space goes through this table. - */ - mov_w r0, (TCR_RES1|TCR_SH0_IS|TCR_ORGN0_WBWA|TCR_IRGN0_WBWA|TCR_T0SZ(0)) - mcr CP32(r0, HTCR) mov_w r0, HSCTLR_SET mcr CP32(r0, HSCTLR) diff --git a/xen/arch/arm/arm32/mmu/head.S b/xen/arch/arm/arm32/mmu/head.S index 1e2bbf0c82..8fa74bd556 100644 --- a/xen/arch/arm/arm32/mmu/head.S +++ b/xen/arch/arm/arm32/mmu/head.S @@ -279,6 +279,21 @@ ENDPROC(create_page_tables) enable_mmu: PRINT("- Turning on paging -\r\n") + /* Set up memory attribute type tables */ + mov_w r0, MAIR0VAL + mov_w r1, MAIR1VAL + mcr CP32(r0, HMAIR0) + mcr CP32(r1, HMAIR1) + + /* + * Set up the HTCR: + * PT walks use Inner-Shareable accesses, + * PT walks are write-back, write-allocate in both cache levels, + * Full 32-bit address space goes through this table. + */ + mov_w r0, (TCR_RES1|TCR_SH0_IS|TCR_ORGN0_WBWA|TCR_IRGN0_WBWA|TCR_T0SZ(0)) + mcr CP32(r0, HTCR) + /* * The state of the TLBs is unknown before turning on the MMU. * Flush them to avoid stale one. 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pr=C From: Ayan Kumar Halder To: CC: Ayan Kumar Halder , Stefano Stabellini , Julien Grall , Bertrand Marquis , Michal Orzel , "Volodymyr Babchuk" Subject: [PATCH v3 2/5] xen/arm: Move some of the functions to common file Date: Sun, 30 Mar 2025 19:03:05 +0100 Message-ID: <20250330180308.2551195-3-ayan.kumar.halder@amd.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20250330180308.2551195-1-ayan.kumar.halder@amd.com> References: <20250330180308.2551195-1-ayan.kumar.halder@amd.com> MIME-Version: 1.0 Received-SPF: None (SATLEXMB03.amd.com: ayan.kumar.halder@amd.com does not designate permitted sender hosts) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: DS3PEPF000099E0:EE_|MW6PR12MB8914:EE_ X-MS-Office365-Filtering-Correlation-Id: dff695b6-cadb-4940-3dc3-08dd6fb5358d X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|82310400026|376014|1800799024|36860700013|34020700016; X-Microsoft-Antispam-Message-Info: zcS8sBshQJXqsHS33c0n7lSFsKrzOJWQqneMvAEaQkq/J7zUWb8G0hDT/gqp/rY1eLZo/TlT/jLYATHHtGjHcUgFTEgrC84vMdu25TEfa3fDlgQyOr77FLD3tseQoFGtUQIOvYCO7UxPYNsdHgvLp/FkbRMqgHJmbB+bDcO765r9QjmFxOeZOuiMFKkd1+IPza+QmErSU1yKPOPpwOSXg5PYsrytjFIsKVRH71UMZZdenCgG6XTw5dncExu8K8dJ8UdZ0eXB57SgGM7C4Hc3bzu7Pl6gJQJSlVLv5kLUkjMZuEPGwBoPyaXNRBqd2RZoztaHA74uXMWu1AZW7KWo+ucWBza7Lqp9BXV51+8b5rMUx5p4vp/YheqU2B1vyQ8RsIWQh/+wIGw3lDQWOqmGaenvTe+pjQUYYjFFcjvSPJ8Bmf6EJXqWXpe4BeQ2uVtN3+O4jINJhU4L1lNRFznU/HMS4qE+6IBG1Qc9bLogyxKXHbqGPjxOnr6IleYuPR3gIv1MJ7qzY5CxwxelYs8gddWHPmVwC9mN6ErxCtcb6tZa4n/s2s9rx7imamSbxhNQqQ7wHNu3cjtFFzKXdfvhXAI2zBZLzAHPT5fAS/TJ8lWYOBLN2eHpI9hv6x9Ib6d4jDCsNvpqtEVKy80rA7VBE0FjpUOJOArnYBZP9oz6u2M3Jbh3eR2RrRlli15/f0NNk8CKg3KmWnOGZ+V6LaqGyIsm2LJtSMf98q++cSdNIlhw3RzeT1qMp4K55nTL5FHA1z1CjdIKpeTxdDldbSv9v8mW5j36gdiIoqpO1ekYAMb5ZG6bMC+xpe28UC+znldq9wtrW9BVBk2i3URK82wY8xlpJjgh9iaIgMbti3j60h2pfeaGf7rx4h27otAUbsl5LQ0FwZaeTZfuQ3pMZofSKhff9tiID2kNKx3AVCYg5U8ZXXwON6t3tWJ0p9Gu8V1MzT9ju864G2FstZOKeaJsDPOzEt+RQ62xep5HYU63B8cBRZvzfBo/nl/MvZxzJ2VbOYJw9EdoQFs5/FZpygaZ0sqDJ0OEjaPleSBBEQ39mw75d+yQvY7ntLyAIYWw4A7EaCieHTcyHW0bHc1EtEHtcUciYlypGEDj0aGG5sCqd5lFJoUiOGYb5QV9obHEsd7ssZWiTadnSRwI6ZH+AK8tfHcAa1QP39d/aaiae6hv7lb7c+gmGXz29SgB1QG65x4f9KswBYTW4G8FqLcTtG5j5Km7emZJOoxTt67uLqQJ4sZH7idAo1Pn50oCR20rNVJZj1W8iXBGPXZ6Xdj/eIRBFMLEe5ww9rlJM1QxFHNOfH1kszHLdPc2c9KxcAVn4L2gfBA1Uz/MryxWkcJChi/k84ES525f+27MWma14F6XHEx3d1AP9fswZS+A8sVY9jMb4uR2iTDRr+WmR//u+8LBlZx2jj+AryMewxynklhtLkCdGSp+O2IaJqkeEkVWmobjmH7/jdCgMKx6hrf59Xme3O7XXSHKQ0ZnxyEJopCibU1TA+sWZJZN2u+m6WkStatT X-Forefront-Antispam-Report: CIP:165.204.84.17;CTRY:US;LANG:en;SCL:1;SRV:;IPV:CAL;SFV:NSPM;H:SATLEXMB03.amd.com;PTR:InfoDomainNonexistent;CAT:NONE;SFS:(13230040)(82310400026)(376014)(1800799024)(36860700013)(34020700016);DIR:OUT;SFP:1101; X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 30 Mar 2025 18:03:43.3909 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: dff695b6-cadb-4940-3dc3-08dd6fb5358d X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB03.amd.com] X-MS-Exchange-CrossTenant-AuthSource: DS3PEPF000099E0.namprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: MW6PR12MB8914 Added a new file prepare_xen_region.inc to hold the common earlyboot MPU regions configurations across arm64 and arm32. prepare_xen_region, enable_boot_cpu, fail_insufficient_regions() will be used by both arm32 and arm64. Thus, they have been moved to prepare_xen_region.inc. REGION_* are moved to arm64/sysregs.h. Introduced LOAD_SYSREG and STORE_SYSREG to read/write to the system registers from the common asm file. One could not reuse READ_SYSREG and WRITE_SYSREG as they have been defined to be invoked from C files. Signed-off-by: Ayan Kumar Halder --- Changes from v1 - 1. enable_mpu() now sets HMAIR{0,1} registers. This is similar to what is being done in enable_mmu(). All the mm related configurations happen in this function. 2. Fixed some typos. v2 - 1. Extracted the arm64 head.S functions/macros in a common file. xen/arch/arm/arm64/mpu/head.S | 132 +----------------- xen/arch/arm/include/asm/arm64/sysregs.h | 15 ++ .../include/asm/mpu/prepare_xen_region.inc | 128 +++++++++++++++++ 3 files changed, 148 insertions(+), 127 deletions(-) create mode 100644 xen/arch/arm/include/asm/mpu/prepare_xen_region.inc diff --git a/xen/arch/arm/arm64/mpu/head.S b/xen/arch/arm/arm64/mpu/head.S index 4d00de4869..90b4c8c18f 100644 --- a/xen/arch/arm/arm64/mpu/head.S +++ b/xen/arch/arm/arm64/mpu/head.S @@ -3,83 +3,7 @@ * Start-of-day code for an Armv8-R MPU system. */ -#include -#include - -/* Backgroud region enable/disable */ -#define SCTLR_ELx_BR BIT(17, UL) - -#define REGION_TEXT_PRBAR 0x38 /* SH=11 AP=10 XN=00 */ -#define REGION_RO_PRBAR 0x3A /* SH=11 AP=10 XN=10 */ -#define REGION_DATA_PRBAR 0x32 /* SH=11 AP=00 XN=10 */ -#define REGION_DEVICE_PRBAR 0x22 /* SH=10 AP=00 XN=10 */ - -#define REGION_NORMAL_PRLAR 0x0f /* NS=0 ATTR=111 EN=1 */ -#define REGION_DEVICE_PRLAR 0x09 /* NS=0 ATTR=100 EN=1 */ - -/* - * Macro to prepare and set a EL2 MPU memory region. - * We will also create an according MPU memory region entry, which - * is a structure of pr_t, in table \prmap. - * - * sel: region selector - * base: reg storing base address - * limit: reg storing limit address - * prbar: store computed PRBAR_EL2 value - * prlar: store computed PRLAR_EL2 value - * maxcount: maximum number of EL2 regions supported - * attr_prbar: PRBAR_EL2-related memory attributes. If not specified it will be - * REGION_DATA_PRBAR - * attr_prlar: PRLAR_EL2-related memory attributes. If not specified it will be - * REGION_NORMAL_PRLAR - * - * Preserves \maxcount - * Output: - * \sel: Next available region selector index. - * Clobbers \base, \limit, \prbar, \prlar - * - * Note that all parameters using registers should be distinct. - */ -.macro prepare_xen_region, sel, base, limit, prbar, prlar, maxcount, attr_prbar=REGION_DATA_PRBAR, attr_prlar=REGION_NORMAL_PRLAR - /* Check if the region is empty */ - cmp \base, \limit - beq 1f - - /* Check if the number of regions exceeded the count specified in MPUIR_EL2 */ - cmp \sel, \maxcount - bge fail_insufficient_regions - - /* Prepare value for PRBAR_EL2 reg and preserve it in \prbar.*/ - and \base, \base, #MPU_REGION_MASK - mov \prbar, #\attr_prbar - orr \prbar, \prbar, \base - - /* Limit address should be inclusive */ - sub \limit, \limit, #1 - and \limit, \limit, #MPU_REGION_MASK - mov \prlar, #\attr_prlar - orr \prlar, \prlar, \limit - - msr PRSELR_EL2, \sel - isb - msr PRBAR_EL2, \prbar - msr PRLAR_EL2, \prlar - dsb sy - isb - - add \sel, \sel, #1 - -1: -.endm - -/* - * Failure caused due to insufficient MPU regions. - */ -FUNC_LOCAL(fail_insufficient_regions) - PRINT("- Selected MPU region is above the implemented number in MPUIR_EL2 -\r\n") -1: wfe - b 1b -END(fail_insufficient_regions) +#include /* * Enable EL2 MPU and data cache @@ -108,62 +32,16 @@ END(enable_mpu) * Maps the various sections of Xen (described in xen.lds.S) as different MPU * regions. * - * Clobbers x0 - x5 + * Clobbers x0 - x6 * */ FUNC(enable_boot_cpu_mm) - /* Get the number of regions specified in MPUIR_EL2 */ - mrs x5, MPUIR_EL2 - and x5, x5, #NUM_MPU_REGIONS_MASK - - /* x0: region sel */ - mov x0, xzr - /* Xen text section. */ - ldr x1, =_stext - ldr x2, =_etext - prepare_xen_region x0, x1, x2, x3, x4, x5, attr_prbar=REGION_TEXT_PRBAR - - /* Xen read-only data section. */ - ldr x1, =_srodata - ldr x2, =_erodata - prepare_xen_region x0, x1, x2, x3, x4, x5, attr_prbar=REGION_RO_PRBAR - - /* Xen read-only after init and data section. (RW data) */ - ldr x1, =__ro_after_init_start - ldr x2, =__init_begin - prepare_xen_region x0, x1, x2, x3, x4, x5 - - /* Xen code section. */ - ldr x1, =__init_begin - ldr x2, =__init_data_begin - prepare_xen_region x0, x1, x2, x3, x4, x5, attr_prbar=REGION_TEXT_PRBAR - - /* Xen data and BSS section. */ - ldr x1, =__init_data_begin - ldr x2, =__bss_end - prepare_xen_region x0, x1, x2, x3, x4, x5 - -#ifdef CONFIG_EARLY_PRINTK - /* Xen early UART section. */ - ldr x1, =CONFIG_EARLY_UART_BASE_ADDRESS - ldr x2, =(CONFIG_EARLY_UART_BASE_ADDRESS + CONFIG_EARLY_UART_SIZE) - prepare_xen_region x0, x1, x2, x3, x4, x5, attr_prbar=REGION_DEVICE_PRBAR, attr_prlar=REGION_DEVICE_PRLAR -#endif - - b enable_mpu + mov x6, lr + enable_boot_cpu x0, x1, x2, x3, x4, x5 + mov lr, x6 ret END(enable_boot_cpu_mm) -/* - * We don't yet support secondary CPUs bring-up. Implement a dummy helper to - * please the common code. - */ -ENTRY(enable_secondary_cpu_mm) - PRINT("- SMP not enabled yet -\r\n") -1: wfe - b 1b -ENDPROC(enable_secondary_cpu_mm) - /* * Local variables: * mode: ASM diff --git a/xen/arch/arm/include/asm/arm64/sysregs.h b/xen/arch/arm/include/asm/arm64/sysregs.h index b593e4028b..9b833fe73b 100644 --- a/xen/arch/arm/include/asm/arm64/sysregs.h +++ b/xen/arch/arm/include/asm/arm64/sysregs.h @@ -462,6 +462,19 @@ #define ZCR_ELx_LEN_SIZE 9 #define ZCR_ELx_LEN_MASK 0x1ff +#define REGION_TEXT_PRBAR 0x38 /* SH=11 AP=10 XN=00 */ +#define REGION_RO_PRBAR 0x3A /* SH=11 AP=10 XN=10 */ +#define REGION_DATA_PRBAR 0x32 /* SH=11 AP=00 XN=10 */ +#define REGION_DEVICE_PRBAR 0x22 /* SH=10 AP=00 XN=10 */ + +#define REGION_NORMAL_PRLAR 0x0f /* NS=0 ATTR=111 EN=1 */ +#define REGION_DEVICE_PRLAR 0x09 /* NS=0 ATTR=100 EN=1 */ + +#define STORE_SYSREG(v, name) "msr " __stringify(name,) #v; +#define LOAD_SYSREG(v, name) "mrs " #v __stringify(,) #name; + +#ifndef __ASSEMBLY__ + /* Access to system registers */ #define WRITE_SYSREG64(v, name) do { \ @@ -481,6 +494,8 @@ #define WRITE_SYSREG_LR(v, index) WRITE_SYSREG(v, ICH_LR_REG(index)) #define READ_SYSREG_LR(index) READ_SYSREG(ICH_LR_REG(index)) +#endif /* __ASSEMBLY__ */ + #endif /* _ASM_ARM_ARM64_SYSREGS_H */ /* diff --git a/xen/arch/arm/include/asm/mpu/prepare_xen_region.inc b/xen/arch/arm/include/asm/mpu/prepare_xen_region.inc new file mode 100644 index 0000000000..3402ed23da --- /dev/null +++ b/xen/arch/arm/include/asm/mpu/prepare_xen_region.inc @@ -0,0 +1,128 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include +#include + +/* Backgroud region enable/disable */ +#define SCTLR_ELx_BR BIT(17, UL) + +/* + * Macro to prepare and set a EL2 MPU memory region. + * We will also create an according MPU memory region entry, which + * is a structure of pr_t, in table \prmap. + * + * sel: region selector + * base: reg storing base address + * limit: reg storing limit address + * prbar: store computed PRBAR_EL2 value + * prlar: store computed PRLAR_EL2 value + * maxcount: maximum number of EL2 regions supported + * attr_prbar: PRBAR_EL2-related memory attributes. If not specified it will be + * REGION_DATA_PRBAR + * attr_prlar: PRLAR_EL2-related memory attributes. If not specified it will be + * REGION_NORMAL_PRLAR + * + * Preserves maxcount + * Output: + * sel: Next available region selector index. + * Clobbers base, limit, prbar, prlar + * + * Note that all parameters using registers should be distinct. + */ +.macro prepare_xen_region, sel, base, limit, prbar, prlar, maxcount, attr_prbar=REGION_DATA_PRBAR, attr_prlar=REGION_NORMAL_PRLAR + /* Check if the region is empty */ + cmp \base, \limit + beq 1f + + /* Check if the number of regions exceeded the count specified in MPUIR_EL2 */ + cmp \sel, \maxcount + bge fail_insufficient_regions + + /* Prepare value for PRBAR_EL2 reg and preserve it in \prbar.*/ + and \base, \base, #MPU_REGION_MASK + mov \prbar, #\attr_prbar + orr \prbar, \prbar, \base + + /* Limit address should be inclusive */ + sub \limit, \limit, #1 + and \limit, \limit, #MPU_REGION_MASK + mov \prlar, #\attr_prlar + orr \prlar, \prlar, \limit + + STORE_SYSREG(\sel, PRSELR_EL2) + isb + STORE_SYSREG(\prbar, PRBAR_EL2) + STORE_SYSREG(\prlar, PRLAR_EL2) + dsb sy + isb + + add \sel, \sel, #1 + +1: +.endm + +.macro enable_boot_cpu, reg0, reg1, reg2, reg3, reg4, reg5 + /* Get the number of regions specified in MPUIR_EL2 */ + LOAD_SYSREG(\reg5, MPUIR_EL2) + and \reg5, \reg5, #NUM_MPU_REGIONS_MASK + + /* reg0: region sel */ + mov \reg0, #0 + /* Xen text section. */ + ldr \reg1, =_stext + ldr \reg2, =_etext + prepare_xen_region \reg0, \reg1, \reg2, \reg3, \reg4, \reg5, attr_prbar=REGION_TEXT_PRBAR + + /* Xen read-only data section. */ + ldr \reg1, =_srodata + ldr \reg2, =_erodata + prepare_xen_region \reg0, \reg1, \reg2, \reg3, \reg4, \reg5, attr_prbar=REGION_RO_PRBAR + + /* Xen read-only after init and data section. (RW data) */ + ldr \reg1, =__ro_after_init_start + ldr \reg2, =__init_begin + prepare_xen_region \reg0, \reg1, \reg2, \reg3, \reg4, \reg5 + + /* Xen code section. */ + ldr \reg1, =__init_begin + ldr \reg2, =__init_data_begin + prepare_xen_region \reg0, \reg1, \reg2, \reg3, \reg4, \reg5, attr_prbar=REGION_TEXT_PRBAR + + /* Xen data and BSS section. */ + ldr \reg1, =__init_data_begin + ldr \reg2, =__bss_end + prepare_xen_region \reg0, \reg1, \reg2, \reg3, \reg4, \reg5 + +#ifdef CONFIG_EARLY_PRINTK + /* Xen early UART section. */ + ldr \reg1, =CONFIG_EARLY_UART_BASE_ADDRESS + ldr \reg2, =(CONFIG_EARLY_UART_BASE_ADDRESS + CONFIG_EARLY_UART_SIZE) + prepare_xen_region \reg0, \reg1, \reg2, \reg3, \reg4, \reg5, attr_prbar=REGION_DEVICE_PRBAR, attr_prlar=REGION_DEVICE_PRLAR +#endif + + bl enable_mpu +.endm + +/* Failure caused due to insufficient MPU regions. */ +FUNC_LOCAL(fail_insufficient_regions) + PRINT("- Selected MPU region is above the implemented number in MPUIR_EL2 -\r\n") +1: wfe + b 1b +END(fail_insufficient_regions) + +/* + * We don't yet support secondary CPUs bring-up. Implement a dummy helper to + * please the common code. + */ +ENTRY(enable_secondary_cpu_mm) + PRINT("- SMP not enabled yet -\r\n") +1: wfe + b 1b +ENDPROC(enable_secondary_cpu_mm) + +/* + * Local variables: + * mode: ASM + * indent-tabs-mode: nil + * End: + */ From patchwork Sun Mar 30 18:03:06 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ayan Kumar Halder X-Patchwork-Id: 14032989 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.xenproject.org (lists.xenproject.org [192.237.175.120]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 19FB0C36014 for ; Sun, 30 Mar 2025 18:04:06 +0000 (UTC) Received: from list by lists.xenproject.org with outflank-mailman.931678.1333895 (Exim 4.92) (envelope-from ) id 1tyx0m-0005RS-FN; Sun, 30 Mar 2025 18:03:56 +0000 X-Outflank-Mailman: Message body and most headers restored to incoming version Received: by outflank-mailman (output) from mailman id 931678.1333895; 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pr=C From: Ayan Kumar Halder To: CC: Ayan Kumar Halder , Stefano Stabellini , Julien Grall , Bertrand Marquis , Michal Orzel , "Volodymyr Babchuk" Subject: [PATCH v3 3/5] xen/arm32: Create the same boot-time MPU regions as arm64 Date: Sun, 30 Mar 2025 19:03:06 +0100 Message-ID: <20250330180308.2551195-4-ayan.kumar.halder@amd.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20250330180308.2551195-1-ayan.kumar.halder@amd.com> References: <20250330180308.2551195-1-ayan.kumar.halder@amd.com> MIME-Version: 1.0 Received-SPF: None (SATLEXMB03.amd.com: ayan.kumar.halder@amd.com does not designate permitted sender hosts) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: DS3PEPF000099DD:EE_|PH0PR12MB7885:EE_ X-MS-Office365-Filtering-Correlation-Id: d1873e49-90e6-44ee-9735-08dd6fb536c1 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|1800799024|376014|36860700013|82310400026|34020700016; X-Microsoft-Antispam-Message-Info: qzgPoDHK6pUfDpN0FFh/WrOaih807MqfdcAlqgzQJyIO9pT41Qn0U3FHd7Eoi3G4FPe4KIm189tNYn8OP/944b2VsRhBVmbc+EgOQ8yp24TizbOzZKl/YLIYUsvWaAPHCLjpcxzGToYwchfKnuWoRFletC+gJQoM45WHWHSgmiwWIkuIx8t+Wp5Q7WNdS2myXrK+0PrrglRUQV3Zj2WVGVeNAjSneMraGkJWx/3j7xArJopNt4+8YdV1ufAkHVOvmnVWNOr6c73iHfimXG8fkhvsA+VPCTqHOK5JarsAMQQu31ggmcEn3btgBhaexZT+T5F22xOEQmEVRJKFNHLDmpXjjdNXnIbH2BgeFo6msW4AgseH2rRFVIsHwUnI24O/DcajNeomqgQhmYkESES8m6MWwxf3Zyp12mHNYMwxnW8Oz3v2bBvnR++KuCrDUoUcpRlHHUAuXqkochpPrrlc5DnRiib9ZgQ/LYSnzVFMQiXJTV7saxQ0jXL7CZFea/cW/025xTCtEqPTyXtyOMWisjgcdyRf9T6han/fwZaqhhEFZmw7p44vRamieairn+/1s8RLYHz2B1b4OqKfaYuvo3y9nggDGZhxfpHXdisd+w1Qed9ZhZ2x5ohep9q8JIKCfN+UTOt8dzUbSBjtIehRM37MsTWKdOKJ1/5qpfmaaR5GEPY0LOKqWEhcKxYK6O1/3eKdbMAMw8SFIyYmacpE5SSCdX0gu+FFhWqNAzZEEc1G8g33vh4pqb18GG2ax+/9WjGy9Jm/dxole01uYnVHP1OzuOlr0gnsOGpbJowIHxh+JuQ5OwCBy2mrXaKjwY9ffk0TxpRH+3YopS2ZaUcQxIHsD7fqFjHKQKbwcTjRB0VrCT/oVNBPaf3JnnCdgc58bwYrrxxXmWYQ2AwnwOSaixvNDFP/jIwh/+K/Ao36wEzHVGwl2DU/sS7AjjPwh8mVYDbP7ZOWMZJhu/tY9WApssIVsJhVbXtdr2TesUDdnsdi5OTYk+fw2f70H3PX2zDRIotB+ikG38Oh7oFZNnJdKZOC0Vx+ywIrRvYv+O0yuzGnBkgu+ibmSmTyGRA88G4imyXe+U9goZBze3kqx6pc1k36KxXkG/nvp5fmSliSjSxToFemLVLO5tFlnQOOOeji1dxKmlWvJPvoqTuk+k3A2O9Iar9n48Z/TOHxtOfP1gc/CgL64SWONcrQ0nH/d0XR6kSCqmliWgVDh5SAwCe/QEIKaMleJ8QomeJBDtTUv2j0luJ3onLK/AdNoauD+q857eUEY1inX7hUJjlcCVcrxP5/ygENUzWJaDykX+QiajC/GoUDf+vsm93IUfYaARzRiGp3miqXBtLjHCT0ppKclBuwBFQ/gYqwJE+0PsfHtz3qdP+jWSRCVqfU/dTdmw4U6BiSu7h/BV1F25soE2ATYz6qcAcSqV2Rv/uvzpfAenwM0/bEb+sbG5cjIYQmdBBHoCF020F6h9SWa3Ij34eRcWTiWgVzSvrGA3urQBuwVHHwG/PAD88WDFbMok27inkQ X-Forefront-Antispam-Report: CIP:165.204.84.17;CTRY:US;LANG:en;SCL:1;SRV:;IPV:CAL;SFV:NSPM;H:SATLEXMB03.amd.com;PTR:InfoDomainNonexistent;CAT:NONE;SFS:(13230040)(1800799024)(376014)(36860700013)(82310400026)(34020700016);DIR:OUT;SFP:1101; X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 30 Mar 2025 18:03:45.4117 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: d1873e49-90e6-44ee-9735-08dd6fb536c1 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB03.amd.com] X-MS-Exchange-CrossTenant-AuthSource: DS3PEPF000099DD.namprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: PH0PR12MB7885 We have created the same boot-time MPU protection regions as Armv8-R AArch64. Also, we have defined REGION_* macros for arm32. The only difference from arm64 is that XN is 1-bit for arm32. The macros have been defined in arm32/sysregs.h. Though REGION_NORMAL_PRLAR and REGION_DEVICE_PRLAR are same between arm32 and arm64, we have duplicated them to keep the definitions at the same place as the other REGION_* macros. Signed-off-by: Ayan Kumar Halder --- Changes from v1 - 1. enable_mpu() now sets HMAIR{0,1} registers. This is similar to what is being done in enable_mmu(). All the mm related configurations happen in this function. 2. Fixed some typos. v2 - 1. Include the common prepare_xen_region.inc in head.S. 2. Define LOAD_SYSREG()/STORE_SYSREG() for arm32. xen/arch/arm/arm32/Makefile | 1 + xen/arch/arm/arm32/mpu/Makefile | 1 + xen/arch/arm/arm32/mpu/head.S | 52 ++++++++++++++++++++++++ xen/arch/arm/include/asm/arm32/sysregs.h | 11 +++++ xen/arch/arm/include/asm/cpregs.h | 4 ++ xen/arch/arm/include/asm/mpu/cpregs.h | 23 +++++++++++ 6 files changed, 92 insertions(+) create mode 100644 xen/arch/arm/arm32/mpu/Makefile create mode 100644 xen/arch/arm/arm32/mpu/head.S create mode 100644 xen/arch/arm/include/asm/mpu/cpregs.h diff --git a/xen/arch/arm/arm32/Makefile b/xen/arch/arm/arm32/Makefile index 40a2b4803f..537969d753 100644 --- a/xen/arch/arm/arm32/Makefile +++ b/xen/arch/arm/arm32/Makefile @@ -1,5 +1,6 @@ obj-y += lib/ obj-$(CONFIG_MMU) += mmu/ +obj-$(CONFIG_MPU) += mpu/ obj-$(CONFIG_EARLY_PRINTK) += debug.o obj-y += domctl.o diff --git a/xen/arch/arm/arm32/mpu/Makefile b/xen/arch/arm/arm32/mpu/Makefile new file mode 100644 index 0000000000..3340058c08 --- /dev/null +++ b/xen/arch/arm/arm32/mpu/Makefile @@ -0,0 +1 @@ +obj-y += head.o diff --git a/xen/arch/arm/arm32/mpu/head.S b/xen/arch/arm/arm32/mpu/head.S new file mode 100644 index 0000000000..30c901525a --- /dev/null +++ b/xen/arch/arm/arm32/mpu/head.S @@ -0,0 +1,52 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Start-of-day code for an Armv8-R MPU system. + */ + +#include +#include + +/* + * Set up the memory attribute type tables and enable EL2 MPU and data cache. + * If the Background region is enabled, then the MPU uses the default memory + * map as the Background region for generating the memory + * attributes when MPU is disabled. + * Since the default memory map of the Armv8-R AArch32 architecture is + * IMPLEMENTATION DEFINED, we intend to turn off the Background region here. + * + * Clobbers r0 - r1 + */ +FUNC_LOCAL(enable_mpu) + /* Set up memory attribute type tables */ + mov_w r0, MAIR0VAL + mov_w r1, MAIR1VAL + mcr CP32(r0, HMAIR0) + mcr CP32(r1, HMAIR1) + + mrc CP32(r0, HSCTLR) + bic r0, r0, #SCTLR_ELx_BR /* Disable Background region */ + orr r0, r0, #SCTLR_Axx_ELx_M /* Enable MPU */ + orr r0, r0, #SCTLR_Axx_ELx_C /* Enable D-cache */ + mcr CP32(r0, HSCTLR) + isb + mov pc, lr +END(enable_mpu) + +/* + * Maps the various sections of Xen (decsribed in xen.lds.S) as different MPU + * regions. + * + * Clobbers r0 - r6 + */ +FUNC(enable_boot_cpu_mm) + mov r6, lr + enable_boot_cpu r0, r1, r2, r3, r4, r5 + mov pc, r6 +END(enable_boot_cpu_mm) + +/* + * Local variables: + * mode: ASM + * indent-tabs-mode: nil + * End: + */ diff --git a/xen/arch/arm/include/asm/arm32/sysregs.h b/xen/arch/arm/include/asm/arm32/sysregs.h index 22871999af..e02c0932e6 100644 --- a/xen/arch/arm/include/asm/arm32/sysregs.h +++ b/xen/arch/arm/include/asm/arm32/sysregs.h @@ -4,6 +4,14 @@ #include #include +#define REGION_TEXT_PRBAR 0x18 /* SH=11 AP=10 XN=0 */ +#define REGION_RO_PRBAR 0x1D /* SH=11 AP=10 XN=1 */ +#define REGION_DATA_PRBAR 0x19 /* SH=11 AP=00 XN=1 */ +#define REGION_DEVICE_PRBAR 0x11 /* SH=10 AP=00 XN=1 */ + +#define REGION_NORMAL_PRLAR 0x0f /* NS=0 ATTR=111 EN=1 */ +#define REGION_DEVICE_PRLAR 0x09 /* NS=0 ATTR=100 EN=1 */ + /* Layout as used in assembly, with src/dest registers mixed in */ #define __CP32(r, coproc, opc1, crn, crm, opc2) coproc, opc1, r, crn, crm, opc2 #define __CP64(r1, r2, coproc, opc, crm) coproc, opc, r1, r2, crm @@ -16,6 +24,9 @@ #define LOAD_CP64(r, name...) "mrrc " __stringify(CP64(%r, %H##r, name)) ";" #define STORE_CP64(r, name...) "mcrr " __stringify(CP64(%r, %H##r, name)) ";" +#define LOAD_SYSREG(v, name) mrc CP32(v, name) +#define STORE_SYSREG(v, name) mcr CP32(v, name) + /* Issue a CP operation which takes no argument, * uses r0 as a placeholder register. */ #define CMD_CP32(name...) "mcr " __stringify(CP32(r0, name)) ";" diff --git a/xen/arch/arm/include/asm/cpregs.h b/xen/arch/arm/include/asm/cpregs.h index aec9e8f329..6019a2cbdd 100644 --- a/xen/arch/arm/include/asm/cpregs.h +++ b/xen/arch/arm/include/asm/cpregs.h @@ -1,6 +1,10 @@ #ifndef __ASM_ARM_CPREGS_H #define __ASM_ARM_CPREGS_H +#ifdef CONFIG_MPU +#include +#endif + /* * AArch32 Co-processor registers. * diff --git a/xen/arch/arm/include/asm/mpu/cpregs.h b/xen/arch/arm/include/asm/mpu/cpregs.h new file mode 100644 index 0000000000..cf63730233 --- /dev/null +++ b/xen/arch/arm/include/asm/mpu/cpregs.h @@ -0,0 +1,23 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef __ASM_ARM_MPU_CPREGS_H +#define __ASM_ARM_MPU_CPREGS_H + +#define HMPUIR p15,4,c0,c0,4 + +/* CP15 CR6: MPU Protection Region Base/Limit/Select Address Register */ +#define HPRSELR p15,4,c6,c2,1 +#define PRBAR_EL2 p15,4,c6,c3,0 +#define PRLAR_EL2 p15,4,c6,c8,1 + +#define MPUIR_EL2 HMPUIR +#define PRSELR_EL2 HPRSELR + +#endif /* __ASM_ARM_MPU_CPREGS_H */ + +/* + * Local variables: + * mode: ASM + * indent-tabs-mode: nil + * End: + */ From patchwork Sun Mar 30 18:03:07 2025 Content-Type: text/plain; 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pr=C From: Ayan Kumar Halder To: CC: Michal Orzel , Stefano Stabellini , Julien Grall , Bertrand Marquis , Volodymyr Babchuk , Ayan Kumar Halder Subject: [PATCH v3 4/5] xen/arm32: Allow ARM_PA_BITS_40 only if !MPU Date: Sun, 30 Mar 2025 19:03:07 +0100 Message-ID: <20250330180308.2551195-5-ayan.kumar.halder@amd.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20250330180308.2551195-1-ayan.kumar.halder@amd.com> References: <20250330180308.2551195-1-ayan.kumar.halder@amd.com> MIME-Version: 1.0 Received-SPF: None (SATLEXMB03.amd.com: ayan.kumar.halder@amd.com does not designate permitted sender hosts) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: DS3PEPF000099DD:EE_|IA1PR12MB7542:EE_ X-MS-Office365-Filtering-Correlation-Id: 86f766f5-1af0-41eb-ffc0-08dd6fb537ed X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|82310400026|36860700013|34020700016|1800799024|376014; X-Microsoft-Antispam-Message-Info: gWeIVktA5KcZWgzQHCjH9be00iEH0qkYUZdwjb7PTNAJMpJ2mwwuoUV2zAhwvQ9Iky7a+9AqbuYY3c1bT8uY7YIJy2+daln2oR+TJx+wU69vJSpoYH7stmpNdngrNZPOBtmfXcDhJm89XzMPkEkh9QCqAw0sFo+b3o0b/nNdRkzG5AIsl5KBhfLzefUFOH3ZnC9izb0fuKzMwaIn+CzCIir6wSwyLk3Knl7B1Twhv+gsfW7EyWzry9OjWobozK+D/1EUDz3oxUrxC2371o1VF229E0ekhFJNLpTL1CsILZuFb3lj/Bt42yXpwSDMgKHYEJ3d3wjnIHMCAHUgURBhfMUCzhYeT3bIn2ejLLwlOvdfzCrz7WmAfjC2W9CCH15YlasCNlLghNjagzjyRxTOxSDY8arc4jFgUy/xvFUeTpUPl7vCXP4grT+DvupokE830cQFJRnspKT4F/J5iveIqWk/+NAxiRCuy/zQyiEI6o1PmzwK3Zslh7WKyIGpW/HmxCbc0AMsIDrrPGr0RwItReUc61TeI7VX3es9Wg733fXhiubOJA8rVFNRBkgnmMp+zgH0uYD2KGh6x06kvPsM5b9yGzwlOGS8ASAgnXb+yjx98+4cWyd7ks4t4qsPsj5c78IiuYrukqX6s5HsFEI+eZP2hDPn5hLbDhFjiwN94zbkBQvNglVukUyaUffgvyit9NLnxqI6fM3FUVOnFsKRYpnEPuXmf2AwluO/F5Fio3mO7/Jy4AHzhzBUAXaZxqch4FiEWOzNhzn9ztSnXyld/qRHa8aHQJA3EqKHTqGjbfEK7cCZKqbo/91X4ZTQuq66D0Wf0qk5Z9er3mkm3QrollRFmwFCFbS+1ZkPMkDBv0FzNstwDeI63OdoqIibagl8L6m+4RPtOIlgu9sr0+DOvW6eLcsC8gQe4vyJxe5zQ1CmUcWYSdMF4+38lXUQupc4AnR7SQRhmzqeDzClIY4Bn90ujBEd/PEDm5M8sc5lOG82TWg3TNNYLuUwDPJSUyLQAQ+dOBVnD+x5vbojOlCs8YeyVFlJtLNopG0EVaFukKa3ieNmrDbX15bb2LUFQhYQx7X2gYgrlv9+0z5CMK3Ak/d0eByF7sWTyIo+HJ+fzh/3Zci4sRYQj777TrGrkexYb2e1R2xJyBk2MwJ2cXDrxobbdnvzqcc2hdxfGLZwlaBKcenhdco0ADd1vcgP7TNBK+fkI4wZAbSafhoAmYAdQqNnPImmD6CDXnMRSyzaQXjoJYJE2N9ONVFUKYMokkrTiBetKKaa1h2z0RHz5WJIjcmxJerSq8brycUk+XB+b2MGPQCx984/epFvlH6bNQDTUmgsmdXQ6Zyg+kxRZJS+5aEjA6nSFLVYXpBYwWMqeHOGp6ad2BTJcZc16qpP8UwCn0/rEezp2O72+9Cbih1xjddhM/MpnGYM9iejb8UIYleoHiQ3vNgwHg/4st3o0UyS7NYPo8C/WSthq+klovuXKk3+6gedcmE+OWcEIFIImlA= X-Forefront-Antispam-Report: CIP:165.204.84.17;CTRY:US;LANG:en;SCL:1;SRV:;IPV:CAL;SFV:NSPM;H:SATLEXMB03.amd.com;PTR:InfoDomainNonexistent;CAT:NONE;SFS:(13230040)(82310400026)(36860700013)(34020700016)(1800799024)(376014);DIR:OUT;SFP:1101; X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 30 Mar 2025 18:03:47.3649 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 86f766f5-1af0-41eb-ffc0-08dd6fb537ed X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB03.amd.com] X-MS-Exchange-CrossTenant-AuthSource: DS3PEPF000099DD.namprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: IA1PR12MB7542 From: Michal Orzel ArmV8-R AArch32 does not support LPAE. The reason being PMSAv8-32 supports 32-bit physical address only. Signed-off-by: Michal Orzel Signed-off-by: Ayan Kumar Halder Acked-by: Julien Grall --- Changes from v1 - 1. New patch. v2 - 1. No changes xen/arch/arm/Kconfig | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/xen/arch/arm/Kconfig b/xen/arch/arm/Kconfig index a4af0b85f1..565f288331 100644 --- a/xen/arch/arm/Kconfig +++ b/xen/arch/arm/Kconfig @@ -58,7 +58,7 @@ config ARM_PA_BITS_32 config ARM_PA_BITS_40 bool "40-bit" - depends on ARM_32 + depends on ARM_32 && !MPU endchoice config PADDR_BITS From patchwork Sun Mar 30 18:03:08 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ayan Kumar Halder X-Patchwork-Id: 14032988 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.xenproject.org (lists.xenproject.org [192.237.175.120]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 15CDEC36010 for ; Sun, 30 Mar 2025 18:04:06 +0000 (UTC) Received: from list by lists.xenproject.org with outflank-mailman.931679.1333905 (Exim 4.92) (envelope-from ) id 1tyx0o-0005jE-O4; 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pr=C From: Ayan Kumar Halder To: CC: Ayan Kumar Halder , Stefano Stabellini , Julien Grall , Bertrand Marquis , Michal Orzel , "Volodymyr Babchuk" Subject: [PATCH v3 5/5] xen/arm32: mpu: Stubs to build MPU for arm32 Date: Sun, 30 Mar 2025 19:03:08 +0100 Message-ID: <20250330180308.2551195-6-ayan.kumar.halder@amd.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20250330180308.2551195-1-ayan.kumar.halder@amd.com> References: <20250330180308.2551195-1-ayan.kumar.halder@amd.com> MIME-Version: 1.0 Received-SPF: None (SATLEXMB04.amd.com: ayan.kumar.halder@amd.com does not designate permitted sender hosts) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: BN2PEPF0000449D:EE_|SA5PPFCAFD069B8:EE_ X-MS-Office365-Filtering-Correlation-Id: e997f276-95ae-4b2b-1903-08dd6fb539a6 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|82310400026|376014|1800799024|34020700016|36860700013|13003099007; X-Microsoft-Antispam-Message-Info: 1mJpm3BhczMtwDiezlXpCjTfDrEfppl32JNqYyJLl2kXKZDhcIM6TFdgJpiABaPYdTvXg9Omh3q36rViGf5kDFoicsRD6PrRzk9MKPqBgnbjX248gzRhp9fcs5pHe1x4/hZuZ1j4S8Z/J6vfYLc/mpwuuibos7/4YOt0uM/4H72+PKnvnTERjhtvfrdSTsGQxTAi7qaJLdKri4jQDXjozuDKcc4ZW3jX+SEFUTW6MGFmU3rS8bNGkdRVfdDiSr8YkksTVhbODCyptzioFYvzwwM454dmDh3C5T/NISG9xLVOJAwwXDZGu2Y51oOkTVyQhbDLGYnJPmLXKihXJwHOMpOTgXuRr0Tuzojt3+JVvFMRUMykegUsSc/04arH0CWyDSvoPIdgNAWxoJpoWJeItFypYwubBtnqgc9Cp4EHhimhk+GwjecSycTckmhfTmCjT8OF8XHvEighRvuHU26IpOPsRTEXpbACs7UZVey4LrSj5Rjc3dyxgoiix7Oau88HIhk7/IRAzVT8FY/5Yx+nHwetHWUhA71HLO/S1fiSg6IgfuwiHeJ4mcmplAXOYGD7zcbjRpZCXyTC/eU9Jq9fe0U/dojiq+dM5JAnshd1hv0qcpg7O8o4V6yNVIxxuKbTuoy3+tme/9uem7+I8xaWKiu1pfBIniVZE4fjo+u4Z0StPWhcSuWsUzvD1SUIKilf4ifZt0fDFSgFuv3xqImWD2Ul9nSbk7uA3x3zT1oIaUZVTWQGlPyLOFhNCxea8jTFcR+g86WJfU36SpX7mlW0Wl2Pjn6tpLypl5uCNjORpZzcPC06wfQICBiI2RDyKduWjpe43W33BRczkHAKt53qtpfExGWethx06WfWlVxbYmxqTxwDD82q755CCtrZ0BKhKZ1z7+pqNRL6PA/nwIZk/gU1LDesNiva43Ca+TNkgKb54VGii+IbPwle5Jflyk9Ons4hMATYNBxXhitE6INpKg4cQphwAPA70e1e9B4y29TRDDzo/r9fm3yJzvgZaXBfBQzUar5/zXxITku2k+x8pV8HMrCOMahMV5e0HVLt+osNyQyghYKF3DEgPbKw3/UweP6rsiN2M9GkE4pwEVm4P9gSfTdIMeC2dB1DmR/D/OBtvtiNxMlRyI/DgplAGj2i5pod3WkXZdhD2hon3SjOTmjlLd4G5kaC4BYchVrDQAy8WGAtvz8wqRY3hAp5Sim4eWr0laTUS3Nd3Vl2e3N3SSNo6/q6aPnmILwyGsmhAQovALsX9WaDdjgpZKP051eJGvFlR77+5GeGozIGVbglUH35g46ZII5r2LiNVr8qUGpHe1v+xWmZY3BScAA/VvSYHJi7o5FyDQaxC4u0EuGLrjVJzLQ6UqHNfQ82P/fXUfU/JVMtloI1owDmb8qxyzLKcXeCrjeqfLQu0VORdr4wsxyA4LTIwYpDITc7bT9rgvdckTJZr/ySsHxovWEIb005otziT7caWIYmOy4Wv37ik5F50tYWfqrkKGDFhxNtEUQ= X-Forefront-Antispam-Report: CIP:165.204.84.17;CTRY:US;LANG:en;SCL:1;SRV:;IPV:CAL;SFV:NSPM;H:SATLEXMB04.amd.com;PTR:InfoDomainNonexistent;CAT:NONE;SFS:(13230040)(82310400026)(376014)(1800799024)(34020700016)(36860700013)(13003099007);DIR:OUT;SFP:1101; X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 30 Mar 2025 18:03:50.2960 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: e997f276-95ae-4b2b-1903-08dd6fb539a6 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: BN2PEPF0000449D.namprd02.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: SA5PPFCAFD069B8 Signed-off-by: Ayan Kumar Halder --- Changes from :- v1, v2 - 1. New patch introduced in v3. 2. Should be applied on top of https://patchwork.kernel.org/project/xen-devel/cover/20250316192445.2376484-1-luca.fancellu@arm.com/ xen/arch/arm/Kconfig | 2 +- xen/arch/arm/arm32/mpu/Makefile | 2 ++ xen/arch/arm/arm32/mpu/p2m.c | 18 ++++++++++++++++++ xen/arch/arm/arm32/mpu/smpboot.c | 23 +++++++++++++++++++++++ xen/arch/arm/include/asm/mm.h | 5 +++++ 5 files changed, 49 insertions(+), 1 deletion(-) create mode 100644 xen/arch/arm/arm32/mpu/p2m.c create mode 100644 xen/arch/arm/arm32/mpu/smpboot.c diff --git a/xen/arch/arm/Kconfig b/xen/arch/arm/Kconfig index 565f288331..a1dd942091 100644 --- a/xen/arch/arm/Kconfig +++ b/xen/arch/arm/Kconfig @@ -1,7 +1,7 @@ config ARM_32 def_bool y depends on "$(ARCH)" = "arm32" - select ARCH_MAP_DOMAIN_PAGE + select ARCH_MAP_DOMAIN_PAGE if MMU config ARM_64 def_bool y diff --git a/xen/arch/arm/arm32/mpu/Makefile b/xen/arch/arm/arm32/mpu/Makefile index 3340058c08..38797f28af 100644 --- a/xen/arch/arm/arm32/mpu/Makefile +++ b/xen/arch/arm/arm32/mpu/Makefile @@ -1 +1,3 @@ obj-y += head.o +obj-y += smpboot.o +obj-y += p2m.o diff --git a/xen/arch/arm/arm32/mpu/p2m.c b/xen/arch/arm/arm32/mpu/p2m.c new file mode 100644 index 0000000000..df8de5c7d8 --- /dev/null +++ b/xen/arch/arm/arm32/mpu/p2m.c @@ -0,0 +1,18 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include +#include + +void __init setup_virt_paging(void) +{ + BUG_ON("unimplemented"); +} + +/* + * Local variables: + * mode: C + * c-file-style: "BSD" + * c-basic-offset: 4 + * indent-tabs-mode: nil + * End: + */ diff --git a/xen/arch/arm/arm32/mpu/smpboot.c b/xen/arch/arm/arm32/mpu/smpboot.c new file mode 100644 index 0000000000..3f3e54294e --- /dev/null +++ b/xen/arch/arm/arm32/mpu/smpboot.c @@ -0,0 +1,23 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include + +int prepare_secondary_mm(int cpu) +{ + BUG_ON("unimplemented"); + return -EINVAL; +} + +void update_boot_mapping(bool enable) +{ + BUG_ON("unimplemented"); +} + +/* + * Local variables: + * mode: C + * c-file-style: "BSD" + * c-basic-offset: 4 + * indent-tabs-mode: nil + * End: + */ diff --git a/xen/arch/arm/include/asm/mm.h b/xen/arch/arm/include/asm/mm.h index fbffaccef4..a894e28ac9 100644 --- a/xen/arch/arm/include/asm/mm.h +++ b/xen/arch/arm/include/asm/mm.h @@ -171,12 +171,17 @@ struct page_info #define PGC_need_scrub PGC_allocated #ifdef CONFIG_ARM_32 +#ifdef CONFIG_MPU +#define is_xen_heap_page(page) false +#define is_xen_heap_mfn(mfn) false +#else #define is_xen_heap_page(page) is_xen_heap_mfn(page_to_mfn(page)) #define is_xen_heap_mfn(mfn) ({ \ unsigned long mfn_ = mfn_x(mfn); \ (mfn_ >= mfn_x(directmap_mfn_start) && \ mfn_ < mfn_x(directmap_mfn_end)); \ }) +#endif #else #define is_xen_heap_page(page) ((page)->count_info & PGC_xen_heap) #define is_xen_heap_mfn(mfn) \