From patchwork Tue Apr 1 11:46:02 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Christian Marangi (Ansuel)" X-Patchwork-Id: 14034716 X-Patchwork-Delegate: kuba@kernel.org Received: from mail-wm1-f44.google.com (mail-wm1-f44.google.com [209.85.128.44]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 005EA20127A; Tue, 1 Apr 2025 11:46:48 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.128.44 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1743508011; cv=none; b=e/cUm+pnMCCPzJZlH1/R96EpnxhhhQiVF9IamWZwkJZ37dHxWJjSt3crMxPXbghREQrhVrnoCsQ+om/Se11Zijl95ckwZo3lT0bbbSlJ1HrJstH6j8aaYddbgjRGTdYFrDf7CM9EQIbWZIrcvSgZtJzlatjs3JHUQwqk33Gcgfk= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1743508011; c=relaxed/simple; bh=EZMVh2db0ZmarXKOQ7m4yP7KorQoZr0yhTBe80XRdC8=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=NSr9ZESGJMIMK3D3q6sJhVINEYDzyvFaz3V6RaRfmh8Va/AWMm7vHbXrCizH9jj8tJPif5kEd0IikN/Zn9FRkYa6oY23g2CiOXM7IhM0SslJfkX9p7VYbTY5ZRsser6MAWpArLqURf3bY0MpH+R6D1CC0OjSvm42p3m9N0Ga858= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com; spf=pass smtp.mailfrom=gmail.com; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b=D/W/bYeo; arc=none smtp.client-ip=209.85.128.44 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=gmail.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="D/W/bYeo" Received: by mail-wm1-f44.google.com with SMTP id 5b1f17b1804b1-43cfe63c592so55821085e9.2; Tue, 01 Apr 2025 04:46:48 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20230601; t=1743508007; x=1744112807; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=z+OVgZAbcP9S/JBP9Hsy4ANWhG6zZP/1wY/sh/4+PQM=; b=D/W/bYeof+dyyzqs8zr3yo7KchAqTvnBlx/YJGNM/NUwD6jvHc6aXAH8xBoOEa/Y2a rH924u30b0OfLAERNd9KMAMB7mJf14S3+srr9/xA/0Pia5Txok67qPBp3u92kL0KqDW+ /wbqOAWZeCkjuLKWTD2QtRef7ksj0iOV1mfxL4v6wJs/tEbYfkhRhwGaa3NzUW4v+pOC QoFSXDPQBY+FOEKxag7ro7PQ5tn3xlFcxeCwZ4pLxl3GfRFAxhNycKNYPG4WZpEomVhS xhUHO3HerZspjcNLiviwrSZjHUwqnbqz63EZo6uV1DFd94w3iSgf3w4pGU3Jlqx/p1dE YNQg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1743508007; x=1744112807; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=z+OVgZAbcP9S/JBP9Hsy4ANWhG6zZP/1wY/sh/4+PQM=; b=GvpzBwyXrzxyHQaaeVgX3FVA7JbRuM2ZvmwgowE1JcpLdeZnG6wT9qtMHnj5okaTPR lCvBCrfqCopua9mc41/J7pfIM9Pwi7RjBQEo42PQ2FEJgjHmtCQrlafWGTH6k4XHwf7D 2uoWkfdDzxXlUmNUDON+GZZGx44Vp87j2HL2oa2V/NKDJR/Hd2RW+q9ai9d/bSHnmQh8 HrgaCXDKxa4+bGHAwqIBgS8tN03sdjvauSFTR+5pbZM7bBAkrU7ilMe08K5r4WrKkE9l /s2ddJ3wRKni9sudi8jdip6FwNfXEC87nflmUCB3yAakwFoTN5nrKUyRBPElMco7Lxf9 pa5A== X-Forwarded-Encrypted: i=1; AJvYcCVPb652c2eiNrE4GC6on8lHZUSEvxNn7fPgkGXpzGmOjtSuQgh9m15WbIhGSUIsVua34b0qnXG7@vger.kernel.org, AJvYcCX4KtKLImbSEJEc+RatMBThmUpSBMUjX2jMNRIp8+ubAulooUYMeSHs3lnjUYnnPvougI9b7cSPHEMV@vger.kernel.org, AJvYcCXkmudvpQKZAuRPJAgviGl4rOTyTs9XTxQt7N7OYEGtIH3pq6ZdmXCCN2/t0yXDQguNUpAI4gmjZo2QoYdp@vger.kernel.org X-Gm-Message-State: AOJu0YzCaQdlPnEOr5IM+YXd6ub4VwCOtY7fdYXuaeC7rD7HDHj0M7os KKGejdAGfGncc/V+swkCnTUlVz193B1wWIPfjVVA2hJqCbU9+SGCFR06Vg== X-Gm-Gg: ASbGnctXIW+Kd7mlR5n/6bstrZTP14MheXfnui2E/D22PtKjC6Xx1EigK6xCbkVnl8/ bGwQtWgdKdJLVN5QuKrqw+pyDii/zwy+a5ecatV14mnwVJmAdtaR3e+DM0SwTkR/3FHTlSFf76h 8RCoQbEgzStLpE+T/YYdi430hjL7AabvLuc7RMocw1VE3J8HtZza6UQEgF7FfgCBWDgPAkxKXpw kTsX4QyuvySQbWuIUOzibWAszKB9mn/TmBOieujivlLDazU/Mu7RwHg63cxyrOG54Pc0s+n1aFA EppdT2pRUHf2btJVgkOIZ8kiJlUqR0FCEKHOZ32cfrmAORn0qWB44DZVmdcUlnC9k1WOgYqbRiG sl6QEah4aoI+QNw== X-Google-Smtp-Source: AGHT+IE4ry0mWog1VRT61Q62f4bhtw7L1usAf8HAbHOKaSLOKsUBr9WzxZ37rCik1qQf/ZTkxjlN/A== X-Received: by 2002:a05:600c:468c:b0:43d:83a:417d with SMTP id 5b1f17b1804b1-43db622a42emr126481265e9.12.1743508006951; Tue, 01 Apr 2025 04:46:46 -0700 (PDT) Received: from localhost.localdomain (93-34-88-225.ip49.fastwebnet.it. [93.34.88.225]) by smtp.googlemail.com with ESMTPSA id 5b1f17b1804b1-43ead679894sm8148175e9.40.2025.04.01.04.46.45 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 01 Apr 2025 04:46:46 -0700 (PDT) From: Christian Marangi To: Christian Marangi , Andrew Lunn , "David S. Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Heiner Kallweit , Russell King , Florian Fainelli , Broadcom internal kernel review list , =?utf-8?q?Marek_Beh=C3=BAn?= , Andrei Botila , Sabrina Dubroca , Daniel Golle , Eric Woudstra , netdev@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Cc: "Russell King (Oracle)" Subject: [net-next RFC PATCH v5 1/6] net: phy: pass PHY driver to .match_phy_device OP Date: Tue, 1 Apr 2025 13:46:02 +0200 Message-ID: <20250401114611.4063-2-ansuelsmth@gmail.com> X-Mailer: git-send-email 2.48.1 In-Reply-To: <20250401114611.4063-1-ansuelsmth@gmail.com> References: <20250401114611.4063-1-ansuelsmth@gmail.com> Precedence: bulk X-Mailing-List: netdev@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-Patchwork-Delegate: kuba@kernel.org X-Patchwork-State: RFC Pass PHY driver pointer to .match_phy_device OP in addition to phydev. Having access to the PHY driver struct might be useful to check the PHY ID of the driver is being matched for in case the PHY ID scanned in the phydev is not consistent. A scenario for this is a PHY that change PHY ID after a firmware is loaded, in such case, the PHY ID stored in PHY device struct is not valid anymore and PHY will manually scan the ID in the match_phy_device function. Having the PHY driver info is also useful for those PHY driver that implement multiple simple .match_phy_device OP to match specific MMD PHY ID. With this extra info if the parsing logic is the same, the matching function can be generalized by using the phy_id in the PHY driver instead of hardcoding. Suggested-by: Russell King (Oracle) Reviewed-by: Russell King (Oracle) Signed-off-by: Christian Marangi --- drivers/net/phy/bcm87xx.c | 6 ++++-- drivers/net/phy/icplus.c | 6 ++++-- drivers/net/phy/marvell10g.c | 12 ++++++++---- drivers/net/phy/micrel.c | 6 ++++-- drivers/net/phy/nxp-c45-tja11xx.c | 12 ++++++++---- drivers/net/phy/nxp-tja11xx.c | 6 ++++-- drivers/net/phy/phy_device.c | 2 +- drivers/net/phy/realtek/realtek_main.c | 27 +++++++++++++++++--------- drivers/net/phy/teranetics.c | 3 ++- include/linux/phy.h | 3 ++- 10 files changed, 55 insertions(+), 28 deletions(-) diff --git a/drivers/net/phy/bcm87xx.c b/drivers/net/phy/bcm87xx.c index e81404bf8994..1e1e2259fc2b 100644 --- a/drivers/net/phy/bcm87xx.c +++ b/drivers/net/phy/bcm87xx.c @@ -185,12 +185,14 @@ static irqreturn_t bcm87xx_handle_interrupt(struct phy_device *phydev) return IRQ_HANDLED; } -static int bcm8706_match_phy_device(struct phy_device *phydev) +static int bcm8706_match_phy_device(struct phy_device *phydev, + const struct phy_driver *phydrv) { return phydev->c45_ids.device_ids[4] == PHY_ID_BCM8706; } -static int bcm8727_match_phy_device(struct phy_device *phydev) +static int bcm8727_match_phy_device(struct phy_device *phydev, + const struct phy_driver *phydrv) { return phydev->c45_ids.device_ids[4] == PHY_ID_BCM8727; } diff --git a/drivers/net/phy/icplus.c b/drivers/net/phy/icplus.c index bbcc7d2b54cd..c0c4f19cfb6a 100644 --- a/drivers/net/phy/icplus.c +++ b/drivers/net/phy/icplus.c @@ -520,12 +520,14 @@ static int ip101a_g_match_phy_device(struct phy_device *phydev, bool ip101a) return ip101a == !ret; } -static int ip101a_match_phy_device(struct phy_device *phydev) +static int ip101a_match_phy_device(struct phy_device *phydev, + const struct phy_driver *phydrv) { return ip101a_g_match_phy_device(phydev, true); } -static int ip101g_match_phy_device(struct phy_device *phydev) +static int ip101g_match_phy_device(struct phy_device *phydev, + const struct phy_driver *phydrv) { return ip101a_g_match_phy_device(phydev, false); } diff --git a/drivers/net/phy/marvell10g.c b/drivers/net/phy/marvell10g.c index 5354c8895163..13e81dff42c1 100644 --- a/drivers/net/phy/marvell10g.c +++ b/drivers/net/phy/marvell10g.c @@ -1264,7 +1264,8 @@ static int mv3310_get_number_of_ports(struct phy_device *phydev) return ret + 1; } -static int mv3310_match_phy_device(struct phy_device *phydev) +static int mv3310_match_phy_device(struct phy_device *phydev, + const struct phy_driver *phydrv) { if ((phydev->c45_ids.device_ids[MDIO_MMD_PMAPMD] & MARVELL_PHY_ID_MASK) != MARVELL_PHY_ID_88X3310) @@ -1273,7 +1274,8 @@ static int mv3310_match_phy_device(struct phy_device *phydev) return mv3310_get_number_of_ports(phydev) == 1; } -static int mv3340_match_phy_device(struct phy_device *phydev) +static int mv3340_match_phy_device(struct phy_device *phydev, + const struct phy_driver *phydrv) { if ((phydev->c45_ids.device_ids[MDIO_MMD_PMAPMD] & MARVELL_PHY_ID_MASK) != MARVELL_PHY_ID_88X3310) @@ -1297,12 +1299,14 @@ static int mv211x_match_phy_device(struct phy_device *phydev, bool has_5g) return !!(val & MDIO_PCS_SPEED_5G) == has_5g; } -static int mv2110_match_phy_device(struct phy_device *phydev) +static int mv2110_match_phy_device(struct phy_device *phydev, + const struct phy_driver *phydrv) { return mv211x_match_phy_device(phydev, true); } -static int mv2111_match_phy_device(struct phy_device *phydev) +static int mv2111_match_phy_device(struct phy_device *phydev, + const struct phy_driver *phydrv) { return mv211x_match_phy_device(phydev, false); } diff --git a/drivers/net/phy/micrel.c b/drivers/net/phy/micrel.c index 24882d30f685..d7f11f16fbd1 100644 --- a/drivers/net/phy/micrel.c +++ b/drivers/net/phy/micrel.c @@ -768,7 +768,8 @@ static int ksz8051_ksz8795_match_phy_device(struct phy_device *phydev, return !ret; } -static int ksz8051_match_phy_device(struct phy_device *phydev) +static int ksz8051_match_phy_device(struct phy_device *phydev, + const struct phy_driver *phydrv) { return ksz8051_ksz8795_match_phy_device(phydev, true); } @@ -888,7 +889,8 @@ static int ksz8061_config_init(struct phy_device *phydev) return kszphy_config_init(phydev); } -static int ksz8795_match_phy_device(struct phy_device *phydev) +static int ksz8795_match_phy_device(struct phy_device *phydev, + const struct phy_driver *phydrv) { return ksz8051_ksz8795_match_phy_device(phydev, false); } diff --git a/drivers/net/phy/nxp-c45-tja11xx.c b/drivers/net/phy/nxp-c45-tja11xx.c index 250a018d5546..bc2b7cc0cebe 100644 --- a/drivers/net/phy/nxp-c45-tja11xx.c +++ b/drivers/net/phy/nxp-c45-tja11xx.c @@ -1971,25 +1971,29 @@ static int nxp_c45_macsec_ability(struct phy_device *phydev) return macsec_ability; } -static int tja1103_match_phy_device(struct phy_device *phydev) +static int tja1103_match_phy_device(struct phy_device *phydev, + const struct phy_driver *phydrv) { return phy_id_compare(phydev->phy_id, PHY_ID_TJA_1103, PHY_ID_MASK) && !nxp_c45_macsec_ability(phydev); } -static int tja1104_match_phy_device(struct phy_device *phydev) +static int tja1104_match_phy_device(struct phy_device *phydev, + const struct phy_driver *phydrv) { return phy_id_compare(phydev->phy_id, PHY_ID_TJA_1103, PHY_ID_MASK) && nxp_c45_macsec_ability(phydev); } -static int tja1120_match_phy_device(struct phy_device *phydev) +static int tja1120_match_phy_device(struct phy_device *phydev, + const struct phy_driver *phydrv) { return phy_id_compare(phydev->phy_id, PHY_ID_TJA_1120, PHY_ID_MASK) && !nxp_c45_macsec_ability(phydev); } -static int tja1121_match_phy_device(struct phy_device *phydev) +static int tja1121_match_phy_device(struct phy_device *phydev, + const struct phy_driver *phydrv) { return phy_id_compare(phydev->phy_id, PHY_ID_TJA_1120, PHY_ID_MASK) && nxp_c45_macsec_ability(phydev); diff --git a/drivers/net/phy/nxp-tja11xx.c b/drivers/net/phy/nxp-tja11xx.c index 07e94a2478ac..3c38a8ddae2f 100644 --- a/drivers/net/phy/nxp-tja11xx.c +++ b/drivers/net/phy/nxp-tja11xx.c @@ -651,12 +651,14 @@ static int tja1102_match_phy_device(struct phy_device *phydev, bool port0) return !ret; } -static int tja1102_p0_match_phy_device(struct phy_device *phydev) +static int tja1102_p0_match_phy_device(struct phy_device *phydev, + const struct phy_driver *phydrv) { return tja1102_match_phy_device(phydev, true); } -static int tja1102_p1_match_phy_device(struct phy_device *phydev) +static int tja1102_p1_match_phy_device(struct phy_device *phydev, + const struct phy_driver *phydrv) { return tja1102_match_phy_device(phydev, false); } diff --git a/drivers/net/phy/phy_device.c b/drivers/net/phy/phy_device.c index 675fbd225378..2d6ceacb2986 100644 --- a/drivers/net/phy/phy_device.c +++ b/drivers/net/phy/phy_device.c @@ -514,7 +514,7 @@ static int phy_bus_match(struct device *dev, const struct device_driver *drv) return 0; if (phydrv->match_phy_device) - return phydrv->match_phy_device(phydev); + return phydrv->match_phy_device(phydev, phydrv); if (phydev->is_c45) { for (i = 1; i < num_ids; i++) { diff --git a/drivers/net/phy/realtek/realtek_main.c b/drivers/net/phy/realtek/realtek_main.c index 893c82479671..b4dc0d6fe4ca 100644 --- a/drivers/net/phy/realtek/realtek_main.c +++ b/drivers/net/phy/realtek/realtek_main.c @@ -1117,13 +1117,15 @@ static bool rtlgen_supports_mmd(struct phy_device *phydev) return val > 0; } -static int rtlgen_match_phy_device(struct phy_device *phydev) +static int rtlgen_match_phy_device(struct phy_device *phydev, + const struct phy_driver *phydrv) { return phydev->phy_id == RTL_GENERIC_PHYID && !rtlgen_supports_2_5gbps(phydev); } -static int rtl8226_match_phy_device(struct phy_device *phydev) +static int rtl8226_match_phy_device(struct phy_device *phydev, + const struct phy_driver *phydrv) { return phydev->phy_id == RTL_GENERIC_PHYID && rtlgen_supports_2_5gbps(phydev) && @@ -1139,32 +1141,38 @@ static int rtlgen_is_c45_match(struct phy_device *phydev, unsigned int id, return !is_c45 && (id == phydev->phy_id); } -static int rtl8221b_match_phy_device(struct phy_device *phydev) +static int rtl8221b_match_phy_device(struct phy_device *phydev, + const struct phy_driver *phydrv) { return phydev->phy_id == RTL_8221B && rtlgen_supports_mmd(phydev); } -static int rtl8221b_vb_cg_c22_match_phy_device(struct phy_device *phydev) +static int rtl8221b_vb_cg_c22_match_phy_device(struct phy_device *phydev, + const struct phy_driver *phydrv) { return rtlgen_is_c45_match(phydev, RTL_8221B_VB_CG, false); } -static int rtl8221b_vb_cg_c45_match_phy_device(struct phy_device *phydev) +static int rtl8221b_vb_cg_c45_match_phy_device(struct phy_device *phydev, + const struct phy_driver *phydrv) { return rtlgen_is_c45_match(phydev, RTL_8221B_VB_CG, true); } -static int rtl8221b_vn_cg_c22_match_phy_device(struct phy_device *phydev) +static int rtl8221b_vn_cg_c22_match_phy_device(struct phy_device *phydev, + const struct phy_driver *phydrv) { return rtlgen_is_c45_match(phydev, RTL_8221B_VN_CG, false); } -static int rtl8221b_vn_cg_c45_match_phy_device(struct phy_device *phydev) +static int rtl8221b_vn_cg_c45_match_phy_device(struct phy_device *phydev, + const struct phy_driver *phydrv) { return rtlgen_is_c45_match(phydev, RTL_8221B_VN_CG, true); } -static int rtl_internal_nbaset_match_phy_device(struct phy_device *phydev) +static int rtl_internal_nbaset_match_phy_device(struct phy_device *phydev, + const struct phy_driver *phydrv) { if (phydev->is_c45) return false; @@ -1182,7 +1190,8 @@ static int rtl_internal_nbaset_match_phy_device(struct phy_device *phydev) return rtlgen_supports_2_5gbps(phydev) && !rtlgen_supports_mmd(phydev); } -static int rtl8251b_c45_match_phy_device(struct phy_device *phydev) +static int rtl8251b_c45_match_phy_device(struct phy_device *phydev, + const struct phy_driver *phydrv) { return rtlgen_is_c45_match(phydev, RTL_8251B, true); } diff --git a/drivers/net/phy/teranetics.c b/drivers/net/phy/teranetics.c index 752d4bf7bb99..46c5ff7d7b56 100644 --- a/drivers/net/phy/teranetics.c +++ b/drivers/net/phy/teranetics.c @@ -67,7 +67,8 @@ static int teranetics_read_status(struct phy_device *phydev) return 0; } -static int teranetics_match_phy_device(struct phy_device *phydev) +static int teranetics_match_phy_device(struct phy_device *phydev, + const struct phy_driver *phydrv) { return phydev->c45_ids.device_ids[3] == PHY_ID_TN2020; } diff --git a/include/linux/phy.h b/include/linux/phy.h index a2bfae80c449..7042ceaadcc6 100644 --- a/include/linux/phy.h +++ b/include/linux/phy.h @@ -990,7 +990,8 @@ struct phy_driver { * driver for the given phydev. If NULL, matching is based on * phy_id and phy_id_mask. */ - int (*match_phy_device)(struct phy_device *phydev); + int (*match_phy_device)(struct phy_device *phydev, + const struct phy_driver *phydrv); /** * @set_wol: Some devices (e.g. qnap TS-119P II) require PHY From patchwork Tue Apr 1 11:46:03 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Christian Marangi (Ansuel)" X-Patchwork-Id: 14034717 X-Patchwork-Delegate: kuba@kernel.org Received: from mail-wm1-f43.google.com (mail-wm1-f43.google.com [209.85.128.43]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 1D468202983; Tue, 1 Apr 2025 11:46:49 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.128.43 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1743508011; cv=none; b=Nf/SxP+ZrC3Z0O3BBqrMTnWw+GiosrJ/7HxBfjWmZPnMx5yisxc+U44UZ99TXhGHEIqX0mf98bypQtseZS/YFzI7PsyHbMUwcWhlfL1Gk4DacxceMDuqLwpTOyiaAvD2CFfWfyFNiDjIt8g8ZfydqnWPY+ZM9v7rW4aAAbTRMfg= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1743508011; c=relaxed/simple; bh=9G4ubJ6lV4V2dWOs0FNh/K1YDBBBYb3K8frA6VqI9G8=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=tbsZGYPywRnuhsuGc3WjunjkKMBaG2lbTNkHq+vawq79eo+DYf9DN8g03MfO5SpF0uPBK6XaUe/5/ftwn2MUUS0XGAySkwyG4PLYOT0GU568Fr0WUrZ8/P3jkxmja0UYHa0BzZK3YJ6/UW4cjBmRUpVIYdF8YhRaPKJKQc/UVpM= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com; spf=pass smtp.mailfrom=gmail.com; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b=We86xZDZ; arc=none smtp.client-ip=209.85.128.43 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=gmail.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="We86xZDZ" Received: by mail-wm1-f43.google.com with SMTP id 5b1f17b1804b1-43ea40a6e98so13256255e9.1; Tue, 01 Apr 2025 04:46:49 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20230601; t=1743508008; x=1744112808; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=pvRhcUvsur4qZV9ZsxMG2pchOpKzL3rOM+elE1weNSU=; b=We86xZDZTCK97fgM2+RqmGwqlJ4Do+O9qtaxfFLYBVRwj92hlqn0ghCAoKuku+qml1 hBD/wlbBp0JBrRS/iApi3jaTvWwZJEO1ln3UItSgNnstdYYjbjlv5ea5sXT/Qd1G12/x 7TIofTQDrO7DlbJL/73EZrqhlvREkwkFY9UAzkRhF50PCd+iHRC2ppTFeUp0CBxfnpTX O4xdaYqLXKXEE7oZ7zLb9F/SonCcrrqNshHbT5CfXG5thPado/wr7ytMGP2a+njFUglK jMsXSUusQqur/ZTJAKSEyEKlLPscz0YCPf0YwaEsLNQPl1Or9b63eyxImjYM+nRt18Nl aOZA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1743508008; x=1744112808; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=pvRhcUvsur4qZV9ZsxMG2pchOpKzL3rOM+elE1weNSU=; b=qIlO9FJolRECn20wAvzuSMETKhcj7PFBCHMI/DV1Pt72TZIQtDMm32TKKYu8kfilZr cqszTdBCnWmCZjl+2ARyTwItj5xTDHWpKescJu1fTqkKS/l9feRHQl1apwLy0pwQ2NQL TMARFxo9lEPFS9LaBE0ukc49PTiG6Sz/6DCkmGTW0px8lXINVH3ZFHP5TmdXBTML9Bed HU+hkolo/LCG+PFWSMFkoBTmx1/7mTSR3SFXGXIRUZfM/Spmarjkl5AgYP0ftoZFmkGW BHjepcGEgTtrBwVD551C9cwAzdK4yotWKLgD0xHqxsC3DacQoJZ5fdNUjwankWy8w5Pu dc1g== X-Forwarded-Encrypted: i=1; AJvYcCUXrki5Dw7Vnh0y912UKcwe/cog+z8fEJSW8QycWkqO2Ks0RV6Z+Vq63pwbaytwD41Cj+n3qh6c9zBO@vger.kernel.org, AJvYcCVnJscTraqf19vUwMl2b4BXfrtEoF8C8VWu97B8y1ZM4ScJXHLgOQG+aKx+EBjkUv7N6aj/WzxY@vger.kernel.org, AJvYcCXjMW3labPQNWiEMDhG6GJFdxKEikXWQaRKN1uG5uH0AdUo5lkrgBGkptJqRLa/Usa0vyydSwW/QdfDc697@vger.kernel.org X-Gm-Message-State: AOJu0YwdEnEyUykvW24Epmor1+uEdeZ3vDdCzOH2tRsRJ74GiUB9M1r3 h8gicBNHZUKUjcgJez51RqTyV3uRvCwBRnFNt7d6u1L1IevOfK3Q X-Gm-Gg: ASbGnct3plrZdscqhks5X/n844lNGx7TRm19iOFErlTZUpsMKfc9eP9ZkKt//uEG3uW eIbX9ezZ8MwzsPEAjyY7yun4xwV6WHwbM7FIyqLRK43eq4uDoBO8+CmZTIvXAmysIbc9pbJrUxN 9VHNljIvMh+hRiQTUVzpCE7Q5RA/tmqEqjwk5EdIfI+z9TReHLxoMQND5eNE1tKq56wmgoWqGak IfvqM0MGAfIlU9S5WOU2H9Ed3R4C9/NMV0R8L7vbWFSp5+irCjA4QVXLErGO0CtJLw20Ku+jP/F aKYwo8SXueqWPiNc0FNc22SFndCS8KFo6Pk/j9nZzI675fZf/0xQMPCiZrHvnI1q3/iz5yJ3avB yobAlrQkn2ya1qQ== X-Google-Smtp-Source: AGHT+IHQ0Hjq73bRHFl+XWRxDmb2IoAYW5dsebo09D2nD52qy2Fc5tL5APjwKqJJcI4Dc3k9ZOB/ug== X-Received: by 2002:a05:600c:1c15:b0:43d:7bfa:2739 with SMTP id 5b1f17b1804b1-43db62bfdcbmr97222135e9.23.1743508008315; Tue, 01 Apr 2025 04:46:48 -0700 (PDT) Received: from localhost.localdomain (93-34-88-225.ip49.fastwebnet.it. [93.34.88.225]) by smtp.googlemail.com with ESMTPSA id 5b1f17b1804b1-43ead679894sm8148175e9.40.2025.04.01.04.46.47 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 01 Apr 2025 04:46:48 -0700 (PDT) From: Christian Marangi To: Christian Marangi , Andrew Lunn , "David S. Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Heiner Kallweit , Russell King , Florian Fainelli , Broadcom internal kernel review list , =?utf-8?q?Marek_Beh=C3=BAn?= , Andrei Botila , Sabrina Dubroca , Daniel Golle , Eric Woudstra , netdev@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Cc: "Russell King (Oracle)" Subject: [net-next RFC PATCH v5 2/6] net: phy: bcm87xx: simplify .match_phy_device OP Date: Tue, 1 Apr 2025 13:46:03 +0200 Message-ID: <20250401114611.4063-3-ansuelsmth@gmail.com> X-Mailer: git-send-email 2.48.1 In-Reply-To: <20250401114611.4063-1-ansuelsmth@gmail.com> References: <20250401114611.4063-1-ansuelsmth@gmail.com> Precedence: bulk X-Mailing-List: netdev@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-Patchwork-Delegate: kuba@kernel.org X-Patchwork-State: RFC Simplify .match_phy_device OP by using a generic function and using the new phy_id PHY driver info instead of hardcoding the matching PHY ID. Reviewed-by: Russell King (Oracle) Signed-off-by: Christian Marangi --- drivers/net/phy/bcm87xx.c | 14 ++++---------- 1 file changed, 4 insertions(+), 10 deletions(-) diff --git a/drivers/net/phy/bcm87xx.c b/drivers/net/phy/bcm87xx.c index 1e1e2259fc2b..299f9a8f30f4 100644 --- a/drivers/net/phy/bcm87xx.c +++ b/drivers/net/phy/bcm87xx.c @@ -185,16 +185,10 @@ static irqreturn_t bcm87xx_handle_interrupt(struct phy_device *phydev) return IRQ_HANDLED; } -static int bcm8706_match_phy_device(struct phy_device *phydev, +static int bcm87xx_match_phy_device(struct phy_device *phydev, const struct phy_driver *phydrv) { - return phydev->c45_ids.device_ids[4] == PHY_ID_BCM8706; -} - -static int bcm8727_match_phy_device(struct phy_device *phydev, - const struct phy_driver *phydrv) -{ - return phydev->c45_ids.device_ids[4] == PHY_ID_BCM8727; + return phydev->c45_ids.device_ids[4] == phydrv->phy_id; } static struct phy_driver bcm87xx_driver[] = { @@ -208,7 +202,7 @@ static struct phy_driver bcm87xx_driver[] = { .read_status = bcm87xx_read_status, .config_intr = bcm87xx_config_intr, .handle_interrupt = bcm87xx_handle_interrupt, - .match_phy_device = bcm8706_match_phy_device, + .match_phy_device = bcm87xx_match_phy_device, }, { .phy_id = PHY_ID_BCM8727, .phy_id_mask = 0xffffffff, @@ -219,7 +213,7 @@ static struct phy_driver bcm87xx_driver[] = { .read_status = bcm87xx_read_status, .config_intr = bcm87xx_config_intr, .handle_interrupt = bcm87xx_handle_interrupt, - .match_phy_device = bcm8727_match_phy_device, + .match_phy_device = bcm87xx_match_phy_device, } }; module_phy_driver(bcm87xx_driver); From patchwork Tue Apr 1 11:46:04 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Christian Marangi (Ansuel)" X-Patchwork-Id: 14034718 X-Patchwork-Delegate: kuba@kernel.org Received: from mail-wm1-f50.google.com (mail-wm1-f50.google.com [209.85.128.50]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 8A75F202C2D; Tue, 1 Apr 2025 11:46:51 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.128.50 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1743508013; cv=none; b=M7J9r03qBEqRZRlAF1k+yyJrVsqjisgrXd+wyjlN03yrbbs7tnllgFz7i3N/2dfYr3ptYAjtZiREFrQV33O9JuwpW6QQ6ochnDrc8HDFTE7JebQ9FVyek4F+37nx+KK89gp5/ajCPd8sIIEbzvGYiD+1YQpgCfgtX709d8SRNPs= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1743508013; c=relaxed/simple; bh=IujCQ9IoIZbeIWphTzYwK68VeGSRhaVRbzlwAfd7wwU=; h=From:To:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=HRxxo5rgxjI1Xh/Vzfzh86hXlvNsVfeGuCejXZLvKxsg8BXnCSLZIJvlnxC6fWunYSPt53l3pU+d6GdbsyT19yLD33LmOoyi7sstIpVC1mOmdTfiAGHG1+e8nGgfAU9Kce9k/2oscADDNbUUr6OYgFMO94E5FnCmljtxgzXjzcI= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com; spf=pass smtp.mailfrom=gmail.com; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b=DQat3XwS; arc=none smtp.client-ip=209.85.128.50 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=gmail.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="DQat3XwS" Received: by mail-wm1-f50.google.com with SMTP id 5b1f17b1804b1-4394a0c65fcso52570015e9.1; Tue, 01 Apr 2025 04:46:51 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20230601; t=1743508010; x=1744112810; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:from:to:cc:subject:date:message-id :reply-to; bh=C3/3eFl4jlQ6T50tlJqQU5aclw0PVg9d0gCXOGIE1ww=; b=DQat3XwSKF9IU3DZ5U4xrs08rLZlo6VLv33T+WTE51vQJ+/ldNOKdr0InOnnJxgAjx QUsr5DoY3gzzzzTRn0/j1bgSPLvWhNe+aEhrqoKeRgwTXnXFUUMW8gU0yI3Dc9Bu3tIr Kxa0oy8K32So3H9Oa6Sl7UGztHQVpkPeXjigYlX2rFQID4j80UIyxKnJMy0nRfwBSchZ oWPfFlLgJmWkkv3O+CdiGwsrrXjFT/d8lGr3VTt0xYhwPYGqyp/93367dy7Mh4hSunQN Ga3T/7z7nsQShUV791ui6s84IHsdrVnwjfAkbwNv5TXaw7mgNlQ9Jw5C0X49g1ntgk+8 2emA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1743508010; x=1744112810; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=C3/3eFl4jlQ6T50tlJqQU5aclw0PVg9d0gCXOGIE1ww=; b=W11ArUwy2A46zvOfwdc9w4DDHTAr2bjBg0mEL8jjoRVXBuZk9cFTswN0J1hCJQ5i5P H2fjwRxCceBfC/jlnTouJ4mvsao+oFf6IvpoYJ2EOaXQYWGlr2QpaPCUikdu8vxrHJwV POhK6v6S1+WuLW5B/spbt524xpbCa+aOx8ILi8L9MqqYeb/mSdH5jHktgrbfFZJ0hpVZ YQn5RPHl30kOhb7cwenaysZV7u9AcRBs7wW7HRZFaEj+c3gaLHvsxxtOmSC5s+GhcKgq FXmleKvUGSrPp5D0ak8+9EhEfhA7fZ5nMr6qlS6YQ59XGI4hGf442O7Oqi64/fFiJaZQ lv7Q== X-Forwarded-Encrypted: i=1; AJvYcCV3Hr543lPtgnp6TuNzPdoyq+Dx2YLXAVat1JEiG16LW5NrJ09kJ+duoaT5fBxLIKCn6Hfnv2zPwkGa@vger.kernel.org, AJvYcCVAha87yFv2mhNb9it72bTWBnAOHS9285cmHxZL5TMVA8v6pKsAkFHMe/ZcIhbLgsenSPU7wtPX@vger.kernel.org, AJvYcCXf8OUSR1U28rFe6zxUk4o0XFVb6XA2kLUKJUgmTxKsX46mGxadSeUEqgEAv/3A0FEJnp5ihA0SSeyYMlvT@vger.kernel.org X-Gm-Message-State: AOJu0YyEM+J1h0YoRe+SVgpqrfLDDbS2uJj8LZiEzQ4YiwToYSswbzcC jjuhN8tk+y7YUkXZ0Uvgbt8SSc6GltJWL7taf5ny2uDajg8M6Xn0 X-Gm-Gg: ASbGncsLHpbZQnC/I04XI/ZGy8UcnknQBuuhp6ssGApt6wxFdW1b9bJteOggWkVKBYL rD+5DQmpxP36tXAdXo3AKgK2mw8UmNhHWIKqR6muZfQRwikCdiWDNayfs2cGefJCyxQY/zT0ewd 85A6Kd4EkiQTBiLTpSwv4MtlJ6ZRKYYX0v6y05eV8qzEyE9iCm+WKu8i8u3mZGL/igX7OSnd6ES WWaMlE6qt8mqH1GtPszAEB+m3yfknI6nilOHsY8ERN/qebiT12Gg4OeACnWOC5tWewOCcx48OcZ xOnpZbmtUhz78i2a7X509OKOud6tUyRj/+hBOKU7WvZwyRhygJTqoHdkuZUcGvmeDmQcaeERwep eXAO+a4WQcdqFZA== X-Google-Smtp-Source: AGHT+IGzStcsNM0lTrd6CNJ5/kLN7VXIH17cdBr6F9hmiGQss8AKVLI/EC1v3Gg1nJaG/xji9hBaPw== X-Received: by 2002:a05:600c:4e48:b0:43d:3df:42d8 with SMTP id 5b1f17b1804b1-43eaa03e0c4mr19310025e9.6.1743508009646; Tue, 01 Apr 2025 04:46:49 -0700 (PDT) Received: from localhost.localdomain (93-34-88-225.ip49.fastwebnet.it. [93.34.88.225]) by smtp.googlemail.com with ESMTPSA id 5b1f17b1804b1-43ead679894sm8148175e9.40.2025.04.01.04.46.48 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 01 Apr 2025 04:46:49 -0700 (PDT) From: Christian Marangi To: Christian Marangi , Andrew Lunn , "David S. Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Heiner Kallweit , Russell King , Florian Fainelli , Broadcom internal kernel review list , =?utf-8?q?Marek_Beh=C3=BAn?= , Andrei Botila , Sabrina Dubroca , Daniel Golle , Eric Woudstra , netdev@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [net-next RFC PATCH v5 3/6] net: phy: nxp-c45-tja11xx: simplify .match_phy_device OP Date: Tue, 1 Apr 2025 13:46:04 +0200 Message-ID: <20250401114611.4063-4-ansuelsmth@gmail.com> X-Mailer: git-send-email 2.48.1 In-Reply-To: <20250401114611.4063-1-ansuelsmth@gmail.com> References: <20250401114611.4063-1-ansuelsmth@gmail.com> Precedence: bulk X-Mailing-List: netdev@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-Patchwork-Delegate: kuba@kernel.org X-Patchwork-State: RFC Simplify .match_phy_device OP by using a generic function and using the new phy_id PHY driver info instead of hardcoding the matching PHY ID with new variant for macsec and no_macsec PHYs. Also make use of PHY_ID_MATCH_MODEL macro and drop PHY_ID_MASK define to introduce phy_id and phy_id_mask again in phy_driver struct. Signed-off-by: Christian Marangi Reviewed-by: Russell King (Oracle) --- drivers/net/phy/nxp-c45-tja11xx.c | 45 ++++++++++++++----------------- 1 file changed, 20 insertions(+), 25 deletions(-) diff --git a/drivers/net/phy/nxp-c45-tja11xx.c b/drivers/net/phy/nxp-c45-tja11xx.c index bc2b7cc0cebe..8880547c4bfa 100644 --- a/drivers/net/phy/nxp-c45-tja11xx.c +++ b/drivers/net/phy/nxp-c45-tja11xx.c @@ -19,7 +19,6 @@ #include "nxp-c45-tja11xx.h" -#define PHY_ID_MASK GENMASK(31, 4) /* Same id: TJA1103, TJA1104 */ #define PHY_ID_TJA_1103 0x001BB010 /* Same id: TJA1120, TJA1121 */ @@ -1971,32 +1970,24 @@ static int nxp_c45_macsec_ability(struct phy_device *phydev) return macsec_ability; } -static int tja1103_match_phy_device(struct phy_device *phydev, - const struct phy_driver *phydrv) +static int tja11xx_no_macsec_match_phy_device(struct phy_device *phydev, + const struct phy_driver *phydrv) { - return phy_id_compare(phydev->phy_id, PHY_ID_TJA_1103, PHY_ID_MASK) && - !nxp_c45_macsec_ability(phydev); -} + if (!phy_id_compare(phydev->phy_id, phydrv->phy_id, + phydrv->phy_id_mask)) + return 0; -static int tja1104_match_phy_device(struct phy_device *phydev, - const struct phy_driver *phydrv) -{ - return phy_id_compare(phydev->phy_id, PHY_ID_TJA_1103, PHY_ID_MASK) && - nxp_c45_macsec_ability(phydev); + return !nxp_c45_macsec_ability(phydev); } -static int tja1120_match_phy_device(struct phy_device *phydev, - const struct phy_driver *phydrv) +static int tja11xx_macsec_match_phy_device(struct phy_device *phydev, + const struct phy_driver *phydrv) { - return phy_id_compare(phydev->phy_id, PHY_ID_TJA_1120, PHY_ID_MASK) && - !nxp_c45_macsec_ability(phydev); -} + if (!phy_id_compare(phydev->phy_id, phydrv->phy_id, + phydrv->phy_id_mask)) + return 0; -static int tja1121_match_phy_device(struct phy_device *phydev, - const struct phy_driver *phydrv) -{ - return phy_id_compare(phydev->phy_id, PHY_ID_TJA_1120, PHY_ID_MASK) && - nxp_c45_macsec_ability(phydev); + return nxp_c45_macsec_ability(phydev); } static const struct nxp_c45_regmap tja1120_regmap = { @@ -2069,6 +2060,7 @@ static const struct nxp_c45_phy_data tja1120_phy_data = { static struct phy_driver nxp_c45_driver[] = { { + PHY_ID_MATCH_MODEL(PHY_ID_TJA_1103), .name = "NXP C45 TJA1103", .get_features = nxp_c45_get_features, .driver_data = &tja1103_phy_data, @@ -2090,9 +2082,10 @@ static struct phy_driver nxp_c45_driver[] = { .get_sqi = nxp_c45_get_sqi, .get_sqi_max = nxp_c45_get_sqi_max, .remove = nxp_c45_remove, - .match_phy_device = tja1103_match_phy_device, + .match_phy_device = tja11xx_no_macsec_match_phy_device, }, { + PHY_ID_MATCH_MODEL(PHY_ID_TJA_1103), .name = "NXP C45 TJA1104", .get_features = nxp_c45_get_features, .driver_data = &tja1103_phy_data, @@ -2114,9 +2107,10 @@ static struct phy_driver nxp_c45_driver[] = { .get_sqi = nxp_c45_get_sqi, .get_sqi_max = nxp_c45_get_sqi_max, .remove = nxp_c45_remove, - .match_phy_device = tja1104_match_phy_device, + .match_phy_device = tja11xx_macsec_match_phy_device, }, { + PHY_ID_MATCH_MODEL(PHY_ID_TJA_1120), .name = "NXP C45 TJA1120", .get_features = nxp_c45_get_features, .driver_data = &tja1120_phy_data, @@ -2139,9 +2133,10 @@ static struct phy_driver nxp_c45_driver[] = { .get_sqi = nxp_c45_get_sqi, .get_sqi_max = nxp_c45_get_sqi_max, .remove = nxp_c45_remove, - .match_phy_device = tja1120_match_phy_device, + .match_phy_device = tja11xx_no_macsec_match_phy_device, }, { + PHY_ID_MATCH_MODEL(PHY_ID_TJA_1120), .name = "NXP C45 TJA1121", .get_features = nxp_c45_get_features, .driver_data = &tja1120_phy_data, @@ -2164,7 +2159,7 @@ static struct phy_driver nxp_c45_driver[] = { .get_sqi = nxp_c45_get_sqi, .get_sqi_max = nxp_c45_get_sqi_max, .remove = nxp_c45_remove, - .match_phy_device = tja1121_match_phy_device, + .match_phy_device = tja11xx_macsec_match_phy_device, }, }; From patchwork Tue Apr 1 11:46:05 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Christian Marangi (Ansuel)" X-Patchwork-Id: 14034719 X-Patchwork-Delegate: kuba@kernel.org Received: from mail-wm1-f43.google.com (mail-wm1-f43.google.com [209.85.128.43]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 12B46202F80; Tue, 1 Apr 2025 11:46:52 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.128.43 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1743508014; cv=none; b=p5fj52uvKk/8aIQ1/hrmUaSz5UcyS2acUxpZ5vTZ8XgjRvZum63WE3llsv3V4nR/QVmFJKXXRneu3uIp9lfAANjg4LhhkMXeH96D4nC5TsueU7g7xQ3jeZ2y3raDt+JAw68+2t0SWfc5RLv98hVBSxAyDtqvJVTjchhHHbSFIug= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1743508014; c=relaxed/simple; bh=Fw8Mhmj4yOddrjW0INHvn2Cdixlrl52m0hiV/iVxoKI=; h=From:To:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=UDezXqP1GWPVF2pvacWuvPODp/0Yq5F/B3pS5zMwbz3AZWlhLHQ19o6RFEoM1LJp+1myfAuFuKAcSV9zGGvZDyeRSdLHQ9d7N+La41CVYSuH7mrM0gcQwu/74SFnEMuEPW3QYpc4n8FbqC5rouLmPY+QUEZJ+kDU8jfzqu7yb/0= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com; spf=pass smtp.mailfrom=gmail.com; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b=Aqsu/3LU; arc=none smtp.client-ip=209.85.128.43 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=gmail.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="Aqsu/3LU" Received: by mail-wm1-f43.google.com with SMTP id 5b1f17b1804b1-43cf3192f3bso55247785e9.1; Tue, 01 Apr 2025 04:46:52 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20230601; t=1743508011; x=1744112811; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:from:to:cc:subject:date:message-id :reply-to; bh=Wx5narcbW6eR+BDfyixrGWiCVXRk99KznhKxGWd0deo=; b=Aqsu/3LUaVXdGEME65+IvxsV4OOT7yZ+gEJ4q1t0WPbkSSU0BBCIQU960svUu2S/cy WX1sZfqpCIdHqihCPaI+PksQu2OZfsqSQ6t2CDu5jUYQnD26SAHct6VEe9QWhvMgzEo7 yq8cwpLSdn/bXaRiYtB6ymC3k3YQk/8E/kZBAZ9OH60p8ZqojOxCEJM9sDinodaCpg0K OfEzrf1OzP/H1vSfuJ3OHEAHsIn8SHL2pQywxDVsss0gOhfrnuBvh1Kr2KHSaROnehm8 8NSrTMnLhzy6blr7OXiDZrunKIGrUSxdVDInD5fqsAWoL56dTbZs7rLuTaxDUB146SIK TnZA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1743508011; x=1744112811; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=Wx5narcbW6eR+BDfyixrGWiCVXRk99KznhKxGWd0deo=; b=BEAN3l43OVYx4q2mLFobaA43mWdAzrcIvOuMvRbZzPaEchnz1anAp11SFVTrP/WuB8 sR++7SycyIrLZ8y5b/jzekyGw5kAjnUg9WMBy2XEOlw1amsOOq+zg5GnQMIkmdqEBgex cZx5+Zt5+c2gBlk1InRH8P/D76eJG9jEZ0GQg+MOGigZGxSrMFpqDSJB2nw3YqodTN9N N+fZhnZOYIEC3jtOweZk1uA3T65G3w9UfHBT198nseWhI6qP5Lm99XGnt5V9zrZ5g8dO 1qVvG5d+ew63gPACgLJvyjaGW70AuJ6utQHkqlCK4tpy0tV7oKxnA7kUXQ1wJdFwEQVm 0sOg== X-Forwarded-Encrypted: i=1; AJvYcCVsS9kWDETekxZRpKINpIdzQ9WFFKQ35lB4HhJEFmDYX5hoid+p9XfzUPuVKMfVhb79Oubur6ubZj0g3Lch@vger.kernel.org, AJvYcCWVtwW1U4JXUFbAPjMIGkz3CwNt4HeGKo7iNrJotrdGZH3RhGjTZVurwypqNRFSRoz04kgw3JGPXuA3@vger.kernel.org, AJvYcCXpQzUT+cU5TGGLOZOonOcUqolQwH01wypP4b1vLfYaIOgK1G/Md7FmOvRIBp2GI03z/DEORm8Z@vger.kernel.org X-Gm-Message-State: AOJu0Yz5cMZz2ByUhOSMMr+MoMu9rXmYchC4uVwBXlGcHYB9Fgi8sI4r bnQcGPYFlxCcIFnvZWxBLKZwKYhYyZ1qMjI5ANn8PqFpSHMAJbuM X-Gm-Gg: ASbGncsjjNJr5UW+rQdABt+gSpmPFyM+BVOEIzGE+EuJV0KR2SFcijRZs8yKmV2Ka5j SwzEgMLYUbkXfQ8PkbpDKh1bKx/jYeh6U1b/TWgUPk9DuMlsmUsmKg9tAJW2fyZdsKluLjbI05I BX9gQN96/+nB3E3qaH9CMejoHYjDg9Yth1FI4hsMJyRYvi3cGNSBMsj3VMfpXGacczU4+T2imwB wPziXfD3JnYOeTo7xsU3FA2WrbG8FjSq9jccxtQSolFw64Muf/PF04RwN52ZJoLMRtE7l9K/X8+ pOFAL/M+PEVVfXTDQTOyU+3fXhjkX4INTwFObABde9SyBHNUY1uPvkWVziGKKPKuQMClRZKZ7cL bwFa18zGogz1ENA== X-Google-Smtp-Source: AGHT+IGxJ3CAuBlaCKITRy3TT/JA7UPtomUF1BU1da5+Ly9ilpxXlI0ARBhp65hG7UQHHRPYWeePJQ== X-Received: by 2002:a05:600c:3ca6:b0:43c:fa0e:471a with SMTP id 5b1f17b1804b1-43db61d9cf5mr128743135e9.5.1743508010946; Tue, 01 Apr 2025 04:46:50 -0700 (PDT) Received: from localhost.localdomain (93-34-88-225.ip49.fastwebnet.it. [93.34.88.225]) by smtp.googlemail.com with ESMTPSA id 5b1f17b1804b1-43ead679894sm8148175e9.40.2025.04.01.04.46.49 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 01 Apr 2025 04:46:50 -0700 (PDT) From: Christian Marangi To: Christian Marangi , Andrew Lunn , "David S. Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Heiner Kallweit , Russell King , Florian Fainelli , Broadcom internal kernel review list , =?utf-8?q?Marek_Beh=C3=BAn?= , Andrei Botila , Sabrina Dubroca , Daniel Golle , Eric Woudstra , netdev@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [net-next RFC PATCH v5 4/6] net: phy: introduce genphy_match_phy_device() Date: Tue, 1 Apr 2025 13:46:05 +0200 Message-ID: <20250401114611.4063-5-ansuelsmth@gmail.com> X-Mailer: git-send-email 2.48.1 In-Reply-To: <20250401114611.4063-1-ansuelsmth@gmail.com> References: <20250401114611.4063-1-ansuelsmth@gmail.com> Precedence: bulk X-Mailing-List: netdev@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-Patchwork-Delegate: kuba@kernel.org X-Patchwork-State: RFC Introduce new API, genphy_match_phy_device(), to provide a way to check to match a PHY driver for a PHY device based on the info stored in the PHY device struct. The function generalize the logic used in phy_bus_match() to check the PHY ID whether if C45 or C22 ID should be used for matching. This is useful for custom .match_phy_device function that wants to use the generic logic under some condition. (example a PHY is already setup and provide the correct PHY ID) Signed-off-by: Christian Marangi Reviewed-by: Russell King (Oracle) --- drivers/net/phy/phy_device.c | 52 +++++++++++++++++++++++++----------- include/linux/phy.h | 3 +++ 2 files changed, 40 insertions(+), 15 deletions(-) diff --git a/drivers/net/phy/phy_device.c b/drivers/net/phy/phy_device.c index 2d6ceacb2986..ead9a047043a 100644 --- a/drivers/net/phy/phy_device.c +++ b/drivers/net/phy/phy_device.c @@ -503,20 +503,26 @@ static int phy_scan_fixups(struct phy_device *phydev) return 0; } -static int phy_bus_match(struct device *dev, const struct device_driver *drv) +/** + * genphy_match_phy_device - match a PHY device with a PHY driver + * @phydev: target phy_device struct + * @phydrv: target phy_driver struct + * + * Description: Checks whether the given PHY device matches the specified + * PHY driver. For Clause 45 PHYs, iterates over the available device + * identifiers and compares them against the driver's expected PHY ID, + * applying the provided mask. For Clause 22 PHYs, a direct ID comparison + * is performed. + * + * Return: 1 if the PHY device matches the driver, 0 otherwise. + */ +int genphy_match_phy_device(struct phy_device *phydev, + const struct phy_driver *phydrv) { - struct phy_device *phydev = to_phy_device(dev); - const struct phy_driver *phydrv = to_phy_driver(drv); - const int num_ids = ARRAY_SIZE(phydev->c45_ids.device_ids); - int i; - - if (!(phydrv->mdiodrv.flags & MDIO_DEVICE_IS_PHY)) - return 0; - - if (phydrv->match_phy_device) - return phydrv->match_phy_device(phydev, phydrv); - if (phydev->is_c45) { + const int num_ids = ARRAY_SIZE(phydev->c45_ids.device_ids); + int i; + for (i = 1; i < num_ids; i++) { if (phydev->c45_ids.device_ids[i] == 0xffffffff) continue; @@ -525,11 +531,27 @@ static int phy_bus_match(struct device *dev, const struct device_driver *drv) phydrv->phy_id, phydrv->phy_id_mask)) return 1; } + return 0; - } else { - return phy_id_compare(phydev->phy_id, phydrv->phy_id, - phydrv->phy_id_mask); } + + return phy_id_compare(phydev->phy_id, phydrv->phy_id, + phydrv->phy_id_mask); +} +EXPORT_SYMBOL_GPL(genphy_match_phy_device); + +static int phy_bus_match(struct device *dev, const struct device_driver *drv) +{ + struct phy_device *phydev = to_phy_device(dev); + const struct phy_driver *phydrv = to_phy_driver(drv); + + if (!(phydrv->mdiodrv.flags & MDIO_DEVICE_IS_PHY)) + return 0; + + if (phydrv->match_phy_device) + return phydrv->match_phy_device(phydev, phydrv); + + return genphy_match_phy_device(phydev, phydrv); } static ssize_t diff --git a/include/linux/phy.h b/include/linux/phy.h index 7042ceaadcc6..b7aa805e0ad6 100644 --- a/include/linux/phy.h +++ b/include/linux/phy.h @@ -1911,6 +1911,9 @@ char *phy_attached_info_irq(struct phy_device *phydev) __malloc; void phy_attached_info(struct phy_device *phydev); +int genphy_match_phy_device(struct phy_device *phydev, + const struct phy_driver *phydrv); + /* Clause 22 PHY */ int genphy_read_abilities(struct phy_device *phydev); int genphy_setup_forced(struct phy_device *phydev); From patchwork Tue Apr 1 11:46:06 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: "Christian Marangi (Ansuel)" X-Patchwork-Id: 14034720 X-Patchwork-Delegate: kuba@kernel.org Received: from mail-wm1-f52.google.com (mail-wm1-f52.google.com [209.85.128.52]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 5DBAB201262; Tue, 1 Apr 2025 11:46:54 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.128.52 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1743508017; cv=none; b=nTfpBs95WeYz5DFrIdIBLjZU3qoqdJNTwvuCHrnDyHGlWOy25IPP9gHJmKp0URAKdZCOwucbtj++VQ+hxoiwZbZwOwKVOXp2a8A+3D+4/JcD2ev6Tgu3qVtw/KqiKmPCZph6M1vKWeHS3s4RTLkfXjRAikOh9ARTwxx0TDOXNsg= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1743508017; c=relaxed/simple; bh=d4fLMhZD83ZveMQkVNpeMfjjS0B/fjS4UrLcm0jZUwM=; h=From:To:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=bepdAjA/1GJEiVJGe0YgN8mmi5XMm7JTGqvwE0B5vfGmsr+d9vzgB56gw08YXVR1vplPRqhBaxc7UFnPh705aXEG25RKYmaKNM/6RxNUAhrfqwRGjvr3eOhUetMtGpZKh4mkSMVKx7hmxAVb3GGtvIeACIFMODSEjd0bArjgrOw= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com; spf=pass smtp.mailfrom=gmail.com; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b=eyk5KHNW; arc=none smtp.client-ip=209.85.128.52 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=gmail.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="eyk5KHNW" Received: by mail-wm1-f52.google.com with SMTP id 5b1f17b1804b1-4394345e4d5so35583765e9.0; Tue, 01 Apr 2025 04:46:54 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20230601; t=1743508012; x=1744112812; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:from:to:cc:subject:date:message-id :reply-to; bh=nZNi4yf32OrfCKXIJjK6u6jEzYc/HIcRcfkoEPFOMMA=; b=eyk5KHNWJDTfqxQbDyl7f+LDfn6JSpRuuN7wpCa3G1teJ3bhP3ABbSTd4wfp9hIlXY JYcmrMZaivQgHdzvf5XJOdGCSDVoo1iQaqHuITpTbd22z6S+PNqD+KBoHghDfizl6R0s zZl2W0tr55tgQ4ScZDePEv8UflP2OtvH3r8I2zSBM9GsdjV43cN7YJBU07Zg0d0QGLBz nhRlfLTboZGj44IE8IoGfle+HC/BnK/mb2sNx65hJLlXWh2ufOKVTt4z1bBzVsu1acN1 6Jr6KkOjKLLzyNiOxn3gnb3NiOZ5qgJIaLa7A7QSlVoRqvzJj4+2J486HU2YEoj7mhSJ pNcw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1743508012; x=1744112812; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=nZNi4yf32OrfCKXIJjK6u6jEzYc/HIcRcfkoEPFOMMA=; b=Qecyn9lfUlVGXrETk3Ym5/cCMF4vNhpFPr/sKCHiAZ0E7PjV8h+QXm+KoghAvjXT5K 4/DeWE7WlW1l/C04XXBlx6PG4Jgd6XBRapfZ398HkAHcbenT6uTfkHpZ8IqxThAsJmFC dsukbbvudg1ePL2FLet9TfSScvSpGVnVhqgupo28CsYnJm62xrT3cpKbNKSlgB/YpPPo 2XLiJtKLvlwz8dqmoSup9NxDRpUUkNYSnhtVXR9eNi1lB6jORiJLpO9He201gDT3lYeD hdCbt1HIBkmhF0UFmv4FK883YMraovIHE8HGi2nTU7SH8CV6LR6lXCAWWh30emuiri+P f8Dw== X-Forwarded-Encrypted: i=1; AJvYcCUIjm/21lPqW6nNZLNdkzDvZjEaoTq/G8PUaYdhHe0RACoeEQ7z+WkwA0ioj4XmVeL3YMcYRoavMm5nAidM@vger.kernel.org, AJvYcCVDewHgRXcbTEE6KJjfkWUMs0P4z/zzq17qTE3cbh/QJPSvybj4iAPVXUAUPnUX2qN16zV2bk7G@vger.kernel.org, AJvYcCW7Gb7pFBUfdrdQEyZjWH4fD36E/h1ut6JWMCaHmDHONp2+z1BX0bu1mCXyi93xc5t1/DV7IClnXPSF@vger.kernel.org X-Gm-Message-State: AOJu0YzpcAgxxtrWwb9v+wSv21psYODQ3PZvE5rriEvxFS7T/0V5T0Ur x8UTX5Mqa46diVurCY8V8XtiEALrJHF8m2G2BXtPZ+mumShTtZbN X-Gm-Gg: ASbGncsCRz7S603sh9yjPVCjfptGhaujyQxd3WgYx09ZBPhC/8zYF0dQuLelAYAIdCw dsRXVIjmuxrxbm+hpJX4JVTyjeA/0Lahrn9Kq8OZCUQeP2g+P/mx5K94glO1s6T/v5bDjZSkspm wKbReuHOi6sRg8uq7BJcuA9luE5mdVGK5hbLoIk5VkVuSWvpdOC1VPW7Ebl6xpY+b9x6sOc3HZw fjvHvL7hjrjh+YqK2Cb4zYZ5Z3SpbjNh51F2E4sj28RBW8iE+B2L+8tmb0q8/9/y1RoEWshePVW cKSFZxKd7RiiSpnX9M7/ljtkoqhnRZcgX4DeEe6N5o3kGyruZ3jHx3dH/Hw0olG8i8rjhH+HkPp C8GbtDLR4EmKeJw== X-Google-Smtp-Source: AGHT+IGfgh6MGZ78CgBQueQro/XF/i9ORic+Vh1CUJ6FWaS6yxmYPKgXQqBZ30NEoNkkQ1TwK5AidQ== X-Received: by 2002:a05:600c:154a:b0:43c:e467:d6ce with SMTP id 5b1f17b1804b1-43db61d75b1mr113349315e9.4.1743508012315; Tue, 01 Apr 2025 04:46:52 -0700 (PDT) Received: from localhost.localdomain (93-34-88-225.ip49.fastwebnet.it. [93.34.88.225]) by smtp.googlemail.com with ESMTPSA id 5b1f17b1804b1-43ead679894sm8148175e9.40.2025.04.01.04.46.51 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 01 Apr 2025 04:46:51 -0700 (PDT) From: Christian Marangi To: Christian Marangi , Andrew Lunn , "David S. Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Heiner Kallweit , Russell King , Florian Fainelli , Broadcom internal kernel review list , =?utf-8?q?Marek_Beh=C3=BAn?= , Andrei Botila , Sabrina Dubroca , Daniel Golle , Eric Woudstra , netdev@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [net-next RFC PATCH v5 5/6] net: phy: Add support for Aeonsemi AS21xxx PHYs Date: Tue, 1 Apr 2025 13:46:06 +0200 Message-ID: <20250401114611.4063-6-ansuelsmth@gmail.com> X-Mailer: git-send-email 2.48.1 In-Reply-To: <20250401114611.4063-1-ansuelsmth@gmail.com> References: <20250401114611.4063-1-ansuelsmth@gmail.com> Precedence: bulk X-Mailing-List: netdev@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-Patchwork-Delegate: kuba@kernel.org X-Patchwork-State: RFC Add support for Aeonsemi AS21xxx 10G C45 PHYs. These PHYs integrate an IPC to setup some configuration and require special handling to sync with the parity bit. The parity bit is a way the IPC use to follow correct order of command sent. Supported PHYs AS21011JB1, AS21011PB1, AS21010JB1, AS21010PB1, AS21511JB1, AS21511PB1, AS21510JB1, AS21510PB1, AS21210JB1, AS21210PB1 that all register with the PHY ID 0x7500 0x7510 before the firmware is loaded. They all support up to 5 LEDs with various HW mode supported. While implementing it was found some strange coincidence with using the same logic for implementing C22 in MMD regs in Broadcom PHYs. For reference here the AS21xxx PHY name logic: AS21x1xxB1 ^ ^^ | |J: Supports SyncE/PTP | |P: No SyncE/PTP support | 1: Supports 2nd Serdes | 2: Not 2nd Serdes support 0: 10G, 5G, 2.5G 5: 5G, 2.5G 2: 2.5G Signed-off-by: Christian Marangi --- MAINTAINERS | 6 + drivers/net/phy/Kconfig | 12 + drivers/net/phy/Makefile | 1 + drivers/net/phy/as21xxx.c | 1067 +++++++++++++++++++++++++++++++++++++ 4 files changed, 1086 insertions(+) create mode 100644 drivers/net/phy/as21xxx.c diff --git a/MAINTAINERS b/MAINTAINERS index 1cd25139cc58..53ca93b0cc18 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -646,6 +646,12 @@ F: drivers/iio/accel/adxl380.h F: drivers/iio/accel/adxl380_i2c.c F: drivers/iio/accel/adxl380_spi.c +AEONSEMI PHY DRIVER +M: Christian Marangi +L: netdev@vger.kernel.org +S: Maintained +F: drivers/net/phy/as21xxx.c + AF8133J THREE-AXIS MAGNETOMETER DRIVER M: Ondřej Jirman S: Maintained diff --git a/drivers/net/phy/Kconfig b/drivers/net/phy/Kconfig index d29f9f7fd2e1..ba897103d68d 100644 --- a/drivers/net/phy/Kconfig +++ b/drivers/net/phy/Kconfig @@ -119,6 +119,18 @@ config AMCC_QT2025_PHY help Adds support for the Applied Micro Circuits Corporation QT2025 PHY. +config AS21XXX_PHY + tristate "Aeonsemi AS21xxx PHYs" + help + Currently supports the Aeonsemi AS21xxx PHY. + + These are C45 PHYs 10G that require all a generic firmware. + + Supported PHYs AS21011JB1, AS21011PB1, AS21010JB1, AS21010PB1, + AS21511JB1, AS21511PB1, AS21510JB1, AS21510PB1, AS21210JB1, + AS21210PB1 that all register with the PHY ID 0x7500 0x7500 + before the firmware is loaded. + source "drivers/net/phy/aquantia/Kconfig" config AX88796B_PHY diff --git a/drivers/net/phy/Makefile b/drivers/net/phy/Makefile index 23ce205ae91d..a505a6db68fd 100644 --- a/drivers/net/phy/Makefile +++ b/drivers/net/phy/Makefile @@ -40,6 +40,7 @@ obj-$(CONFIG_AIR_EN8811H_PHY) += air_en8811h.o obj-$(CONFIG_AMD_PHY) += amd.o obj-$(CONFIG_AMCC_QT2025_PHY) += qt2025.o obj-$(CONFIG_AQUANTIA_PHY) += aquantia/ +obj-$(CONFIG_AS21XXX_PHY) += as21xxx.o ifdef CONFIG_AX88796B_RUST_PHY obj-$(CONFIG_AX88796B_PHY) += ax88796b_rust.o else diff --git a/drivers/net/phy/as21xxx.c b/drivers/net/phy/as21xxx.c new file mode 100644 index 000000000000..8e1d0845db36 --- /dev/null +++ b/drivers/net/phy/as21xxx.c @@ -0,0 +1,1067 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Aeonsemi AS21XXxX PHY Driver + * + * Author: Christian Marangi + */ + +#include +#include +#include +#include +#include + +#define VEND1_GLB_REG_CPU_RESET_ADDR_LO_BASEADDR 0x3 +#define VEND1_GLB_REG_CPU_RESET_ADDR_HI_BASEADDR 0x4 + +#define VEND1_GLB_REG_CPU_CTRL 0xe +#define VEND1_GLB_CPU_CTRL_MASK GENMASK(4, 0) +#define VEND1_GLB_CPU_CTRL_LED_POLARITY_MASK GENMASK(12, 8) +#define VEND1_GLB_CPU_CTRL_LED_POLARITY(_n) FIELD_PREP(VEND1_GLB_CPU_CTRL_LED_POLARITY_MASK, \ + BIT(_n)) + +#define VEND1_FW_START_ADDR 0x100 + +#define VEND1_GLB_REG_MDIO_INDIRECT_ADDRCMD 0x101 +#define VEND1_GLB_REG_MDIO_INDIRECT_LOAD 0x102 + +#define VEND1_GLB_REG_MDIO_INDIRECT_STATUS 0x103 + +#define VEND1_PTP_CLK 0x142 +#define VEND1_PTP_CLK_EN BIT(6) + +/* 5 LED at step of 0x20 + * FE: Fast-Ethernet (10/100) + * GE: Gigabit-Ethernet (1000) + * NG: New-Generation (2500/5000/10000) + */ +#define VEND1_LED_REG(_n) (0x1800 + ((_n) * 0x10)) +#define VEND1_LED_REG_A_EVENT GENMASK(15, 11) +#define VEND1_LED_CONF 0x1881 +#define VEND1_LED_CONFG_BLINK GENMASK(7, 0) + +#define VEND1_SPEED_STATUS 0x4002 +#define VEND1_SPEED_MASK GENMASK(7, 0) +#define VEND1_SPEED_10000 FIELD_PREP_CONST(VEND1_SPEED_MASK, 0x3) +#define VEND1_SPEED_5000 FIELD_PREP_CONST(VEND1_SPEED_MASK, 0x5) +#define VEND1_SPEED_2500 FIELD_PREP_CONST(VEND1_SPEED_MASK, 0x9) +#define VEND1_SPEED_1000 FIELD_PREP_CONST(VEND1_SPEED_MASK, 0x10) +#define VEND1_SPEED_100 FIELD_PREP_CONST(VEND1_SPEED_MASK, 0x20) +#define VEND1_SPEED_10 FIELD_PREP_CONST(VEND1_SPEED_MASK, 0x0) + +#define VEND1_IPC_CMD 0x5801 +#define AEON_IPC_CMD_PARITY BIT(15) +#define AEON_IPC_CMD_SIZE GENMASK(10, 6) +#define AEON_IPC_CMD_OPCODE GENMASK(5, 0) + +#define IPC_CMD_NOOP 0x0 /* Do nothing */ +#define IPC_CMD_INFO 0x1 /* Get Firmware Version */ +#define IPC_CMD_SYS_CPU 0x2 /* SYS_CPU */ +#define IPC_CMD_BULK_DATA 0xa /* Pass bulk data in ipc registers. */ +#define IPC_CMD_BULK_WRITE 0xc /* Write bulk data to memory */ +#define IPC_CMD_CFG_PARAM 0x1a /* Write config parameters to memory */ +#define IPC_CMD_NG_TESTMODE 0x1b /* Set NG test mode and tone */ +#define IPC_CMD_TEMP_MON 0x15 /* Temperature monitoring function */ +#define IPC_CMD_SET_LED 0x23 /* Set led */ + +#define VEND1_IPC_STS 0x5802 +#define AEON_IPC_STS_PARITY BIT(15) +#define AEON_IPC_STS_SIZE GENMASK(14, 10) +#define AEON_IPC_STS_OPCODE GENMASK(9, 4) +#define AEON_IPC_STS_STATUS GENMASK(3, 0) +#define AEON_IPC_STS_STATUS_RCVD FIELD_PREP_CONST(AEON_IPC_STS_STATUS, 0x1) +#define AEON_IPC_STS_STATUS_PROCESS FIELD_PREP_CONST(AEON_IPC_STS_STATUS, 0x2) +#define AEON_IPC_STS_STATUS_SUCCESS FIELD_PREP_CONST(AEON_IPC_STS_STATUS, 0x4) +#define AEON_IPC_STS_STATUS_ERROR FIELD_PREP_CONST(AEON_IPC_STS_STATUS, 0x8) +#define AEON_IPC_STS_STATUS_BUSY FIELD_PREP_CONST(AEON_IPC_STS_STATUS, 0xe) +#define AEON_IPC_STS_STATUS_READY FIELD_PREP_CONST(AEON_IPC_STS_STATUS, 0xf) + +#define VEND1_IPC_DATA0 0x5808 +#define VEND1_IPC_DATA1 0x5809 +#define VEND1_IPC_DATA2 0x580a +#define VEND1_IPC_DATA3 0x580b +#define VEND1_IPC_DATA4 0x580c +#define VEND1_IPC_DATA5 0x580d +#define VEND1_IPC_DATA6 0x580e +#define VEND1_IPC_DATA7 0x580f +#define VEND1_IPC_DATA(_n) (VEND1_IPC_DATA0 + (_n)) + +/* Sub command of CMD_INFO */ +#define IPC_INFO_VERSION 0x1 + +/* Sub command of CMD_SYS_CPU */ +#define IPC_SYS_CPU_REBOOT 0x3 +#define IPC_SYS_CPU_IMAGE_OFST 0x4 +#define IPC_SYS_CPU_IMAGE_CHECK 0x5 +#define IPC_SYS_CPU_PHY_ENABLE 0x6 + +/* Sub command of CMD_CFG_PARAM */ +#define IPC_CFG_PARAM_DIRECT 0x4 + +/* CFG DIRECT sub command */ +#define IPC_CFG_PARAM_DIRECT_NG_PHYCTRL 0x1 +#define IPC_CFG_PARAM_DIRECT_CU_AN 0x2 +#define IPC_CFG_PARAM_DIRECT_SDS_PCS 0x3 +#define IPC_CFG_PARAM_DIRECT_AUTO_EEE 0x4 +#define IPC_CFG_PARAM_DIRECT_SDS_PMA 0x5 +#define IPC_CFG_PARAM_DIRECT_DPC_RA 0x6 +#define IPC_CFG_PARAM_DIRECT_DPC_PKT_CHK 0x7 +#define IPC_CFG_PARAM_DIRECT_DPC_SDS_WAIT_ETH 0x8 +#define IPC_CFG_PARAM_DIRECT_WDT 0x9 +#define IPC_CFG_PARAM_DIRECT_SDS_RESTART_AN 0x10 +#define IPC_CFG_PARAM_DIRECT_TEMP_MON 0x11 +#define IPC_CFG_PARAM_DIRECT_WOL 0x12 + +/* Sub command of CMD_TEMP_MON */ +#define IPC_CMD_TEMP_MON_GET 0x4 + +#define AS21XXX_MDIO_AN_C22 0xffe0 + +#define PHY_ID_AS21XXX 0x75009410 +/* AS21xxx ID Legend + * AS21x1xxB1 + * ^ ^^ + * | |J: Supports SyncE/PTP + * | |P: No SyncE/PTP support + * | 1: Supports 2nd Serdes + * | 2: Not 2nd Serdes support + * 0: 10G, 5G, 2.5G + * 5: 5G, 2.5G + * 2: 2.5G + */ +#define PHY_ID_AS21011JB1 0x75009402 +#define PHY_ID_AS21011PB1 0x75009412 +#define PHY_ID_AS21010JB1 0x75009422 +#define PHY_ID_AS21010PB1 0x75009432 +#define PHY_ID_AS21511JB1 0x75009442 +#define PHY_ID_AS21511PB1 0x75009452 +#define PHY_ID_AS21510JB1 0x75009462 +#define PHY_ID_AS21510PB1 0x75009472 +#define PHY_ID_AS21210JB1 0x75009482 +#define PHY_ID_AS21210PB1 0x75009492 +#define PHY_VENDOR_AEONSEMI 0x75009400 + +#define AEON_MAX_LDES 5 +#define AEON_IPC_DELAY 10000 +#define AEON_IPC_TIMEOUT (AEON_IPC_DELAY * 100) +#define AEON_IPC_DATA_MAX (8 * sizeof(u16)) + +#define AEON_BOOT_ADDR 0x1000 +#define AEON_CPU_BOOT_ADDR 0x2000 +#define AEON_CPU_CTRL_FW_LOAD (BIT(4) | BIT(2) | BIT(1) | BIT(0)) +#define AEON_CPU_CTRL_FW_START BIT(0) + +enum as21xxx_led_event { + VEND1_LED_REG_A_EVENT_ON_10 = 0x0, + VEND1_LED_REG_A_EVENT_ON_100, + VEND1_LED_REG_A_EVENT_ON_1000, + VEND1_LED_REG_A_EVENT_ON_2500, + VEND1_LED_REG_A_EVENT_ON_5000, + VEND1_LED_REG_A_EVENT_ON_10000, + VEND1_LED_REG_A_EVENT_ON_FE_GE, + VEND1_LED_REG_A_EVENT_ON_NG, + VEND1_LED_REG_A_EVENT_ON_FULL_DUPLEX, + VEND1_LED_REG_A_EVENT_ON_COLLISION, + VEND1_LED_REG_A_EVENT_BLINK_TX, + VEND1_LED_REG_A_EVENT_BLINK_RX, + VEND1_LED_REG_A_EVENT_BLINK_ACT, + VEND1_LED_REG_A_EVENT_ON_LINK, + VEND1_LED_REG_A_EVENT_ON_LINK_BLINK_ACT, + VEND1_LED_REG_A_EVENT_ON_LINK_BLINK_RX, + VEND1_LED_REG_A_EVENT_ON_FE_GE_BLINK_ACT, + VEND1_LED_REG_A_EVENT_ON_NG_BLINK_ACT, + VEND1_LED_REG_A_EVENT_ON_NG_BLINK_FE_GE, + VEND1_LED_REG_A_EVENT_ON_FD_BLINK_COLLISION, + VEND1_LED_REG_A_EVENT_ON, + VEND1_LED_REG_A_EVENT_OFF, +}; + +struct as21xxx_led_pattern_info { + unsigned int pattern; + u16 val; +}; + +struct as21xxx_priv { + bool parity_status; + /* Protect concurrent IPC access */ + struct mutex ipc_lock; +}; + +static struct as21xxx_led_pattern_info as21xxx_led_supported_pattern[] = { + { + .pattern = BIT(TRIGGER_NETDEV_LINK_10), + .val = VEND1_LED_REG_A_EVENT_ON_10 + }, + { + .pattern = BIT(TRIGGER_NETDEV_LINK_100), + .val = VEND1_LED_REG_A_EVENT_ON_100 + }, + { + .pattern = BIT(TRIGGER_NETDEV_LINK_1000), + .val = VEND1_LED_REG_A_EVENT_ON_1000 + }, + { + .pattern = BIT(TRIGGER_NETDEV_LINK_2500), + .val = VEND1_LED_REG_A_EVENT_ON_2500 + }, + { + .pattern = BIT(TRIGGER_NETDEV_LINK_5000), + .val = VEND1_LED_REG_A_EVENT_ON_5000 + }, + { + .pattern = BIT(TRIGGER_NETDEV_LINK_10000), + .val = VEND1_LED_REG_A_EVENT_ON_10000 + }, + { + .pattern = BIT(TRIGGER_NETDEV_LINK), + .val = VEND1_LED_REG_A_EVENT_ON_LINK + }, + { + .pattern = BIT(TRIGGER_NETDEV_LINK_10) | + BIT(TRIGGER_NETDEV_LINK_100) | + BIT(TRIGGER_NETDEV_LINK_1000), + .val = VEND1_LED_REG_A_EVENT_ON_FE_GE + }, + { + .pattern = BIT(TRIGGER_NETDEV_LINK_2500) | + BIT(TRIGGER_NETDEV_LINK_5000) | + BIT(TRIGGER_NETDEV_LINK_10000), + .val = VEND1_LED_REG_A_EVENT_ON_NG + }, + { + .pattern = BIT(TRIGGER_NETDEV_FULL_DUPLEX), + .val = VEND1_LED_REG_A_EVENT_ON_FULL_DUPLEX + }, + { + .pattern = BIT(TRIGGER_NETDEV_TX), + .val = VEND1_LED_REG_A_EVENT_BLINK_TX + }, + { + .pattern = BIT(TRIGGER_NETDEV_RX), + .val = VEND1_LED_REG_A_EVENT_BLINK_RX + }, + { + .pattern = BIT(TRIGGER_NETDEV_TX) | + BIT(TRIGGER_NETDEV_RX), + .val = VEND1_LED_REG_A_EVENT_BLINK_ACT + }, + { + .pattern = BIT(TRIGGER_NETDEV_LINK_10) | + BIT(TRIGGER_NETDEV_LINK_100) | + BIT(TRIGGER_NETDEV_LINK_1000) | + BIT(TRIGGER_NETDEV_LINK_2500) | + BIT(TRIGGER_NETDEV_LINK_5000) | + BIT(TRIGGER_NETDEV_LINK_10000), + .val = VEND1_LED_REG_A_EVENT_ON_LINK + }, + { + .pattern = BIT(TRIGGER_NETDEV_LINK_10) | + BIT(TRIGGER_NETDEV_LINK_100) | + BIT(TRIGGER_NETDEV_LINK_1000) | + BIT(TRIGGER_NETDEV_LINK_2500) | + BIT(TRIGGER_NETDEV_LINK_5000) | + BIT(TRIGGER_NETDEV_LINK_10000) | + BIT(TRIGGER_NETDEV_TX) | + BIT(TRIGGER_NETDEV_RX), + .val = VEND1_LED_REG_A_EVENT_ON_LINK_BLINK_ACT + }, + { + .pattern = BIT(TRIGGER_NETDEV_LINK_10) | + BIT(TRIGGER_NETDEV_LINK_100) | + BIT(TRIGGER_NETDEV_LINK_1000) | + BIT(TRIGGER_NETDEV_LINK_2500) | + BIT(TRIGGER_NETDEV_LINK_5000) | + BIT(TRIGGER_NETDEV_LINK_10000) | + BIT(TRIGGER_NETDEV_RX), + .val = VEND1_LED_REG_A_EVENT_ON_LINK_BLINK_RX + }, + { + .pattern = BIT(TRIGGER_NETDEV_LINK_10) | + BIT(TRIGGER_NETDEV_LINK_100) | + BIT(TRIGGER_NETDEV_LINK_1000) | + BIT(TRIGGER_NETDEV_TX) | + BIT(TRIGGER_NETDEV_RX), + .val = VEND1_LED_REG_A_EVENT_ON_FE_GE_BLINK_ACT + }, + { + .pattern = BIT(TRIGGER_NETDEV_LINK_2500) | + BIT(TRIGGER_NETDEV_LINK_5000) | + BIT(TRIGGER_NETDEV_LINK_10000) | + BIT(TRIGGER_NETDEV_TX) | + BIT(TRIGGER_NETDEV_RX), + .val = VEND1_LED_REG_A_EVENT_ON_NG_BLINK_ACT + } +}; + +static int aeon_firmware_boot(struct phy_device *phydev, const u8 *data, + size_t size) +{ + int i, ret; + u16 val; + + ret = phy_modify_mmd(phydev, MDIO_MMD_VEND1, VEND1_GLB_REG_CPU_CTRL, + VEND1_GLB_CPU_CTRL_MASK, AEON_CPU_CTRL_FW_LOAD); + if (ret) + return ret; + + ret = phy_write_mmd(phydev, MDIO_MMD_VEND1, VEND1_FW_START_ADDR, + AEON_BOOT_ADDR); + if (ret) + return ret; + + ret = phy_modify_mmd(phydev, MDIO_MMD_VEND1, + VEND1_GLB_REG_MDIO_INDIRECT_ADDRCMD, + 0x3ffc, 0xc000); + if (ret) + return ret; + + val = phy_read_mmd(phydev, MDIO_MMD_VEND1, + VEND1_GLB_REG_MDIO_INDIRECT_STATUS); + if (val > 1) { + phydev_err(phydev, "wrong origin mdio_indirect_status: %x\n", val); + return -EINVAL; + } + + /* Firmware is always aligned to u16 */ + for (i = 0; i < size; i += 2) { + val = data[i + 1] << 8 | data[i]; + + ret = phy_write_mmd(phydev, MDIO_MMD_VEND1, + VEND1_GLB_REG_MDIO_INDIRECT_LOAD, val); + if (ret) + return ret; + } + + ret = phy_write_mmd(phydev, MDIO_MMD_VEND1, + VEND1_GLB_REG_CPU_RESET_ADDR_LO_BASEADDR, + lower_16_bits(AEON_CPU_BOOT_ADDR)); + if (ret) + return ret; + + ret = phy_write_mmd(phydev, MDIO_MMD_VEND1, + VEND1_GLB_REG_CPU_RESET_ADDR_HI_BASEADDR, + upper_16_bits(AEON_CPU_BOOT_ADDR)); + if (ret) + return ret; + + return phy_modify_mmd(phydev, MDIO_MMD_VEND1, VEND1_GLB_REG_CPU_CTRL, + VEND1_GLB_CPU_CTRL_MASK, AEON_CPU_CTRL_FW_START); +} + +static int aeon_firmware_load(struct phy_device *phydev) +{ + struct device *dev = &phydev->mdio.dev; + const struct firmware *fw; + const char *fw_name; + int ret; + + ret = of_property_read_string(dev->of_node, "firmware-name", + &fw_name); + if (ret) + return ret; + + ret = request_firmware(&fw, fw_name, dev); + if (ret) { + phydev_err(phydev, "failed to find FW file %s (%d)\n", + fw_name, ret); + return ret; + } + + ret = aeon_firmware_boot(phydev, fw->data, fw->size); + + release_firmware(fw); + + return ret; +} + +static int aeon_ipcs_wait_cmd(struct phy_device *phydev, bool parity_status) +{ + u16 val; + + /* Exit condition logic: + * - Wait for parity bit equal + * - Wait for status success, error OR ready + */ + return phy_read_mmd_poll_timeout(phydev, MDIO_MMD_VEND1, VEND1_IPC_STS, val, + FIELD_GET(AEON_IPC_STS_PARITY, val) == parity_status && + (val & AEON_IPC_STS_STATUS) != AEON_IPC_STS_STATUS_RCVD && + (val & AEON_IPC_STS_STATUS) != AEON_IPC_STS_STATUS_PROCESS && + (val & AEON_IPC_STS_STATUS) != AEON_IPC_STS_STATUS_BUSY, + AEON_IPC_DELAY, AEON_IPC_TIMEOUT, false); +} + +static int aeon_ipc_send_cmd(struct phy_device *phydev, + struct as21xxx_priv *priv, + u16 cmd, u16 *ret_sts) +{ + bool curr_parity; + int ret; + + /* The IPC sync by using a single parity bit. + * Each CMD have alternately this bit set or clear + * to understand correct flow and packet order. + */ + curr_parity = priv->parity_status; + if (priv->parity_status) + cmd |= AEON_IPC_CMD_PARITY; + + /* Always update parity for next packet */ + priv->parity_status = !priv->parity_status; + + ret = phy_write_mmd(phydev, MDIO_MMD_VEND1, VEND1_IPC_CMD, cmd); + if (ret) + return ret; + + /* Wait for packet to be processed */ + usleep_range(AEON_IPC_DELAY, AEON_IPC_DELAY + 5000); + + /* With no ret_sts, ignore waiting for packet completion + * (ipc parity bit sync) + */ + if (!ret_sts) + return 0; + + ret = aeon_ipcs_wait_cmd(phydev, curr_parity); + if (ret) + return ret; + + ret = phy_read_mmd(phydev, MDIO_MMD_VEND1, VEND1_IPC_STS); + if (ret < 0) + return ret; + + *ret_sts = ret; + if ((*ret_sts & AEON_IPC_STS_STATUS) != AEON_IPC_STS_STATUS_SUCCESS) + return -EINVAL; + + return 0; +} + +static int aeon_ipc_send_msg(struct phy_device *phydev, + u16 opcode, u16 *data, unsigned int data_len, + u16 *ret_sts) +{ + struct as21xxx_priv *priv = phydev->priv; + u16 cmd; + int ret; + int i; + + /* IPC have a max of 8 register to transfer data, + * make sure we never exceed this. + */ + if (data_len > AEON_IPC_DATA_MAX) + return -EINVAL; + + mutex_lock(&priv->ipc_lock); + + for (i = 0; i < data_len / sizeof(u16); i++) + phy_write_mmd(phydev, MDIO_MMD_VEND1, VEND1_IPC_DATA(i), + data[i]); + + cmd = FIELD_PREP(AEON_IPC_CMD_SIZE, data_len) | + FIELD_PREP(AEON_IPC_CMD_OPCODE, opcode); + ret = aeon_ipc_send_cmd(phydev, priv, cmd, ret_sts); + if (ret) + phydev_err(phydev, "failed to send ipc msg for %x: %d\n", + opcode, ret); + + mutex_unlock(&priv->ipc_lock); + + return ret; +} + +static int aeon_ipc_rcv_msg(struct phy_device *phydev, + u16 ret_sts, u16 *data) +{ + struct as21xxx_priv *priv = phydev->priv; + unsigned int size; + int ret; + int i; + + if ((ret_sts & AEON_IPC_STS_STATUS) == AEON_IPC_STS_STATUS_ERROR) + return -EINVAL; + + /* Prevent IPC from stack smashing the kernel */ + size = FIELD_GET(AEON_IPC_STS_SIZE, ret_sts); + if (size > AEON_IPC_DATA_MAX) + return -EINVAL; + + mutex_lock(&priv->ipc_lock); + + for (i = 0; i < DIV_ROUND_UP(size, sizeof(u16)); i++) { + ret = phy_read_mmd(phydev, MDIO_MMD_VEND1, VEND1_IPC_DATA(i)); + if (ret < 0) { + size = ret; + goto out; + } + + data[i] = ret; + } + +out: + mutex_unlock(&priv->ipc_lock); + + return size; +} + +static int aeon_ipc_noop(struct phy_device *phydev, + struct as21xxx_priv *priv, u16 *ret_sts) +{ + u16 cmd; + + cmd = FIELD_PREP(AEON_IPC_CMD_SIZE, 0) | + FIELD_PREP(AEON_IPC_CMD_OPCODE, IPC_CMD_NOOP); + + return aeon_ipc_send_cmd(phydev, priv, cmd, ret_sts); +} + +/* Logic to sync parity bit with IPC. + * We send 2 NOP cmd with same partity and we wait for IPC + * to handle the packet only for the second one. This way + * we make sure we are sync for every next cmd. + */ +static int aeon_ipc_sync_parity(struct phy_device *phydev, + struct as21xxx_priv *priv) +{ + u16 ret_sts; + int ret; + + mutex_lock(&priv->ipc_lock); + + /* Send NOP with no parity */ + aeon_ipc_noop(phydev, priv, NULL); + + /* Reset packet parity */ + priv->parity_status = false; + + /* Send second NOP with no parity */ + ret = aeon_ipc_noop(phydev, priv, &ret_sts); + + mutex_unlock(&priv->ipc_lock); + + /* We expect to return -EINVAL */ + if (ret != -EINVAL) + return ret; + + if ((ret_sts & AEON_IPC_STS_STATUS) != AEON_IPC_STS_STATUS_READY) { + phydev_err(phydev, "Invalid IPC status on sync parity: %x\n", + ret_sts); + return -EINVAL; + } + + return 0; +} + +static int aeon_ipc_get_fw_version(struct phy_device *phydev) +{ + u16 ret_data[8], data[1]; + u16 ret_sts; + int ret; + + data[0] = IPC_INFO_VERSION; + ret = aeon_ipc_send_msg(phydev, IPC_CMD_INFO, data, + sizeof(data), &ret_sts); + if (ret) + return ret; + + ret = aeon_ipc_rcv_msg(phydev, ret_sts, ret_data); + if (ret < 0) + return ret; + + phydev_info(phydev, "Firmware Version: %s\n", (char *)ret_data); + + return 0; +} + +static int aeon_dpc_ra_enable(struct phy_device *phydev) +{ + u16 data[2]; + u16 ret_sts; + + data[0] = IPC_CFG_PARAM_DIRECT; + data[1] = IPC_CFG_PARAM_DIRECT_DPC_RA; + + return aeon_ipc_send_msg(phydev, IPC_CMD_CFG_PARAM, data, + sizeof(data), &ret_sts); +} + +static int as21xxx_probe(struct phy_device *phydev) +{ + struct as21xxx_priv *priv; + int ret; + + priv = devm_kzalloc(&phydev->mdio.dev, + sizeof(*priv), GFP_KERNEL); + if (!priv) + return -ENOMEM; + phydev->priv = priv; + + ret = devm_mutex_init(&phydev->mdio.dev, + &priv->ipc_lock); + if (ret) + return ret; + + ret = aeon_ipc_sync_parity(phydev, priv); + if (ret) + return ret; + + ret = aeon_ipc_get_fw_version(phydev); + if (ret) + return ret; + + /* Enable PTP clk if not already Enabled */ + ret = phy_set_bits_mmd(phydev, MDIO_MMD_VEND1, VEND1_PTP_CLK, + VEND1_PTP_CLK_EN); + if (ret) + return ret; + + return aeon_dpc_ra_enable(phydev); +} + +static int as21xxx_read_link(struct phy_device *phydev, int *bmcr) +{ + int status; + + /* Normal C22 BMCR report inconsistent data, use + * the mapped C22 in C45 to have more consistent link info. + */ + *bmcr = phy_read_mmd(phydev, MDIO_MMD_AN, + AS21XXX_MDIO_AN_C22 + MII_BMCR); + if (*bmcr < 0) + return *bmcr; + + /* Autoneg is being started, therefore disregard current + * link status and report link as down. + */ + if (*bmcr & BMCR_ANRESTART) { + phydev->link = 0; + return 0; + } + + status = phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_STAT1); + if (status < 0) + return status; + + phydev->link = !!(status & MDIO_STAT1_LSTATUS); + + return 0; +} + +static int as21xxx_read_c22_lpa(struct phy_device *phydev) +{ + int lpagb; + + /* MII_STAT1000 are only filled in the mapped C22 + * in C45, use that to fill lpagb values and check. + */ + lpagb = phy_read_mmd(phydev, MDIO_MMD_AN, + AS21XXX_MDIO_AN_C22 + MII_STAT1000); + if (lpagb < 0) + return lpagb; + + if (lpagb & LPA_1000MSFAIL) { + int adv = phy_read_mmd(phydev, MDIO_MMD_AN, + AS21XXX_MDIO_AN_C22 + MII_CTRL1000); + + if (adv < 0) + return adv; + + if (adv & CTL1000_ENABLE_MASTER) + phydev_err(phydev, "Master/Slave resolution failed, maybe conflicting manual settings?\n"); + else + phydev_err(phydev, "Master/Slave resolution failed\n"); + return -ENOLINK; + } + + mii_stat1000_mod_linkmode_lpa_t(phydev->lp_advertising, + lpagb); + + return 0; +} + +static int as21xxx_read_status(struct phy_device *phydev) +{ + int bmcr, old_link = phydev->link; + int ret; + + ret = as21xxx_read_link(phydev, &bmcr); + if (ret) + return ret; + + /* why bother the PHY if nothing can have changed */ + if (phydev->autoneg == AUTONEG_ENABLE && old_link && phydev->link) + return 0; + + phydev->speed = SPEED_UNKNOWN; + phydev->duplex = DUPLEX_UNKNOWN; + phydev->pause = 0; + phydev->asym_pause = 0; + + if (phydev->autoneg == AUTONEG_ENABLE) { + ret = genphy_c45_read_lpa(phydev); + if (ret) + return ret; + + ret = as21xxx_read_c22_lpa(phydev); + if (ret) + return ret; + + phy_resolve_aneg_linkmode(phydev); + } else { + int speed; + + linkmode_zero(phydev->lp_advertising); + + speed = phy_read_mmd(phydev, MDIO_MMD_VEND1, + VEND1_SPEED_STATUS); + if (speed < 0) + return speed; + + switch (speed & VEND1_SPEED_STATUS) { + case VEND1_SPEED_10000: + phydev->speed = SPEED_10000; + phydev->duplex = DUPLEX_FULL; + break; + case VEND1_SPEED_5000: + phydev->speed = SPEED_5000; + phydev->duplex = DUPLEX_FULL; + break; + case VEND1_SPEED_2500: + phydev->speed = SPEED_2500; + phydev->duplex = DUPLEX_FULL; + break; + case VEND1_SPEED_1000: + phydev->speed = SPEED_1000; + if (bmcr & BMCR_FULLDPLX) + phydev->duplex = DUPLEX_FULL; + else + phydev->duplex = DUPLEX_HALF; + break; + case VEND1_SPEED_100: + phydev->speed = SPEED_100; + phydev->duplex = DUPLEX_FULL; + break; + case VEND1_SPEED_10: + phydev->speed = SPEED_10; + phydev->duplex = DUPLEX_FULL; + break; + default: + return -EINVAL; + } + } + + return 0; +} + +static int as21xxx_led_brightness_set(struct phy_device *phydev, + u8 index, enum led_brightness value) +{ + u16 val = VEND1_LED_REG_A_EVENT_OFF; + + if (index > AEON_MAX_LDES) + return -EINVAL; + + if (value) + val = VEND1_LED_REG_A_EVENT_ON; + + return phy_modify_mmd(phydev, MDIO_MMD_VEND1, + VEND1_LED_REG(index), + VEND1_LED_REG_A_EVENT, + FIELD_PREP(VEND1_LED_REG_A_EVENT, val)); +} + +static int as21xxx_led_hw_is_supported(struct phy_device *phydev, u8 index, + unsigned long rules) +{ + int i; + + if (index > AEON_MAX_LDES) + return -EINVAL; + + for (i = 0; i < ARRAY_SIZE(as21xxx_led_supported_pattern); i++) + if (rules == as21xxx_led_supported_pattern[i].pattern) + return 0; + + return -EOPNOTSUPP; +} + +static int as21xxx_led_hw_control_get(struct phy_device *phydev, u8 index, + unsigned long *rules) +{ + int i, val; + + if (index > AEON_MAX_LDES) + return -EINVAL; + + val = phy_read_mmd(phydev, MDIO_MMD_VEND1, VEND1_LED_REG(index)); + if (val < 0) + return val; + + val = FIELD_GET(VEND1_LED_REG_A_EVENT, val); + for (i = 0; i < ARRAY_SIZE(as21xxx_led_supported_pattern); i++) + if (val == as21xxx_led_supported_pattern[i].val) { + *rules = as21xxx_led_supported_pattern[i].pattern; + return 0; + } + + /* Should be impossible */ + return -EINVAL; +} + +static int as21xxx_led_hw_control_set(struct phy_device *phydev, u8 index, + unsigned long rules) +{ + u16 val = 0; + int i; + + if (index > AEON_MAX_LDES) + return -EINVAL; + + for (i = 0; i < ARRAY_SIZE(as21xxx_led_supported_pattern); i++) + if (rules == as21xxx_led_supported_pattern[i].pattern) { + val = as21xxx_led_supported_pattern[i].val; + break; + } + + return phy_modify_mmd(phydev, MDIO_MMD_VEND1, + VEND1_LED_REG(index), + VEND1_LED_REG_A_EVENT, + FIELD_PREP(VEND1_LED_REG_A_EVENT, val)); +} + +static int as21xxx_led_polarity_set(struct phy_device *phydev, int index, + unsigned long modes) +{ + bool led_active_low = false; + u16 mask, val = 0; + u32 mode; + + if (index > AEON_MAX_LDES) + return -EINVAL; + + for_each_set_bit(mode, &modes, __PHY_LED_MODES_NUM) { + switch (mode) { + case PHY_LED_ACTIVE_LOW: + led_active_low = true; + break; + case PHY_LED_ACTIVE_HIGH: /* default mode */ + led_active_low = false; + break; + default: + return -EINVAL; + } + } + + mask = VEND1_GLB_CPU_CTRL_LED_POLARITY(index); + if (led_active_low) + val = VEND1_GLB_CPU_CTRL_LED_POLARITY(index); + + return phy_modify_mmd(phydev, MDIO_MMD_VEND1, + VEND1_GLB_REG_CPU_CTRL, + mask, val); +} + +static int as21xxx_match_phy_device(struct phy_device *phydev, + const struct phy_driver *phydrv) +{ + struct as21xxx_priv *priv; + u16 ret_sts; + u32 phy_id; + int ret; + + /* Skip PHY that are not AS21xxx or already have firmware loaded */ + if (phydev->c45_ids.device_ids[MDIO_MMD_PCS] != PHY_ID_AS21XXX) + return genphy_match_phy_device(phydev, phydrv); + + /* Read PHY ID to handle firmware just loaded */ + ret = phy_read_mmd(phydev, MDIO_MMD_PCS, MII_PHYSID1); + if (ret < 0) + return ret; + phy_id = ret << 16; + + ret = phy_read_mmd(phydev, MDIO_MMD_PCS, MII_PHYSID2); + if (ret < 0) + return ret; + phy_id |= ret; + + /* With PHY ID not the generic AS21xxx one assume + * the firmware just loaded + */ + if (phy_id != PHY_ID_AS21XXX) + return phy_id == phydrv->phy_id; + + /* Allocate temp priv and load the firmware */ + priv = kzalloc(sizeof(*priv), GFP_KERNEL); + if (!priv) + return -ENOMEM; + + mutex_init(&priv->ipc_lock); + + ret = aeon_firmware_load(phydev); + if (ret) + goto out; + + /* Sync parity... */ + ret = aeon_ipc_sync_parity(phydev, priv); + if (ret) + goto out; + + /* ...and send a third NOOP cmd to wait for firmware finish loading */ + ret = aeon_ipc_noop(phydev, priv, &ret_sts); + if (ret) + goto out; + +out: + mutex_destroy(&priv->ipc_lock); + kfree(priv); + + /* Return not maching anyway as PHY ID will change after + * firmware is loaded. This relies on the driver probe + * order where the first PHY driver probed is the + * generic one. + */ + return ret; +} + +static struct phy_driver as21xxx_drivers[] = { + { + /* PHY expose in C45 as 0x7500 0x9410 + * before firmware is loaded. + * This driver entry must be attempted first to load + * the firmware and thus update the ID registers. + */ + PHY_ID_MATCH_EXACT(PHY_ID_AS21XXX), + .name = "Aeonsemi AS21xxx", + .match_phy_device = as21xxx_match_phy_device, + }, + { + PHY_ID_MATCH_EXACT(PHY_ID_AS21011JB1), + .name = "Aeonsemi AS21011JB1", + .probe = as21xxx_probe, + .match_phy_device = as21xxx_match_phy_device, + .read_status = as21xxx_read_status, + .led_brightness_set = as21xxx_led_brightness_set, + .led_hw_is_supported = as21xxx_led_hw_is_supported, + .led_hw_control_set = as21xxx_led_hw_control_set, + .led_hw_control_get = as21xxx_led_hw_control_get, + .led_polarity_set = as21xxx_led_polarity_set, + }, + { + PHY_ID_MATCH_EXACT(PHY_ID_AS21011PB1), + .name = "Aeonsemi AS21011PB1", + .probe = as21xxx_probe, + .match_phy_device = as21xxx_match_phy_device, + .read_status = as21xxx_read_status, + .led_brightness_set = as21xxx_led_brightness_set, + .led_hw_is_supported = as21xxx_led_hw_is_supported, + .led_hw_control_set = as21xxx_led_hw_control_set, + .led_hw_control_get = as21xxx_led_hw_control_get, + .led_polarity_set = as21xxx_led_polarity_set, + }, + { + PHY_ID_MATCH_EXACT(PHY_ID_AS21010PB1), + .name = "Aeonsemi AS21010PB1", + .probe = as21xxx_probe, + .match_phy_device = as21xxx_match_phy_device, + .read_status = as21xxx_read_status, + .led_brightness_set = as21xxx_led_brightness_set, + .led_hw_is_supported = as21xxx_led_hw_is_supported, + .led_hw_control_set = as21xxx_led_hw_control_set, + .led_hw_control_get = as21xxx_led_hw_control_get, + .led_polarity_set = as21xxx_led_polarity_set, + }, + { + PHY_ID_MATCH_EXACT(PHY_ID_AS21010JB1), + .name = "Aeonsemi AS21010JB1", + .probe = as21xxx_probe, + .match_phy_device = as21xxx_match_phy_device, + .read_status = as21xxx_read_status, + .led_brightness_set = as21xxx_led_brightness_set, + .led_hw_is_supported = as21xxx_led_hw_is_supported, + .led_hw_control_set = as21xxx_led_hw_control_set, + .led_hw_control_get = as21xxx_led_hw_control_get, + .led_polarity_set = as21xxx_led_polarity_set, + }, + { + PHY_ID_MATCH_EXACT(PHY_ID_AS21210PB1), + .name = "Aeonsemi AS21210PB1", + .probe = as21xxx_probe, + .match_phy_device = as21xxx_match_phy_device, + .read_status = as21xxx_read_status, + .led_brightness_set = as21xxx_led_brightness_set, + .led_hw_is_supported = as21xxx_led_hw_is_supported, + .led_hw_control_set = as21xxx_led_hw_control_set, + .led_hw_control_get = as21xxx_led_hw_control_get, + .led_polarity_set = as21xxx_led_polarity_set, + }, + { + PHY_ID_MATCH_EXACT(PHY_ID_AS21510JB1), + .name = "Aeonsemi AS21510JB1", + .probe = as21xxx_probe, + .match_phy_device = as21xxx_match_phy_device, + .read_status = as21xxx_read_status, + .led_brightness_set = as21xxx_led_brightness_set, + .led_hw_is_supported = as21xxx_led_hw_is_supported, + .led_hw_control_set = as21xxx_led_hw_control_set, + .led_hw_control_get = as21xxx_led_hw_control_get, + .led_polarity_set = as21xxx_led_polarity_set, + }, + { + PHY_ID_MATCH_EXACT(PHY_ID_AS21510PB1), + .name = "Aeonsemi AS21510PB1", + .probe = as21xxx_probe, + .match_phy_device = as21xxx_match_phy_device, + .read_status = as21xxx_read_status, + .led_brightness_set = as21xxx_led_brightness_set, + .led_hw_is_supported = as21xxx_led_hw_is_supported, + .led_hw_control_set = as21xxx_led_hw_control_set, + .led_hw_control_get = as21xxx_led_hw_control_get, + .led_polarity_set = as21xxx_led_polarity_set, + }, + { + PHY_ID_MATCH_EXACT(PHY_ID_AS21511JB1), + .name = "Aeonsemi AS21511JB1", + .probe = as21xxx_probe, + .match_phy_device = as21xxx_match_phy_device, + .read_status = as21xxx_read_status, + .led_brightness_set = as21xxx_led_brightness_set, + .led_hw_is_supported = as21xxx_led_hw_is_supported, + .led_hw_control_set = as21xxx_led_hw_control_set, + .led_hw_control_get = as21xxx_led_hw_control_get, + .led_polarity_set = as21xxx_led_polarity_set, + }, + { + PHY_ID_MATCH_EXACT(PHY_ID_AS21210JB1), + .name = "Aeonsemi AS21210JB1", + .probe = as21xxx_probe, + .match_phy_device = as21xxx_match_phy_device, + .read_status = as21xxx_read_status, + .led_brightness_set = as21xxx_led_brightness_set, + .led_hw_is_supported = as21xxx_led_hw_is_supported, + .led_hw_control_set = as21xxx_led_hw_control_set, + .led_hw_control_get = as21xxx_led_hw_control_get, + .led_polarity_set = as21xxx_led_polarity_set, + }, + { + PHY_ID_MATCH_EXACT(PHY_ID_AS21511PB1), + .name = "Aeonsemi AS21511PB1", + .probe = as21xxx_probe, + .match_phy_device = as21xxx_match_phy_device, + .read_status = as21xxx_read_status, + .led_brightness_set = as21xxx_led_brightness_set, + .led_hw_is_supported = as21xxx_led_hw_is_supported, + .led_hw_control_set = as21xxx_led_hw_control_set, + .led_hw_control_get = as21xxx_led_hw_control_get, + .led_polarity_set = as21xxx_led_polarity_set, + }, +}; +module_phy_driver(as21xxx_drivers); + +static struct mdio_device_id __maybe_unused as21xxx_tbl[] = { + { PHY_ID_MATCH_VENDOR(PHY_VENDOR_AEONSEMI) }, + { } +}; +MODULE_DEVICE_TABLE(mdio, as21xxx_tbl); + +MODULE_DESCRIPTION("Aeonsemi AS21xxx PHY driver"); +MODULE_AUTHOR("Christian Marangi "); +MODULE_LICENSE("GPL"); From patchwork Tue Apr 1 11:46:07 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Christian Marangi (Ansuel)" X-Patchwork-Id: 14034721 X-Patchwork-Delegate: kuba@kernel.org Received: from mail-wm1-f41.google.com (mail-wm1-f41.google.com [209.85.128.41]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 57F38204098; Tue, 1 Apr 2025 11:46:55 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.128.41 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1743508019; cv=none; b=fBXyo6Ksvrb/vx2ZxV7hj3D1nJSeVu+6rbQjbd1v0dkvxq2D2k9h7Gl6EfIidExD43DULuSUJZco9CmufCa/SpCwkeGhE0FT7RPqdq4Xkv9f9gmQNUB19veENOMEN4nsLWjTZn3EcBdX9nFNt6ETUFH4oh/8mo6jsIZvAPcgzCc= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1743508019; c=relaxed/simple; bh=4THuh4l2cNhIbqy6HlF/J7Hc+TBYJG/XLk/3DEKuZfU=; h=From:To:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=l+z2761lW9aTAJ7bCbBvQYDi1yaMoY/WvWsxLlr3xmR1xijH/PTcTNvQI+j80C1ilVVhuwRiOXXUBJAZrEBLvsAS6gUM5lIxFehhUhrH8Lh+OCZThrXK48Gu6CDMv82otNbgAtyn2rZ5Y4LKaXDE8U0UVjKoUFOh7mZhOPMbKKY= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com; spf=pass smtp.mailfrom=gmail.com; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b=ewBH0D1y; arc=none smtp.client-ip=209.85.128.41 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=gmail.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="ewBH0D1y" Received: by mail-wm1-f41.google.com with SMTP id 5b1f17b1804b1-43d0c18e84eso24931165e9.3; Tue, 01 Apr 2025 04:46:55 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20230601; t=1743508014; x=1744112814; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:from:to:cc:subject:date:message-id :reply-to; bh=1XrhBUQXr1bVfeeEaE7z+isBFAKnFsoBJygdtgcyNsY=; b=ewBH0D1yOLtVc7ULAh5fwUBFzWVbixVbkBq9vbUFCuDU6+NnVUiWhiHTrngGvYAQi1 Wu1KbikOY2zeX1n+kUF4nrQNhjl7ZxtCnHeHCBlCs7RZ7GGdKehmKhIXpENBaML4haTT v7Fh1fZkyvhj0SWrAfZt5kiYAgAaMYoAWOICCl6kGDKP3kynompF9Da2CNJ1k1Ib8JZ3 /nXDs0ehmqtUcuxjUrtPhJ0LDxzooNzjqh2m9Qs0rvuQ2B5KEzClt+0pQ94eAV2H3z5s jFxQ77PsZ/dKJhgDZXIjngCqWsFa9lZ+Zdmv+7t8q6B8F2RxGk+Y9FGwWt4zy3SDdDbL CM7A== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1743508014; x=1744112814; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=1XrhBUQXr1bVfeeEaE7z+isBFAKnFsoBJygdtgcyNsY=; b=hpJPLwk+GJcYVha3+RTul76XDy0zVNBzSo67AXWAxjyvicBuxFRd/WHMjS/XSj0OM9 NZw83SXTOf8h1l8JdicIK2y5FmhqxDng+QJNEvpxtgbhG70AivQ4+W3lsjYGai9W+2Uz IW/uV5d+zh9C4aAZSQYOF0u88vpksCVLxAtQMLDDH0etuf4B7JqNGGvA3wVD7wx2kRqM Avol91dQqD6aPNo6BtC6j2srNifijVY/gI/ulKPZq/ZlcneTOQ7LinNDQbsFWOFP+Zw8 yjRnDOFzvTdEm4Tgn4nKwd/19gL/gucSzdwukubWNzfPfcSz0+DASYa3WaHcBm2wyjOM 1xYQ== X-Forwarded-Encrypted: i=1; AJvYcCUbpi0O4OeiORhSSngd8Xzd08yy1cMkeeb+1qZl2qW5mrkdX2fObCHKLSDk03hgfRpnQaDvlYZfSIQi@vger.kernel.org, AJvYcCVD4nZisD+S5plZqGzgFDhPMnMmqgDofQUgMfwdszxRm3CMIbR8jwC1z9pj8FcbTqt8RJ702wZk@vger.kernel.org, AJvYcCVrEXXaNYGVrv81s7LfKdiZRjxeJuYoT7R3jydDP+E8icOIEiurOq+Odz92pAORLN6dGNgVWDj0icQuRZjp@vger.kernel.org X-Gm-Message-State: AOJu0YzIAJyomOovqLEiP2lwFixQ8aecpekAMnkxSRURmqdVVqzSuSkx LmWcu2A8Xlcew4ALv8eFRsa/z+ep0mKGHKyvCdVjIe7FNnnRoPHa X-Gm-Gg: ASbGnctjvCc9W/OATk4elH+X1YeiJNe+vDvKJT3L6/FNizHFS8MQoOFFN1QkGNtmESd 8/xrxdo+JWww+aQ5g1dMKG40+gN5fTuoDmdGqjdqNivanjvCkO1B8/ITG1OVAFNakFzAySN+YFg bv8zLPrtViQev6149VBlY62YbkFoB397cgj0n9fkDPaD2f2ux+DXTWdnFSgEyTp2V8ICJWLWzX7 2aGMsfPwnpO0Rd83dZNZcRUBO43s551L4CyN92QHE+oNxL/iy+D1klEjstyTj9KGoCZ0NPRSQr0 VoRotv/XfKjoj95yK7YkBwrtXc3clouMnVCFMUhraUK35WFlpGkcuM1MLKEbdsU9c+ThIoQ8vBu bkW6/S2GzmWtUITxVZ5AK97dZ X-Google-Smtp-Source: AGHT+IH6dilQJLlHGgeFR3Ax8B3Ld3g5aXQaayD1pRKUbQJUZ4aGA9CVqtKPy6UCRne+8g3E6M/oRw== X-Received: by 2002:a05:600c:1f89:b0:43d:36c:f24 with SMTP id 5b1f17b1804b1-43db61fed40mr104748755e9.13.1743508014190; Tue, 01 Apr 2025 04:46:54 -0700 (PDT) Received: from localhost.localdomain (93-34-88-225.ip49.fastwebnet.it. [93.34.88.225]) by smtp.googlemail.com with ESMTPSA id 5b1f17b1804b1-43ead679894sm8148175e9.40.2025.04.01.04.46.52 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 01 Apr 2025 04:46:53 -0700 (PDT) From: Christian Marangi To: Christian Marangi , Andrew Lunn , "David S. Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Heiner Kallweit , Russell King , Florian Fainelli , Broadcom internal kernel review list , =?utf-8?q?Marek_Beh=C3=BAn?= , Andrei Botila , Sabrina Dubroca , Daniel Golle , Eric Woudstra , netdev@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [net-next RFC PATCH v5 6/6] dt-bindings: net: Document support for Aeonsemi PHYs Date: Tue, 1 Apr 2025 13:46:07 +0200 Message-ID: <20250401114611.4063-7-ansuelsmth@gmail.com> X-Mailer: git-send-email 2.48.1 In-Reply-To: <20250401114611.4063-1-ansuelsmth@gmail.com> References: <20250401114611.4063-1-ansuelsmth@gmail.com> Precedence: bulk X-Mailing-List: netdev@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-Patchwork-Delegate: kuba@kernel.org X-Patchwork-State: RFC Add Aeonsemi PHYs and the requirement of a firmware to correctly work. Also document the max number of LEDs supported and what PHY ID expose when no firmware is loaded. Supported PHYs AS21011JB1, AS21011PB1, AS21010JB1, AS21010PB1, AS21511JB1, AS21511PB1, AS21510JB1, AS21510PB1, AS21210JB1, AS21210PB1 that all register with the PHY ID 0x7500 0x9410 on C45 registers before the firmware is loaded. Reviewed-by: Rob Herring (Arm) Signed-off-by: Christian Marangi --- .../bindings/net/aeonsemi,as21xxx.yaml | 122 ++++++++++++++++++ MAINTAINERS | 1 + 2 files changed, 123 insertions(+) create mode 100644 Documentation/devicetree/bindings/net/aeonsemi,as21xxx.yaml diff --git a/Documentation/devicetree/bindings/net/aeonsemi,as21xxx.yaml b/Documentation/devicetree/bindings/net/aeonsemi,as21xxx.yaml new file mode 100644 index 000000000000..69eb29dc4d7b --- /dev/null +++ b/Documentation/devicetree/bindings/net/aeonsemi,as21xxx.yaml @@ -0,0 +1,122 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/net/aeonsemi,as21xxx.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Aeonsemi AS21XXX Ethernet PHY + +maintainers: + - Christian Marangi + +description: | + Aeonsemi AS21xxx Ethernet PHYs requires a firmware to be loaded to actually + work. The same firmware is compatible with various PHYs of the same family. + + A PHY with not firmware loaded will be exposed on the MDIO bus with ID + 0x7500 0x7500 or 0x7500 0x9410 on C45 registers. + + This can be done and is implemented by OEM in 2 different way: + - Attached SPI flash directly to the PHY with the firmware. The PHY + will self load the firmware in the presence of this configuration. + - Manually provided firmware loaded from a file in the filesystem. + + Each PHY can support up to 5 LEDs. + + AS2xxx PHY Name logic: + + AS21x1xxB1 + ^ ^^ + | |J: Supports SyncE/PTP + | |P: No SyncE/PTP support + | 1: Supports 2nd Serdes + | 2: Not 2nd Serdes support + 0: 10G, 5G, 2.5G + 5: 5G, 2.5G + 2: 2.5G + +allOf: + - $ref: ethernet-phy.yaml# + +select: + properties: + compatible: + contains: + enum: + - ethernet-phy-id7500.9410 + - ethernet-phy-id7500.9402 + - ethernet-phy-id7500.9412 + - ethernet-phy-id7500.9422 + - ethernet-phy-id7500.9432 + - ethernet-phy-id7500.9442 + - ethernet-phy-id7500.9452 + - ethernet-phy-id7500.9462 + - ethernet-phy-id7500.9472 + - ethernet-phy-id7500.9482 + - ethernet-phy-id7500.9492 + required: + - compatible + +properties: + reg: + maxItems: 1 + + firmware-name: + description: specify the name of PHY firmware to load + maxItems: 1 + +required: + - compatible + - reg + +if: + properties: + compatible: + contains: + const: ethernet-phy-id7500.9410 +then: + required: + - firmware-name +else: + properties: + firmware-name: false + +unevaluatedProperties: false + +examples: + - | + #include + + mdio { + #address-cells = <1>; + #size-cells = <0>; + + ethernet-phy@1f { + compatible = "ethernet-phy-id7500.9410", + "ethernet-phy-ieee802.3-c45"; + + reg = <31>; + firmware-name = "as21x1x_fw.bin"; + + leds { + #address-cells = <1>; + #size-cells = <0>; + + led@0 { + reg = <0>; + color = ; + function = LED_FUNCTION_LAN; + function-enumerator = <0>; + default-state = "keep"; + }; + + led@1 { + reg = <1>; + color = ; + function = LED_FUNCTION_LAN; + function-enumerator = <1>; + default-state = "keep"; + }; + }; + }; + }; diff --git a/MAINTAINERS b/MAINTAINERS index 53ca93b0cc18..310530649a48 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -650,6 +650,7 @@ AEONSEMI PHY DRIVER M: Christian Marangi L: netdev@vger.kernel.org S: Maintained +F: Documentation/devicetree/bindings/net/aeonsemi,as21xxx.yaml F: drivers/net/phy/as21xxx.c AF8133J THREE-AXIS MAGNETOMETER DRIVER