From patchwork Wed Apr 2 08:31:49 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Kandpal, Suraj" X-Patchwork-Id: 14035634 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id DB9E7C28B20 for ; Wed, 2 Apr 2025 08:32:02 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 7321B10E6EC; Wed, 2 Apr 2025 08:32:02 +0000 (UTC) Authentication-Results: gabe.freedesktop.org; dkim=pass (2048-bit key; unprotected) header.d=intel.com header.i=@intel.com header.b="MXTC1ihj"; dkim-atps=neutral Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.19]) by gabe.freedesktop.org (Postfix) with ESMTPS id 5515F10E6EB; Wed, 2 Apr 2025 08:32:01 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1743582722; x=1775118722; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=I2LeGh5U+qwOwmqqifV0117BsN2SWDGAAH8Nn3DxVnk=; b=MXTC1ihjI5Ot9euJoAClSTvCZEODT/Oo8q4C5zw71D8mBRcAqVByfOPl B8G/rkxjhhya4PX/ZCuDDMP3H0vImj3XHuBefECMUOIkQ2HlGNj80BTx5 MzI6buX0YMgZRtDJ5Mavh5HSjKseCredxoWBahOsqTA9jAtlDAB81gLaw T7W6wPPriRRTcDtmuCxcAQ/8gQ7wmfL49KDBz9SONQto9pBkhEhrQh2oC 95iu0yNA8ycITmmLPL1LmQOveGWvkKweC4rqKBC2aFtywG0SW3ImbqMBJ OIyXeHu9RFyQbtzLn3Oy4Ux31rj2EO6kpvyHUVDn5cnYBNLSNIOxAozW8 g==; X-CSE-ConnectionGUID: vEjFKBrNSvqEdl1VFCtOVw== X-CSE-MsgGUID: kQpVL1gUQ7yewffUs8mj7g== X-IronPort-AV: E=McAfee;i="6700,10204,11391"; a="44828652" X-IronPort-AV: E=Sophos;i="6.14,295,1736841600"; d="scan'208";a="44828652" Received: from fmviesa007.fm.intel.com ([10.60.135.147]) by orvoesa111.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 02 Apr 2025 01:32:02 -0700 X-CSE-ConnectionGUID: eWVhUIisRdWWSjpaKkZ8AQ== X-CSE-MsgGUID: oX3BFckrSJmqWR3ChfDVjg== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.14,295,1736841600"; d="scan'208";a="126612282" Received: from kandpal-x299-ud4-pro.iind.intel.com ([10.190.239.10]) by fmviesa007.fm.intel.com with ESMTP; 02 Apr 2025 01:31:58 -0700 From: Suraj Kandpal To: intel-xe@lists.freedesktop.org, intel-gfx@lists.freedesktop.org Cc: ankit.k.nautiyal@intel.com, uma.shankar@intel.com, jani.nikula@intel.com, mika.kahola@intel.com, ville.syrjala@intel.com, Suraj Kandpal Subject: [PATCH 01/16] drm/i915/dpll: Rename intel_shared_dpll_state Date: Wed, 2 Apr 2025 14:01:49 +0530 Message-Id: <20250402083204.1523470-2-suraj.kandpal@intel.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20250402083204.1523470-1-suraj.kandpal@intel.com> References: <20250402083204.1523470-1-suraj.kandpal@intel.com> MIME-Version: 1.0 X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" Rename intel_shared_dpll_state to just intel_dpll_state since it may not necessarily store share dpll state info specially since DISPLAY_VER >= 14 PLL's are not shared. Also change the name of variables which may have been assoiciated as a shared_dpll. Signed-off-by: Suraj Kandpal --- .../drm/i915/display/intel_display_types.h | 2 +- drivers/gpu/drm/i915/display/intel_dpll_mgr.c | 56 +++++++++---------- drivers/gpu/drm/i915/display/intel_dpll_mgr.h | 8 +-- 3 files changed, 33 insertions(+), 33 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h b/drivers/gpu/drm/i915/display/intel_display_types.h index 367b53a9eae2..7d1c64f7b405 100644 --- a/drivers/gpu/drm/i915/display/intel_display_types.h +++ b/drivers/gpu/drm/i915/display/intel_display_types.h @@ -591,7 +591,7 @@ struct intel_atomic_state { bool dpll_set, modeset; - struct intel_shared_dpll_state shared_dpll[I915_NUM_PLLS]; + struct intel_dpll_state dpll_state[I915_NUM_PLLS]; struct intel_dp_tunnel_inherited_state *inherited_dp_tunnels; diff --git a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c index ec7feef1ef59..6edb4570d764 100644 --- a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c +++ b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c @@ -119,17 +119,17 @@ struct intel_dpll_mgr { static void intel_atomic_duplicate_dpll_state(struct intel_display *display, - struct intel_shared_dpll_state *shared_dpll) + struct intel_dpll_state *dpll_state) { struct intel_shared_dpll *pll; int i; /* Copy shared dpll state */ for_each_shared_dpll(display, pll, i) - shared_dpll[pll->index] = pll->state; + dpll_state[pll->index] = pll->state; } -static struct intel_shared_dpll_state * +static struct intel_dpll_state * intel_atomic_get_shared_dpll_state(struct drm_atomic_state *s) { struct intel_atomic_state *state = to_intel_atomic_state(s); @@ -141,10 +141,10 @@ intel_atomic_get_shared_dpll_state(struct drm_atomic_state *s) state->dpll_set = true; intel_atomic_duplicate_dpll_state(display, - state->shared_dpll); + state->dpll_state); } - return state->shared_dpll; + return state->dpll_state; } /** @@ -362,11 +362,11 @@ intel_find_shared_dpll(struct intel_atomic_state *state, { struct intel_display *display = to_intel_display(crtc); unsigned long dpll_mask_all = intel_dpll_mask_all(display); - struct intel_shared_dpll_state *shared_dpll; + struct intel_dpll_state *dpll_state; struct intel_shared_dpll *unused_pll = NULL; enum intel_dpll_id id; - shared_dpll = intel_atomic_get_shared_dpll_state(&state->base); + dpll_state = intel_atomic_get_shared_dpll_state(&state->base); drm_WARN_ON(display->drm, dpll_mask & ~dpll_mask_all); @@ -378,20 +378,20 @@ intel_find_shared_dpll(struct intel_atomic_state *state, continue; /* Only want to check enabled timings first */ - if (shared_dpll[pll->index].pipe_mask == 0) { + if (dpll_state[pll->index].pipe_mask == 0) { if (!unused_pll) unused_pll = pll; continue; } if (memcmp(dpll_hw_state, - &shared_dpll[pll->index].hw_state, + &dpll_state[pll->index].hw_state, sizeof(*dpll_hw_state)) == 0) { drm_dbg_kms(display->drm, "[CRTC:%d:%s] sharing existing %s (pipe mask 0x%x, active 0x%x)\n", crtc->base.base.id, crtc->base.name, pll->info->name, - shared_dpll[pll->index].pipe_mask, + dpll_state[pll->index].pipe_mask, pll->active_mask); return pll; } @@ -412,20 +412,20 @@ intel_find_shared_dpll(struct intel_atomic_state *state, * intel_reference_shared_dpll_crtc - Get a DPLL reference for a CRTC * @crtc: CRTC on which behalf the reference is taken * @pll: DPLL for which the reference is taken - * @shared_dpll_state: the DPLL atomic state in which the reference is tracked + * @dpll_state: the DPLL atomic state in which the reference is tracked * * Take a reference for @pll tracking the use of it by @crtc. */ static void intel_reference_shared_dpll_crtc(const struct intel_crtc *crtc, const struct intel_shared_dpll *pll, - struct intel_shared_dpll_state *shared_dpll_state) + struct intel_dpll_state *dpll_state) { struct intel_display *display = to_intel_display(crtc); - drm_WARN_ON(display->drm, (shared_dpll_state->pipe_mask & BIT(crtc->pipe)) != 0); + drm_WARN_ON(display->drm, (dpll_state->pipe_mask & BIT(crtc->pipe)) != 0); - shared_dpll_state->pipe_mask |= BIT(crtc->pipe); + dpll_state->pipe_mask |= BIT(crtc->pipe); drm_dbg_kms(display->drm, "[CRTC:%d:%s] reserving %s\n", crtc->base.base.id, crtc->base.name, pll->info->name); @@ -437,34 +437,34 @@ intel_reference_shared_dpll(struct intel_atomic_state *state, const struct intel_shared_dpll *pll, const struct intel_dpll_hw_state *dpll_hw_state) { - struct intel_shared_dpll_state *shared_dpll; + struct intel_dpll_state *dpll_state; - shared_dpll = intel_atomic_get_shared_dpll_state(&state->base); + dpll_state = intel_atomic_get_shared_dpll_state(&state->base); - if (shared_dpll[pll->index].pipe_mask == 0) - shared_dpll[pll->index].hw_state = *dpll_hw_state; + if (dpll_state[pll->index].pipe_mask == 0) + dpll_state[pll->index].hw_state = *dpll_hw_state; - intel_reference_shared_dpll_crtc(crtc, pll, &shared_dpll[pll->index]); + intel_reference_shared_dpll_crtc(crtc, pll, &dpll_state[pll->index]); } /** * intel_unreference_shared_dpll_crtc - Drop a DPLL reference for a CRTC * @crtc: CRTC on which behalf the reference is dropped * @pll: DPLL for which the reference is dropped - * @shared_dpll_state: the DPLL atomic state in which the reference is tracked + * @dpll_state: the DPLL atomic state in which the reference is tracked * * Drop a reference for @pll tracking the end of use of it by @crtc. */ void intel_unreference_shared_dpll_crtc(const struct intel_crtc *crtc, const struct intel_shared_dpll *pll, - struct intel_shared_dpll_state *shared_dpll_state) + struct intel_dpll_state *dpll_state) { struct intel_display *display = to_intel_display(crtc); - drm_WARN_ON(display->drm, (shared_dpll_state->pipe_mask & BIT(crtc->pipe)) == 0); + drm_WARN_ON(display->drm, (dpll_state->pipe_mask & BIT(crtc->pipe)) == 0); - shared_dpll_state->pipe_mask &= ~BIT(crtc->pipe); + dpll_state->pipe_mask &= ~BIT(crtc->pipe); drm_dbg_kms(display->drm, "[CRTC:%d:%s] releasing %s\n", crtc->base.base.id, crtc->base.name, pll->info->name); @@ -474,11 +474,11 @@ static void intel_unreference_shared_dpll(struct intel_atomic_state *state, const struct intel_crtc *crtc, const struct intel_shared_dpll *pll) { - struct intel_shared_dpll_state *shared_dpll; + struct intel_dpll_state *dpll_state; - shared_dpll = intel_atomic_get_shared_dpll_state(&state->base); + dpll_state = intel_atomic_get_shared_dpll_state(&state->base); - intel_unreference_shared_dpll_crtc(crtc, pll, &shared_dpll[pll->index]); + intel_unreference_shared_dpll_crtc(crtc, pll, &dpll_state[pll->index]); } static void intel_put_dpll(struct intel_atomic_state *state, @@ -511,7 +511,7 @@ static void intel_put_dpll(struct intel_atomic_state *state, void intel_shared_dpll_swap_state(struct intel_atomic_state *state) { struct intel_display *display = to_intel_display(state); - struct intel_shared_dpll_state *shared_dpll = state->shared_dpll; + struct intel_dpll_state *dpll_state = state->dpll_state; struct intel_shared_dpll *pll; int i; @@ -519,7 +519,7 @@ void intel_shared_dpll_swap_state(struct intel_atomic_state *state) return; for_each_shared_dpll(display, pll, i) - swap(pll->state, shared_dpll[pll->index]); + swap(pll->state, dpll_state[pll->index]); } static bool ibx_pch_dpll_get_hw_state(struct intel_display *display, diff --git a/drivers/gpu/drm/i915/display/intel_dpll_mgr.h b/drivers/gpu/drm/i915/display/intel_dpll_mgr.h index caffb084830c..fe6c676737bb 100644 --- a/drivers/gpu/drm/i915/display/intel_dpll_mgr.h +++ b/drivers/gpu/drm/i915/display/intel_dpll_mgr.h @@ -280,7 +280,7 @@ struct intel_dpll_hw_state { }; /** - * struct intel_shared_dpll_state - hold the DPLL atomic state + * struct intel_dpll_state - hold the DPLL atomic state * * This structure holds an atomic state for the DPLL, that can represent * either its current state (in struct &intel_shared_dpll) or a desired @@ -289,7 +289,7 @@ struct intel_dpll_hw_state { * * See also intel_reserve_shared_dplls() and intel_release_shared_dplls(). */ -struct intel_shared_dpll_state { +struct intel_dpll_state { /** * @pipe_mask: mask of pipes using this DPLL, active or not */ @@ -353,7 +353,7 @@ struct intel_shared_dpll { * Store the state for the pll, including its hw state * and CRTCs using it. */ - struct intel_shared_dpll_state state; + struct intel_dpll_state state; /** * @index: index for atomic state @@ -406,7 +406,7 @@ void intel_release_shared_dplls(struct intel_atomic_state *state, struct intel_crtc *crtc); void intel_unreference_shared_dpll_crtc(const struct intel_crtc *crtc, const struct intel_shared_dpll *pll, - struct intel_shared_dpll_state *shared_dpll_state); + struct intel_dpll_state *shared_dpll_state); void icl_set_active_port_dpll(struct intel_crtc_state *crtc_state, enum icl_port_dpll_id port_dpll_id); void intel_update_active_dpll(struct intel_atomic_state *state, From patchwork Wed Apr 2 08:31:50 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Kandpal, Suraj" X-Patchwork-Id: 14035635 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 38ECFC36014 for ; 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X-CSE-ConnectionGUID: b47IhSR6RTOkJh5NHnHO3w== X-CSE-MsgGUID: pRqVhg2jRIqlb5/db5mmww== X-IronPort-AV: E=McAfee;i="6700,10204,11391"; a="44828654" X-IronPort-AV: E=Sophos;i="6.14,295,1736841600"; d="scan'208";a="44828654" Received: from fmviesa007.fm.intel.com ([10.60.135.147]) by orvoesa111.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 02 Apr 2025 01:32:04 -0700 X-CSE-ConnectionGUID: KpvmjC3rTMK/kseT5enECw== X-CSE-MsgGUID: 7Xf8+ycCTJ61jx0chnlFRA== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.14,295,1736841600"; d="scan'208";a="126612301" Received: from kandpal-x299-ud4-pro.iind.intel.com ([10.190.239.10]) by fmviesa007.fm.intel.com with ESMTP; 02 Apr 2025 01:32:01 -0700 From: Suraj Kandpal To: intel-xe@lists.freedesktop.org, intel-gfx@lists.freedesktop.org Cc: ankit.k.nautiyal@intel.com, uma.shankar@intel.com, jani.nikula@intel.com, mika.kahola@intel.com, ville.syrjala@intel.com, Suraj Kandpal Subject: [PATCH 02/16] drm/i915/dpll: Rename macro for_each_shared_dpll Date: Wed, 2 Apr 2025 14:01:50 +0530 Message-Id: <20250402083204.1523470-3-suraj.kandpal@intel.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20250402083204.1523470-1-suraj.kandpal@intel.com> References: <20250402083204.1523470-1-suraj.kandpal@intel.com> MIME-Version: 1.0 X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" Rename the macro for_each_shared_dpll to for_each_dpll since this loop will not necessarily be used for only shared dpll in future. Signed-off-by: Suraj Kandpal --- .../gpu/drm/i915/display/intel_display_debugfs.c | 2 +- drivers/gpu/drm/i915/display/intel_dpll_mgr.c | 16 ++++++++-------- drivers/gpu/drm/i915/display/intel_dpll_mgr.h | 2 +- drivers/gpu/drm/i915/display/intel_pch_refclk.c | 2 +- 4 files changed, 11 insertions(+), 11 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_display_debugfs.c b/drivers/gpu/drm/i915/display/intel_display_debugfs.c index 4c784bb7e14b..a317c6646382 100644 --- a/drivers/gpu/drm/i915/display/intel_display_debugfs.c +++ b/drivers/gpu/drm/i915/display/intel_display_debugfs.c @@ -634,7 +634,7 @@ static int i915_shared_dplls_info(struct seq_file *m, void *unused) display->dpll.ref_clks.nssc, display->dpll.ref_clks.ssc); - for_each_shared_dpll(display, pll, i) { + for_each_dpll(display, pll, i) { drm_printf(&p, "DPLL%i: %s, id: %i\n", pll->index, pll->info->name, pll->info->id); drm_printf(&p, " pipe_mask: 0x%x, active: 0x%x, on: %s\n", diff --git a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c index 6edb4570d764..bbb51119ef5b 100644 --- a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c +++ b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c @@ -124,8 +124,8 @@ intel_atomic_duplicate_dpll_state(struct intel_display *display, struct intel_shared_dpll *pll; int i; - /* Copy shared dpll state */ - for_each_shared_dpll(display, pll, i) + /* Copy dpll state */ + for_each_dpll(display, pll, i) dpll_state[pll->index] = pll->state; } @@ -162,7 +162,7 @@ intel_get_shared_dpll_by_id(struct intel_display *display, struct intel_shared_dpll *pll; int i; - for_each_shared_dpll(display, pll, i) { + for_each_dpll(display, pll, i) { if (pll->info->id == id) return pll; } @@ -345,7 +345,7 @@ intel_dpll_mask_all(struct intel_display *display) unsigned long dpll_mask = 0; int i; - for_each_shared_dpll(display, pll, i) { + for_each_dpll(display, pll, i) { drm_WARN_ON(display->drm, dpll_mask & BIT(pll->info->id)); dpll_mask |= BIT(pll->info->id); @@ -518,7 +518,7 @@ void intel_shared_dpll_swap_state(struct intel_atomic_state *state) if (!state->dpll_set) return; - for_each_shared_dpll(display, pll, i) + for_each_dpll(display, pll, i) swap(pll->state, dpll_state[pll->index]); } @@ -4543,7 +4543,7 @@ void intel_dpll_readout_hw_state(struct intel_display *display) struct intel_shared_dpll *pll; int i; - for_each_shared_dpll(display, pll, i) + for_each_dpll(display, pll, i) readout_dpll_hw_state(display, pll); } @@ -4572,7 +4572,7 @@ void intel_dpll_sanitize_state(struct intel_display *display) intel_cx0_pll_power_save_wa(display); - for_each_shared_dpll(display, pll, i) + for_each_dpll(display, pll, i) sanitize_dpll_state(display, pll); } @@ -4721,6 +4721,6 @@ void intel_shared_dpll_verify_disabled(struct intel_atomic_state *state) struct intel_shared_dpll *pll; int i; - for_each_shared_dpll(display, pll, i) + for_each_dpll(display, pll, i) verify_single_dpll_state(display, pll, NULL, NULL); } diff --git a/drivers/gpu/drm/i915/display/intel_dpll_mgr.h b/drivers/gpu/drm/i915/display/intel_dpll_mgr.h index fe6c676737bb..d93072486831 100644 --- a/drivers/gpu/drm/i915/display/intel_dpll_mgr.h +++ b/drivers/gpu/drm/i915/display/intel_dpll_mgr.h @@ -30,7 +30,7 @@ #include "intel_display_power.h" #include "intel_wakeref.h" -#define for_each_shared_dpll(__display, __pll, __i) \ +#define for_each_dpll(__display, __pll, __i) \ for ((__i) = 0; (__i) < (__display)->dpll.num_shared_dpll && \ ((__pll) = &(__display)->dpll.shared_dplls[(__i)]) ; (__i)++) diff --git a/drivers/gpu/drm/i915/display/intel_pch_refclk.c b/drivers/gpu/drm/i915/display/intel_pch_refclk.c index 1307a478861a..611f3b8dffef 100644 --- a/drivers/gpu/drm/i915/display/intel_pch_refclk.c +++ b/drivers/gpu/drm/i915/display/intel_pch_refclk.c @@ -536,7 +536,7 @@ static void ilk_init_pch_refclk(struct intel_display *display) } /* Check if any DPLLs are using the SSC source */ - for_each_shared_dpll(display, pll, i) { + for_each_dpll(display, pll, i) { u32 temp; temp = intel_de_read(display, PCH_DPLL(pll->info->id)); From patchwork Wed Apr 2 08:31:51 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Kandpal, Suraj" X-Patchwork-Id: 14035636 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 275AAC3601A for ; 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X-CSE-ConnectionGUID: NKdo6BUPQjqhQgwUyqkPdQ== X-CSE-MsgGUID: eMI1F8oiS1yaeUzqfWJNeA== X-IronPort-AV: E=McAfee;i="6700,10204,11391"; a="44828660" X-IronPort-AV: E=Sophos;i="6.14,295,1736841600"; d="scan'208";a="44828660" Received: from fmviesa007.fm.intel.com ([10.60.135.147]) by orvoesa111.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 02 Apr 2025 01:32:07 -0700 X-CSE-ConnectionGUID: ndggQlVXSL6bT6RvOTno0g== X-CSE-MsgGUID: 3zf4CLbgSHGlJSUXVIPxCg== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.14,295,1736841600"; d="scan'208";a="126612322" Received: from kandpal-x299-ud4-pro.iind.intel.com ([10.190.239.10]) by fmviesa007.fm.intel.com with ESMTP; 02 Apr 2025 01:32:04 -0700 From: Suraj Kandpal To: intel-xe@lists.freedesktop.org, intel-gfx@lists.freedesktop.org Cc: ankit.k.nautiyal@intel.com, uma.shankar@intel.com, jani.nikula@intel.com, mika.kahola@intel.com, ville.syrjala@intel.com, Suraj Kandpal Subject: [PATCH 03/16] drm/i915/dpll: Rename intel_shared_dpll_funcs Date: Wed, 2 Apr 2025 14:01:51 +0530 Message-Id: <20250402083204.1523470-4-suraj.kandpal@intel.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20250402083204.1523470-1-suraj.kandpal@intel.com> References: <20250402083204.1523470-1-suraj.kandpal@intel.com> MIME-Version: 1.0 X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" Rename intel_shared_dpll_funcs to intel_global_dpll_funcs since it needs to represent both shared and individual dplls. --v2 -Change intel_global_dpll to intel_dpll_global to be more in line with the naming standard where the name should start with the file name [Jani] Signed-off-by: Suraj Kandpal --- drivers/gpu/drm/i915/display/intel_dpll_mgr.c | 24 +++++++++---------- drivers/gpu/drm/i915/display/intel_dpll_mgr.h | 4 ++-- 2 files changed, 14 insertions(+), 14 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c index bbb51119ef5b..92ca2a544e2f 100644 --- a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c +++ b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c @@ -61,7 +61,7 @@ */ /* platform specific hooks for managing DPLLs */ -struct intel_shared_dpll_funcs { +struct intel_dpll_global_funcs { /* * Hook for enabling the pll, called from intel_enable_shared_dpll() if * the pll is not already enabled. @@ -668,7 +668,7 @@ static bool ibx_compare_hw_state(const struct intel_dpll_hw_state *_a, a->fp1 == b->fp1; } -static const struct intel_shared_dpll_funcs ibx_pch_dpll_funcs = { +static const struct intel_dpll_global_funcs ibx_pch_dpll_funcs = { .enable = ibx_pch_dpll_enable, .disable = ibx_pch_dpll_disable, .get_hw_state = ibx_pch_dpll_get_hw_state, @@ -1268,14 +1268,14 @@ static bool hsw_compare_hw_state(const struct intel_dpll_hw_state *_a, a->spll == b->spll; } -static const struct intel_shared_dpll_funcs hsw_ddi_wrpll_funcs = { +static const struct intel_dpll_global_funcs hsw_ddi_wrpll_funcs = { .enable = hsw_ddi_wrpll_enable, .disable = hsw_ddi_wrpll_disable, .get_hw_state = hsw_ddi_wrpll_get_hw_state, .get_freq = hsw_ddi_wrpll_get_freq, }; -static const struct intel_shared_dpll_funcs hsw_ddi_spll_funcs = { +static const struct intel_dpll_global_funcs hsw_ddi_spll_funcs = { .enable = hsw_ddi_spll_enable, .disable = hsw_ddi_spll_disable, .get_hw_state = hsw_ddi_spll_get_hw_state, @@ -1300,7 +1300,7 @@ static bool hsw_ddi_lcpll_get_hw_state(struct intel_display *display, return true; } -static const struct intel_shared_dpll_funcs hsw_ddi_lcpll_funcs = { +static const struct intel_dpll_global_funcs hsw_ddi_lcpll_funcs = { .enable = hsw_ddi_lcpll_enable, .disable = hsw_ddi_lcpll_disable, .get_hw_state = hsw_ddi_lcpll_get_hw_state, @@ -2002,14 +2002,14 @@ static bool skl_compare_hw_state(const struct intel_dpll_hw_state *_a, a->cfgcr2 == b->cfgcr2; } -static const struct intel_shared_dpll_funcs skl_ddi_pll_funcs = { +static const struct intel_dpll_global_funcs skl_ddi_pll_funcs = { .enable = skl_ddi_pll_enable, .disable = skl_ddi_pll_disable, .get_hw_state = skl_ddi_pll_get_hw_state, .get_freq = skl_ddi_pll_get_freq, }; -static const struct intel_shared_dpll_funcs skl_ddi_dpll0_funcs = { +static const struct intel_dpll_global_funcs skl_ddi_dpll0_funcs = { .enable = skl_ddi_dpll0_enable, .disable = skl_ddi_dpll0_disable, .get_hw_state = skl_ddi_dpll0_get_hw_state, @@ -2484,7 +2484,7 @@ static bool bxt_compare_hw_state(const struct intel_dpll_hw_state *_a, a->pcsdw12 == b->pcsdw12; } -static const struct intel_shared_dpll_funcs bxt_ddi_pll_funcs = { +static const struct intel_dpll_global_funcs bxt_ddi_pll_funcs = { .enable = bxt_ddi_pll_enable, .disable = bxt_ddi_pll_disable, .get_hw_state = bxt_ddi_pll_get_hw_state, @@ -4129,21 +4129,21 @@ static bool icl_compare_hw_state(const struct intel_dpll_hw_state *_a, a->mg_pll_tdc_coldst_bias == b->mg_pll_tdc_coldst_bias; } -static const struct intel_shared_dpll_funcs combo_pll_funcs = { +static const struct intel_dpll_global_funcs combo_pll_funcs = { .enable = combo_pll_enable, .disable = combo_pll_disable, .get_hw_state = combo_pll_get_hw_state, .get_freq = icl_ddi_combo_pll_get_freq, }; -static const struct intel_shared_dpll_funcs tbt_pll_funcs = { +static const struct intel_dpll_global_funcs tbt_pll_funcs = { .enable = tbt_pll_enable, .disable = tbt_pll_disable, .get_hw_state = tbt_pll_get_hw_state, .get_freq = icl_ddi_tbt_pll_get_freq, }; -static const struct intel_shared_dpll_funcs mg_pll_funcs = { +static const struct intel_dpll_global_funcs mg_pll_funcs = { .enable = mg_pll_enable, .disable = mg_pll_disable, .get_hw_state = mg_pll_get_hw_state, @@ -4191,7 +4191,7 @@ static const struct intel_dpll_mgr ehl_pll_mgr = { .compare_hw_state = icl_compare_hw_state, }; -static const struct intel_shared_dpll_funcs dkl_pll_funcs = { +static const struct intel_dpll_global_funcs dkl_pll_funcs = { .enable = mg_pll_enable, .disable = mg_pll_disable, .get_hw_state = dkl_pll_get_hw_state, diff --git a/drivers/gpu/drm/i915/display/intel_dpll_mgr.h b/drivers/gpu/drm/i915/display/intel_dpll_mgr.h index d93072486831..2080118be523 100644 --- a/drivers/gpu/drm/i915/display/intel_dpll_mgr.h +++ b/drivers/gpu/drm/i915/display/intel_dpll_mgr.h @@ -41,7 +41,7 @@ struct intel_crtc; struct intel_crtc_state; struct intel_encoder; struct intel_shared_dpll; -struct intel_shared_dpll_funcs; +struct intel_dpll_global_funcs; /** * enum intel_dpll_id - possible DPLL ids @@ -314,7 +314,7 @@ struct dpll_info { /** * @funcs: platform specific hooks */ - const struct intel_shared_dpll_funcs *funcs; + const struct intel_dpll_global_funcs *funcs; /** * @id: unique identifier for this DPLL From patchwork Wed Apr 2 08:31:52 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Kandpal, Suraj" X-Patchwork-Id: 14035637 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 7A89CC3601B for ; Wed, 2 Apr 2025 08:32:11 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 10E8510E6F1; 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a="44828668" X-IronPort-AV: E=Sophos;i="6.14,295,1736841600"; d="scan'208";a="44828668" Received: from fmviesa007.fm.intel.com ([10.60.135.147]) by orvoesa111.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 02 Apr 2025 01:32:10 -0700 X-CSE-ConnectionGUID: 725RGRN/ReqcYcehaNMBIg== X-CSE-MsgGUID: +ABR5pAST0GI5cCO+KVzSQ== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.14,295,1736841600"; d="scan'208";a="126612339" Received: from kandpal-x299-ud4-pro.iind.intel.com ([10.190.239.10]) by fmviesa007.fm.intel.com with ESMTP; 02 Apr 2025 01:32:06 -0700 From: Suraj Kandpal To: intel-xe@lists.freedesktop.org, intel-gfx@lists.freedesktop.org Cc: ankit.k.nautiyal@intel.com, uma.shankar@intel.com, jani.nikula@intel.com, mika.kahola@intel.com, ville.syrjala@intel.com, Suraj Kandpal Subject: [PATCH 04/16] drm/i915/dpll: Rename intel_shared_dpll Date: Wed, 2 Apr 2025 14:01:52 +0530 Message-Id: <20250402083204.1523470-5-suraj.kandpal@intel.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20250402083204.1523470-1-suraj.kandpal@intel.com> References: <20250402083204.1523470-1-suraj.kandpal@intel.com> MIME-Version: 1.0 X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" Rename intel_shared_dpll to intel_dpll_global to represent both shared and individual dplls. Since from MTL each PHY has it's own PLL making the shared PLL naming a little outdated. In an effort to make this framework accepting of future changes this needs to be done. --v2 -Use intel_dpll_global to make sure names start with the filename [Jani/Ville] -Explain the need of this rename [Jani] Signed-off-by: Suraj Kandpal --- drivers/gpu/drm/i915/display/icl_dsi.c | 2 +- drivers/gpu/drm/i915/display/intel_ddi.c | 52 ++-- drivers/gpu/drm/i915/display/intel_ddi.h | 6 +- drivers/gpu/drm/i915/display/intel_display.c | 12 +- .../gpu/drm/i915/display/intel_display_core.h | 4 +- .../drm/i915/display/intel_display_debugfs.c | 2 +- .../drm/i915/display/intel_display_types.h | 6 +- drivers/gpu/drm/i915/display/intel_dpll.c | 4 +- drivers/gpu/drm/i915/display/intel_dpll_mgr.c | 228 +++++++++--------- drivers/gpu/drm/i915/display/intel_dpll_mgr.h | 18 +- drivers/gpu/drm/i915/display/intel_fdi.c | 2 +- drivers/gpu/drm/i915/display/intel_lvds.c | 2 +- .../drm/i915/display/intel_modeset_setup.c | 8 +- .../gpu/drm/i915/display/intel_pch_display.c | 10 +- .../gpu/drm/i915/display/intel_pch_refclk.c | 2 +- 15 files changed, 179 insertions(+), 179 deletions(-) diff --git a/drivers/gpu/drm/i915/display/icl_dsi.c b/drivers/gpu/drm/i915/display/icl_dsi.c index b69c713fb79a..97c20c493e4d 100644 --- a/drivers/gpu/drm/i915/display/icl_dsi.c +++ b/drivers/gpu/drm/i915/display/icl_dsi.c @@ -658,7 +658,7 @@ static void gen11_dsi_map_pll(struct intel_encoder *encoder, { struct intel_display *display = to_intel_display(encoder); struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder); - struct intel_shared_dpll *pll = crtc_state->shared_dpll; + struct intel_dpll_global *pll = crtc_state->dpll_global; enum phy phy; u32 val; diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c b/drivers/gpu/drm/i915/display/intel_ddi.c index 56068b2ef964..a8934ea5077d 100644 --- a/drivers/gpu/drm/i915/display/intel_ddi.c +++ b/drivers/gpu/drm/i915/display/intel_ddi.c @@ -234,7 +234,7 @@ static void intel_wait_ddi_buf_active(struct intel_encoder *encoder) port_name(port)); } -static u32 hsw_pll_to_ddi_pll_sel(const struct intel_shared_dpll *pll) +static u32 hsw_pll_to_ddi_pll_sel(const struct intel_dpll_global *pll) { switch (pll->info->id) { case DPLL_ID_WRPLL1: @@ -258,7 +258,7 @@ static u32 hsw_pll_to_ddi_pll_sel(const struct intel_shared_dpll *pll) static u32 icl_pll_to_ddi_clk_sel(struct intel_encoder *encoder, const struct intel_crtc_state *crtc_state) { - const struct intel_shared_dpll *pll = crtc_state->shared_dpll; + const struct intel_dpll_global *pll = crtc_state->dpll_global; int clock = crtc_state->port_clock; const enum intel_dpll_id id = pll->info->id; @@ -1559,7 +1559,7 @@ static bool _icl_ddi_is_clock_enabled(struct intel_display *display, i915_reg_t return !(intel_de_read(display, reg) & clk_off); } -static struct intel_shared_dpll * +static struct intel_dpll_global * _icl_ddi_get_pll(struct intel_display *display, i915_reg_t reg, u32 clk_sel_mask, u32 clk_sel_shift) { @@ -1574,7 +1574,7 @@ static void adls_ddi_enable_clock(struct intel_encoder *encoder, const struct intel_crtc_state *crtc_state) { struct intel_display *display = to_intel_display(encoder); - const struct intel_shared_dpll *pll = crtc_state->shared_dpll; + const struct intel_dpll_global *pll = crtc_state->dpll_global; enum phy phy = intel_encoder_to_phy(encoder); if (drm_WARN_ON(display->drm, !pll)) @@ -1604,7 +1604,7 @@ static bool adls_ddi_is_clock_enabled(struct intel_encoder *encoder) ICL_DPCLKA_CFGCR0_DDI_CLK_OFF(phy)); } -static struct intel_shared_dpll *adls_ddi_get_pll(struct intel_encoder *encoder) +static struct intel_dpll_global *adls_ddi_get_pll(struct intel_encoder *encoder) { struct intel_display *display = to_intel_display(encoder); enum phy phy = intel_encoder_to_phy(encoder); @@ -1618,7 +1618,7 @@ static void rkl_ddi_enable_clock(struct intel_encoder *encoder, const struct intel_crtc_state *crtc_state) { struct intel_display *display = to_intel_display(encoder); - const struct intel_shared_dpll *pll = crtc_state->shared_dpll; + const struct intel_dpll_global *pll = crtc_state->dpll_global; enum phy phy = intel_encoder_to_phy(encoder); if (drm_WARN_ON(display->drm, !pll)) @@ -1648,7 +1648,7 @@ static bool rkl_ddi_is_clock_enabled(struct intel_encoder *encoder) RKL_DPCLKA_CFGCR0_DDI_CLK_OFF(phy)); } -static struct intel_shared_dpll *rkl_ddi_get_pll(struct intel_encoder *encoder) +static struct intel_dpll_global *rkl_ddi_get_pll(struct intel_encoder *encoder) { struct intel_display *display = to_intel_display(encoder); enum phy phy = intel_encoder_to_phy(encoder); @@ -1662,7 +1662,7 @@ static void dg1_ddi_enable_clock(struct intel_encoder *encoder, const struct intel_crtc_state *crtc_state) { struct intel_display *display = to_intel_display(encoder); - const struct intel_shared_dpll *pll = crtc_state->shared_dpll; + const struct intel_dpll_global *pll = crtc_state->dpll_global; enum phy phy = intel_encoder_to_phy(encoder); if (drm_WARN_ON(display->drm, !pll)) @@ -1701,7 +1701,7 @@ static bool dg1_ddi_is_clock_enabled(struct intel_encoder *encoder) DG1_DPCLKA_CFGCR0_DDI_CLK_OFF(phy)); } -static struct intel_shared_dpll *dg1_ddi_get_pll(struct intel_encoder *encoder) +static struct intel_dpll_global *dg1_ddi_get_pll(struct intel_encoder *encoder) { struct intel_display *display = to_intel_display(encoder); enum phy phy = intel_encoder_to_phy(encoder); @@ -1728,7 +1728,7 @@ static void icl_ddi_combo_enable_clock(struct intel_encoder *encoder, const struct intel_crtc_state *crtc_state) { struct intel_display *display = to_intel_display(encoder); - const struct intel_shared_dpll *pll = crtc_state->shared_dpll; + const struct intel_dpll_global *pll = crtc_state->dpll_global; enum phy phy = intel_encoder_to_phy(encoder); if (drm_WARN_ON(display->drm, !pll)) @@ -1758,7 +1758,7 @@ static bool icl_ddi_combo_is_clock_enabled(struct intel_encoder *encoder) ICL_DPCLKA_CFGCR0_DDI_CLK_OFF(phy)); } -struct intel_shared_dpll *icl_ddi_combo_get_pll(struct intel_encoder *encoder) +struct intel_dpll_global *icl_ddi_combo_get_pll(struct intel_encoder *encoder) { struct intel_display *display = to_intel_display(encoder); enum phy phy = intel_encoder_to_phy(encoder); @@ -1772,7 +1772,7 @@ static void jsl_ddi_tc_enable_clock(struct intel_encoder *encoder, const struct intel_crtc_state *crtc_state) { struct intel_display *display = to_intel_display(encoder); - const struct intel_shared_dpll *pll = crtc_state->shared_dpll; + const struct intel_dpll_global *pll = crtc_state->dpll_global; enum port port = encoder->port; if (drm_WARN_ON(display->drm, !pll)) @@ -1815,7 +1815,7 @@ static void icl_ddi_tc_enable_clock(struct intel_encoder *encoder, const struct intel_crtc_state *crtc_state) { struct intel_display *display = to_intel_display(encoder); - const struct intel_shared_dpll *pll = crtc_state->shared_dpll; + const struct intel_dpll_global *pll = crtc_state->dpll_global; enum tc_port tc_port = intel_encoder_to_tc(encoder); enum port port = encoder->port; @@ -1866,7 +1866,7 @@ static bool icl_ddi_tc_is_clock_enabled(struct intel_encoder *encoder) return !(tmp & ICL_DPCLKA_CFGCR0_TC_CLK_OFF(tc_port)); } -static struct intel_shared_dpll *icl_ddi_tc_get_pll(struct intel_encoder *encoder) +static struct intel_dpll_global *icl_ddi_tc_get_pll(struct intel_encoder *encoder) { struct intel_display *display = to_intel_display(encoder); enum tc_port tc_port = intel_encoder_to_tc(encoder); @@ -1896,7 +1896,7 @@ static struct intel_shared_dpll *icl_ddi_tc_get_pll(struct intel_encoder *encode return intel_get_shared_dpll_by_id(display, id); } -static struct intel_shared_dpll *bxt_ddi_get_pll(struct intel_encoder *encoder) +static struct intel_dpll_global *bxt_ddi_get_pll(struct intel_encoder *encoder) { struct intel_display *display = to_intel_display(encoder->base.dev); enum intel_dpll_id id; @@ -1923,7 +1923,7 @@ static void skl_ddi_enable_clock(struct intel_encoder *encoder, const struct intel_crtc_state *crtc_state) { struct intel_display *display = to_intel_display(encoder); - const struct intel_shared_dpll *pll = crtc_state->shared_dpll; + const struct intel_dpll_global *pll = crtc_state->dpll_global; enum port port = encoder->port; if (drm_WARN_ON(display->drm, !pll)) @@ -1965,7 +1965,7 @@ static bool skl_ddi_is_clock_enabled(struct intel_encoder *encoder) return !(intel_de_read(display, DPLL_CTRL2) & DPLL_CTRL2_DDI_CLK_OFF(port)); } -static struct intel_shared_dpll *skl_ddi_get_pll(struct intel_encoder *encoder) +static struct intel_dpll_global *skl_ddi_get_pll(struct intel_encoder *encoder) { struct intel_display *display = to_intel_display(encoder); enum port port = encoder->port; @@ -1991,7 +1991,7 @@ void hsw_ddi_enable_clock(struct intel_encoder *encoder, const struct intel_crtc_state *crtc_state) { struct intel_display *display = to_intel_display(encoder); - const struct intel_shared_dpll *pll = crtc_state->shared_dpll; + const struct intel_dpll_global *pll = crtc_state->dpll_global; enum port port = encoder->port; if (drm_WARN_ON(display->drm, !pll)) @@ -2016,7 +2016,7 @@ bool hsw_ddi_is_clock_enabled(struct intel_encoder *encoder) return intel_de_read(display, PORT_CLK_SEL(port)) != PORT_CLK_SEL_NONE; } -static struct intel_shared_dpll *hsw_ddi_get_pll(struct intel_encoder *encoder) +static struct intel_dpll_global *hsw_ddi_get_pll(struct intel_encoder *encoder) { struct intel_display *display = to_intel_display(encoder); enum port port = encoder->port; @@ -4184,7 +4184,7 @@ static void intel_ddi_get_config(struct intel_encoder *encoder, void intel_ddi_get_clock(struct intel_encoder *encoder, struct intel_crtc_state *crtc_state, - struct intel_shared_dpll *pll) + struct intel_dpll_global *pll) { struct intel_display *display = to_intel_display(encoder); enum icl_port_dpll_id port_dpll_id = ICL_PORT_DPLL_DEFAULT; @@ -4200,7 +4200,7 @@ void intel_ddi_get_clock(struct intel_encoder *encoder, icl_set_active_port_dpll(crtc_state, port_dpll_id); - crtc_state->port_clock = intel_dpll_get_freq(display, crtc_state->shared_dpll, + crtc_state->port_clock = intel_dpll_get_freq(display, crtc_state->dpll_global, &crtc_state->dpll_hw_state); } @@ -4254,7 +4254,7 @@ static void icl_ddi_combo_get_config(struct intel_encoder *encoder, intel_ddi_get_config(encoder, crtc_state); } -static bool icl_ddi_tc_pll_is_tbt(const struct intel_shared_dpll *pll) +static bool icl_ddi_tc_pll_is_tbt(const struct intel_dpll_global *pll) { return pll->info->id == DPLL_ID_ICL_TBTPLL; } @@ -4264,7 +4264,7 @@ icl_ddi_tc_port_pll_type(struct intel_encoder *encoder, const struct intel_crtc_state *crtc_state) { struct intel_display *display = to_intel_display(encoder); - const struct intel_shared_dpll *pll = crtc_state->shared_dpll; + const struct intel_dpll_global *pll = crtc_state->dpll_global; if (drm_WARN_ON(display->drm, !pll)) return ICL_PORT_DPLL_DEFAULT; @@ -4287,7 +4287,7 @@ intel_ddi_port_pll_type(struct intel_encoder *encoder, static void icl_ddi_tc_get_clock(struct intel_encoder *encoder, struct intel_crtc_state *crtc_state, - struct intel_shared_dpll *pll) + struct intel_dpll_global *pll) { struct intel_display *display = to_intel_display(encoder); enum icl_port_dpll_id port_dpll_id; @@ -4310,10 +4310,10 @@ static void icl_ddi_tc_get_clock(struct intel_encoder *encoder, icl_set_active_port_dpll(crtc_state, port_dpll_id); - if (icl_ddi_tc_pll_is_tbt(crtc_state->shared_dpll)) + if (icl_ddi_tc_pll_is_tbt(crtc_state->dpll_global)) crtc_state->port_clock = icl_calc_tbt_pll_link(display, encoder->port); else - crtc_state->port_clock = intel_dpll_get_freq(display, crtc_state->shared_dpll, + crtc_state->port_clock = intel_dpll_get_freq(display, crtc_state->dpll_global, &crtc_state->dpll_hw_state); } diff --git a/drivers/gpu/drm/i915/display/intel_ddi.h b/drivers/gpu/drm/i915/display/intel_ddi.h index 353eb04079e9..c41341b7e5cf 100644 --- a/drivers/gpu/drm/i915/display/intel_ddi.h +++ b/drivers/gpu/drm/i915/display/intel_ddi.h @@ -18,7 +18,7 @@ struct intel_display; struct intel_dp; struct intel_dpll_hw_state; struct intel_encoder; -struct intel_shared_dpll; +struct intel_dpll_global; enum pipe; enum port; enum transcoder; @@ -40,7 +40,7 @@ void intel_ddi_enable_clock(struct intel_encoder *encoder, void intel_ddi_disable_clock(struct intel_encoder *encoder); void intel_ddi_get_clock(struct intel_encoder *encoder, struct intel_crtc_state *crtc_state, - struct intel_shared_dpll *pll); + struct intel_dpll_global *pll); void hsw_ddi_enable_clock(struct intel_encoder *encoder, const struct intel_crtc_state *crtc_state); void hsw_ddi_disable_clock(struct intel_encoder *encoder); @@ -50,7 +50,7 @@ intel_ddi_port_pll_type(struct intel_encoder *encoder, const struct intel_crtc_state *crtc_state); void hsw_ddi_get_config(struct intel_encoder *encoder, struct intel_crtc_state *crtc_state); -struct intel_shared_dpll *icl_ddi_combo_get_pll(struct intel_encoder *encoder); +struct intel_dpll_global *icl_ddi_combo_get_pll(struct intel_encoder *encoder); void hsw_prepare_dp_ddi_buffers(struct intel_encoder *encoder, const struct intel_crtc_state *crtc_state); void intel_wait_ddi_buf_idle(struct intel_display *display, enum port port); diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c index c540e2cae1f0..5b808bad61e0 100644 --- a/drivers/gpu/drm/i915/display/intel_display.c +++ b/drivers/gpu/drm/i915/display/intel_display.c @@ -1322,7 +1322,7 @@ static void intel_encoders_update_prepare(struct intel_atomic_state *state) if (intel_crtc_needs_modeset(new_crtc_state)) continue; - new_crtc_state->shared_dpll = old_crtc_state->shared_dpll; + new_crtc_state->dpll_global = old_crtc_state->dpll_global; new_crtc_state->dpll_hw_state = old_crtc_state->dpll_hw_state; } } @@ -1661,7 +1661,7 @@ static void hsw_crtc_enable(struct intel_atomic_state *state, intel_encoders_pre_pll_enable(state, crtc); - if (new_crtc_state->shared_dpll) + if (new_crtc_state->dpll_global) intel_enable_shared_dpll(new_crtc_state); intel_encoders_pre_enable(state, crtc); @@ -1957,7 +1957,7 @@ static void get_crtc_power_domains(struct intel_crtc_state *crtc_state, if (HAS_DDI(display) && crtc_state->has_audio) set_bit(POWER_DOMAIN_AUDIO_MMIO, mask->bits); - if (crtc_state->shared_dpll) + if (crtc_state->dpll_global) set_bit(POWER_DOMAIN_DISPLAY_CORE, mask->bits); if (crtc_state->dsc.compression_enable) @@ -4498,7 +4498,7 @@ copy_joiner_crtc_state_modeset(struct intel_atomic_state *state, /* preserve some things from the slave's original crtc state */ saved_state->uapi = secondary_crtc_state->uapi; saved_state->scaler_state = secondary_crtc_state->scaler_state; - saved_state->shared_dpll = secondary_crtc_state->shared_dpll; + saved_state->dpll_global = secondary_crtc_state->dpll_global; saved_state->crc_enabled = secondary_crtc_state->crc_enabled; intel_crtc_free_hw_state(secondary_crtc_state); @@ -4561,7 +4561,7 @@ intel_crtc_prepare_cleared_state(struct intel_atomic_state *state, saved_state->uapi = crtc_state->uapi; saved_state->inherited = crtc_state->inherited; saved_state->scaler_state = crtc_state->scaler_state; - saved_state->shared_dpll = crtc_state->shared_dpll; + saved_state->dpll_global = crtc_state->dpll_global; saved_state->dpll_hw_state = crtc_state->dpll_hw_state; memcpy(saved_state->icl_port_dplls, crtc_state->icl_port_dplls, sizeof(saved_state->icl_port_dplls)); @@ -5313,7 +5313,7 @@ intel_pipe_config_compare(const struct intel_crtc_state *current_config, PIPE_CONF_CHECK_BOOL(double_wide); if (display->dpll.mgr) - PIPE_CONF_CHECK_P(shared_dpll); + PIPE_CONF_CHECK_P(dpll_global); /* FIXME convert everything over the dpll_mgr */ if (display->dpll.mgr || HAS_GMCH(display)) diff --git a/drivers/gpu/drm/i915/display/intel_display_core.h b/drivers/gpu/drm/i915/display/intel_display_core.h index 3673275f9061..b23ff1c34bdf 100644 --- a/drivers/gpu/drm/i915/display/intel_display_core.h +++ b/drivers/gpu/drm/i915/display/intel_display_core.h @@ -126,8 +126,8 @@ struct intel_audio { struct intel_dpll { struct mutex lock; - int num_shared_dpll; - struct intel_shared_dpll shared_dplls[I915_NUM_PLLS]; + int num_dpll_global; + struct intel_dpll_global dpll_globals[I915_NUM_PLLS]; const struct intel_dpll_mgr *mgr; struct { diff --git a/drivers/gpu/drm/i915/display/intel_display_debugfs.c b/drivers/gpu/drm/i915/display/intel_display_debugfs.c index a317c6646382..db26998e0baa 100644 --- a/drivers/gpu/drm/i915/display/intel_display_debugfs.c +++ b/drivers/gpu/drm/i915/display/intel_display_debugfs.c @@ -625,7 +625,7 @@ static int i915_shared_dplls_info(struct seq_file *m, void *unused) { struct intel_display *display = node_to_intel_display(m->private); struct drm_printer p = drm_seq_file_printer(m); - struct intel_shared_dpll *pll; + struct intel_dpll_global *pll; int i; drm_modeset_lock_all(display->drm); diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h b/drivers/gpu/drm/i915/display/intel_display_types.h index 7d1c64f7b405..e080ffb32546 100644 --- a/drivers/gpu/drm/i915/display/intel_display_types.h +++ b/drivers/gpu/drm/i915/display/intel_display_types.h @@ -1075,8 +1075,8 @@ struct intel_crtc_state { * haswell. */ struct dpll dpll; - /* Selected dpll when shared or NULL. */ - struct intel_shared_dpll *shared_dpll; + /* Selected dpll. */ + struct intel_dpll_global *dpll_global; /* Actual register state of the dpll, for shared dpll cross-checking. */ struct intel_dpll_hw_state dpll_hw_state; @@ -1086,7 +1086,7 @@ struct intel_crtc_state { * setting shared_dpll and dpll_hw_state to one of these reserved ones. */ struct icl_port_dpll { - struct intel_shared_dpll *pll; + struct intel_dpll_global *pll; struct intel_dpll_hw_state hw_state; } icl_port_dplls[ICL_PORT_DPLL_COUNT]; diff --git a/drivers/gpu/drm/i915/display/intel_dpll.c b/drivers/gpu/drm/i915/display/intel_dpll.c index 0481b1365b85..c6d29382378b 100644 --- a/drivers/gpu/drm/i915/display/intel_dpll.c +++ b/drivers/gpu/drm/i915/display/intel_dpll.c @@ -1770,9 +1770,9 @@ int intel_dpll_crtc_get_shared_dpll(struct intel_atomic_state *state, int ret; drm_WARN_ON(display->drm, !intel_crtc_needs_modeset(crtc_state)); - drm_WARN_ON(display->drm, !crtc_state->hw.enable && crtc_state->shared_dpll); + drm_WARN_ON(display->drm, !crtc_state->hw.enable && crtc_state->dpll_global); - if (!crtc_state->hw.enable || crtc_state->shared_dpll) + if (!crtc_state->hw.enable || crtc_state->dpll_global) return 0; if (!display->funcs.dpll->crtc_get_shared_dpll) diff --git a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c index 92ca2a544e2f..833c90f3f0f1 100644 --- a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c +++ b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c @@ -67,7 +67,7 @@ struct intel_dpll_global_funcs { * the pll is not already enabled. */ void (*enable)(struct intel_display *display, - struct intel_shared_dpll *pll, + struct intel_dpll_global *pll, const struct intel_dpll_hw_state *dpll_hw_state); /* @@ -76,7 +76,7 @@ struct intel_dpll_global_funcs { * tracked users for it. */ void (*disable)(struct intel_display *display, - struct intel_shared_dpll *pll); + struct intel_dpll_global *pll); /* * Hook for reading the values currently programmed to the DPLL @@ -84,7 +84,7 @@ struct intel_dpll_global_funcs { * verification after a mode set. */ bool (*get_hw_state)(struct intel_display *display, - struct intel_shared_dpll *pll, + struct intel_dpll_global *pll, struct intel_dpll_hw_state *dpll_hw_state); /* @@ -92,7 +92,7 @@ struct intel_dpll_global_funcs { * in state. */ int (*get_freq)(struct intel_display *i915, - const struct intel_shared_dpll *pll, + const struct intel_dpll_global *pll, const struct intel_dpll_hw_state *dpll_hw_state); }; @@ -121,7 +121,7 @@ static void intel_atomic_duplicate_dpll_state(struct intel_display *display, struct intel_dpll_state *dpll_state) { - struct intel_shared_dpll *pll; + struct intel_dpll_global *pll; int i; /* Copy dpll state */ @@ -155,11 +155,11 @@ intel_atomic_get_shared_dpll_state(struct drm_atomic_state *s) * Returns: * A pointer to the DPLL with @id */ -struct intel_shared_dpll * +struct intel_dpll_global * intel_get_shared_dpll_by_id(struct intel_display *display, enum intel_dpll_id id) { - struct intel_shared_dpll *pll; + struct intel_dpll_global *pll; int i; for_each_dpll(display, pll, i) { @@ -173,7 +173,7 @@ intel_get_shared_dpll_by_id(struct intel_display *display, /* For ILK+ */ void assert_shared_dpll(struct intel_display *display, - struct intel_shared_dpll *pll, + struct intel_dpll_global *pll, bool state) { bool cur_state; @@ -202,7 +202,7 @@ enum intel_dpll_id icl_tc_port_to_pll_id(enum tc_port tc_port) static i915_reg_t intel_combo_pll_enable_reg(struct intel_display *display, - struct intel_shared_dpll *pll) + struct intel_dpll_global *pll) { if (display->platform.dg1) return DG1_DPLL_ENABLE(pll->info->id); @@ -215,7 +215,7 @@ intel_combo_pll_enable_reg(struct intel_display *display, static i915_reg_t intel_tc_pll_enable_reg(struct intel_display *display, - struct intel_shared_dpll *pll) + struct intel_dpll_global *pll) { const enum intel_dpll_id id = pll->info->id; enum tc_port tc_port = icl_pll_id_to_tc_port(id); @@ -227,7 +227,7 @@ intel_tc_pll_enable_reg(struct intel_display *display, } static void _intel_enable_shared_dpll(struct intel_display *display, - struct intel_shared_dpll *pll) + struct intel_dpll_global *pll) { if (pll->info->power_domain) pll->wakeref = intel_display_power_get(display, pll->info->power_domain); @@ -237,7 +237,7 @@ static void _intel_enable_shared_dpll(struct intel_display *display, } static void _intel_disable_shared_dpll(struct intel_display *display, - struct intel_shared_dpll *pll) + struct intel_dpll_global *pll) { pll->info->funcs->disable(display, pll); pll->on = false; @@ -256,7 +256,7 @@ void intel_enable_shared_dpll(const struct intel_crtc_state *crtc_state) { struct intel_display *display = to_intel_display(crtc_state); struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); - struct intel_shared_dpll *pll = crtc_state->shared_dpll; + struct intel_dpll_global *pll = crtc_state->dpll_global; unsigned int pipe_mask = intel_crtc_joined_pipe_mask(crtc_state); unsigned int old_mask; @@ -302,7 +302,7 @@ void intel_disable_shared_dpll(const struct intel_crtc_state *crtc_state) { struct intel_display *display = to_intel_display(crtc_state); struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); - struct intel_shared_dpll *pll = crtc_state->shared_dpll; + struct intel_dpll_global *pll = crtc_state->dpll_global; unsigned int pipe_mask = intel_crtc_joined_pipe_mask(crtc_state); /* PCH only available on ILK+ */ @@ -341,7 +341,7 @@ void intel_disable_shared_dpll(const struct intel_crtc_state *crtc_state) static unsigned long intel_dpll_mask_all(struct intel_display *display) { - struct intel_shared_dpll *pll; + struct intel_dpll_global *pll; unsigned long dpll_mask = 0; int i; @@ -354,7 +354,7 @@ intel_dpll_mask_all(struct intel_display *display) return dpll_mask; } -static struct intel_shared_dpll * +static struct intel_dpll_global * intel_find_shared_dpll(struct intel_atomic_state *state, const struct intel_crtc *crtc, const struct intel_dpll_hw_state *dpll_hw_state, @@ -363,7 +363,7 @@ intel_find_shared_dpll(struct intel_atomic_state *state, struct intel_display *display = to_intel_display(crtc); unsigned long dpll_mask_all = intel_dpll_mask_all(display); struct intel_dpll_state *dpll_state; - struct intel_shared_dpll *unused_pll = NULL; + struct intel_dpll_global *unused_pll = NULL; enum intel_dpll_id id; dpll_state = intel_atomic_get_shared_dpll_state(&state->base); @@ -371,7 +371,7 @@ intel_find_shared_dpll(struct intel_atomic_state *state, drm_WARN_ON(display->drm, dpll_mask & ~dpll_mask_all); for_each_set_bit(id, &dpll_mask, fls(dpll_mask_all)) { - struct intel_shared_dpll *pll; + struct intel_dpll_global *pll; pll = intel_get_shared_dpll_by_id(display, id); if (!pll) @@ -418,7 +418,7 @@ intel_find_shared_dpll(struct intel_atomic_state *state, */ static void intel_reference_shared_dpll_crtc(const struct intel_crtc *crtc, - const struct intel_shared_dpll *pll, + const struct intel_dpll_global *pll, struct intel_dpll_state *dpll_state) { struct intel_display *display = to_intel_display(crtc); @@ -434,7 +434,7 @@ intel_reference_shared_dpll_crtc(const struct intel_crtc *crtc, static void intel_reference_shared_dpll(struct intel_atomic_state *state, const struct intel_crtc *crtc, - const struct intel_shared_dpll *pll, + const struct intel_dpll_global *pll, const struct intel_dpll_hw_state *dpll_hw_state) { struct intel_dpll_state *dpll_state; @@ -457,7 +457,7 @@ intel_reference_shared_dpll(struct intel_atomic_state *state, */ void intel_unreference_shared_dpll_crtc(const struct intel_crtc *crtc, - const struct intel_shared_dpll *pll, + const struct intel_dpll_global *pll, struct intel_dpll_state *dpll_state) { struct intel_display *display = to_intel_display(crtc); @@ -472,7 +472,7 @@ intel_unreference_shared_dpll_crtc(const struct intel_crtc *crtc, static void intel_unreference_shared_dpll(struct intel_atomic_state *state, const struct intel_crtc *crtc, - const struct intel_shared_dpll *pll) + const struct intel_dpll_global *pll) { struct intel_dpll_state *dpll_state; @@ -489,12 +489,12 @@ static void intel_put_dpll(struct intel_atomic_state *state, struct intel_crtc_state *new_crtc_state = intel_atomic_get_new_crtc_state(state, crtc); - new_crtc_state->shared_dpll = NULL; + new_crtc_state->dpll_global = NULL; - if (!old_crtc_state->shared_dpll) + if (!old_crtc_state->dpll_global) return; - intel_unreference_shared_dpll(state, crtc, old_crtc_state->shared_dpll); + intel_unreference_shared_dpll(state, crtc, old_crtc_state->dpll_global); } /** @@ -512,7 +512,7 @@ void intel_shared_dpll_swap_state(struct intel_atomic_state *state) { struct intel_display *display = to_intel_display(state); struct intel_dpll_state *dpll_state = state->dpll_state; - struct intel_shared_dpll *pll; + struct intel_dpll_global *pll; int i; if (!state->dpll_set) @@ -523,7 +523,7 @@ void intel_shared_dpll_swap_state(struct intel_atomic_state *state) } static bool ibx_pch_dpll_get_hw_state(struct intel_display *display, - struct intel_shared_dpll *pll, + struct intel_dpll_global *pll, struct intel_dpll_hw_state *dpll_hw_state) { struct i9xx_dpll_hw_state *hw_state = &dpll_hw_state->i9xx; @@ -559,7 +559,7 @@ static void ibx_assert_pch_refclk_enabled(struct intel_display *display) } static void ibx_pch_dpll_enable(struct intel_display *display, - struct intel_shared_dpll *pll, + struct intel_dpll_global *pll, const struct intel_dpll_hw_state *dpll_hw_state) { const struct i9xx_dpll_hw_state *hw_state = &dpll_hw_state->i9xx; @@ -588,7 +588,7 @@ static void ibx_pch_dpll_enable(struct intel_display *display, } static void ibx_pch_dpll_disable(struct intel_display *display, - struct intel_shared_dpll *pll) + struct intel_dpll_global *pll) { const enum intel_dpll_id id = pll->info->id; @@ -612,7 +612,7 @@ static int ibx_get_dpll(struct intel_atomic_state *state, struct drm_i915_private *i915 = to_i915(display->drm); struct intel_crtc_state *crtc_state = intel_atomic_get_new_crtc_state(state, crtc); - struct intel_shared_dpll *pll; + struct intel_dpll_global *pll; enum intel_dpll_id id; if (HAS_PCH_IBX(i915)) { @@ -638,7 +638,7 @@ static int ibx_get_dpll(struct intel_atomic_state *state, intel_reference_shared_dpll(state, crtc, pll, &crtc_state->dpll_hw_state); - crtc_state->shared_dpll = pll; + crtc_state->dpll_global = pll; return 0; } @@ -690,7 +690,7 @@ static const struct intel_dpll_mgr pch_pll_mgr = { }; static void hsw_ddi_wrpll_enable(struct intel_display *display, - struct intel_shared_dpll *pll, + struct intel_dpll_global *pll, const struct intel_dpll_hw_state *dpll_hw_state) { const struct hsw_dpll_hw_state *hw_state = &dpll_hw_state->hsw; @@ -702,7 +702,7 @@ static void hsw_ddi_wrpll_enable(struct intel_display *display, } static void hsw_ddi_spll_enable(struct intel_display *display, - struct intel_shared_dpll *pll, + struct intel_dpll_global *pll, const struct intel_dpll_hw_state *dpll_hw_state) { const struct hsw_dpll_hw_state *hw_state = &dpll_hw_state->hsw; @@ -713,7 +713,7 @@ static void hsw_ddi_spll_enable(struct intel_display *display, } static void hsw_ddi_wrpll_disable(struct intel_display *display, - struct intel_shared_dpll *pll) + struct intel_dpll_global *pll) { const enum intel_dpll_id id = pll->info->id; @@ -729,7 +729,7 @@ static void hsw_ddi_wrpll_disable(struct intel_display *display, } static void hsw_ddi_spll_disable(struct intel_display *display, - struct intel_shared_dpll *pll) + struct intel_dpll_global *pll) { enum intel_dpll_id id = pll->info->id; @@ -745,7 +745,7 @@ static void hsw_ddi_spll_disable(struct intel_display *display, } static bool hsw_ddi_wrpll_get_hw_state(struct intel_display *display, - struct intel_shared_dpll *pll, + struct intel_dpll_global *pll, struct intel_dpll_hw_state *dpll_hw_state) { struct hsw_dpll_hw_state *hw_state = &dpll_hw_state->hsw; @@ -767,7 +767,7 @@ static bool hsw_ddi_wrpll_get_hw_state(struct intel_display *display, } static bool hsw_ddi_spll_get_hw_state(struct intel_display *display, - struct intel_shared_dpll *pll, + struct intel_dpll_global *pll, struct intel_dpll_hw_state *dpll_hw_state) { struct hsw_dpll_hw_state *hw_state = &dpll_hw_state->hsw; @@ -994,7 +994,7 @@ hsw_ddi_calculate_wrpll(int clock /* in Hz */, } static int hsw_ddi_wrpll_get_freq(struct intel_display *display, - const struct intel_shared_dpll *pll, + const struct intel_dpll_global *pll, const struct intel_dpll_hw_state *dpll_hw_state) { const struct hsw_dpll_hw_state *hw_state = &dpll_hw_state->hsw; @@ -1057,7 +1057,7 @@ hsw_ddi_wrpll_compute_dpll(struct intel_atomic_state *state, return 0; } -static struct intel_shared_dpll * +static struct intel_dpll_global * hsw_ddi_wrpll_get_dpll(struct intel_atomic_state *state, struct intel_crtc *crtc) { @@ -1088,11 +1088,11 @@ hsw_ddi_lcpll_compute_dpll(struct intel_crtc_state *crtc_state) } } -static struct intel_shared_dpll * +static struct intel_dpll_global * hsw_ddi_lcpll_get_dpll(struct intel_crtc_state *crtc_state) { struct intel_display *display = to_intel_display(crtc_state); - struct intel_shared_dpll *pll; + struct intel_dpll_global *pll; enum intel_dpll_id pll_id; int clock = crtc_state->port_clock; @@ -1120,7 +1120,7 @@ hsw_ddi_lcpll_get_dpll(struct intel_crtc_state *crtc_state) } static int hsw_ddi_lcpll_get_freq(struct intel_display *display, - const struct intel_shared_dpll *pll, + const struct intel_dpll_global *pll, const struct intel_dpll_hw_state *dpll_hw_state) { int link_clock = 0; @@ -1160,7 +1160,7 @@ hsw_ddi_spll_compute_dpll(struct intel_atomic_state *state, return 0; } -static struct intel_shared_dpll * +static struct intel_dpll_global * hsw_ddi_spll_get_dpll(struct intel_atomic_state *state, struct intel_crtc *crtc) { @@ -1172,7 +1172,7 @@ hsw_ddi_spll_get_dpll(struct intel_atomic_state *state, } static int hsw_ddi_spll_get_freq(struct intel_display *display, - const struct intel_shared_dpll *pll, + const struct intel_dpll_global *pll, const struct intel_dpll_hw_state *dpll_hw_state) { const struct hsw_dpll_hw_state *hw_state = &dpll_hw_state->hsw; @@ -1219,7 +1219,7 @@ static int hsw_get_dpll(struct intel_atomic_state *state, { struct intel_crtc_state *crtc_state = intel_atomic_get_new_crtc_state(state, crtc); - struct intel_shared_dpll *pll = NULL; + struct intel_dpll_global *pll = NULL; if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI)) pll = hsw_ddi_wrpll_get_dpll(state, crtc); @@ -1234,7 +1234,7 @@ static int hsw_get_dpll(struct intel_atomic_state *state, intel_reference_shared_dpll(state, crtc, pll, &crtc_state->dpll_hw_state); - crtc_state->shared_dpll = pll; + crtc_state->dpll_global = pll; return 0; } @@ -1283,18 +1283,18 @@ static const struct intel_dpll_global_funcs hsw_ddi_spll_funcs = { }; static void hsw_ddi_lcpll_enable(struct intel_display *display, - struct intel_shared_dpll *pll, + struct intel_dpll_global *pll, const struct intel_dpll_hw_state *hw_state) { } static void hsw_ddi_lcpll_disable(struct intel_display *display, - struct intel_shared_dpll *pll) + struct intel_dpll_global *pll) { } static bool hsw_ddi_lcpll_get_hw_state(struct intel_display *display, - struct intel_shared_dpll *pll, + struct intel_dpll_global *pll, struct intel_dpll_hw_state *dpll_hw_state) { return true; @@ -1362,7 +1362,7 @@ static const struct skl_dpll_regs skl_dpll_regs[4] = { }; static void skl_ddi_pll_write_ctrl1(struct intel_display *display, - struct intel_shared_dpll *pll, + struct intel_dpll_global *pll, const struct skl_dpll_hw_state *hw_state) { const enum intel_dpll_id id = pll->info->id; @@ -1376,7 +1376,7 @@ static void skl_ddi_pll_write_ctrl1(struct intel_display *display, } static void skl_ddi_pll_enable(struct intel_display *display, - struct intel_shared_dpll *pll, + struct intel_dpll_global *pll, const struct intel_dpll_hw_state *dpll_hw_state) { const struct skl_dpll_hw_state *hw_state = &dpll_hw_state->skl; @@ -1398,7 +1398,7 @@ static void skl_ddi_pll_enable(struct intel_display *display, } static void skl_ddi_dpll0_enable(struct intel_display *display, - struct intel_shared_dpll *pll, + struct intel_dpll_global *pll, const struct intel_dpll_hw_state *dpll_hw_state) { const struct skl_dpll_hw_state *hw_state = &dpll_hw_state->skl; @@ -1407,7 +1407,7 @@ static void skl_ddi_dpll0_enable(struct intel_display *display, } static void skl_ddi_pll_disable(struct intel_display *display, - struct intel_shared_dpll *pll) + struct intel_dpll_global *pll) { const struct skl_dpll_regs *regs = skl_dpll_regs; const enum intel_dpll_id id = pll->info->id; @@ -1418,12 +1418,12 @@ static void skl_ddi_pll_disable(struct intel_display *display, } static void skl_ddi_dpll0_disable(struct intel_display *display, - struct intel_shared_dpll *pll) + struct intel_dpll_global *pll) { } static bool skl_ddi_pll_get_hw_state(struct intel_display *display, - struct intel_shared_dpll *pll, + struct intel_dpll_global *pll, struct intel_dpll_hw_state *dpll_hw_state) { struct skl_dpll_hw_state *hw_state = &dpll_hw_state->skl; @@ -1461,7 +1461,7 @@ static bool skl_ddi_pll_get_hw_state(struct intel_display *display, } static bool skl_ddi_dpll0_get_hw_state(struct intel_display *display, - struct intel_shared_dpll *pll, + struct intel_dpll_global *pll, struct intel_dpll_hw_state *dpll_hw_state) { struct skl_dpll_hw_state *hw_state = &dpll_hw_state->skl; @@ -1734,7 +1734,7 @@ skl_ddi_calculate_wrpll(int clock, } static int skl_ddi_wrpll_get_freq(struct intel_display *display, - const struct intel_shared_dpll *pll, + const struct intel_dpll_global *pll, const struct intel_dpll_hw_state *dpll_hw_state) { const struct skl_dpll_hw_state *hw_state = &dpll_hw_state->skl; @@ -1882,7 +1882,7 @@ skl_ddi_dp_set_dpll_hw_state(struct intel_crtc_state *crtc_state) } static int skl_ddi_lcpll_get_freq(struct intel_display *display, - const struct intel_shared_dpll *pll, + const struct intel_dpll_global *pll, const struct intel_dpll_hw_state *dpll_hw_state) { const struct skl_dpll_hw_state *hw_state = &dpll_hw_state->skl; @@ -1937,7 +1937,7 @@ static int skl_get_dpll(struct intel_atomic_state *state, { struct intel_crtc_state *crtc_state = intel_atomic_get_new_crtc_state(state, crtc); - struct intel_shared_dpll *pll; + struct intel_dpll_global *pll; if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_EDP)) pll = intel_find_shared_dpll(state, crtc, @@ -1955,13 +1955,13 @@ static int skl_get_dpll(struct intel_atomic_state *state, intel_reference_shared_dpll(state, crtc, pll, &crtc_state->dpll_hw_state); - crtc_state->shared_dpll = pll; + crtc_state->dpll_global = pll; return 0; } static int skl_ddi_pll_get_freq(struct intel_display *display, - const struct intel_shared_dpll *pll, + const struct intel_dpll_global *pll, const struct intel_dpll_hw_state *dpll_hw_state) { const struct skl_dpll_hw_state *hw_state = &dpll_hw_state->skl; @@ -2036,7 +2036,7 @@ static const struct intel_dpll_mgr skl_pll_mgr = { }; static void bxt_ddi_pll_enable(struct intel_display *display, - struct intel_shared_dpll *pll, + struct intel_dpll_global *pll, const struct intel_dpll_hw_state *dpll_hw_state) { const struct bxt_dpll_hw_state *hw_state = &dpll_hw_state->bxt; @@ -2139,7 +2139,7 @@ static void bxt_ddi_pll_enable(struct intel_display *display, } static void bxt_ddi_pll_disable(struct intel_display *display, - struct intel_shared_dpll *pll) + struct intel_dpll_global *pll) { enum port port = (enum port)pll->info->id; /* 1:1 port->PLL mapping */ @@ -2158,7 +2158,7 @@ static void bxt_ddi_pll_disable(struct intel_display *display, } static bool bxt_ddi_pll_get_hw_state(struct intel_display *display, - struct intel_shared_dpll *pll, + struct intel_dpll_global *pll, struct intel_dpll_hw_state *dpll_hw_state) { struct bxt_dpll_hw_state *hw_state = &dpll_hw_state->bxt; @@ -2358,7 +2358,7 @@ static int bxt_ddi_set_dpll_hw_state(struct intel_crtc_state *crtc_state, } static int bxt_ddi_pll_get_freq(struct intel_display *display, - const struct intel_shared_dpll *pll, + const struct intel_dpll_global *pll, const struct intel_dpll_hw_state *dpll_hw_state) { const struct bxt_dpll_hw_state *hw_state = &dpll_hw_state->bxt; @@ -2427,7 +2427,7 @@ static int bxt_get_dpll(struct intel_atomic_state *state, struct intel_display *display = to_intel_display(state); struct intel_crtc_state *crtc_state = intel_atomic_get_new_crtc_state(state, crtc); - struct intel_shared_dpll *pll; + struct intel_dpll_global *pll; enum intel_dpll_id id; /* 1:1 mapping between ports and PLLs */ @@ -2440,7 +2440,7 @@ static int bxt_get_dpll(struct intel_atomic_state *state, intel_reference_shared_dpll(state, crtc, pll, &crtc_state->dpll_hw_state); - crtc_state->shared_dpll = pll; + crtc_state->dpll_global = pll; return 0; } @@ -2755,7 +2755,7 @@ static int icl_calc_tbt_pll(struct intel_crtc_state *crtc_state, } static int icl_ddi_tbt_pll_get_freq(struct intel_display *display, - const struct intel_shared_dpll *pll, + const struct intel_dpll_global *pll, const struct intel_dpll_hw_state *dpll_hw_state) { /* @@ -2826,7 +2826,7 @@ icl_calc_wrpll(struct intel_crtc_state *crtc_state, } static int icl_ddi_combo_pll_get_freq(struct intel_display *display, - const struct intel_shared_dpll *pll, + const struct intel_dpll_global *pll, const struct intel_dpll_hw_state *dpll_hw_state) { const struct icl_dpll_hw_state *hw_state = &dpll_hw_state->icl; @@ -3199,7 +3199,7 @@ static int icl_calc_mg_pll_state(struct intel_crtc_state *crtc_state, } static int icl_ddi_mg_pll_get_freq(struct intel_display *display, - const struct intel_shared_dpll *pll, + const struct intel_dpll_global *pll, const struct intel_dpll_hw_state *dpll_hw_state) { const struct icl_dpll_hw_state *hw_state = &dpll_hw_state->icl; @@ -3285,7 +3285,7 @@ void icl_set_active_port_dpll(struct intel_crtc_state *crtc_state, struct icl_port_dpll *port_dpll = &crtc_state->icl_port_dplls[port_dpll_id]; - crtc_state->shared_dpll = port_dpll->pll; + crtc_state->dpll_global = port_dpll->pll; crtc_state->dpll_hw_state = port_dpll->hw_state; } @@ -3428,8 +3428,8 @@ static int icl_compute_tc_phy_dplls(struct intel_atomic_state *state, return ret; /* this is mainly for the fastset check */ - if (old_crtc_state->shared_dpll && - old_crtc_state->shared_dpll->info->id == DPLL_ID_ICL_TBTPLL) + if (old_crtc_state->dpll_global && + old_crtc_state->dpll_global->info->id == DPLL_ID_ICL_TBTPLL) icl_set_active_port_dpll(crtc_state, ICL_PORT_DPLL_DEFAULT); else icl_set_active_port_dpll(crtc_state, ICL_PORT_DPLL_MG_PHY); @@ -3521,7 +3521,7 @@ static void icl_put_dplls(struct intel_atomic_state *state, intel_atomic_get_new_crtc_state(state, crtc); enum icl_port_dpll_id id; - new_crtc_state->shared_dpll = NULL; + new_crtc_state->dpll_global = NULL; for (id = ICL_PORT_DPLL_DEFAULT; id < ICL_PORT_DPLL_COUNT; id++) { const struct icl_port_dpll *old_port_dpll = @@ -3539,7 +3539,7 @@ static void icl_put_dplls(struct intel_atomic_state *state, } static bool mg_pll_get_hw_state(struct intel_display *display, - struct intel_shared_dpll *pll, + struct intel_dpll_global *pll, struct intel_dpll_hw_state *dpll_hw_state) { struct icl_dpll_hw_state *hw_state = &dpll_hw_state->icl; @@ -3606,7 +3606,7 @@ static bool mg_pll_get_hw_state(struct intel_display *display, } static bool dkl_pll_get_hw_state(struct intel_display *display, - struct intel_shared_dpll *pll, + struct intel_dpll_global *pll, struct intel_dpll_hw_state *dpll_hw_state) { struct icl_dpll_hw_state *hw_state = &dpll_hw_state->icl; @@ -3678,7 +3678,7 @@ static bool dkl_pll_get_hw_state(struct intel_display *display, } static bool icl_pll_get_hw_state(struct intel_display *display, - struct intel_shared_dpll *pll, + struct intel_dpll_global *pll, struct intel_dpll_hw_state *dpll_hw_state, i915_reg_t enable_reg) { @@ -3739,7 +3739,7 @@ static bool icl_pll_get_hw_state(struct intel_display *display, } static bool combo_pll_get_hw_state(struct intel_display *display, - struct intel_shared_dpll *pll, + struct intel_dpll_global *pll, struct intel_dpll_hw_state *dpll_hw_state) { i915_reg_t enable_reg = intel_combo_pll_enable_reg(display, pll); @@ -3748,14 +3748,14 @@ static bool combo_pll_get_hw_state(struct intel_display *display, } static bool tbt_pll_get_hw_state(struct intel_display *display, - struct intel_shared_dpll *pll, + struct intel_dpll_global *pll, struct intel_dpll_hw_state *dpll_hw_state) { return icl_pll_get_hw_state(display, pll, dpll_hw_state, TBT_PLL_ENABLE); } static void icl_dpll_write(struct intel_display *display, - struct intel_shared_dpll *pll, + struct intel_dpll_global *pll, const struct icl_dpll_hw_state *hw_state) { const enum intel_dpll_id id = pll->info->id; @@ -3797,7 +3797,7 @@ static void icl_dpll_write(struct intel_display *display, } static void icl_mg_pll_write(struct intel_display *display, - struct intel_shared_dpll *pll, + struct intel_dpll_global *pll, const struct icl_dpll_hw_state *hw_state) { enum tc_port tc_port = icl_pll_id_to_tc_port(pll->info->id); @@ -3840,7 +3840,7 @@ static void icl_mg_pll_write(struct intel_display *display, } static void dkl_pll_write(struct intel_display *display, - struct intel_shared_dpll *pll, + struct intel_dpll_global *pll, const struct icl_dpll_hw_state *hw_state) { enum tc_port tc_port = icl_pll_id_to_tc_port(pll->info->id); @@ -3905,7 +3905,7 @@ static void dkl_pll_write(struct intel_display *display, } static void icl_pll_power_enable(struct intel_display *display, - struct intel_shared_dpll *pll, + struct intel_dpll_global *pll, i915_reg_t enable_reg) { intel_de_rmw(display, enable_reg, 0, PLL_POWER_ENABLE); @@ -3920,7 +3920,7 @@ static void icl_pll_power_enable(struct intel_display *display, } static void icl_pll_enable(struct intel_display *display, - struct intel_shared_dpll *pll, + struct intel_dpll_global *pll, i915_reg_t enable_reg) { intel_de_rmw(display, enable_reg, 0, PLL_ENABLE); @@ -3930,7 +3930,7 @@ static void icl_pll_enable(struct intel_display *display, drm_err(display->drm, "PLL %d not locked\n", pll->info->id); } -static void adlp_cmtg_clock_gating_wa(struct intel_display *display, struct intel_shared_dpll *pll) +static void adlp_cmtg_clock_gating_wa(struct intel_display *display, struct intel_dpll_global *pll) { u32 val; @@ -3955,7 +3955,7 @@ static void adlp_cmtg_clock_gating_wa(struct intel_display *display, struct inte } static void combo_pll_enable(struct intel_display *display, - struct intel_shared_dpll *pll, + struct intel_dpll_global *pll, const struct intel_dpll_hw_state *dpll_hw_state) { const struct icl_dpll_hw_state *hw_state = &dpll_hw_state->icl; @@ -3979,7 +3979,7 @@ static void combo_pll_enable(struct intel_display *display, } static void tbt_pll_enable(struct intel_display *display, - struct intel_shared_dpll *pll, + struct intel_dpll_global *pll, const struct intel_dpll_hw_state *dpll_hw_state) { const struct icl_dpll_hw_state *hw_state = &dpll_hw_state->icl; @@ -4000,7 +4000,7 @@ static void tbt_pll_enable(struct intel_display *display, } static void mg_pll_enable(struct intel_display *display, - struct intel_shared_dpll *pll, + struct intel_dpll_global *pll, const struct intel_dpll_hw_state *dpll_hw_state) { const struct icl_dpll_hw_state *hw_state = &dpll_hw_state->icl; @@ -4025,7 +4025,7 @@ static void mg_pll_enable(struct intel_display *display, } static void icl_pll_disable(struct intel_display *display, - struct intel_shared_dpll *pll, + struct intel_dpll_global *pll, i915_reg_t enable_reg) { /* The first steps are done by intel_ddi_post_disable(). */ @@ -4056,7 +4056,7 @@ static void icl_pll_disable(struct intel_display *display, } static void combo_pll_disable(struct intel_display *display, - struct intel_shared_dpll *pll) + struct intel_dpll_global *pll) { i915_reg_t enable_reg = intel_combo_pll_enable_reg(display, pll); @@ -4064,13 +4064,13 @@ static void combo_pll_disable(struct intel_display *display, } static void tbt_pll_disable(struct intel_display *display, - struct intel_shared_dpll *pll) + struct intel_dpll_global *pll) { icl_pll_disable(display, pll, TBT_PLL_ENABLE); } static void mg_pll_disable(struct intel_display *display, - struct intel_shared_dpll *pll) + struct intel_dpll_global *pll) { i915_reg_t enable_reg = intel_tc_pll_enable_reg(display, pll); @@ -4347,19 +4347,19 @@ void intel_shared_dpll_init(struct intel_display *display) for (i = 0; dpll_info[i].name; i++) { if (drm_WARN_ON(display->drm, - i >= ARRAY_SIZE(display->dpll.shared_dplls))) + i >= ARRAY_SIZE(display->dpll.dpll_globals))) break; /* must fit into unsigned long bitmask on 32bit */ if (drm_WARN_ON(display->drm, dpll_info[i].id >= 32)) break; - display->dpll.shared_dplls[i].info = &dpll_info[i]; - display->dpll.shared_dplls[i].index = i; + display->dpll.dpll_globals[i].info = &dpll_info[i]; + display->dpll.dpll_globals[i].index = i; } display->dpll.mgr = dpll_mgr; - display->dpll.num_shared_dpll = i; + display->dpll.num_dpll_global = i; } /** @@ -4483,7 +4483,7 @@ void intel_update_active_dpll(struct intel_atomic_state *state, * Return the output frequency corresponding to @pll's passed in @dpll_hw_state. */ int intel_dpll_get_freq(struct intel_display *display, - const struct intel_shared_dpll *pll, + const struct intel_dpll_global *pll, const struct intel_dpll_hw_state *dpll_hw_state) { if (drm_WARN_ON(display->drm, !pll->info->funcs->get_freq)) @@ -4501,14 +4501,14 @@ int intel_dpll_get_freq(struct intel_display *display, * Read out @pll's hardware state into @dpll_hw_state. */ bool intel_dpll_get_hw_state(struct intel_display *display, - struct intel_shared_dpll *pll, + struct intel_dpll_global *pll, struct intel_dpll_hw_state *dpll_hw_state) { return pll->info->funcs->get_hw_state(display, pll, dpll_hw_state); } static void readout_dpll_hw_state(struct intel_display *display, - struct intel_shared_dpll *pll) + struct intel_dpll_global *pll) { struct intel_crtc *crtc; @@ -4522,7 +4522,7 @@ static void readout_dpll_hw_state(struct intel_display *display, struct intel_crtc_state *crtc_state = to_intel_crtc_state(crtc->base.state); - if (crtc_state->hw.active && crtc_state->shared_dpll == pll) + if (crtc_state->hw.active && crtc_state->dpll_global == pll) intel_reference_shared_dpll_crtc(crtc, pll, &pll->state); } pll->active_mask = pll->state.pipe_mask; @@ -4540,7 +4540,7 @@ void intel_dpll_update_ref_clks(struct intel_display *display) void intel_dpll_readout_hw_state(struct intel_display *display) { - struct intel_shared_dpll *pll; + struct intel_dpll_global *pll; int i; for_each_dpll(display, pll, i) @@ -4548,7 +4548,7 @@ void intel_dpll_readout_hw_state(struct intel_display *display) } static void sanitize_dpll_state(struct intel_display *display, - struct intel_shared_dpll *pll) + struct intel_dpll_global *pll) { if (!pll->on) return; @@ -4567,7 +4567,7 @@ static void sanitize_dpll_state(struct intel_display *display, void intel_dpll_sanitize_state(struct intel_display *display) { - struct intel_shared_dpll *pll; + struct intel_dpll_global *pll; int i; intel_cx0_pll_power_save_wa(display); @@ -4624,7 +4624,7 @@ bool intel_dpll_compare_hw_state(struct intel_display *display, static void verify_single_dpll_state(struct intel_display *display, - struct intel_shared_dpll *pll, + struct intel_dpll_global *pll, struct intel_crtc *crtc, const struct intel_crtc_state *new_crtc_state) { @@ -4677,8 +4677,8 @@ verify_single_dpll_state(struct intel_display *display, pll->info->name); } -static bool has_alt_port_dpll(const struct intel_shared_dpll *old_pll, - const struct intel_shared_dpll *new_pll) +static bool has_alt_port_dpll(const struct intel_dpll_global *old_pll, + const struct intel_dpll_global *new_pll) { return old_pll && new_pll && old_pll != new_pll && (old_pll->info->is_alt_port_dpll || new_pll->info->is_alt_port_dpll); @@ -4693,22 +4693,22 @@ void intel_shared_dpll_state_verify(struct intel_atomic_state *state, const struct intel_crtc_state *new_crtc_state = intel_atomic_get_new_crtc_state(state, crtc); - if (new_crtc_state->shared_dpll) - verify_single_dpll_state(display, new_crtc_state->shared_dpll, + if (new_crtc_state->dpll_global) + verify_single_dpll_state(display, new_crtc_state->dpll_global, crtc, new_crtc_state); - if (old_crtc_state->shared_dpll && - old_crtc_state->shared_dpll != new_crtc_state->shared_dpll) { + if (old_crtc_state->dpll_global && + old_crtc_state->dpll_global != new_crtc_state->dpll_global) { u8 pipe_mask = BIT(crtc->pipe); - struct intel_shared_dpll *pll = old_crtc_state->shared_dpll; + struct intel_dpll_global *pll = old_crtc_state->dpll_global; INTEL_DISPLAY_STATE_WARN(display, pll->active_mask & pipe_mask, "%s: pll active mismatch (didn't expect pipe %c in active mask (0x%x))\n", pll->info->name, pipe_name(crtc->pipe), pll->active_mask); /* TC ports have both MG/TC and TBT PLL referenced simultaneously */ - INTEL_DISPLAY_STATE_WARN(display, !has_alt_port_dpll(old_crtc_state->shared_dpll, - new_crtc_state->shared_dpll) && + INTEL_DISPLAY_STATE_WARN(display, !has_alt_port_dpll(old_crtc_state->dpll_global, + new_crtc_state->dpll_global) && pll->state.pipe_mask & pipe_mask, "%s: pll enabled crtcs mismatch (found pipe %c in enabled mask (0x%x))\n", pll->info->name, pipe_name(crtc->pipe), pll->state.pipe_mask); @@ -4718,7 +4718,7 @@ void intel_shared_dpll_state_verify(struct intel_atomic_state *state, void intel_shared_dpll_verify_disabled(struct intel_atomic_state *state) { struct intel_display *display = to_intel_display(state); - struct intel_shared_dpll *pll; + struct intel_dpll_global *pll; int i; for_each_dpll(display, pll, i) diff --git a/drivers/gpu/drm/i915/display/intel_dpll_mgr.h b/drivers/gpu/drm/i915/display/intel_dpll_mgr.h index 2080118be523..bd52e30d83bd 100644 --- a/drivers/gpu/drm/i915/display/intel_dpll_mgr.h +++ b/drivers/gpu/drm/i915/display/intel_dpll_mgr.h @@ -31,8 +31,8 @@ #include "intel_wakeref.h" #define for_each_dpll(__display, __pll, __i) \ - for ((__i) = 0; (__i) < (__display)->dpll.num_shared_dpll && \ - ((__pll) = &(__display)->dpll.shared_dplls[(__i)]) ; (__i)++) + for ((__i) = 0; (__i) < (__display)->dpll.num_dpll_global && \ + ((__pll) = &(__display)->dpll.dpll_globals[(__i)]) ; (__i)++) enum tc_port; struct drm_printer; @@ -344,9 +344,9 @@ struct dpll_info { }; /** - * struct intel_shared_dpll - display PLL with tracked state and users + * struct intel_dpll_global - display PLL with tracked state and users */ -struct intel_shared_dpll { +struct intel_dpll_global { /** * @state: * @@ -388,11 +388,11 @@ struct intel_shared_dpll { #define SKL_DPLL3 3 /* shared dpll functions */ -struct intel_shared_dpll * +struct intel_dpll_global * intel_get_shared_dpll_by_id(struct intel_display *display, enum intel_dpll_id id); void assert_shared_dpll(struct intel_display *display, - struct intel_shared_dpll *pll, + struct intel_dpll_global *pll, bool state); #define assert_shared_dpll_enabled(d, p) assert_shared_dpll(d, p, true) #define assert_shared_dpll_disabled(d, p) assert_shared_dpll(d, p, false) @@ -405,7 +405,7 @@ int intel_reserve_shared_dplls(struct intel_atomic_state *state, void intel_release_shared_dplls(struct intel_atomic_state *state, struct intel_crtc *crtc); void intel_unreference_shared_dpll_crtc(const struct intel_crtc *crtc, - const struct intel_shared_dpll *pll, + const struct intel_dpll_global *pll, struct intel_dpll_state *shared_dpll_state); void icl_set_active_port_dpll(struct intel_crtc_state *crtc_state, enum icl_port_dpll_id port_dpll_id); @@ -413,10 +413,10 @@ void intel_update_active_dpll(struct intel_atomic_state *state, struct intel_crtc *crtc, struct intel_encoder *encoder); int intel_dpll_get_freq(struct intel_display *display, - const struct intel_shared_dpll *pll, + const struct intel_dpll_global *pll, const struct intel_dpll_hw_state *dpll_hw_state); bool intel_dpll_get_hw_state(struct intel_display *display, - struct intel_shared_dpll *pll, + struct intel_dpll_global *pll, struct intel_dpll_hw_state *dpll_hw_state); void intel_enable_shared_dpll(const struct intel_crtc_state *crtc_state); void intel_disable_shared_dpll(const struct intel_crtc_state *crtc_state); diff --git a/drivers/gpu/drm/i915/display/intel_fdi.c b/drivers/gpu/drm/i915/display/intel_fdi.c index 40deee0769ae..acc0b45eced0 100644 --- a/drivers/gpu/drm/i915/display/intel_fdi.c +++ b/drivers/gpu/drm/i915/display/intel_fdi.c @@ -911,7 +911,7 @@ void hsw_fdi_link_train(struct intel_encoder *encoder, intel_de_write(display, FDI_RX_CTL(PIPE_A), rx_ctl_val); /* Configure Port Clock Select */ - drm_WARN_ON(display->drm, crtc_state->shared_dpll->info->id != DPLL_ID_SPLL); + drm_WARN_ON(display->drm, crtc_state->dpll_global->info->id != DPLL_ID_SPLL); intel_ddi_enable_clock(encoder, crtc_state); /* Start the training iterating through available voltages and emphasis, diff --git a/drivers/gpu/drm/i915/display/intel_lvds.c b/drivers/gpu/drm/i915/display/intel_lvds.c index 89d26913e253..bc8725aa99da 100644 --- a/drivers/gpu/drm/i915/display/intel_lvds.c +++ b/drivers/gpu/drm/i915/display/intel_lvds.c @@ -251,7 +251,7 @@ static void intel_pre_enable_lvds(struct intel_atomic_state *state, if (HAS_PCH_SPLIT(i915)) { assert_fdi_rx_pll_disabled(display, pipe); - assert_shared_dpll_disabled(display, crtc_state->shared_dpll); + assert_shared_dpll_disabled(display, crtc_state->dpll_global); } else { assert_pll_disabled(display, pipe); } diff --git a/drivers/gpu/drm/i915/display/intel_modeset_setup.c b/drivers/gpu/drm/i915/display/intel_modeset_setup.c index 3cc915739677..427eff400b53 100644 --- a/drivers/gpu/drm/i915/display/intel_modeset_setup.c +++ b/drivers/gpu/drm/i915/display/intel_modeset_setup.c @@ -91,10 +91,10 @@ static void intel_crtc_disable_noatomic_begin(struct intel_crtc *crtc, crtc->active = false; crtc->base.enabled = false; - if (crtc_state->shared_dpll) + if (crtc_state->dpll_global) intel_unreference_shared_dpll_crtc(crtc, - crtc_state->shared_dpll, - &crtc_state->shared_dpll->state); + crtc_state->dpll_global, + &crtc_state->dpll_global->state); } static void set_encoder_for_connector(struct intel_connector *connector, @@ -568,7 +568,7 @@ static bool has_bogus_dpll_config(const struct intel_crtc_state *crtc_state) */ return IS_SANDYBRIDGE(i915) && crtc_state->hw.active && - crtc_state->shared_dpll && + crtc_state->dpll_global && crtc_state->port_clock == 0; } diff --git a/drivers/gpu/drm/i915/display/intel_pch_display.c b/drivers/gpu/drm/i915/display/intel_pch_display.c index b909ed18a5b2..57303ecb77ad 100644 --- a/drivers/gpu/drm/i915/display/intel_pch_display.c +++ b/drivers/gpu/drm/i915/display/intel_pch_display.c @@ -255,7 +255,7 @@ static void ilk_enable_pch_transcoder(const struct intel_crtc_state *crtc_state) u32 val, pipeconf_val; /* Make sure PCH DPLL is enabled */ - assert_shared_dpll_enabled(display, crtc_state->shared_dpll); + assert_shared_dpll_enabled(display, crtc_state->dpll_global); /* FDI must be feeding us bits for PCH ports */ assert_fdi_tx_enabled(display, pipe); @@ -387,7 +387,7 @@ void ilk_pch_enable(struct intel_atomic_state *state, temp = intel_de_read(display, PCH_DPLL_SEL); temp |= TRANS_DPLL_ENABLE(pipe); sel = TRANS_DPLLB_SEL(pipe); - if (crtc_state->shared_dpll == + if (crtc_state->dpll_global == intel_get_shared_dpll_by_id(display, DPLL_ID_PCH_PLL_B)) temp |= sel; else @@ -504,7 +504,7 @@ void ilk_pch_get_config(struct intel_crtc_state *crtc_state) struct intel_display *display = to_intel_display(crtc_state); struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); - struct intel_shared_dpll *pll; + struct intel_dpll_global *pll; enum pipe pipe = crtc->pipe; enum intel_dpll_id pll_id; bool pll_active; @@ -536,8 +536,8 @@ void ilk_pch_get_config(struct intel_crtc_state *crtc_state) pll_id = DPLL_ID_PCH_PLL_A; } - crtc_state->shared_dpll = intel_get_shared_dpll_by_id(display, pll_id); - pll = crtc_state->shared_dpll; + crtc_state->dpll_global = intel_get_shared_dpll_by_id(display, pll_id); + pll = crtc_state->dpll_global; pll_active = intel_dpll_get_hw_state(display, pll, &crtc_state->dpll_hw_state); diff --git a/drivers/gpu/drm/i915/display/intel_pch_refclk.c b/drivers/gpu/drm/i915/display/intel_pch_refclk.c index 611f3b8dffef..24e050d00db9 100644 --- a/drivers/gpu/drm/i915/display/intel_pch_refclk.c +++ b/drivers/gpu/drm/i915/display/intel_pch_refclk.c @@ -500,7 +500,7 @@ static void ilk_init_pch_refclk(struct intel_display *display) { struct drm_i915_private *dev_priv = to_i915(display->drm); struct intel_encoder *encoder; - struct intel_shared_dpll *pll; + struct intel_dpll_global *pll; int i; u32 val, final; bool has_lvds = false; From patchwork Wed Apr 2 08:31:53 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Kandpal, Suraj" X-Patchwork-Id: 14035639 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 1B90AC28B20 for ; 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X-CSE-ConnectionGUID: 5ry3QZVUQViIj8iI0ac6tw== X-CSE-MsgGUID: 8Gn/QfsES/ukCE1wk3mVwg== X-IronPort-AV: E=McAfee;i="6700,10204,11391"; a="44828682" X-IronPort-AV: E=Sophos;i="6.14,295,1736841600"; d="scan'208";a="44828682" Received: from fmviesa007.fm.intel.com ([10.60.135.147]) by orvoesa111.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 02 Apr 2025 01:32:13 -0700 X-CSE-ConnectionGUID: RRdK7xeITaK+8oRib4qnOQ== X-CSE-MsgGUID: Nrq7K9BqTLy5NzjgfRCJ5w== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.14,295,1736841600"; d="scan'208";a="126612356" Received: from kandpal-x299-ud4-pro.iind.intel.com ([10.190.239.10]) by fmviesa007.fm.intel.com with ESMTP; 02 Apr 2025 01:32:10 -0700 From: Suraj Kandpal To: intel-xe@lists.freedesktop.org, intel-gfx@lists.freedesktop.org Cc: ankit.k.nautiyal@intel.com, uma.shankar@intel.com, jani.nikula@intel.com, mika.kahola@intel.com, ville.syrjala@intel.com, Suraj Kandpal Subject: [PATCH 05/16] drm/i915/dpll: Move away from using shared dpll Date: Wed, 2 Apr 2025 14:01:53 +0530 Message-Id: <20250402083204.1523470-6-suraj.kandpal@intel.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20250402083204.1523470-1-suraj.kandpal@intel.com> References: <20250402083204.1523470-1-suraj.kandpal@intel.com> MIME-Version: 1.0 X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" Rename functions to move away from using shared dpll in the dpll framework as much as possible since dpll may not always be shared. --v2 -Use intel_dpll_global instead of global_dpll [Jani] Signed-off-by: Suraj Kandpal --- drivers/gpu/drm/i915/display/intel_ddi.c | 14 +- drivers/gpu/drm/i915/display/intel_display.c | 8 +- .../drm/i915/display/intel_display_driver.c | 2 +- drivers/gpu/drm/i915/display/intel_dpll.c | 10 +- drivers/gpu/drm/i915/display/intel_dpll_mgr.c | 150 +++++++++--------- drivers/gpu/drm/i915/display/intel_dpll_mgr.h | 32 ++-- drivers/gpu/drm/i915/display/intel_lvds.c | 2 +- .../drm/i915/display/intel_modeset_setup.c | 2 +- .../drm/i915/display/intel_modeset_verify.c | 4 +- .../gpu/drm/i915/display/intel_pch_display.c | 14 +- 10 files changed, 119 insertions(+), 119 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c b/drivers/gpu/drm/i915/display/intel_ddi.c index a8934ea5077d..3fe330bf2636 100644 --- a/drivers/gpu/drm/i915/display/intel_ddi.c +++ b/drivers/gpu/drm/i915/display/intel_ddi.c @@ -1567,7 +1567,7 @@ _icl_ddi_get_pll(struct intel_display *display, i915_reg_t reg, id = (intel_de_read(display, reg) & clk_sel_mask) >> clk_sel_shift; - return intel_get_shared_dpll_by_id(display, id); + return intel_get_dpll_global_by_id(display, id); } static void adls_ddi_enable_clock(struct intel_encoder *encoder, @@ -1721,7 +1721,7 @@ static struct intel_dpll_global *dg1_ddi_get_pll(struct intel_encoder *encoder) if (phy >= PHY_C) id += DPLL_ID_DG1_DPLL2; - return intel_get_shared_dpll_by_id(display, id); + return intel_get_dpll_global_by_id(display, id); } static void icl_ddi_combo_enable_clock(struct intel_encoder *encoder, @@ -1893,7 +1893,7 @@ static struct intel_dpll_global *icl_ddi_tc_get_pll(struct intel_encoder *encode return NULL; } - return intel_get_shared_dpll_by_id(display, id); + return intel_get_dpll_global_by_id(display, id); } static struct intel_dpll_global *bxt_ddi_get_pll(struct intel_encoder *encoder) @@ -1916,7 +1916,7 @@ static struct intel_dpll_global *bxt_ddi_get_pll(struct intel_encoder *encoder) return NULL; } - return intel_get_shared_dpll_by_id(display, id); + return intel_get_dpll_global_by_id(display, id); } static void skl_ddi_enable_clock(struct intel_encoder *encoder, @@ -1984,7 +1984,7 @@ static struct intel_dpll_global *skl_ddi_get_pll(struct intel_encoder *encoder) id = (tmp & DPLL_CTRL2_DDI_CLK_SEL_MASK(port)) >> DPLL_CTRL2_DDI_CLK_SEL_SHIFT(port); - return intel_get_shared_dpll_by_id(display, id); + return intel_get_dpll_global_by_id(display, id); } void hsw_ddi_enable_clock(struct intel_encoder *encoder, @@ -2051,7 +2051,7 @@ static struct intel_dpll_global *hsw_ddi_get_pll(struct intel_encoder *encoder) return NULL; } - return intel_get_shared_dpll_by_id(display, id); + return intel_get_dpll_global_by_id(display, id); } void intel_ddi_enable_clock(struct intel_encoder *encoder, @@ -2758,7 +2758,7 @@ static void tgl_ddi_pre_enable_dp(struct intel_atomic_state *state, * 4. Enable the port PLL. * * The PLL enabling itself was already done before this function by - * hsw_crtc_enable()->intel_enable_shared_dpll(). We need only + * hsw_crtc_enable()->intel_enable_dpll_global(). We need only * configure the PLL to port mapping here. */ intel_ddi_enable_clock(encoder, crtc_state); diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c index 5b808bad61e0..904b9544515b 100644 --- a/drivers/gpu/drm/i915/display/intel_display.c +++ b/drivers/gpu/drm/i915/display/intel_display.c @@ -1662,7 +1662,7 @@ static void hsw_crtc_enable(struct intel_atomic_state *state, intel_encoders_pre_pll_enable(state, crtc); if (new_crtc_state->dpll_global) - intel_enable_shared_dpll(new_crtc_state); + intel_enable_dpll_global(new_crtc_state); intel_encoders_pre_enable(state, crtc); @@ -1791,7 +1791,7 @@ static void hsw_crtc_disable(struct intel_atomic_state *state, intel_encoders_disable(state, crtc); intel_encoders_post_disable(state, crtc); - intel_disable_shared_dpll(old_crtc_state); + intel_disable_dpll_global(old_crtc_state); intel_encoders_post_pll_disable(state, crtc); @@ -6429,7 +6429,7 @@ int intel_atomic_check(struct drm_device *dev, any_ms = true; - intel_release_shared_dplls(state, crtc); + intel_release_dpll_globals(state, crtc); } if (any_ms && !check_digital_port_conflicts(state)) { @@ -7523,7 +7523,7 @@ static int intel_atomic_swap_state(struct intel_atomic_state *state) intel_atomic_swap_global_state(state); - intel_shared_dpll_swap_state(state); + intel_dpll_swap_state(state); intel_atomic_track_fbs(state); diff --git a/drivers/gpu/drm/i915/display/intel_display_driver.c b/drivers/gpu/drm/i915/display/intel_display_driver.c index 4edadebad13b..b6c670c54eb1 100644 --- a/drivers/gpu/drm/i915/display/intel_display_driver.c +++ b/drivers/gpu/drm/i915/display/intel_display_driver.c @@ -441,7 +441,7 @@ int intel_display_driver_probe_nogem(struct intel_display *display) } intel_plane_possible_crtcs_init(display); - intel_shared_dpll_init(display); + intel_dpll_global_init(display); intel_fdi_pll_freq_update(display); intel_update_czclk(display); diff --git a/drivers/gpu/drm/i915/display/intel_dpll.c b/drivers/gpu/drm/i915/display/intel_dpll.c index c6d29382378b..04fb76a399ab 100644 --- a/drivers/gpu/drm/i915/display/intel_dpll.c +++ b/drivers/gpu/drm/i915/display/intel_dpll.c @@ -1162,7 +1162,7 @@ static int hsw_crtc_compute_clock(struct intel_atomic_state *state, intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DSI)) return 0; - ret = intel_compute_shared_dplls(state, crtc, encoder); + ret = intel_compute_dpll_globals(state, crtc, encoder); if (ret) return ret; @@ -1190,7 +1190,7 @@ static int hsw_crtc_get_shared_dpll(struct intel_atomic_state *state, intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DSI)) return 0; - return intel_reserve_shared_dplls(state, crtc, encoder); + return intel_reserve_dpll_globals(state, crtc, encoder); } static int dg2_crtc_compute_clock(struct intel_atomic_state *state, @@ -1224,7 +1224,7 @@ static int mtl_crtc_compute_clock(struct intel_atomic_state *state, if (ret) return ret; - /* TODO: Do the readback via intel_compute_shared_dplls() */ + /* TODO: Do the readback via intel_compute_dpll_globals() */ crtc_state->port_clock = intel_cx0pll_calc_port_clock(encoder, &crtc_state->dpll_hw_state.cx0pll); crtc_state->hw.adjusted_mode.crtc_clock = intel_crtc_dotclock(crtc_state); @@ -1397,7 +1397,7 @@ static int ilk_crtc_compute_clock(struct intel_atomic_state *state, ilk_compute_dpll(crtc_state, &crtc_state->dpll, &crtc_state->dpll); - ret = intel_compute_shared_dplls(state, crtc, NULL); + ret = intel_compute_dpll_globals(state, crtc, NULL); if (ret) return ret; @@ -1417,7 +1417,7 @@ static int ilk_crtc_get_shared_dpll(struct intel_atomic_state *state, if (!crtc_state->has_pch_encoder) return 0; - return intel_reserve_shared_dplls(state, crtc, NULL); + return intel_reserve_dpll_globals(state, crtc, NULL); } static u32 vlv_dpll(const struct intel_crtc_state *crtc_state) diff --git a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c index 833c90f3f0f1..e6546d735799 100644 --- a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c +++ b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c @@ -49,21 +49,21 @@ * share a PLL if their configurations match. * * This file provides an abstraction over display PLLs. The function - * intel_shared_dpll_init() initializes the PLLs for the given platform. The + * intel_dpll_global_init() initializes the PLLs for the given platform. The * users of a PLL are tracked and that tracking is integrated with the atomic * modset interface. During an atomic operation, required PLLs can be reserved * for a given CRTC and encoder configuration by calling - * intel_reserve_shared_dplls() and previously reserved PLLs can be released - * with intel_release_shared_dplls(). + * intel_reserve_dpll_globals() and previously reserved PLLs can be released + * with intel_release_dpll_globals(). * Changes to the users are first staged in the atomic state, and then made - * effective by calling intel_shared_dpll_swap_state() during the atomic + * effective by calling intel_dpll_swap_state() during the atomic * commit phase. */ /* platform specific hooks for managing DPLLs */ struct intel_dpll_global_funcs { /* - * Hook for enabling the pll, called from intel_enable_shared_dpll() if + * Hook for enabling the pll, called from intel_enable_dpll_global() if * the pll is not already enabled. */ void (*enable)(struct intel_display *display, @@ -71,7 +71,7 @@ struct intel_dpll_global_funcs { const struct intel_dpll_hw_state *dpll_hw_state); /* - * Hook for disabling the pll, called from intel_disable_shared_dpll() + * Hook for disabling the pll, called from intel_disable_dpll_global() * only when it is safe to disable the pll, i.e., there are no more * tracked users for it. */ @@ -130,7 +130,7 @@ intel_atomic_duplicate_dpll_state(struct intel_display *display, } static struct intel_dpll_state * -intel_atomic_get_shared_dpll_state(struct drm_atomic_state *s) +intel_atomic_get_dpll_global_state(struct drm_atomic_state *s) { struct intel_atomic_state *state = to_intel_atomic_state(s); struct intel_display *display = to_intel_display(state); @@ -148,7 +148,7 @@ intel_atomic_get_shared_dpll_state(struct drm_atomic_state *s) } /** - * intel_get_shared_dpll_by_id - get a DPLL given its id + * intel_get_dpll_global_by_id - get a DPLL given its id * @display: intel_display device instance * @id: pll id * @@ -156,7 +156,7 @@ intel_atomic_get_shared_dpll_state(struct drm_atomic_state *s) * A pointer to the DPLL with @id */ struct intel_dpll_global * -intel_get_shared_dpll_by_id(struct intel_display *display, +intel_get_dpll_global_by_id(struct intel_display *display, enum intel_dpll_id id) { struct intel_dpll_global *pll; @@ -172,7 +172,7 @@ intel_get_shared_dpll_by_id(struct intel_display *display, } /* For ILK+ */ -void assert_shared_dpll(struct intel_display *display, +void assert_dpll_global(struct intel_display *display, struct intel_dpll_global *pll, bool state) { @@ -247,12 +247,12 @@ static void _intel_disable_shared_dpll(struct intel_display *display, } /** - * intel_enable_shared_dpll - enable a CRTC's shared DPLL - * @crtc_state: CRTC, and its state, which has a shared DPLL + * intel_enable_dpll_global - enable a CRTC's global DPLL + * @crtc_state: CRTC, and its state, which has a DPLL * - * Enable the shared DPLL used by @crtc. + * Enable DPLL used by @crtc. */ -void intel_enable_shared_dpll(const struct intel_crtc_state *crtc_state) +void intel_enable_dpll_global(const struct intel_crtc_state *crtc_state) { struct intel_display *display = to_intel_display(crtc_state); struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); @@ -279,7 +279,7 @@ void intel_enable_shared_dpll(const struct intel_crtc_state *crtc_state) if (old_mask) { drm_WARN_ON(display->drm, !pll->on); - assert_shared_dpll_enabled(display, pll); + assert_dpll_global_enabled(display, pll); goto out; } drm_WARN_ON(display->drm, pll->on); @@ -293,12 +293,12 @@ void intel_enable_shared_dpll(const struct intel_crtc_state *crtc_state) } /** - * intel_disable_shared_dpll - disable a CRTC's shared DPLL + * intel_disable_dpll_global - disable a CRTC's shared DPLL * @crtc_state: CRTC, and its state, which has a shared DPLL * - * Disable the shared DPLL used by @crtc. + * Disable DPLL used by @crtc. */ -void intel_disable_shared_dpll(const struct intel_crtc_state *crtc_state) +void intel_disable_dpll_global(const struct intel_crtc_state *crtc_state) { struct intel_display *display = to_intel_display(crtc_state); struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); @@ -323,7 +323,7 @@ void intel_disable_shared_dpll(const struct intel_crtc_state *crtc_state) pll->info->name, pll->active_mask, pll->on, crtc->base.base.id, crtc->base.name); - assert_shared_dpll_enabled(display, pll); + assert_dpll_global_enabled(display, pll); drm_WARN_ON(display->drm, !pll->on); pll->active_mask &= ~pipe_mask; @@ -355,7 +355,7 @@ intel_dpll_mask_all(struct intel_display *display) } static struct intel_dpll_global * -intel_find_shared_dpll(struct intel_atomic_state *state, +intel_find_dpll_global(struct intel_atomic_state *state, const struct intel_crtc *crtc, const struct intel_dpll_hw_state *dpll_hw_state, unsigned long dpll_mask) @@ -366,14 +366,14 @@ intel_find_shared_dpll(struct intel_atomic_state *state, struct intel_dpll_global *unused_pll = NULL; enum intel_dpll_id id; - dpll_state = intel_atomic_get_shared_dpll_state(&state->base); + dpll_state = intel_atomic_get_dpll_global_state(&state->base); drm_WARN_ON(display->drm, dpll_mask & ~dpll_mask_all); for_each_set_bit(id, &dpll_mask, fls(dpll_mask_all)) { struct intel_dpll_global *pll; - pll = intel_get_shared_dpll_by_id(display, id); + pll = intel_get_dpll_global_by_id(display, id); if (!pll) continue; @@ -409,7 +409,7 @@ intel_find_shared_dpll(struct intel_atomic_state *state, } /** - * intel_reference_shared_dpll_crtc - Get a DPLL reference for a CRTC + * intel_reference_dpll_global_crtc - Get a DPLL reference for a CRTC * @crtc: CRTC on which behalf the reference is taken * @pll: DPLL for which the reference is taken * @dpll_state: the DPLL atomic state in which the reference is tracked @@ -417,7 +417,7 @@ intel_find_shared_dpll(struct intel_atomic_state *state, * Take a reference for @pll tracking the use of it by @crtc. */ static void -intel_reference_shared_dpll_crtc(const struct intel_crtc *crtc, +intel_reference_dpll_global_crtc(const struct intel_crtc *crtc, const struct intel_dpll_global *pll, struct intel_dpll_state *dpll_state) { @@ -432,23 +432,23 @@ intel_reference_shared_dpll_crtc(const struct intel_crtc *crtc, } static void -intel_reference_shared_dpll(struct intel_atomic_state *state, +intel_reference_dpll_global(struct intel_atomic_state *state, const struct intel_crtc *crtc, const struct intel_dpll_global *pll, const struct intel_dpll_hw_state *dpll_hw_state) { struct intel_dpll_state *dpll_state; - dpll_state = intel_atomic_get_shared_dpll_state(&state->base); + dpll_state = intel_atomic_get_dpll_global_state(&state->base); if (dpll_state[pll->index].pipe_mask == 0) dpll_state[pll->index].hw_state = *dpll_hw_state; - intel_reference_shared_dpll_crtc(crtc, pll, &dpll_state[pll->index]); + intel_reference_dpll_global_crtc(crtc, pll, &dpll_state[pll->index]); } /** - * intel_unreference_shared_dpll_crtc - Drop a DPLL reference for a CRTC + * intel_unreference_dpll_global_crtc - Drop a DPLL reference for a CRTC * @crtc: CRTC on which behalf the reference is dropped * @pll: DPLL for which the reference is dropped * @dpll_state: the DPLL atomic state in which the reference is tracked @@ -456,7 +456,7 @@ intel_reference_shared_dpll(struct intel_atomic_state *state, * Drop a reference for @pll tracking the end of use of it by @crtc. */ void -intel_unreference_shared_dpll_crtc(const struct intel_crtc *crtc, +intel_unreference_dpll_global_crtc(const struct intel_crtc *crtc, const struct intel_dpll_global *pll, struct intel_dpll_state *dpll_state) { @@ -470,15 +470,15 @@ intel_unreference_shared_dpll_crtc(const struct intel_crtc *crtc, crtc->base.base.id, crtc->base.name, pll->info->name); } -static void intel_unreference_shared_dpll(struct intel_atomic_state *state, +static void intel_unreference_dpll_global(struct intel_atomic_state *state, const struct intel_crtc *crtc, const struct intel_dpll_global *pll) { struct intel_dpll_state *dpll_state; - dpll_state = intel_atomic_get_shared_dpll_state(&state->base); + dpll_state = intel_atomic_get_dpll_global_state(&state->base); - intel_unreference_shared_dpll_crtc(crtc, pll, &dpll_state[pll->index]); + intel_unreference_dpll_global_crtc(crtc, pll, &dpll_state[pll->index]); } static void intel_put_dpll(struct intel_atomic_state *state, @@ -494,11 +494,11 @@ static void intel_put_dpll(struct intel_atomic_state *state, if (!old_crtc_state->dpll_global) return; - intel_unreference_shared_dpll(state, crtc, old_crtc_state->dpll_global); + intel_unreference_dpll_global(state, crtc, old_crtc_state->dpll_global); } /** - * intel_shared_dpll_swap_state - make atomic DPLL configuration effective + * intel_dpll_swap_state - make atomic DPLL configuration effective * @state: atomic state * * This is the dpll version of drm_atomic_helper_swap_state() since the @@ -508,7 +508,7 @@ static void intel_put_dpll(struct intel_atomic_state *state, * i.e. it also puts the current state into @state, even though there is no * need for that at this moment. */ -void intel_shared_dpll_swap_state(struct intel_atomic_state *state) +void intel_dpll_swap_state(struct intel_atomic_state *state) { struct intel_display *display = to_intel_display(state); struct intel_dpll_state *dpll_state = state->dpll_state; @@ -618,14 +618,14 @@ static int ibx_get_dpll(struct intel_atomic_state *state, if (HAS_PCH_IBX(i915)) { /* Ironlake PCH has a fixed PLL->PCH pipe mapping. */ id = (enum intel_dpll_id) crtc->pipe; - pll = intel_get_shared_dpll_by_id(display, id); + pll = intel_get_dpll_global_by_id(display, id); drm_dbg_kms(display->drm, "[CRTC:%d:%s] using pre-allocated %s\n", crtc->base.base.id, crtc->base.name, pll->info->name); } else { - pll = intel_find_shared_dpll(state, crtc, + pll = intel_find_dpll_global(state, crtc, &crtc_state->dpll_hw_state, BIT(DPLL_ID_PCH_PLL_B) | BIT(DPLL_ID_PCH_PLL_A)); @@ -635,7 +635,7 @@ static int ibx_get_dpll(struct intel_atomic_state *state, return -EINVAL; /* reference the pll */ - intel_reference_shared_dpll(state, crtc, + intel_reference_dpll_global(state, crtc, pll, &crtc_state->dpll_hw_state); crtc_state->dpll_global = pll; @@ -1064,7 +1064,7 @@ hsw_ddi_wrpll_get_dpll(struct intel_atomic_state *state, struct intel_crtc_state *crtc_state = intel_atomic_get_new_crtc_state(state, crtc); - return intel_find_shared_dpll(state, crtc, + return intel_find_dpll_global(state, crtc, &crtc_state->dpll_hw_state, BIT(DPLL_ID_WRPLL2) | BIT(DPLL_ID_WRPLL1)); @@ -1111,7 +1111,7 @@ hsw_ddi_lcpll_get_dpll(struct intel_crtc_state *crtc_state) return NULL; } - pll = intel_get_shared_dpll_by_id(display, pll_id); + pll = intel_get_dpll_global_by_id(display, pll_id); if (!pll) return NULL; @@ -1167,7 +1167,7 @@ hsw_ddi_spll_get_dpll(struct intel_atomic_state *state, struct intel_crtc_state *crtc_state = intel_atomic_get_new_crtc_state(state, crtc); - return intel_find_shared_dpll(state, crtc, &crtc_state->dpll_hw_state, + return intel_find_dpll_global(state, crtc, &crtc_state->dpll_hw_state, BIT(DPLL_ID_SPLL)); } @@ -1231,7 +1231,7 @@ static int hsw_get_dpll(struct intel_atomic_state *state, if (!pll) return -EINVAL; - intel_reference_shared_dpll(state, crtc, + intel_reference_dpll_global(state, crtc, pll, &crtc_state->dpll_hw_state); crtc_state->dpll_global = pll; @@ -1940,11 +1940,11 @@ static int skl_get_dpll(struct intel_atomic_state *state, struct intel_dpll_global *pll; if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_EDP)) - pll = intel_find_shared_dpll(state, crtc, + pll = intel_find_dpll_global(state, crtc, &crtc_state->dpll_hw_state, BIT(DPLL_ID_SKL_DPLL0)); else - pll = intel_find_shared_dpll(state, crtc, + pll = intel_find_dpll_global(state, crtc, &crtc_state->dpll_hw_state, BIT(DPLL_ID_SKL_DPLL3) | BIT(DPLL_ID_SKL_DPLL2) | @@ -1952,7 +1952,7 @@ static int skl_get_dpll(struct intel_atomic_state *state, if (!pll) return -EINVAL; - intel_reference_shared_dpll(state, crtc, + intel_reference_dpll_global(state, crtc, pll, &crtc_state->dpll_hw_state); crtc_state->dpll_global = pll; @@ -2432,12 +2432,12 @@ static int bxt_get_dpll(struct intel_atomic_state *state, /* 1:1 mapping between ports and PLLs */ id = (enum intel_dpll_id) encoder->port; - pll = intel_get_shared_dpll_by_id(display, id); + pll = intel_get_dpll_global_by_id(display, id); drm_dbg_kms(display->drm, "[CRTC:%d:%s] using pre-allocated %s\n", crtc->base.base.id, crtc->base.name, pll->info->name); - intel_reference_shared_dpll(state, crtc, + intel_reference_dpll_global(state, crtc, pll, &crtc_state->dpll_hw_state); crtc_state->dpll_global = pll; @@ -3388,13 +3388,13 @@ static int icl_get_combo_phy_dpll(struct intel_atomic_state *state, /* Eliminate DPLLs from consideration if reserved by HTI */ dpll_mask &= ~intel_hti_dpll_mask(display); - port_dpll->pll = intel_find_shared_dpll(state, crtc, + port_dpll->pll = intel_find_dpll_global(state, crtc, &port_dpll->hw_state, dpll_mask); if (!port_dpll->pll) return -EINVAL; - intel_reference_shared_dpll(state, crtc, + intel_reference_dpll_global(state, crtc, port_dpll->pll, &port_dpll->hw_state); icl_update_active_dpll(state, crtc, encoder); @@ -3452,25 +3452,25 @@ static int icl_get_tc_phy_dplls(struct intel_atomic_state *state, int ret; port_dpll = &crtc_state->icl_port_dplls[ICL_PORT_DPLL_DEFAULT]; - port_dpll->pll = intel_find_shared_dpll(state, crtc, + port_dpll->pll = intel_find_dpll_global(state, crtc, &port_dpll->hw_state, BIT(DPLL_ID_ICL_TBTPLL)); if (!port_dpll->pll) return -EINVAL; - intel_reference_shared_dpll(state, crtc, + intel_reference_dpll_global(state, crtc, port_dpll->pll, &port_dpll->hw_state); port_dpll = &crtc_state->icl_port_dplls[ICL_PORT_DPLL_MG_PHY]; dpll_id = icl_tc_port_to_pll_id(intel_encoder_to_tc(encoder)); - port_dpll->pll = intel_find_shared_dpll(state, crtc, + port_dpll->pll = intel_find_dpll_global(state, crtc, &port_dpll->hw_state, BIT(dpll_id)); if (!port_dpll->pll) { ret = -EINVAL; goto err_unreference_tbt_pll; } - intel_reference_shared_dpll(state, crtc, + intel_reference_dpll_global(state, crtc, port_dpll->pll, &port_dpll->hw_state); icl_update_active_dpll(state, crtc, encoder); @@ -3479,7 +3479,7 @@ static int icl_get_tc_phy_dplls(struct intel_atomic_state *state, err_unreference_tbt_pll: port_dpll = &crtc_state->icl_port_dplls[ICL_PORT_DPLL_DEFAULT]; - intel_unreference_shared_dpll(state, crtc, port_dpll->pll); + intel_unreference_dpll_global(state, crtc, port_dpll->pll); return ret; } @@ -3534,7 +3534,7 @@ static void icl_put_dplls(struct intel_atomic_state *state, if (!old_port_dpll->pll) continue; - intel_unreference_shared_dpll(state, crtc, old_port_dpll->pll); + intel_unreference_dpll_global(state, crtc, old_port_dpll->pll); } } @@ -4300,12 +4300,12 @@ static const struct intel_dpll_mgr adlp_pll_mgr = { }; /** - * intel_shared_dpll_init - Initialize shared DPLLs + * intel_dpll_global_init - Initialize DPLLs * @display: intel_display device * - * Initialize shared DPLLs for @display. + * Initialize DPLLs for @display. */ -void intel_shared_dpll_init(struct intel_display *display) +void intel_dpll_global_init(struct intel_display *display) { struct drm_i915_private *i915 = to_i915(display->drm); const struct intel_dpll_mgr *dpll_mgr = NULL; @@ -4363,7 +4363,7 @@ void intel_shared_dpll_init(struct intel_display *display) } /** - * intel_compute_shared_dplls - compute DPLL state CRTC and encoder combination + * intel_compute_dpll_globals - compute DPLL state CRTC and encoder combination * @state: atomic state * @crtc: CRTC to compute DPLLs for * @encoder: encoder @@ -4371,12 +4371,12 @@ void intel_shared_dpll_init(struct intel_display *display) * This function computes the DPLL state for the given CRTC and encoder. * * The new configuration in the atomic commit @state is made effective by - * calling intel_shared_dpll_swap_state(). + * calling intel_dpll_swap_state(). * * Returns: * 0 on success, negative error code on failure. */ -int intel_compute_shared_dplls(struct intel_atomic_state *state, +int intel_compute_dpll_globals(struct intel_atomic_state *state, struct intel_crtc *crtc, struct intel_encoder *encoder) { @@ -4390,7 +4390,7 @@ int intel_compute_shared_dplls(struct intel_atomic_state *state, } /** - * intel_reserve_shared_dplls - reserve DPLLs for CRTC and encoder combination + * intel_reserve_dpll_globals - reserve DPLLs for CRTC and encoder combination * @state: atomic state * @crtc: CRTC to reserve DPLLs for * @encoder: encoder @@ -4400,16 +4400,16 @@ int intel_compute_shared_dplls(struct intel_atomic_state *state, * state. * * The new configuration in the atomic commit @state is made effective by - * calling intel_shared_dpll_swap_state(). + * calling intel_dpll_swap_state(). * * The reserved DPLLs should be released by calling - * intel_release_shared_dplls(). + * intel_release_dpll_globals(). * * Returns: * 0 if all required DPLLs were successfully reserved, * negative error code otherwise. */ -int intel_reserve_shared_dplls(struct intel_atomic_state *state, +int intel_reserve_dpll_globals(struct intel_atomic_state *state, struct intel_crtc *crtc, struct intel_encoder *encoder) { @@ -4423,17 +4423,17 @@ int intel_reserve_shared_dplls(struct intel_atomic_state *state, } /** - * intel_release_shared_dplls - end use of DPLLs by CRTC in atomic state + * intel_release_dpll_globals - end use of DPLLs by CRTC in atomic state * @state: atomic state * @crtc: crtc from which the DPLLs are to be released * - * This function releases all DPLLs reserved by intel_reserve_shared_dplls() + * This function releases all DPLLs reserved by intel_reserve_dpll_globals() * from the current atomic commit @state and the old @crtc atomic state. * * The new configuration in the atomic commit @state is made effective by - * calling intel_shared_dpll_swap_state(). + * calling intel_dpll_swap_state(). */ -void intel_release_shared_dplls(struct intel_atomic_state *state, +void intel_release_dpll_globals(struct intel_atomic_state *state, struct intel_crtc *crtc) { struct intel_display *display = to_intel_display(state); @@ -4442,7 +4442,7 @@ void intel_release_shared_dplls(struct intel_atomic_state *state, /* * FIXME: this function is called for every platform having a * compute_clock hook, even though the platform doesn't yet support - * the shared DPLL framework and intel_reserve_shared_dplls() is not + * the global DPLL framework and intel_reserve_dpll_globals() is not * called on those. */ if (!dpll_mgr) @@ -4458,7 +4458,7 @@ void intel_release_shared_dplls(struct intel_atomic_state *state, * @encoder: encoder determining the type of port DPLL * * Update the active DPLL for the given @crtc/@encoder in @crtc's atomic state, - * from the port DPLLs reserved previously by intel_reserve_shared_dplls(). The + * from the port DPLLs reserved previously by intel_reserve_dpll_globals(). The * DPLL selected will be based on the current mode of the encoder's port. */ void intel_update_active_dpll(struct intel_atomic_state *state, @@ -4523,7 +4523,7 @@ static void readout_dpll_hw_state(struct intel_display *display, to_intel_crtc_state(crtc->base.state); if (crtc_state->hw.active && crtc_state->dpll_global == pll) - intel_reference_shared_dpll_crtc(crtc, pll, &pll->state); + intel_reference_dpll_global_crtc(crtc, pll, &pll->state); } pll->active_mask = pll->state.pipe_mask; @@ -4684,8 +4684,8 @@ static bool has_alt_port_dpll(const struct intel_dpll_global *old_pll, (old_pll->info->is_alt_port_dpll || new_pll->info->is_alt_port_dpll); } -void intel_shared_dpll_state_verify(struct intel_atomic_state *state, - struct intel_crtc *crtc) +void intel_dpll_state_verify(struct intel_atomic_state *state, + struct intel_crtc *crtc) { struct intel_display *display = to_intel_display(state); const struct intel_crtc_state *old_crtc_state = @@ -4715,7 +4715,7 @@ void intel_shared_dpll_state_verify(struct intel_atomic_state *state, } } -void intel_shared_dpll_verify_disabled(struct intel_atomic_state *state) +void intel_dpll_global_verify_disabled(struct intel_atomic_state *state) { struct intel_display *display = to_intel_display(state); struct intel_dpll_global *pll; diff --git a/drivers/gpu/drm/i915/display/intel_dpll_mgr.h b/drivers/gpu/drm/i915/display/intel_dpll_mgr.h index bd52e30d83bd..6215da164ffc 100644 --- a/drivers/gpu/drm/i915/display/intel_dpll_mgr.h +++ b/drivers/gpu/drm/i915/display/intel_dpll_mgr.h @@ -387,24 +387,24 @@ struct intel_dpll_global { #define SKL_DPLL2 2 #define SKL_DPLL3 3 -/* shared dpll functions */ +/* global dpll functions */ struct intel_dpll_global * -intel_get_shared_dpll_by_id(struct intel_display *display, +intel_get_dpll_global_by_id(struct intel_display *display, enum intel_dpll_id id); -void assert_shared_dpll(struct intel_display *display, +void assert_dpll_global(struct intel_display *display, struct intel_dpll_global *pll, bool state); -#define assert_shared_dpll_enabled(d, p) assert_shared_dpll(d, p, true) -#define assert_shared_dpll_disabled(d, p) assert_shared_dpll(d, p, false) -int intel_compute_shared_dplls(struct intel_atomic_state *state, +#define assert_dpll_global_enabled(d, p) assert_dpll_global(d, p, true) +#define assert_dpll_global_disabled(d, p) assert_dpll_global(d, p, false) +int intel_compute_dpll_globals(struct intel_atomic_state *state, struct intel_crtc *crtc, struct intel_encoder *encoder); -int intel_reserve_shared_dplls(struct intel_atomic_state *state, +int intel_reserve_dpll_globals(struct intel_atomic_state *state, struct intel_crtc *crtc, struct intel_encoder *encoder); -void intel_release_shared_dplls(struct intel_atomic_state *state, +void intel_release_dpll_globals(struct intel_atomic_state *state, struct intel_crtc *crtc); -void intel_unreference_shared_dpll_crtc(const struct intel_crtc *crtc, +void intel_unreference_dpll_global_crtc(const struct intel_crtc *crtc, const struct intel_dpll_global *pll, struct intel_dpll_state *shared_dpll_state); void icl_set_active_port_dpll(struct intel_crtc_state *crtc_state, @@ -418,10 +418,10 @@ int intel_dpll_get_freq(struct intel_display *display, bool intel_dpll_get_hw_state(struct intel_display *display, struct intel_dpll_global *pll, struct intel_dpll_hw_state *dpll_hw_state); -void intel_enable_shared_dpll(const struct intel_crtc_state *crtc_state); -void intel_disable_shared_dpll(const struct intel_crtc_state *crtc_state); -void intel_shared_dpll_swap_state(struct intel_atomic_state *state); -void intel_shared_dpll_init(struct intel_display *display); +void intel_enable_dpll_global(const struct intel_crtc_state *crtc_state); +void intel_disable_dpll_global(const struct intel_crtc_state *crtc_state); +void intel_dpll_swap_state(struct intel_atomic_state *state); +void intel_dpll_global_init(struct intel_display *display); void intel_dpll_update_ref_clks(struct intel_display *display); void intel_dpll_readout_hw_state(struct intel_display *display); void intel_dpll_sanitize_state(struct intel_display *display); @@ -435,8 +435,8 @@ bool intel_dpll_compare_hw_state(struct intel_display *display, enum intel_dpll_id icl_tc_port_to_pll_id(enum tc_port tc_port); bool intel_dpll_is_combophy(enum intel_dpll_id id); -void intel_shared_dpll_state_verify(struct intel_atomic_state *state, - struct intel_crtc *crtc); -void intel_shared_dpll_verify_disabled(struct intel_atomic_state *state); +void intel_dpll_state_verify(struct intel_atomic_state *state, + struct intel_crtc *crtc); +void intel_dpll_global_verify_disabled(struct intel_atomic_state *state); #endif /* _INTEL_DPLL_MGR_H_ */ diff --git a/drivers/gpu/drm/i915/display/intel_lvds.c b/drivers/gpu/drm/i915/display/intel_lvds.c index bc8725aa99da..52f61a120b70 100644 --- a/drivers/gpu/drm/i915/display/intel_lvds.c +++ b/drivers/gpu/drm/i915/display/intel_lvds.c @@ -251,7 +251,7 @@ static void intel_pre_enable_lvds(struct intel_atomic_state *state, if (HAS_PCH_SPLIT(i915)) { assert_fdi_rx_pll_disabled(display, pipe); - assert_shared_dpll_disabled(display, crtc_state->dpll_global); + assert_dpll_global_disabled(display, crtc_state->dpll_global); } else { assert_pll_disabled(display, pipe); } diff --git a/drivers/gpu/drm/i915/display/intel_modeset_setup.c b/drivers/gpu/drm/i915/display/intel_modeset_setup.c index 427eff400b53..4221d1566c8a 100644 --- a/drivers/gpu/drm/i915/display/intel_modeset_setup.c +++ b/drivers/gpu/drm/i915/display/intel_modeset_setup.c @@ -92,7 +92,7 @@ static void intel_crtc_disable_noatomic_begin(struct intel_crtc *crtc, crtc->base.enabled = false; if (crtc_state->dpll_global) - intel_unreference_shared_dpll_crtc(crtc, + intel_unreference_dpll_global_crtc(crtc, crtc_state->dpll_global, &crtc_state->dpll_global->state); } diff --git a/drivers/gpu/drm/i915/display/intel_modeset_verify.c b/drivers/gpu/drm/i915/display/intel_modeset_verify.c index a008412fdd04..eb080a1d8a42 100644 --- a/drivers/gpu/drm/i915/display/intel_modeset_verify.c +++ b/drivers/gpu/drm/i915/display/intel_modeset_verify.c @@ -246,7 +246,7 @@ void intel_modeset_verify_crtc(struct intel_atomic_state *state, intel_wm_state_verify(state, crtc); verify_connector_state(state, crtc); verify_crtc_state(state, crtc); - intel_shared_dpll_state_verify(state, crtc); + intel_dpll_state_verify(state, crtc); intel_mpllb_state_verify(state, crtc); intel_cx0pll_state_verify(state, crtc); } @@ -255,5 +255,5 @@ void intel_modeset_verify_disabled(struct intel_atomic_state *state) { verify_encoder_state(state); verify_connector_state(state, NULL); - intel_shared_dpll_verify_disabled(state); + intel_dpll_global_verify_disabled(state); } diff --git a/drivers/gpu/drm/i915/display/intel_pch_display.c b/drivers/gpu/drm/i915/display/intel_pch_display.c index 57303ecb77ad..aa39d0fb1e23 100644 --- a/drivers/gpu/drm/i915/display/intel_pch_display.c +++ b/drivers/gpu/drm/i915/display/intel_pch_display.c @@ -255,7 +255,7 @@ static void ilk_enable_pch_transcoder(const struct intel_crtc_state *crtc_state) u32 val, pipeconf_val; /* Make sure PCH DPLL is enabled */ - assert_shared_dpll_enabled(display, crtc_state->dpll_global); + assert_dpll_global_enabled(display, crtc_state->dpll_global); /* FDI must be feeding us bits for PCH ports */ assert_fdi_tx_enabled(display, pipe); @@ -388,7 +388,7 @@ void ilk_pch_enable(struct intel_atomic_state *state, temp |= TRANS_DPLL_ENABLE(pipe); sel = TRANS_DPLLB_SEL(pipe); if (crtc_state->dpll_global == - intel_get_shared_dpll_by_id(display, DPLL_ID_PCH_PLL_B)) + intel_get_dpll_global_by_id(display, DPLL_ID_PCH_PLL_B)) temp |= sel; else temp &= ~sel; @@ -400,11 +400,11 @@ void ilk_pch_enable(struct intel_atomic_state *state, * transcoder, and we actually should do this to not upset any PCH * transcoder that already use the clock when we share it. * - * Note that enable_shared_dpll tries to do the right thing, but - * get_shared_dpll unconditionally resets the pll - we need that + * Note that enable_dpll_global tries to do the right thing, but + * get_dpll_global unconditionally resets the pll - we need that * to have the right LVDS enable sequence. */ - intel_enable_shared_dpll(crtc_state); + intel_enable_dpll_global(crtc_state); /* set transcoder timing, panel must allow it */ assert_pps_unlocked(display, pipe); @@ -479,7 +479,7 @@ void ilk_pch_post_disable(struct intel_atomic_state *state, ilk_fdi_pll_disable(crtc); - intel_disable_shared_dpll(old_crtc_state); + intel_disable_dpll_global(old_crtc_state); } static void ilk_pch_clock_get(struct intel_crtc_state *crtc_state) @@ -536,7 +536,7 @@ void ilk_pch_get_config(struct intel_crtc_state *crtc_state) pll_id = DPLL_ID_PCH_PLL_A; } - crtc_state->dpll_global = intel_get_shared_dpll_by_id(display, pll_id); + crtc_state->dpll_global = intel_get_dpll_global_by_id(display, pll_id); pll = crtc_state->dpll_global; pll_active = intel_dpll_get_hw_state(display, pll, From patchwork Wed Apr 2 08:31:54 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Kandpal, Suraj" X-Patchwork-Id: 14035638 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 1389EC3601C for ; Wed, 2 Apr 2025 08:32:17 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 9B03D10E6EB; Wed, 2 Apr 2025 08:32:16 +0000 (UTC) Authentication-Results: gabe.freedesktop.org; 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a="44828688" X-IronPort-AV: E=Sophos;i="6.14,295,1736841600"; d="scan'208";a="44828688" Received: from fmviesa007.fm.intel.com ([10.60.135.147]) by orvoesa111.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 02 Apr 2025 01:32:16 -0700 X-CSE-ConnectionGUID: ILr/TmWoTDmsybWJwAS1IQ== X-CSE-MsgGUID: z5/CZW4BT7eqsevZR+B2Aw== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.14,295,1736841600"; d="scan'208";a="126612368" Received: from kandpal-x299-ud4-pro.iind.intel.com ([10.190.239.10]) by fmviesa007.fm.intel.com with ESMTP; 02 Apr 2025 01:32:13 -0700 From: Suraj Kandpal To: intel-xe@lists.freedesktop.org, intel-gfx@lists.freedesktop.org Cc: ankit.k.nautiyal@intel.com, uma.shankar@intel.com, jani.nikula@intel.com, mika.kahola@intel.com, ville.syrjala@intel.com, Suraj Kandpal Subject: [PATCH 06/16] drm/i915/dpll: Rename crtc_get_shared_dpll Date: Wed, 2 Apr 2025 14:01:54 +0530 Message-Id: <20250402083204.1523470-7-suraj.kandpal@intel.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20250402083204.1523470-1-suraj.kandpal@intel.com> References: <20250402083204.1523470-1-suraj.kandpal@intel.com> MIME-Version: 1.0 X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" Rename crtc_get_shared_dpll to take into the individual PLL framework which came in at DISPLAY_VER >= 14. --v2 -Change naming to dpll_global to keep consistency with rest of the naming Signed-off-by: Suraj Kandpal --- drivers/gpu/drm/i915/display/intel_display.c | 2 +- drivers/gpu/drm/i915/display/intel_dpll.c | 16 ++++++++-------- drivers/gpu/drm/i915/display/intel_dpll.h | 2 +- 3 files changed, 10 insertions(+), 10 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c index 904b9544515b..0c77fb02c565 100644 --- a/drivers/gpu/drm/i915/display/intel_display.c +++ b/drivers/gpu/drm/i915/display/intel_display.c @@ -4222,7 +4222,7 @@ static int intel_crtc_atomic_check(struct intel_atomic_state *state, crtc_state->update_wm_post = true; if (intel_crtc_needs_modeset(crtc_state)) { - ret = intel_dpll_crtc_get_shared_dpll(state, crtc); + ret = intel_dpll_crtc_get_dpll_global(state, crtc); if (ret) return ret; } diff --git a/drivers/gpu/drm/i915/display/intel_dpll.c b/drivers/gpu/drm/i915/display/intel_dpll.c index 04fb76a399ab..eac588566d7c 100644 --- a/drivers/gpu/drm/i915/display/intel_dpll.c +++ b/drivers/gpu/drm/i915/display/intel_dpll.c @@ -27,7 +27,7 @@ struct intel_dpll_funcs { int (*crtc_compute_clock)(struct intel_atomic_state *state, struct intel_crtc *crtc); - int (*crtc_get_shared_dpll)(struct intel_atomic_state *state, + int (*crtc_get_dpll_global)(struct intel_atomic_state *state, struct intel_crtc *crtc); }; @@ -1177,7 +1177,7 @@ static int hsw_crtc_compute_clock(struct intel_atomic_state *state, return 0; } -static int hsw_crtc_get_shared_dpll(struct intel_atomic_state *state, +static int hsw_crtc_get_dpll_global(struct intel_atomic_state *state, struct intel_crtc *crtc) { struct intel_display *display = to_intel_display(state); @@ -1407,7 +1407,7 @@ static int ilk_crtc_compute_clock(struct intel_atomic_state *state, return ret; } -static int ilk_crtc_get_shared_dpll(struct intel_atomic_state *state, +static int ilk_crtc_get_dpll_global(struct intel_atomic_state *state, struct intel_crtc *crtc) { struct intel_crtc_state *crtc_state = @@ -1703,12 +1703,12 @@ static const struct intel_dpll_funcs dg2_dpll_funcs = { static const struct intel_dpll_funcs hsw_dpll_funcs = { .crtc_compute_clock = hsw_crtc_compute_clock, - .crtc_get_shared_dpll = hsw_crtc_get_shared_dpll, + .crtc_get_dpll_global = hsw_crtc_get_dpll_global, }; static const struct intel_dpll_funcs ilk_dpll_funcs = { .crtc_compute_clock = ilk_crtc_compute_clock, - .crtc_get_shared_dpll = ilk_crtc_get_shared_dpll, + .crtc_get_dpll_global = ilk_crtc_get_dpll_global, }; static const struct intel_dpll_funcs chv_dpll_funcs = { @@ -1761,7 +1761,7 @@ int intel_dpll_crtc_compute_clock(struct intel_atomic_state *state, return 0; } -int intel_dpll_crtc_get_shared_dpll(struct intel_atomic_state *state, +int intel_dpll_crtc_get_dpll_global(struct intel_atomic_state *state, struct intel_crtc *crtc) { struct intel_display *display = to_intel_display(state); @@ -1775,10 +1775,10 @@ int intel_dpll_crtc_get_shared_dpll(struct intel_atomic_state *state, if (!crtc_state->hw.enable || crtc_state->dpll_global) return 0; - if (!display->funcs.dpll->crtc_get_shared_dpll) + if (!display->funcs.dpll->crtc_get_dpll_global) return 0; - ret = display->funcs.dpll->crtc_get_shared_dpll(state, crtc); + ret = display->funcs.dpll->crtc_get_dpll_global(state, crtc); if (ret) { drm_dbg_kms(display->drm, "[CRTC:%d:%s] Couldn't get a shared DPLL\n", crtc->base.base.id, crtc->base.name); diff --git a/drivers/gpu/drm/i915/display/intel_dpll.h b/drivers/gpu/drm/i915/display/intel_dpll.h index 280e90a57c87..81c9249f293b 100644 --- a/drivers/gpu/drm/i915/display/intel_dpll.h +++ b/drivers/gpu/drm/i915/display/intel_dpll.h @@ -19,7 +19,7 @@ struct intel_dpll_hw_state; void intel_dpll_init_clock_hook(struct intel_display *display); int intel_dpll_crtc_compute_clock(struct intel_atomic_state *state, struct intel_crtc *crtc); -int intel_dpll_crtc_get_shared_dpll(struct intel_atomic_state *state, +int intel_dpll_crtc_get_dpll_global(struct intel_atomic_state *state, struct intel_crtc *crtc); int i9xx_calc_dpll_params(int refclk, struct dpll *clock); u32 i9xx_dpll_compute_fp(const struct dpll *dpll); From patchwork Wed Apr 2 08:31:55 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Kandpal, Suraj" X-Patchwork-Id: 14035640 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 3CE96C3601C for ; Wed, 2 Apr 2025 08:32:20 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id C5ACB10E6E9; Wed, 2 Apr 2025 08:32:19 +0000 (UTC) Authentication-Results: gabe.freedesktop.org; dkim=pass (2048-bit key; unprotected) header.d=intel.com header.i=@intel.com header.b="hpWaITcY"; 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d="scan'208";a="44828696" Received: from fmviesa007.fm.intel.com ([10.60.135.147]) by orvoesa111.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 02 Apr 2025 01:32:19 -0700 X-CSE-ConnectionGUID: NmNJ0lT9SDaNnZUPunioQw== X-CSE-MsgGUID: xwjSf8scRAe1vbc/d7VQCw== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.14,295,1736841600"; d="scan'208";a="126612406" Received: from kandpal-x299-ud4-pro.iind.intel.com ([10.190.239.10]) by fmviesa007.fm.intel.com with ESMTP; 02 Apr 2025 01:32:15 -0700 From: Suraj Kandpal To: intel-xe@lists.freedesktop.org, intel-gfx@lists.freedesktop.org Cc: ankit.k.nautiyal@intel.com, uma.shankar@intel.com, jani.nikula@intel.com, mika.kahola@intel.com, ville.syrjala@intel.com, Suraj Kandpal Subject: [PATCH 07/16] drm/i915/dpll: Change argument for enable hook in intel_global_dpll_funcs Date: Wed, 2 Apr 2025 14:01:55 +0530 Message-Id: <20250402083204.1523470-8-suraj.kandpal@intel.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20250402083204.1523470-1-suraj.kandpal@intel.com> References: <20250402083204.1523470-1-suraj.kandpal@intel.com> MIME-Version: 1.0 X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" Change the arguments for enable hook in intel_global_dpll_funcs to only accept crtc_state. This is because we really don't need those extra arguments everything can be derived from crtc_state and we need both intel_encoder and crtc_state for PLL enablement when DISPLAY_VER() >= 14 which requires us to pass this crtc state if we want the future PLL framework to fit into the existing one and not use the intel_ddi hooks --v2 -Rename global_dpll to dpll_global to keep consistency with filename [Jani/Ville] Signed-off-by: Suraj Kandpal --- drivers/gpu/drm/i915/display/intel_dpll_mgr.c | 100 ++++++++++-------- 1 file changed, 54 insertions(+), 46 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c index e6546d735799..869118f868f6 100644 --- a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c +++ b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c @@ -66,9 +66,8 @@ struct intel_dpll_global_funcs { * Hook for enabling the pll, called from intel_enable_dpll_global() if * the pll is not already enabled. */ - void (*enable)(struct intel_display *display, - struct intel_dpll_global *pll, - const struct intel_dpll_hw_state *dpll_hw_state); + void (*enable)(const struct intel_crtc_state *state, + struct intel_encoder *encoder); /* * Hook for disabling the pll, called from intel_disable_dpll_global() @@ -226,13 +225,15 @@ intel_tc_pll_enable_reg(struct intel_display *display, return MG_PLL_ENABLE(tc_port); } -static void _intel_enable_shared_dpll(struct intel_display *display, - struct intel_dpll_global *pll) +static void _intel_enable_shared_dpll(const struct intel_crtc_state *crtc_state) { + struct intel_display *display = to_intel_display(crtc_state); + struct intel_dpll_global *pll = crtc_state->dpll_global; + if (pll->info->power_domain) pll->wakeref = intel_display_power_get(display, pll->info->power_domain); - pll->info->funcs->enable(display, pll, &pll->state.hw_state); + pll->info->funcs->enable(crtc_state, NULL); pll->on = true; } @@ -286,7 +287,7 @@ void intel_enable_dpll_global(const struct intel_crtc_state *crtc_state) drm_dbg_kms(display->drm, "enabling %s\n", pll->info->name); - _intel_enable_shared_dpll(display, pll); + _intel_enable_shared_dpll(crtc_state); out: mutex_unlock(&display->dpll.lock); @@ -558,11 +559,12 @@ static void ibx_assert_pch_refclk_enabled(struct intel_display *display) "PCH refclk assertion failure, should be active but is disabled\n"); } -static void ibx_pch_dpll_enable(struct intel_display *display, - struct intel_dpll_global *pll, - const struct intel_dpll_hw_state *dpll_hw_state) +static void ibx_pch_dpll_enable(const struct intel_crtc_state *crtc_state, + struct intel_encoder *encoder) { - const struct i9xx_dpll_hw_state *hw_state = &dpll_hw_state->i9xx; + struct intel_display *display = to_intel_display(crtc_state); + struct intel_dpll_global *pll = crtc_state->dpll_global; + const struct i9xx_dpll_hw_state *hw_state = &crtc_state->dpll_hw_state.i9xx; const enum intel_dpll_id id = pll->info->id; /* PCH refclock must be enabled first */ @@ -689,11 +691,12 @@ static const struct intel_dpll_mgr pch_pll_mgr = { .compare_hw_state = ibx_compare_hw_state, }; -static void hsw_ddi_wrpll_enable(struct intel_display *display, - struct intel_dpll_global *pll, - const struct intel_dpll_hw_state *dpll_hw_state) +static void hsw_ddi_wrpll_enable(const struct intel_crtc_state *crtc_state, + struct intel_encoder *encoder) { - const struct hsw_dpll_hw_state *hw_state = &dpll_hw_state->hsw; + struct intel_display *display = to_intel_display(crtc_state); + struct intel_dpll_global *pll = crtc_state->dpll_global; + const struct hsw_dpll_hw_state *hw_state = &crtc_state->dpll_hw_state.hsw; const enum intel_dpll_id id = pll->info->id; intel_de_write(display, WRPLL_CTL(id), hw_state->wrpll); @@ -701,11 +704,11 @@ static void hsw_ddi_wrpll_enable(struct intel_display *display, udelay(20); } -static void hsw_ddi_spll_enable(struct intel_display *display, - struct intel_dpll_global *pll, - const struct intel_dpll_hw_state *dpll_hw_state) +static void hsw_ddi_spll_enable(const struct intel_crtc_state *crtc_state, + struct intel_encoder *encoder) { - const struct hsw_dpll_hw_state *hw_state = &dpll_hw_state->hsw; + struct intel_display *display = to_intel_display(crtc_state); + const struct hsw_dpll_hw_state *hw_state = &crtc_state->dpll_hw_state.hsw; intel_de_write(display, SPLL_CTL, hw_state->spll); intel_de_posting_read(display, SPLL_CTL); @@ -1282,9 +1285,8 @@ static const struct intel_dpll_global_funcs hsw_ddi_spll_funcs = { .get_freq = hsw_ddi_spll_get_freq, }; -static void hsw_ddi_lcpll_enable(struct intel_display *display, - struct intel_dpll_global *pll, - const struct intel_dpll_hw_state *hw_state) +static void hsw_ddi_lcpll_enable(const struct intel_crtc_state *crtc_state, + struct intel_encoder *encoder) { } @@ -1375,11 +1377,12 @@ static void skl_ddi_pll_write_ctrl1(struct intel_display *display, intel_de_posting_read(display, DPLL_CTRL1); } -static void skl_ddi_pll_enable(struct intel_display *display, - struct intel_dpll_global *pll, - const struct intel_dpll_hw_state *dpll_hw_state) +static void skl_ddi_pll_enable(const struct intel_crtc_state *crtc_state, + struct intel_encoder *encoder) { - const struct skl_dpll_hw_state *hw_state = &dpll_hw_state->skl; + struct intel_display *display = to_intel_display(crtc_state); + struct intel_dpll_global *pll = crtc_state->dpll_global; + const struct skl_dpll_hw_state *hw_state = &crtc_state->dpll_hw_state.skl; const struct skl_dpll_regs *regs = skl_dpll_regs; const enum intel_dpll_id id = pll->info->id; @@ -1397,11 +1400,12 @@ static void skl_ddi_pll_enable(struct intel_display *display, drm_err(display->drm, "DPLL %d not locked\n", id); } -static void skl_ddi_dpll0_enable(struct intel_display *display, - struct intel_dpll_global *pll, - const struct intel_dpll_hw_state *dpll_hw_state) +static void skl_ddi_dpll0_enable(const struct intel_crtc_state *crtc_state, + struct intel_encoder *encoder) { - const struct skl_dpll_hw_state *hw_state = &dpll_hw_state->skl; + struct intel_display *display = to_intel_display(crtc_state); + struct intel_dpll_global *pll = crtc_state->dpll_global; + const struct skl_dpll_hw_state *hw_state = &crtc_state->dpll_hw_state.skl; skl_ddi_pll_write_ctrl1(display, pll, hw_state); } @@ -2035,11 +2039,12 @@ static const struct intel_dpll_mgr skl_pll_mgr = { .compare_hw_state = skl_compare_hw_state, }; -static void bxt_ddi_pll_enable(struct intel_display *display, - struct intel_dpll_global *pll, - const struct intel_dpll_hw_state *dpll_hw_state) +static void bxt_ddi_pll_enable(const struct intel_crtc_state *crtc_state, + struct intel_encoder *encoder) { - const struct bxt_dpll_hw_state *hw_state = &dpll_hw_state->bxt; + struct intel_display *display = to_intel_display(crtc_state); + struct intel_dpll_global *pll = crtc_state->dpll_global; + const struct bxt_dpll_hw_state *hw_state = &crtc_state->dpll_hw_state.bxt; enum port port = (enum port)pll->info->id; /* 1:1 port->PLL mapping */ enum dpio_phy phy = DPIO_PHY0; enum dpio_channel ch = DPIO_CH0; @@ -3954,11 +3959,12 @@ static void adlp_cmtg_clock_gating_wa(struct intel_display *display, struct inte drm_dbg_kms(display->drm, "Unexpected flags in TRANS_CMTG_CHICKEN: %08x\n", val); } -static void combo_pll_enable(struct intel_display *display, - struct intel_dpll_global *pll, - const struct intel_dpll_hw_state *dpll_hw_state) +static void combo_pll_enable(const struct intel_crtc_state *crtc_state, + struct intel_encoder *encoder) { - const struct icl_dpll_hw_state *hw_state = &dpll_hw_state->icl; + struct intel_display *display = to_intel_display(crtc_state); + struct intel_dpll_global *pll = crtc_state->dpll_global; + const struct icl_dpll_hw_state *hw_state = &crtc_state->dpll_hw_state.icl; i915_reg_t enable_reg = intel_combo_pll_enable_reg(display, pll); icl_pll_power_enable(display, pll, enable_reg); @@ -3978,11 +3984,12 @@ static void combo_pll_enable(struct intel_display *display, /* DVFS post sequence would be here. See the comment above. */ } -static void tbt_pll_enable(struct intel_display *display, - struct intel_dpll_global *pll, - const struct intel_dpll_hw_state *dpll_hw_state) +static void tbt_pll_enable(const struct intel_crtc_state *crtc_state, + struct intel_encoder *encoder) { - const struct icl_dpll_hw_state *hw_state = &dpll_hw_state->icl; + struct intel_display *display = to_intel_display(crtc_state); + struct intel_dpll_global *pll = crtc_state->dpll_global; + const struct icl_dpll_hw_state *hw_state = &crtc_state->dpll_hw_state.icl; icl_pll_power_enable(display, pll, TBT_PLL_ENABLE); @@ -3999,11 +4006,12 @@ static void tbt_pll_enable(struct intel_display *display, /* DVFS post sequence would be here. See the comment above. */ } -static void mg_pll_enable(struct intel_display *display, - struct intel_dpll_global *pll, - const struct intel_dpll_hw_state *dpll_hw_state) +static void mg_pll_enable(const struct intel_crtc_state *crtc_state, + struct intel_encoder *encoder) { - const struct icl_dpll_hw_state *hw_state = &dpll_hw_state->icl; + struct intel_display *display = to_intel_display(crtc_state); + struct intel_dpll_global *pll = crtc_state->dpll_global; + const struct icl_dpll_hw_state *hw_state = &crtc_state->dpll_hw_state.icl; i915_reg_t enable_reg = intel_tc_pll_enable_reg(display, pll); icl_pll_power_enable(display, pll, enable_reg); From patchwork Wed Apr 2 08:31:56 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Kandpal, Suraj" X-Patchwork-Id: 14035641 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 79AFEC3601A for ; Wed, 2 Apr 2025 08:32:23 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 0CE6610E6F7; Wed, 2 Apr 2025 08:32:23 +0000 (UTC) Authentication-Results: gabe.freedesktop.org; dkim=pass (2048-bit key; unprotected) header.d=intel.com header.i=@intel.com header.b="JhRI+Lpb"; dkim-atps=neutral Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.19]) by gabe.freedesktop.org (Postfix) with ESMTPS id 77B9C10E6F4; Wed, 2 Apr 2025 08:32:21 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1743582742; x=1775118742; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=sgeJ/jpS+8Gg1DuhanW5jWtA0RIhb37mk9c85Xfcw1Q=; b=JhRI+Lpb+1qdEcxdJMOYZPPHnhinrhTSQCfm9+WrrCnKgtgHGh2LKiNT /sa2fE7CJ/8Wkfho5w607mCLz1QOO9e04kv5stsDPKZ6FGKbCvGrQDjLC rdMYFen1CowFY/HIDP1dBtI/E+66NCqxnxzYA8bzzfY+y1zShqYRHh3pa m4QHZXhKLPg4h6YsHgKQiD/Qtvzm5ZP8MqrkAKNe2L2ZCK6EfBsWWveHK ygczcR0Dy2wEUKRmDk/N/72OehG2bzNdRzmAl8nmuVNs/whpd34HTQmUN Cvgfu58xzc547k5k9BMBjwcQyqKhny7BQ+IbrhfuUXIQT6S+NhkwkrdZd Q==; X-CSE-ConnectionGUID: yh8zDq45RsurGxXvzPVrzQ== X-CSE-MsgGUID: IgVlRr/XQIGLQXPYHRy9SQ== X-IronPort-AV: E=McAfee;i="6700,10204,11391"; a="44828705" X-IronPort-AV: E=Sophos;i="6.14,295,1736841600"; d="scan'208";a="44828705" Received: from fmviesa007.fm.intel.com ([10.60.135.147]) by orvoesa111.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 02 Apr 2025 01:32:22 -0700 X-CSE-ConnectionGUID: BcXvdNltRGqz9xBfGYO/aQ== X-CSE-MsgGUID: on8efsVfTsaGJfcmvcj+og== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.14,295,1736841600"; d="scan'208";a="126612423" Received: from kandpal-x299-ud4-pro.iind.intel.com ([10.190.239.10]) by fmviesa007.fm.intel.com with ESMTP; 02 Apr 2025 01:32:18 -0700 From: Suraj Kandpal To: intel-xe@lists.freedesktop.org, intel-gfx@lists.freedesktop.org Cc: ankit.k.nautiyal@intel.com, uma.shankar@intel.com, jani.nikula@intel.com, mika.kahola@intel.com, ville.syrjala@intel.com, Suraj Kandpal Subject: [PATCH 08/16] drm/i915/drm: Rename disable hook in intel_dpll_global_func Date: Wed, 2 Apr 2025 14:01:56 +0530 Message-Id: <20250402083204.1523470-9-suraj.kandpal@intel.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20250402083204.1523470-1-suraj.kandpal@intel.com> References: <20250402083204.1523470-1-suraj.kandpal@intel.com> MIME-Version: 1.0 X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" Rename the disable hook to disable_shared_dpll since it will be used only to disable shared dpll and not individual PLL going forward. Signed-off-by: Suraj Kandpal --- drivers/gpu/drm/i915/display/intel_dpll_mgr.c | 30 +++++++++---------- 1 file changed, 15 insertions(+), 15 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c index 869118f868f6..48efc25e18dc 100644 --- a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c +++ b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c @@ -70,12 +70,12 @@ struct intel_dpll_global_funcs { struct intel_encoder *encoder); /* - * Hook for disabling the pll, called from intel_disable_dpll_global() + * Hook for disabling the shared pll, called from intel_disable_global_dpll() * only when it is safe to disable the pll, i.e., there are no more * tracked users for it. */ - void (*disable)(struct intel_display *display, - struct intel_dpll_global *pll); + void (*shared_dpll_disable)(struct intel_display *display, + struct intel_dpll_global *pll); /* * Hook for reading the values currently programmed to the DPLL @@ -240,7 +240,7 @@ static void _intel_enable_shared_dpll(const struct intel_crtc_state *crtc_state) static void _intel_disable_shared_dpll(struct intel_display *display, struct intel_dpll_global *pll) { - pll->info->funcs->disable(display, pll); + pll->info->funcs->shared_dpll_disable(display, pll); pll->on = false; if (pll->info->power_domain) @@ -672,7 +672,7 @@ static bool ibx_compare_hw_state(const struct intel_dpll_hw_state *_a, static const struct intel_dpll_global_funcs ibx_pch_dpll_funcs = { .enable = ibx_pch_dpll_enable, - .disable = ibx_pch_dpll_disable, + .shared_dpll_disable = ibx_pch_dpll_disable, .get_hw_state = ibx_pch_dpll_get_hw_state, }; @@ -1273,14 +1273,14 @@ static bool hsw_compare_hw_state(const struct intel_dpll_hw_state *_a, static const struct intel_dpll_global_funcs hsw_ddi_wrpll_funcs = { .enable = hsw_ddi_wrpll_enable, - .disable = hsw_ddi_wrpll_disable, + .shared_dpll_disable = hsw_ddi_wrpll_disable, .get_hw_state = hsw_ddi_wrpll_get_hw_state, .get_freq = hsw_ddi_wrpll_get_freq, }; static const struct intel_dpll_global_funcs hsw_ddi_spll_funcs = { .enable = hsw_ddi_spll_enable, - .disable = hsw_ddi_spll_disable, + .shared_dpll_disable = hsw_ddi_spll_disable, .get_hw_state = hsw_ddi_spll_get_hw_state, .get_freq = hsw_ddi_spll_get_freq, }; @@ -1304,7 +1304,7 @@ static bool hsw_ddi_lcpll_get_hw_state(struct intel_display *display, static const struct intel_dpll_global_funcs hsw_ddi_lcpll_funcs = { .enable = hsw_ddi_lcpll_enable, - .disable = hsw_ddi_lcpll_disable, + .shared_dpll_disable = hsw_ddi_lcpll_disable, .get_hw_state = hsw_ddi_lcpll_get_hw_state, .get_freq = hsw_ddi_lcpll_get_freq, }; @@ -2008,14 +2008,14 @@ static bool skl_compare_hw_state(const struct intel_dpll_hw_state *_a, static const struct intel_dpll_global_funcs skl_ddi_pll_funcs = { .enable = skl_ddi_pll_enable, - .disable = skl_ddi_pll_disable, + .shared_dpll_disable = skl_ddi_pll_disable, .get_hw_state = skl_ddi_pll_get_hw_state, .get_freq = skl_ddi_pll_get_freq, }; static const struct intel_dpll_global_funcs skl_ddi_dpll0_funcs = { .enable = skl_ddi_dpll0_enable, - .disable = skl_ddi_dpll0_disable, + .shared_dpll_disable = skl_ddi_dpll0_disable, .get_hw_state = skl_ddi_dpll0_get_hw_state, .get_freq = skl_ddi_pll_get_freq, }; @@ -2491,7 +2491,7 @@ static bool bxt_compare_hw_state(const struct intel_dpll_hw_state *_a, static const struct intel_dpll_global_funcs bxt_ddi_pll_funcs = { .enable = bxt_ddi_pll_enable, - .disable = bxt_ddi_pll_disable, + .shared_dpll_disable = bxt_ddi_pll_disable, .get_hw_state = bxt_ddi_pll_get_hw_state, .get_freq = bxt_ddi_pll_get_freq, }; @@ -4139,21 +4139,21 @@ static bool icl_compare_hw_state(const struct intel_dpll_hw_state *_a, static const struct intel_dpll_global_funcs combo_pll_funcs = { .enable = combo_pll_enable, - .disable = combo_pll_disable, + .shared_dpll_disable = combo_pll_disable, .get_hw_state = combo_pll_get_hw_state, .get_freq = icl_ddi_combo_pll_get_freq, }; static const struct intel_dpll_global_funcs tbt_pll_funcs = { .enable = tbt_pll_enable, - .disable = tbt_pll_disable, + .shared_dpll_disable = tbt_pll_disable, .get_hw_state = tbt_pll_get_hw_state, .get_freq = icl_ddi_tbt_pll_get_freq, }; static const struct intel_dpll_global_funcs mg_pll_funcs = { .enable = mg_pll_enable, - .disable = mg_pll_disable, + .shared_dpll_disable = mg_pll_disable, .get_hw_state = mg_pll_get_hw_state, .get_freq = icl_ddi_mg_pll_get_freq, }; @@ -4201,7 +4201,7 @@ static const struct intel_dpll_mgr ehl_pll_mgr = { static const struct intel_dpll_global_funcs dkl_pll_funcs = { .enable = mg_pll_enable, - .disable = mg_pll_disable, + .shared_dpll_disable = mg_pll_disable, .get_hw_state = dkl_pll_get_hw_state, .get_freq = icl_ddi_mg_pll_get_freq, }; From patchwork Wed Apr 2 08:31:57 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Kandpal, Suraj" X-Patchwork-Id: 14035642 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 8BB7BC36014 for ; Wed, 2 Apr 2025 08:32:25 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 1DEF410E6FE; Wed, 2 Apr 2025 08:32:25 +0000 (UTC) Authentication-Results: gabe.freedesktop.org; dkim=pass (2048-bit key; unprotected) header.d=intel.com header.i=@intel.com header.b="bIpDxuFK"; dkim-atps=neutral Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.19]) by gabe.freedesktop.org (Postfix) with ESMTPS id DDB7D10E6F8; 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02 Apr 2025 01:32:24 -0700 X-CSE-ConnectionGUID: RIoFwmCISsaUz8exLBTEyA== X-CSE-MsgGUID: Znugq25HR36+2SslywYNoA== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.14,295,1736841600"; d="scan'208";a="126612433" Received: from kandpal-x299-ud4-pro.iind.intel.com ([10.190.239.10]) by fmviesa007.fm.intel.com with ESMTP; 02 Apr 2025 01:32:21 -0700 From: Suraj Kandpal To: intel-xe@lists.freedesktop.org, intel-gfx@lists.freedesktop.org Cc: ankit.k.nautiyal@intel.com, uma.shankar@intel.com, jani.nikula@intel.com, mika.kahola@intel.com, ville.syrjala@intel.com, Suraj Kandpal Subject: [PATCH 09/16] drm/i915/dpll: Introduce new hook in intel_dpll_global_func Date: Wed, 2 Apr 2025 14:01:57 +0530 Message-Id: <20250402083204.1523470-10-suraj.kandpal@intel.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20250402083204.1523470-1-suraj.kandpal@intel.com> References: <20250402083204.1523470-1-suraj.kandpal@intel.com> MIME-Version: 1.0 X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" Introduce disable hook to disable individual dpll which is to be used by DISPLAY_VER() >= 14. --v2 -Rename intel_global_dpll to intel_dpll_global [Jani/Ville] Signed-off-by: Suraj Kandpal --- drivers/gpu/drm/i915/display/intel_dpll_mgr.c | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c index 48efc25e18dc..27181ddc4e0f 100644 --- a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c +++ b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c @@ -69,6 +69,12 @@ struct intel_dpll_global_funcs { void (*enable)(const struct intel_crtc_state *state, struct intel_encoder *encoder); + /* + * Hook for disabling the individual pll, used from DISPLAY_VER() >= 14 + */ + void (*disable)(struct intel_display *display, + struct intel_dpll_global *pll); + /* * Hook for disabling the shared pll, called from intel_disable_global_dpll() * only when it is safe to disable the pll, i.e., there are no more From patchwork Wed Apr 2 08:31:58 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Kandpal, Suraj" X-Patchwork-Id: 14035643 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 84DF2C3601A for ; Wed, 2 Apr 2025 08:32:28 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 0F15710E6FD; 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a="44828717" X-IronPort-AV: E=Sophos;i="6.14,295,1736841600"; d="scan'208";a="44828717" Received: from fmviesa007.fm.intel.com ([10.60.135.147]) by orvoesa111.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 02 Apr 2025 01:32:27 -0700 X-CSE-ConnectionGUID: s91JPY4OSzCTktIAFaVvDg== X-CSE-MsgGUID: 41n5IyiUTiqsPcSthQgjQw== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.14,295,1736841600"; d="scan'208";a="126612438" Received: from kandpal-x299-ud4-pro.iind.intel.com ([10.190.239.10]) by fmviesa007.fm.intel.com with ESMTP; 02 Apr 2025 01:32:24 -0700 From: Suraj Kandpal To: intel-xe@lists.freedesktop.org, intel-gfx@lists.freedesktop.org Cc: ankit.k.nautiyal@intel.com, uma.shankar@intel.com, jani.nikula@intel.com, mika.kahola@intel.com, ville.syrjala@intel.com, Suraj Kandpal Subject: [PATCH 10/16] drm/i915/dpll: Add intel_encoder argument to get_hw_state hook Date: Wed, 2 Apr 2025 14:01:58 +0530 Message-Id: <20250402083204.1523470-11-suraj.kandpal@intel.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20250402083204.1523470-1-suraj.kandpal@intel.com> References: <20250402083204.1523470-1-suraj.kandpal@intel.com> MIME-Version: 1.0 X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" Add intel_encoder argument in the get_hw_state hook as encoders and the data stored within them are essential to read the hw state starting DISPLAY_VER() >= 14. Signed-off-by: Suraj Kandpal --- drivers/gpu/drm/i915/display/intel_dpll_mgr.c | 38 ++++++++++++------- 1 file changed, 25 insertions(+), 13 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c index 27181ddc4e0f..287ad58dc95c 100644 --- a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c +++ b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c @@ -90,7 +90,8 @@ struct intel_dpll_global_funcs { */ bool (*get_hw_state)(struct intel_display *display, struct intel_dpll_global *pll, - struct intel_dpll_hw_state *dpll_hw_state); + struct intel_dpll_hw_state *dpll_hw_state, + struct intel_encoder *encoder); /* * Hook for calculating the pll's output frequency based on its passed @@ -531,7 +532,8 @@ void intel_dpll_swap_state(struct intel_atomic_state *state) static bool ibx_pch_dpll_get_hw_state(struct intel_display *display, struct intel_dpll_global *pll, - struct intel_dpll_hw_state *dpll_hw_state) + struct intel_dpll_hw_state *dpll_hw_state, + struct intel_encoder *encoder) { struct i9xx_dpll_hw_state *hw_state = &dpll_hw_state->i9xx; const enum intel_dpll_id id = pll->info->id; @@ -755,7 +757,8 @@ static void hsw_ddi_spll_disable(struct intel_display *display, static bool hsw_ddi_wrpll_get_hw_state(struct intel_display *display, struct intel_dpll_global *pll, - struct intel_dpll_hw_state *dpll_hw_state) + struct intel_dpll_hw_state *dpll_hw_state, + struct intel_encoder *encoder) { struct hsw_dpll_hw_state *hw_state = &dpll_hw_state->hsw; const enum intel_dpll_id id = pll->info->id; @@ -777,7 +780,8 @@ static bool hsw_ddi_wrpll_get_hw_state(struct intel_display *display, static bool hsw_ddi_spll_get_hw_state(struct intel_display *display, struct intel_dpll_global *pll, - struct intel_dpll_hw_state *dpll_hw_state) + struct intel_dpll_hw_state *dpll_hw_state, + struct intel_encoder *encoder) { struct hsw_dpll_hw_state *hw_state = &dpll_hw_state->hsw; intel_wakeref_t wakeref; @@ -1303,7 +1307,8 @@ static void hsw_ddi_lcpll_disable(struct intel_display *display, static bool hsw_ddi_lcpll_get_hw_state(struct intel_display *display, struct intel_dpll_global *pll, - struct intel_dpll_hw_state *dpll_hw_state) + struct intel_dpll_hw_state *dpll_hw_state, + struct intel_encoder *encoder) { return true; } @@ -1434,7 +1439,8 @@ static void skl_ddi_dpll0_disable(struct intel_display *display, static bool skl_ddi_pll_get_hw_state(struct intel_display *display, struct intel_dpll_global *pll, - struct intel_dpll_hw_state *dpll_hw_state) + struct intel_dpll_hw_state *dpll_hw_state, + struct intel_encoder *encoder) { struct skl_dpll_hw_state *hw_state = &dpll_hw_state->skl; const struct skl_dpll_regs *regs = skl_dpll_regs; @@ -1472,7 +1478,8 @@ static bool skl_ddi_pll_get_hw_state(struct intel_display *display, static bool skl_ddi_dpll0_get_hw_state(struct intel_display *display, struct intel_dpll_global *pll, - struct intel_dpll_hw_state *dpll_hw_state) + struct intel_dpll_hw_state *dpll_hw_state, + struct intel_encoder *encoder) { struct skl_dpll_hw_state *hw_state = &dpll_hw_state->skl; const struct skl_dpll_regs *regs = skl_dpll_regs; @@ -2170,7 +2177,8 @@ static void bxt_ddi_pll_disable(struct intel_display *display, static bool bxt_ddi_pll_get_hw_state(struct intel_display *display, struct intel_dpll_global *pll, - struct intel_dpll_hw_state *dpll_hw_state) + struct intel_dpll_hw_state *dpll_hw_state, + struct intel_encoder *encoder) { struct bxt_dpll_hw_state *hw_state = &dpll_hw_state->bxt; enum port port = (enum port)pll->info->id; /* 1:1 port->PLL mapping */ @@ -3551,7 +3559,8 @@ static void icl_put_dplls(struct intel_atomic_state *state, static bool mg_pll_get_hw_state(struct intel_display *display, struct intel_dpll_global *pll, - struct intel_dpll_hw_state *dpll_hw_state) + struct intel_dpll_hw_state *dpll_hw_state, + struct intel_encoder *encoder) { struct icl_dpll_hw_state *hw_state = &dpll_hw_state->icl; const enum intel_dpll_id id = pll->info->id; @@ -3618,7 +3627,8 @@ static bool mg_pll_get_hw_state(struct intel_display *display, static bool dkl_pll_get_hw_state(struct intel_display *display, struct intel_dpll_global *pll, - struct intel_dpll_hw_state *dpll_hw_state) + struct intel_dpll_hw_state *dpll_hw_state, + struct intel_encoder *encoder) { struct icl_dpll_hw_state *hw_state = &dpll_hw_state->icl; const enum intel_dpll_id id = pll->info->id; @@ -3751,7 +3761,8 @@ static bool icl_pll_get_hw_state(struct intel_display *display, static bool combo_pll_get_hw_state(struct intel_display *display, struct intel_dpll_global *pll, - struct intel_dpll_hw_state *dpll_hw_state) + struct intel_dpll_hw_state *dpll_hw_state, + struct intel_encoder *encoder) { i915_reg_t enable_reg = intel_combo_pll_enable_reg(display, pll); @@ -3760,7 +3771,8 @@ static bool combo_pll_get_hw_state(struct intel_display *display, static bool tbt_pll_get_hw_state(struct intel_display *display, struct intel_dpll_global *pll, - struct intel_dpll_hw_state *dpll_hw_state) + struct intel_dpll_hw_state *dpll_hw_state, + struct intel_encoder *encoder) { return icl_pll_get_hw_state(display, pll, dpll_hw_state, TBT_PLL_ENABLE); } @@ -4518,7 +4530,7 @@ bool intel_dpll_get_hw_state(struct intel_display *display, struct intel_dpll_global *pll, struct intel_dpll_hw_state *dpll_hw_state) { - return pll->info->funcs->get_hw_state(display, pll, dpll_hw_state); + return pll->info->funcs->get_hw_state(display, pll, dpll_hw_state, NULL); } static void readout_dpll_hw_state(struct intel_display *display, From patchwork Wed Apr 2 08:31:59 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Kandpal, Suraj" X-Patchwork-Id: 14035644 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id B1D27C28B20 for ; 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X-CSE-ConnectionGUID: bzwlwwtCQZGOVF/NZplTug== X-CSE-MsgGUID: kyz6EDKSQHuzUJawaxgGDg== X-IronPort-AV: E=McAfee;i="6700,10204,11391"; a="44828725" X-IronPort-AV: E=Sophos;i="6.14,295,1736841600"; d="scan'208";a="44828725" Received: from fmviesa007.fm.intel.com ([10.60.135.147]) by orvoesa111.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 02 Apr 2025 01:32:30 -0700 X-CSE-ConnectionGUID: lcMaggfDTeO9dovQnXkjAQ== X-CSE-MsgGUID: /TimetrrQOmRbCm72FNl0g== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.14,295,1736841600"; d="scan'208";a="126612448" Received: from kandpal-x299-ud4-pro.iind.intel.com ([10.190.239.10]) by fmviesa007.fm.intel.com with ESMTP; 02 Apr 2025 01:32:26 -0700 From: Suraj Kandpal To: intel-xe@lists.freedesktop.org, intel-gfx@lists.freedesktop.org Cc: ankit.k.nautiyal@intel.com, uma.shankar@intel.com, jani.nikula@intel.com, mika.kahola@intel.com, ville.syrjala@intel.com, Suraj Kandpal Subject: [PATCH 11/16] drm/i915/dpll: Change arguments for get_freq hook Date: Wed, 2 Apr 2025 14:01:59 +0530 Message-Id: <20250402083204.1523470-12-suraj.kandpal@intel.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20250402083204.1523470-1-suraj.kandpal@intel.com> References: <20250402083204.1523470-1-suraj.kandpal@intel.com> MIME-Version: 1.0 X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" Change the arguments for get_freq hook in intel_dpll_global_funcs to use only intel_crtc_state and intel_encoder since that all we need and the rest can be derived from the above two. Signed-off-by: Suraj Kandpal --- drivers/gpu/drm/i915/display/intel_ddi.c | 6 +- drivers/gpu/drm/i915/display/intel_dpll_mgr.c | 107 +++++++++--------- drivers/gpu/drm/i915/display/intel_dpll_mgr.h | 5 +- 3 files changed, 57 insertions(+), 61 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c b/drivers/gpu/drm/i915/display/intel_ddi.c index 3fe330bf2636..2f1f7dd20e80 100644 --- a/drivers/gpu/drm/i915/display/intel_ddi.c +++ b/drivers/gpu/drm/i915/display/intel_ddi.c @@ -4200,8 +4200,7 @@ void intel_ddi_get_clock(struct intel_encoder *encoder, icl_set_active_port_dpll(crtc_state, port_dpll_id); - crtc_state->port_clock = intel_dpll_get_freq(display, crtc_state->dpll_global, - &crtc_state->dpll_hw_state); + crtc_state->port_clock = intel_dpll_get_freq(crtc_state, encoder); } static void mtl_ddi_get_config(struct intel_encoder *encoder, @@ -4313,8 +4312,7 @@ static void icl_ddi_tc_get_clock(struct intel_encoder *encoder, if (icl_ddi_tc_pll_is_tbt(crtc_state->dpll_global)) crtc_state->port_clock = icl_calc_tbt_pll_link(display, encoder->port); else - crtc_state->port_clock = intel_dpll_get_freq(display, crtc_state->dpll_global, - &crtc_state->dpll_hw_state); + crtc_state->port_clock = intel_dpll_get_freq(crtc_state, encoder); } static void icl_ddi_tc_get_config(struct intel_encoder *encoder, diff --git a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c index 287ad58dc95c..8b4c35245190 100644 --- a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c +++ b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c @@ -76,7 +76,7 @@ struct intel_dpll_global_funcs { struct intel_dpll_global *pll); /* - * Hook for disabling the shared pll, called from intel_disable_global_dpll() + * Hook for disabling the shared pll, called from intel_disable_dpll_global() * only when it is safe to disable the pll, i.e., there are no more * tracked users for it. */ @@ -97,9 +97,8 @@ struct intel_dpll_global_funcs { * Hook for calculating the pll's output frequency based on its passed * in state. */ - int (*get_freq)(struct intel_display *i915, - const struct intel_dpll_global *pll, - const struct intel_dpll_hw_state *dpll_hw_state); + int (*get_freq)(struct intel_crtc_state *crtc_state, + struct intel_encoder *encoder); }; struct intel_dpll_mgr { @@ -1006,11 +1005,11 @@ hsw_ddi_calculate_wrpll(int clock /* in Hz */, *r2_out = best.r2; } -static int hsw_ddi_wrpll_get_freq(struct intel_display *display, - const struct intel_dpll_global *pll, - const struct intel_dpll_hw_state *dpll_hw_state) +static int hsw_ddi_wrpll_get_freq(struct intel_crtc_state *crtc_state, + struct intel_encoder *encoder) { - const struct hsw_dpll_hw_state *hw_state = &dpll_hw_state->hsw; + struct intel_display *display = to_intel_display(crtc_state); + const struct hsw_dpll_hw_state *hw_state = &crtc_state->dpll_hw_state.hsw; int refclk; int n, p, r; u32 wrpll = hw_state->wrpll; @@ -1051,7 +1050,6 @@ static int hsw_ddi_wrpll_compute_dpll(struct intel_atomic_state *state, struct intel_crtc *crtc) { - struct intel_display *display = to_intel_display(state); struct intel_crtc_state *crtc_state = intel_atomic_get_new_crtc_state(state, crtc); struct hsw_dpll_hw_state *hw_state = &crtc_state->dpll_hw_state.hsw; @@ -1064,8 +1062,7 @@ hsw_ddi_wrpll_compute_dpll(struct intel_atomic_state *state, WRPLL_DIVIDER_REFERENCE(r2) | WRPLL_DIVIDER_FEEDBACK(n2) | WRPLL_DIVIDER_POST(p); - crtc_state->port_clock = hsw_ddi_wrpll_get_freq(display, NULL, - &crtc_state->dpll_hw_state); + crtc_state->port_clock = hsw_ddi_wrpll_get_freq(crtc_state, NULL); return 0; } @@ -1132,10 +1129,11 @@ hsw_ddi_lcpll_get_dpll(struct intel_crtc_state *crtc_state) return pll; } -static int hsw_ddi_lcpll_get_freq(struct intel_display *display, - const struct intel_dpll_global *pll, - const struct intel_dpll_hw_state *dpll_hw_state) +static int hsw_ddi_lcpll_get_freq(struct intel_crtc_state *crtc_state, + struct intel_encoder *encoder) { + struct intel_display *display = to_intel_display(crtc_state); + struct intel_dpll_global *pll = crtc_state->dpll_global; int link_clock = 0; switch (pll->info->id) { @@ -1184,11 +1182,11 @@ hsw_ddi_spll_get_dpll(struct intel_atomic_state *state, BIT(DPLL_ID_SPLL)); } -static int hsw_ddi_spll_get_freq(struct intel_display *display, - const struct intel_dpll_global *pll, - const struct intel_dpll_hw_state *dpll_hw_state) +static int hsw_ddi_spll_get_freq(struct intel_crtc_state *crtc_state, + struct intel_encoder *encoder) { - const struct hsw_dpll_hw_state *hw_state = &dpll_hw_state->hsw; + struct intel_display *display = to_intel_display(crtc_state); + const struct hsw_dpll_hw_state *hw_state = &crtc_state->dpll_hw_state.hsw; int link_clock = 0; switch (hw_state->spll & SPLL_FREQ_MASK) { @@ -1977,20 +1975,21 @@ static int skl_get_dpll(struct intel_atomic_state *state, return 0; } -static int skl_ddi_pll_get_freq(struct intel_display *display, - const struct intel_dpll_global *pll, - const struct intel_dpll_hw_state *dpll_hw_state) +static int skl_ddi_pll_get_freq(struct intel_crtc_state *crtc_state, + struct intel_encoder *encoder) { - const struct skl_dpll_hw_state *hw_state = &dpll_hw_state->skl; + struct intel_display *display = to_intel_display(crtc_state); + struct intel_dpll_global *pll = crtc_state->dpll_global; + const struct skl_dpll_hw_state *hw_state = &crtc_state->dpll_hw_state.skl; /* * ctrl1 register is already shifted for each pll, just use 0 to get * the internal shift for each field */ if (hw_state->ctrl1 & DPLL_CTRL1_HDMI_MODE(0)) - return skl_ddi_wrpll_get_freq(display, pll, dpll_hw_state); + return skl_ddi_wrpll_get_freq(display, pll, &crtc_state->dpll_hw_state); else - return skl_ddi_lcpll_get_freq(display, pll, dpll_hw_state); + return skl_ddi_lcpll_get_freq(display, pll, &crtc_state->dpll_hw_state); } static void skl_update_dpll_ref_clks(struct intel_display *display) @@ -2376,11 +2375,11 @@ static int bxt_ddi_set_dpll_hw_state(struct intel_crtc_state *crtc_state, return 0; } -static int bxt_ddi_pll_get_freq(struct intel_display *display, - const struct intel_dpll_global *pll, - const struct intel_dpll_hw_state *dpll_hw_state) +static int bxt_ddi_pll_get_freq(struct intel_crtc_state *crtc_state, + struct intel_encoder *encoder) { - const struct bxt_dpll_hw_state *hw_state = &dpll_hw_state->bxt; + struct intel_display *display = to_intel_display(crtc_state); + const struct bxt_dpll_hw_state *hw_state = &crtc_state->dpll_hw_state.bxt; struct dpll clock; clock.m1 = 2; @@ -2408,7 +2407,6 @@ bxt_ddi_dp_set_dpll_hw_state(struct intel_crtc_state *crtc_state) static int bxt_ddi_hdmi_set_dpll_hw_state(struct intel_crtc_state *crtc_state) { - struct intel_display *display = to_intel_display(crtc_state); struct dpll clk_div = {}; int ret; @@ -2418,8 +2416,7 @@ bxt_ddi_hdmi_set_dpll_hw_state(struct intel_crtc_state *crtc_state) if (ret) return ret; - crtc_state->port_clock = bxt_ddi_pll_get_freq(display, NULL, - &crtc_state->dpll_hw_state); + crtc_state->port_clock = bxt_ddi_pll_get_freq(crtc_state, NULL); return 0; } @@ -2773,10 +2770,11 @@ static int icl_calc_tbt_pll(struct intel_crtc_state *crtc_state, return 0; } -static int icl_ddi_tbt_pll_get_freq(struct intel_display *display, - const struct intel_dpll_global *pll, - const struct intel_dpll_hw_state *dpll_hw_state) +static int icl_ddi_tbt_pll_get_freq(struct intel_crtc_state *crtc_state, + struct intel_encoder *encoder) { + struct intel_display *display = to_intel_display(crtc_state); + /* * The PLL outputs multiple frequencies at the same time, selection is * made at DDI clock mux level. @@ -2844,11 +2842,11 @@ icl_calc_wrpll(struct intel_crtc_state *crtc_state, return 0; } -static int icl_ddi_combo_pll_get_freq(struct intel_display *display, - const struct intel_dpll_global *pll, - const struct intel_dpll_hw_state *dpll_hw_state) +static int icl_ddi_combo_pll_get_freq(struct intel_crtc_state *crtc_state, + struct intel_encoder *encoder) { - const struct icl_dpll_hw_state *hw_state = &dpll_hw_state->icl; + struct intel_display *display = to_intel_display(crtc_state); + const struct icl_dpll_hw_state *hw_state = &crtc_state->dpll_hw_state.icl; int ref_clock = icl_wrpll_ref_clock(display); u32 dco_fraction; u32 p0, p1, p2, dco_freq; @@ -3217,11 +3215,11 @@ static int icl_calc_mg_pll_state(struct intel_crtc_state *crtc_state, return 0; } -static int icl_ddi_mg_pll_get_freq(struct intel_display *display, - const struct intel_dpll_global *pll, - const struct intel_dpll_hw_state *dpll_hw_state) +static int icl_ddi_mg_pll_get_freq(struct intel_crtc_state *crtc_state, + struct intel_encoder *encoder) { - const struct icl_dpll_hw_state *hw_state = &dpll_hw_state->icl; + struct intel_display *display = to_intel_display(crtc_state); + const struct icl_dpll_hw_state *hw_state = &crtc_state->dpll_hw_state.icl; u32 m1, m2_int, m2_frac, div1, div2, ref_clock; u64 tmp; @@ -3354,8 +3352,7 @@ static int icl_compute_combo_phy_dpll(struct intel_atomic_state *state, /* this is mainly for the fastset check */ icl_set_active_port_dpll(crtc_state, ICL_PORT_DPLL_DEFAULT); - crtc_state->port_clock = icl_ddi_combo_pll_get_freq(display, NULL, - &port_dpll->hw_state); + crtc_state->port_clock = icl_ddi_combo_pll_get_freq(crtc_state, NULL); return 0; } @@ -3453,8 +3450,7 @@ static int icl_compute_tc_phy_dplls(struct intel_atomic_state *state, else icl_set_active_port_dpll(crtc_state, ICL_PORT_DPLL_MG_PHY); - crtc_state->port_clock = icl_ddi_mg_pll_get_freq(display, NULL, - &port_dpll->hw_state); + crtc_state->port_clock = icl_ddi_mg_pll_get_freq(crtc_state, NULL); return 0; } @@ -4502,20 +4498,23 @@ void intel_update_active_dpll(struct intel_atomic_state *state, /** * intel_dpll_get_freq - calculate the DPLL's output frequency - * @display: intel_display device - * @pll: DPLL for which to calculate the output frequency - * @dpll_hw_state: DPLL state from which to calculate the output frequency + * @crtc_state: crtc_state which contains the DPLL state from which we + * calculate frequency + * @encoder: Encoder for which the freq is calculated * - * Return the output frequency corresponding to @pll's passed in @dpll_hw_state. + * Return the output frequency corresponding to @pll's passed in + * @crtc_state->dpll_hw_state. */ -int intel_dpll_get_freq(struct intel_display *display, - const struct intel_dpll_global *pll, - const struct intel_dpll_hw_state *dpll_hw_state) +int intel_dpll_get_freq(struct intel_crtc_state *crtc_state, + struct intel_encoder *encoder) { + struct intel_display *display = to_intel_display(crtc_state); + struct intel_dpll_global *pll = crtc_state->dpll_global; + if (drm_WARN_ON(display->drm, !pll->info->funcs->get_freq)) return 0; - return pll->info->funcs->get_freq(display, pll, dpll_hw_state); + return pll->info->funcs->get_freq(crtc_state, encoder); } /** diff --git a/drivers/gpu/drm/i915/display/intel_dpll_mgr.h b/drivers/gpu/drm/i915/display/intel_dpll_mgr.h index 6215da164ffc..d039056efbbc 100644 --- a/drivers/gpu/drm/i915/display/intel_dpll_mgr.h +++ b/drivers/gpu/drm/i915/display/intel_dpll_mgr.h @@ -412,9 +412,8 @@ void icl_set_active_port_dpll(struct intel_crtc_state *crtc_state, void intel_update_active_dpll(struct intel_atomic_state *state, struct intel_crtc *crtc, struct intel_encoder *encoder); -int intel_dpll_get_freq(struct intel_display *display, - const struct intel_dpll_global *pll, - const struct intel_dpll_hw_state *dpll_hw_state); +int intel_dpll_get_freq(struct intel_crtc_state *crtc_state, + struct intel_encoder *encoder); bool intel_dpll_get_hw_state(struct intel_display *display, struct intel_dpll_global *pll, struct intel_dpll_hw_state *dpll_hw_state); From patchwork Wed Apr 2 08:32:00 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Kandpal, Suraj" X-Patchwork-Id: 14035645 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 0F222C3601B for ; Wed, 2 Apr 2025 08:32:34 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 9642010E6F8; Wed, 2 Apr 2025 08:32:33 +0000 (UTC) Authentication-Results: gabe.freedesktop.org; dkim=pass (2048-bit key; unprotected) header.d=intel.com header.i=@intel.com header.b="IGIecHYE"; dkim-atps=neutral Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.19]) by gabe.freedesktop.org (Postfix) with ESMTPS id 4825110E705; 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02 Apr 2025 01:32:33 -0700 X-CSE-ConnectionGUID: jc7oHtw1RN2cHSlo9Ikbwg== X-CSE-MsgGUID: ygOfsukWRk+yaZNC9/E/kQ== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.14,295,1736841600"; d="scan'208";a="126612460" Received: from kandpal-x299-ud4-pro.iind.intel.com ([10.190.239.10]) by fmviesa007.fm.intel.com with ESMTP; 02 Apr 2025 01:32:29 -0700 From: Suraj Kandpal To: intel-xe@lists.freedesktop.org, intel-gfx@lists.freedesktop.org Cc: ankit.k.nautiyal@intel.com, uma.shankar@intel.com, jani.nikula@intel.com, mika.kahola@intel.com, ville.syrjala@intel.com, Suraj Kandpal Subject: [PATCH 12/16] drm/i915/dpll: Rename intel_[enable/disable]_global_dpll Date: Wed, 2 Apr 2025 14:02:00 +0530 Message-Id: <20250402083204.1523470-13-suraj.kandpal@intel.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20250402083204.1523470-1-suraj.kandpal@intel.com> References: <20250402083204.1523470-1-suraj.kandpal@intel.com> MIME-Version: 1.0 X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" Rename intel_[enable/disable]_global_dpll to intel_dpll_[enable/disable] in an effort to make sure all functions that are exported start with the filename. Signed-off-by: Suraj Kandpal --- drivers/gpu/drm/i915/display/intel_display.c | 4 ++-- drivers/gpu/drm/i915/display/intel_dpll_mgr.c | 8 ++++---- drivers/gpu/drm/i915/display/intel_dpll_mgr.h | 4 ++-- drivers/gpu/drm/i915/display/intel_pch_display.c | 6 +++--- 4 files changed, 11 insertions(+), 11 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c index 0c77fb02c565..759479f576d8 100644 --- a/drivers/gpu/drm/i915/display/intel_display.c +++ b/drivers/gpu/drm/i915/display/intel_display.c @@ -1662,7 +1662,7 @@ static void hsw_crtc_enable(struct intel_atomic_state *state, intel_encoders_pre_pll_enable(state, crtc); if (new_crtc_state->dpll_global) - intel_enable_dpll_global(new_crtc_state); + intel_dpll_enable(new_crtc_state); intel_encoders_pre_enable(state, crtc); @@ -1791,7 +1791,7 @@ static void hsw_crtc_disable(struct intel_atomic_state *state, intel_encoders_disable(state, crtc); intel_encoders_post_disable(state, crtc); - intel_disable_dpll_global(old_crtc_state); + intel_dpll_disable(old_crtc_state); intel_encoders_post_pll_disable(state, crtc); diff --git a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c index 8b4c35245190..97447ac0fcdf 100644 --- a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c +++ b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c @@ -254,12 +254,12 @@ static void _intel_disable_shared_dpll(struct intel_display *display, } /** - * intel_enable_dpll_global - enable a CRTC's global DPLL + * intel_dpll_enable - enable a CRTC's global DPLL * @crtc_state: CRTC, and its state, which has a DPLL * * Enable DPLL used by @crtc. */ -void intel_enable_dpll_global(const struct intel_crtc_state *crtc_state) +void intel_dpll_enable(const struct intel_crtc_state *crtc_state) { struct intel_display *display = to_intel_display(crtc_state); struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); @@ -300,12 +300,12 @@ void intel_enable_dpll_global(const struct intel_crtc_state *crtc_state) } /** - * intel_disable_dpll_global - disable a CRTC's shared DPLL + * intel_dpll_disable - disable a CRTC's shared DPLL * @crtc_state: CRTC, and its state, which has a shared DPLL * * Disable DPLL used by @crtc. */ -void intel_disable_dpll_global(const struct intel_crtc_state *crtc_state) +void intel_dpll_disable(const struct intel_crtc_state *crtc_state) { struct intel_display *display = to_intel_display(crtc_state); struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); diff --git a/drivers/gpu/drm/i915/display/intel_dpll_mgr.h b/drivers/gpu/drm/i915/display/intel_dpll_mgr.h index d039056efbbc..bc93cb36b737 100644 --- a/drivers/gpu/drm/i915/display/intel_dpll_mgr.h +++ b/drivers/gpu/drm/i915/display/intel_dpll_mgr.h @@ -417,8 +417,8 @@ int intel_dpll_get_freq(struct intel_crtc_state *crtc_state, bool intel_dpll_get_hw_state(struct intel_display *display, struct intel_dpll_global *pll, struct intel_dpll_hw_state *dpll_hw_state); -void intel_enable_dpll_global(const struct intel_crtc_state *crtc_state); -void intel_disable_dpll_global(const struct intel_crtc_state *crtc_state); +void intel_dpll_enable(const struct intel_crtc_state *crtc_state); +void intel_dpll_disable(const struct intel_crtc_state *crtc_state); void intel_dpll_swap_state(struct intel_atomic_state *state); void intel_dpll_global_init(struct intel_display *display); void intel_dpll_update_ref_clks(struct intel_display *display); diff --git a/drivers/gpu/drm/i915/display/intel_pch_display.c b/drivers/gpu/drm/i915/display/intel_pch_display.c index aa39d0fb1e23..4297afd5a37f 100644 --- a/drivers/gpu/drm/i915/display/intel_pch_display.c +++ b/drivers/gpu/drm/i915/display/intel_pch_display.c @@ -400,11 +400,11 @@ void ilk_pch_enable(struct intel_atomic_state *state, * transcoder, and we actually should do this to not upset any PCH * transcoder that already use the clock when we share it. * - * Note that enable_dpll_global tries to do the right thing, but + * Note that dpll_enable tries to do the right thing, but * get_dpll_global unconditionally resets the pll - we need that * to have the right LVDS enable sequence. */ - intel_enable_dpll_global(crtc_state); + intel_dpll_enable(crtc_state); /* set transcoder timing, panel must allow it */ assert_pps_unlocked(display, pipe); @@ -479,7 +479,7 @@ void ilk_pch_post_disable(struct intel_atomic_state *state, ilk_fdi_pll_disable(crtc); - intel_disable_dpll_global(old_crtc_state); + intel_dpll_disable(old_crtc_state); } static void ilk_pch_clock_get(struct intel_crtc_state *crtc_state) From patchwork Wed Apr 2 08:32:01 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Kandpal, Suraj" X-Patchwork-Id: 14035646 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id F055FC28B20 for ; Wed, 2 Apr 2025 08:32:35 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 8B13710E701; Wed, 2 Apr 2025 08:32:35 +0000 (UTC) Authentication-Results: gabe.freedesktop.org; dkim=pass (2048-bit key; unprotected) header.d=intel.com header.i=@intel.com header.b="dkvl5MiY"; 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d="scan'208";a="44828737" Received: from fmviesa007.fm.intel.com ([10.60.135.147]) by orvoesa111.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 02 Apr 2025 01:32:35 -0700 X-CSE-ConnectionGUID: GlvXKnT9SYuaNPiG2Jm/2w== X-CSE-MsgGUID: n1Hije6XSA6pJbeOPVswtg== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.14,295,1736841600"; d="scan'208";a="126612471" Received: from kandpal-x299-ud4-pro.iind.intel.com ([10.190.239.10]) by fmviesa007.fm.intel.com with ESMTP; 02 Apr 2025 01:32:32 -0700 From: Suraj Kandpal To: intel-xe@lists.freedesktop.org, intel-gfx@lists.freedesktop.org Cc: ankit.k.nautiyal@intel.com, uma.shankar@intel.com, jani.nikula@intel.com, mika.kahola@intel.com, ville.syrjala@intel.com, Suraj Kandpal Subject: [PATCH 13/16] drm/i915/dpll: Rename intel_unreference_dpll_global_crtc Date: Wed, 2 Apr 2025 14:02:01 +0530 Message-Id: <20250402083204.1523470-14-suraj.kandpal@intel.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20250402083204.1523470-1-suraj.kandpal@intel.com> References: <20250402083204.1523470-1-suraj.kandpal@intel.com> MIME-Version: 1.0 X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" Rename intel_unreference_dpll_global_crtc to intel_dpll_unreference_crtc in an effort to keep names of exported functions start with the filename. Signed-off-by: Suraj Kandpal --- drivers/gpu/drm/i915/display/intel_dpll_mgr.c | 10 +++++----- drivers/gpu/drm/i915/display/intel_dpll_mgr.h | 6 +++--- drivers/gpu/drm/i915/display/intel_modeset_setup.c | 6 +++--- 3 files changed, 11 insertions(+), 11 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c index 97447ac0fcdf..dd1f2104d5b1 100644 --- a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c +++ b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c @@ -455,7 +455,7 @@ intel_reference_dpll_global(struct intel_atomic_state *state, } /** - * intel_unreference_dpll_global_crtc - Drop a DPLL reference for a CRTC + * intel_dpll_unreference_crtc - Drop a DPLL reference for a CRTC * @crtc: CRTC on which behalf the reference is dropped * @pll: DPLL for which the reference is dropped * @dpll_state: the DPLL atomic state in which the reference is tracked @@ -463,9 +463,9 @@ intel_reference_dpll_global(struct intel_atomic_state *state, * Drop a reference for @pll tracking the end of use of it by @crtc. */ void -intel_unreference_dpll_global_crtc(const struct intel_crtc *crtc, - const struct intel_dpll_global *pll, - struct intel_dpll_state *dpll_state) +intel_dpll_unreference_crtc(const struct intel_crtc *crtc, + const struct intel_dpll_global *pll, + struct intel_dpll_state *dpll_state) { struct intel_display *display = to_intel_display(crtc); @@ -485,7 +485,7 @@ static void intel_unreference_dpll_global(struct intel_atomic_state *state, dpll_state = intel_atomic_get_dpll_global_state(&state->base); - intel_unreference_dpll_global_crtc(crtc, pll, &dpll_state[pll->index]); + intel_dpll_unreference_crtc(crtc, pll, &dpll_state[pll->index]); } static void intel_put_dpll(struct intel_atomic_state *state, diff --git a/drivers/gpu/drm/i915/display/intel_dpll_mgr.h b/drivers/gpu/drm/i915/display/intel_dpll_mgr.h index bc93cb36b737..f240018416c7 100644 --- a/drivers/gpu/drm/i915/display/intel_dpll_mgr.h +++ b/drivers/gpu/drm/i915/display/intel_dpll_mgr.h @@ -404,9 +404,9 @@ int intel_reserve_dpll_globals(struct intel_atomic_state *state, struct intel_encoder *encoder); void intel_release_dpll_globals(struct intel_atomic_state *state, struct intel_crtc *crtc); -void intel_unreference_dpll_global_crtc(const struct intel_crtc *crtc, - const struct intel_dpll_global *pll, - struct intel_dpll_state *shared_dpll_state); +void intel_dpll_unreference_crtc(const struct intel_crtc *crtc, + const struct intel_dpll_global *pll, + struct intel_dpll_state *shared_dpll_state); void icl_set_active_port_dpll(struct intel_crtc_state *crtc_state, enum icl_port_dpll_id port_dpll_id); void intel_update_active_dpll(struct intel_atomic_state *state, diff --git a/drivers/gpu/drm/i915/display/intel_modeset_setup.c b/drivers/gpu/drm/i915/display/intel_modeset_setup.c index 4221d1566c8a..191027c9bd4f 100644 --- a/drivers/gpu/drm/i915/display/intel_modeset_setup.c +++ b/drivers/gpu/drm/i915/display/intel_modeset_setup.c @@ -92,9 +92,9 @@ static void intel_crtc_disable_noatomic_begin(struct intel_crtc *crtc, crtc->base.enabled = false; if (crtc_state->dpll_global) - intel_unreference_dpll_global_crtc(crtc, - crtc_state->dpll_global, - &crtc_state->dpll_global->state); + intel_dpll_unreference_crtc(crtc, + crtc_state->dpll_global, + &crtc_state->dpll_global->state); } static void set_encoder_for_connector(struct intel_connector *connector, From patchwork Wed Apr 2 08:32:02 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Kandpal, Suraj" X-Patchwork-Id: 14035647 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 88BD2C28B20 for ; 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X-CSE-ConnectionGUID: EOcq39OfT2uu5Bs8x/ji3A== X-CSE-MsgGUID: yrIlSLh7QWa9lTW0I2nOMA== X-IronPort-AV: E=McAfee;i="6700,10204,11391"; a="44828742" X-IronPort-AV: E=Sophos;i="6.14,295,1736841600"; d="scan'208";a="44828742" Received: from fmviesa007.fm.intel.com ([10.60.135.147]) by orvoesa111.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 02 Apr 2025 01:32:38 -0700 X-CSE-ConnectionGUID: G3QQBuyVTDaHNaHqyHgZ8g== X-CSE-MsgGUID: +is+Z48EQkWPwzy7Pu0+gg== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.14,295,1736841600"; d="scan'208";a="126612481" Received: from kandpal-x299-ud4-pro.iind.intel.com ([10.190.239.10]) by fmviesa007.fm.intel.com with ESMTP; 02 Apr 2025 01:32:35 -0700 From: Suraj Kandpal To: intel-xe@lists.freedesktop.org, intel-gfx@lists.freedesktop.org Cc: ankit.k.nautiyal@intel.com, uma.shankar@intel.com, jani.nikula@intel.com, mika.kahola@intel.com, ville.syrjala@intel.com, Suraj Kandpal Subject: [PATCH 14/16] drm/i915/dpll: Rename intel__dpll_globals Date: Wed, 2 Apr 2025 14:02:02 +0530 Message-Id: <20250402083204.1523470-15-suraj.kandpal@intel.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20250402083204.1523470-1-suraj.kandpal@intel.com> References: <20250402083204.1523470-1-suraj.kandpal@intel.com> MIME-Version: 1.0 X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" Rename intel__dpll_globals to intel_dpll_ in an effort to keep names of exported functions start with the filename. Signed-off-by: Suraj Kandpal --- drivers/gpu/drm/i915/display/intel_display.c | 2 +- drivers/gpu/drm/i915/display/intel_dpll.c | 4 +-- drivers/gpu/drm/i915/display/intel_dpll_mgr.c | 26 +++++++++---------- drivers/gpu/drm/i915/display/intel_dpll_mgr.h | 10 +++---- 4 files changed, 21 insertions(+), 21 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c index 759479f576d8..5afc5e678844 100644 --- a/drivers/gpu/drm/i915/display/intel_display.c +++ b/drivers/gpu/drm/i915/display/intel_display.c @@ -6429,7 +6429,7 @@ int intel_atomic_check(struct drm_device *dev, any_ms = true; - intel_release_dpll_globals(state, crtc); + intel_dpll_release(state, crtc); } if (any_ms && !check_digital_port_conflicts(state)) { diff --git a/drivers/gpu/drm/i915/display/intel_dpll.c b/drivers/gpu/drm/i915/display/intel_dpll.c index eac588566d7c..13a70ef95804 100644 --- a/drivers/gpu/drm/i915/display/intel_dpll.c +++ b/drivers/gpu/drm/i915/display/intel_dpll.c @@ -1190,7 +1190,7 @@ static int hsw_crtc_get_dpll_global(struct intel_atomic_state *state, intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DSI)) return 0; - return intel_reserve_dpll_globals(state, crtc, encoder); + return intel_dpll_reserve(state, crtc, encoder); } static int dg2_crtc_compute_clock(struct intel_atomic_state *state, @@ -1417,7 +1417,7 @@ static int ilk_crtc_get_dpll_global(struct intel_atomic_state *state, if (!crtc_state->has_pch_encoder) return 0; - return intel_reserve_dpll_globals(state, crtc, NULL); + return intel_dpll_reserve(state, crtc, NULL); } static u32 vlv_dpll(const struct intel_crtc_state *crtc_state) diff --git a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c index dd1f2104d5b1..7faf1b2e6399 100644 --- a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c +++ b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c @@ -53,8 +53,8 @@ * users of a PLL are tracked and that tracking is integrated with the atomic * modset interface. During an atomic operation, required PLLs can be reserved * for a given CRTC and encoder configuration by calling - * intel_reserve_dpll_globals() and previously reserved PLLs can be released - * with intel_release_dpll_globals(). + * intel_dpll_reserve() and previously reserved PLLs can be released + * with intel_dpll_release(). * Changes to the users are first staged in the atomic state, and then made * effective by calling intel_dpll_swap_state() during the atomic * commit phase. @@ -4412,7 +4412,7 @@ int intel_compute_dpll_globals(struct intel_atomic_state *state, } /** - * intel_reserve_dpll_globals - reserve DPLLs for CRTC and encoder combination + * intel_dpll_reserve - reserve DPLLs for CRTC and encoder combination * @state: atomic state * @crtc: CRTC to reserve DPLLs for * @encoder: encoder @@ -4425,15 +4425,15 @@ int intel_compute_dpll_globals(struct intel_atomic_state *state, * calling intel_dpll_swap_state(). * * The reserved DPLLs should be released by calling - * intel_release_dpll_globals(). + * intel_dpll_release(). * * Returns: * 0 if all required DPLLs were successfully reserved, * negative error code otherwise. */ -int intel_reserve_dpll_globals(struct intel_atomic_state *state, - struct intel_crtc *crtc, - struct intel_encoder *encoder) +int intel_dpll_reserve(struct intel_atomic_state *state, + struct intel_crtc *crtc, + struct intel_encoder *encoder) { struct intel_display *display = to_intel_display(state); const struct intel_dpll_mgr *dpll_mgr = display->dpll.mgr; @@ -4445,18 +4445,18 @@ int intel_reserve_dpll_globals(struct intel_atomic_state *state, } /** - * intel_release_dpll_globals - end use of DPLLs by CRTC in atomic state + * intel_dpll_release - end use of DPLLs by CRTC in atomic state * @state: atomic state * @crtc: crtc from which the DPLLs are to be released * - * This function releases all DPLLs reserved by intel_reserve_dpll_globals() + * This function releases all DPLLs reserved by intel_dpll_reserve() * from the current atomic commit @state and the old @crtc atomic state. * * The new configuration in the atomic commit @state is made effective by * calling intel_dpll_swap_state(). */ -void intel_release_dpll_globals(struct intel_atomic_state *state, - struct intel_crtc *crtc) +void intel_dpll_release(struct intel_atomic_state *state, + struct intel_crtc *crtc) { struct intel_display *display = to_intel_display(state); const struct intel_dpll_mgr *dpll_mgr = display->dpll.mgr; @@ -4464,7 +4464,7 @@ void intel_release_dpll_globals(struct intel_atomic_state *state, /* * FIXME: this function is called for every platform having a * compute_clock hook, even though the platform doesn't yet support - * the global DPLL framework and intel_reserve_dpll_globals() is not + * the global DPLL framework and intel_dpll_reserve() is not * called on those. */ if (!dpll_mgr) @@ -4480,7 +4480,7 @@ void intel_release_dpll_globals(struct intel_atomic_state *state, * @encoder: encoder determining the type of port DPLL * * Update the active DPLL for the given @crtc/@encoder in @crtc's atomic state, - * from the port DPLLs reserved previously by intel_reserve_dpll_globals(). The + * from the port DPLLs reserved previously by intel_dpll_reserve(). The * DPLL selected will be based on the current mode of the encoder's port. */ void intel_update_active_dpll(struct intel_atomic_state *state, diff --git a/drivers/gpu/drm/i915/display/intel_dpll_mgr.h b/drivers/gpu/drm/i915/display/intel_dpll_mgr.h index f240018416c7..b6d5a15b8103 100644 --- a/drivers/gpu/drm/i915/display/intel_dpll_mgr.h +++ b/drivers/gpu/drm/i915/display/intel_dpll_mgr.h @@ -399,11 +399,11 @@ void assert_dpll_global(struct intel_display *display, int intel_compute_dpll_globals(struct intel_atomic_state *state, struct intel_crtc *crtc, struct intel_encoder *encoder); -int intel_reserve_dpll_globals(struct intel_atomic_state *state, - struct intel_crtc *crtc, - struct intel_encoder *encoder); -void intel_release_dpll_globals(struct intel_atomic_state *state, - struct intel_crtc *crtc); +int intel_dpll_reserve(struct intel_atomic_state *state, + struct intel_crtc *crtc, + struct intel_encoder *encoder); +void intel_dpll_release(struct intel_atomic_state *state, + struct intel_crtc *crtc); void intel_dpll_unreference_crtc(const struct intel_crtc *crtc, const struct intel_dpll_global *pll, struct intel_dpll_state *shared_dpll_state); From patchwork Wed Apr 2 08:32:03 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Kandpal, Suraj" X-Patchwork-Id: 14035648 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 122A6C36014 for ; Wed, 2 Apr 2025 08:32:47 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 56EBE10E706; Wed, 2 Apr 2025 08:32:47 +0000 (UTC) Authentication-Results: gabe.freedesktop.org; dkim=pass (2048-bit key; unprotected) header.d=intel.com header.i=@intel.com header.b="Kcs+lRnY"; dkim-atps=neutral Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.19]) by gabe.freedesktop.org (Postfix) with ESMTPS id 4C06C10E6FA; Wed, 2 Apr 2025 08:32:46 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1743582767; x=1775118767; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=3+ytsS8HPHMx2ncAobC51QTCD1Sy5sEta5d+18zWfFs=; b=Kcs+lRnYoJYAEBI7AHslIDbcUJcRZKiKXftkVmH0VaMc3S0GRFQwQjv8 dbwxz/3oPuXikGvAjbcxpOztuMeFRKTaNVDw756vgrd6ip+uLjCBuQ5wt CNN7Hd3SwwT5vrlu4A5fS6t7m0h1ji9phOccLosX++qja5FlScaLGKMJ0 HEmBngZPjvNQY3C0/47fyMQiHdMCvDFpwghpPJ6n8bFF+Zvk0FmV0umCv Qsn5oOGOe3tsVoypEfmtFmSOM1uIhnn08s8cd2ad0NpH40bol1Yj58ltM cVGuuMQYTsnwBdK059o2k2vhCYH+2N8f+R7+vynjCdqZPWJqDOZ5dFA44 g==; X-CSE-ConnectionGUID: r9kl2+2rQxysUb8+pHulRw== X-CSE-MsgGUID: 3oGUabn6QEa9pyvnnudP6Q== X-IronPort-AV: E=McAfee;i="6700,10204,11391"; a="44828745" X-IronPort-AV: E=Sophos;i="6.14,295,1736841600"; d="scan'208";a="44828745" Received: from fmviesa007.fm.intel.com ([10.60.135.147]) by orvoesa111.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 02 Apr 2025 01:32:41 -0700 X-CSE-ConnectionGUID: cFuT/lrSRhmflz5dPdnqjg== X-CSE-MsgGUID: IBNawXVsT920PRPErhLFOw== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.14,295,1736841600"; d="scan'208";a="126612494" Received: from kandpal-x299-ud4-pro.iind.intel.com ([10.190.239.10]) by fmviesa007.fm.intel.com with ESMTP; 02 Apr 2025 01:32:37 -0700 From: Suraj Kandpal To: intel-xe@lists.freedesktop.org, intel-gfx@lists.freedesktop.org Cc: ankit.k.nautiyal@intel.com, uma.shankar@intel.com, jani.nikula@intel.com, mika.kahola@intel.com, ville.syrjala@intel.com, Suraj Kandpal Subject: [PATCH 15/16] drm/i915/dpll: Rename intel_compute_dpll_globals Date: Wed, 2 Apr 2025 14:02:03 +0530 Message-Id: <20250402083204.1523470-16-suraj.kandpal@intel.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20250402083204.1523470-1-suraj.kandpal@intel.com> References: <20250402083204.1523470-1-suraj.kandpal@intel.com> MIME-Version: 1.0 X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" Rename intel_compute_dpll_globals to intel_dpll_compute in an effort to make sure all function names that are exported have the filename at start. Signed-off-by: Suraj Kandpal --- drivers/gpu/drm/i915/display/intel_dpll.c | 6 +++--- drivers/gpu/drm/i915/display/intel_dpll_mgr.c | 8 ++++---- drivers/gpu/drm/i915/display/intel_dpll_mgr.h | 6 +++--- 3 files changed, 10 insertions(+), 10 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_dpll.c b/drivers/gpu/drm/i915/display/intel_dpll.c index 13a70ef95804..1cdd54e5beaf 100644 --- a/drivers/gpu/drm/i915/display/intel_dpll.c +++ b/drivers/gpu/drm/i915/display/intel_dpll.c @@ -1162,7 +1162,7 @@ static int hsw_crtc_compute_clock(struct intel_atomic_state *state, intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DSI)) return 0; - ret = intel_compute_dpll_globals(state, crtc, encoder); + ret = intel_dpll_compute(state, crtc, encoder); if (ret) return ret; @@ -1224,7 +1224,7 @@ static int mtl_crtc_compute_clock(struct intel_atomic_state *state, if (ret) return ret; - /* TODO: Do the readback via intel_compute_dpll_globals() */ + /* TODO: Do the readback via intel_dpll_compute() */ crtc_state->port_clock = intel_cx0pll_calc_port_clock(encoder, &crtc_state->dpll_hw_state.cx0pll); crtc_state->hw.adjusted_mode.crtc_clock = intel_crtc_dotclock(crtc_state); @@ -1397,7 +1397,7 @@ static int ilk_crtc_compute_clock(struct intel_atomic_state *state, ilk_compute_dpll(crtc_state, &crtc_state->dpll, &crtc_state->dpll); - ret = intel_compute_dpll_globals(state, crtc, NULL); + ret = intel_dpll_compute(state, crtc, NULL); if (ret) return ret; diff --git a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c index 7faf1b2e6399..03c08ada0261 100644 --- a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c +++ b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c @@ -4385,7 +4385,7 @@ void intel_dpll_global_init(struct intel_display *display) } /** - * intel_compute_dpll_globals - compute DPLL state CRTC and encoder combination + * intel_dpll_compute - compute DPLL state CRTC and encoder combination * @state: atomic state * @crtc: CRTC to compute DPLLs for * @encoder: encoder @@ -4398,9 +4398,9 @@ void intel_dpll_global_init(struct intel_display *display) * Returns: * 0 on success, negative error code on failure. */ -int intel_compute_dpll_globals(struct intel_atomic_state *state, - struct intel_crtc *crtc, - struct intel_encoder *encoder) +int intel_dpll_compute(struct intel_atomic_state *state, + struct intel_crtc *crtc, + struct intel_encoder *encoder) { struct intel_display *display = to_intel_display(state); const struct intel_dpll_mgr *dpll_mgr = display->dpll.mgr; diff --git a/drivers/gpu/drm/i915/display/intel_dpll_mgr.h b/drivers/gpu/drm/i915/display/intel_dpll_mgr.h index b6d5a15b8103..9bd71aba6c6a 100644 --- a/drivers/gpu/drm/i915/display/intel_dpll_mgr.h +++ b/drivers/gpu/drm/i915/display/intel_dpll_mgr.h @@ -396,9 +396,9 @@ void assert_dpll_global(struct intel_display *display, bool state); #define assert_dpll_global_enabled(d, p) assert_dpll_global(d, p, true) #define assert_dpll_global_disabled(d, p) assert_dpll_global(d, p, false) -int intel_compute_dpll_globals(struct intel_atomic_state *state, - struct intel_crtc *crtc, - struct intel_encoder *encoder); +int intel_dpll_compute(struct intel_atomic_state *state, + struct intel_crtc *crtc, + struct intel_encoder *encoder); int intel_dpll_reserve(struct intel_atomic_state *state, struct intel_crtc *crtc, struct intel_encoder *encoder); From patchwork Wed Apr 2 08:32:04 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Kandpal, Suraj" X-Patchwork-Id: 14035649 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id CE8B8C3601F for ; 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X-CSE-ConnectionGUID: shZNAGY1TX2IYEvKc2461g== X-CSE-MsgGUID: AB4xn+OzSFS59xePZNurag== X-IronPort-AV: E=McAfee;i="6700,10204,11391"; a="44828747" X-IronPort-AV: E=Sophos;i="6.14,295,1736841600"; d="scan'208";a="44828747" Received: from fmviesa007.fm.intel.com ([10.60.135.147]) by orvoesa111.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 02 Apr 2025 01:32:43 -0700 X-CSE-ConnectionGUID: 45y4IOESSUiKA5SxttEjmw== X-CSE-MsgGUID: CapqJ9tuT8iRHfIZk3A6bw== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.14,295,1736841600"; d="scan'208";a="126612501" Received: from kandpal-x299-ud4-pro.iind.intel.com ([10.190.239.10]) by fmviesa007.fm.intel.com with ESMTP; 02 Apr 2025 01:32:40 -0700 From: Suraj Kandpal To: intel-xe@lists.freedesktop.org, intel-gfx@lists.freedesktop.org Cc: ankit.k.nautiyal@intel.com, uma.shankar@intel.com, jani.nikula@intel.com, mika.kahola@intel.com, ville.syrjala@intel.com, Suraj Kandpal Subject: [PATCH 16/16] drm/i915/dpll: Rename intel_update_active_dpll Date: Wed, 2 Apr 2025 14:02:04 +0530 Message-Id: <20250402083204.1523470-17-suraj.kandpal@intel.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20250402083204.1523470-1-suraj.kandpal@intel.com> References: <20250402083204.1523470-1-suraj.kandpal@intel.com> MIME-Version: 1.0 X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" Rename intel_update_active_dpll to intel_dpll_update_active in an effort to have function names which are exported to start with filenames they are exported from. Signed-off-by: Suraj Kandpal --- drivers/gpu/drm/i915/display/intel_ddi.c | 2 +- drivers/gpu/drm/i915/display/intel_dpll_mgr.c | 4 ++-- drivers/gpu/drm/i915/display/intel_dpll_mgr.h | 2 +- 3 files changed, 4 insertions(+), 4 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c b/drivers/gpu/drm/i915/display/intel_ddi.c index 2f1f7dd20e80..1253fa35a5d0 100644 --- a/drivers/gpu/drm/i915/display/intel_ddi.c +++ b/drivers/gpu/drm/i915/display/intel_ddi.c @@ -3647,7 +3647,7 @@ void intel_ddi_update_active_dpll(struct intel_atomic_state *state, for_each_intel_crtc_in_pipe_mask(display->drm, pipe_crtc, intel_crtc_joined_pipe_mask(crtc_state)) - intel_update_active_dpll(state, pipe_crtc, encoder); + intel_dpll_update_active(state, pipe_crtc, encoder); } /* diff --git a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c index 03c08ada0261..2b86775c464e 100644 --- a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c +++ b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c @@ -4474,7 +4474,7 @@ void intel_dpll_release(struct intel_atomic_state *state, } /** - * intel_update_active_dpll - update the active DPLL for a CRTC/encoder + * intel_dpll_update_active - update the active DPLL for a CRTC/encoder * @state: atomic state * @crtc: the CRTC for which to update the active DPLL * @encoder: encoder determining the type of port DPLL @@ -4483,7 +4483,7 @@ void intel_dpll_release(struct intel_atomic_state *state, * from the port DPLLs reserved previously by intel_dpll_reserve(). The * DPLL selected will be based on the current mode of the encoder's port. */ -void intel_update_active_dpll(struct intel_atomic_state *state, +void intel_dpll_update_active(struct intel_atomic_state *state, struct intel_crtc *crtc, struct intel_encoder *encoder) { diff --git a/drivers/gpu/drm/i915/display/intel_dpll_mgr.h b/drivers/gpu/drm/i915/display/intel_dpll_mgr.h index 9bd71aba6c6a..b6d985e4e3ec 100644 --- a/drivers/gpu/drm/i915/display/intel_dpll_mgr.h +++ b/drivers/gpu/drm/i915/display/intel_dpll_mgr.h @@ -409,7 +409,7 @@ void intel_dpll_unreference_crtc(const struct intel_crtc *crtc, struct intel_dpll_state *shared_dpll_state); void icl_set_active_port_dpll(struct intel_crtc_state *crtc_state, enum icl_port_dpll_id port_dpll_id); -void intel_update_active_dpll(struct intel_atomic_state *state, +void intel_dpll_update_active(struct intel_atomic_state *state, struct intel_crtc *crtc, struct intel_encoder *encoder); int intel_dpll_get_freq(struct intel_crtc_state *crtc_state,