From patchwork Wed Apr 2 12:37:32 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Hans Zhang <18255117159@163.com> X-Patchwork-Id: 14035915 Received: from m16.mail.163.com (m16.mail.163.com [117.135.210.2]) by smtp.subspace.kernel.org (Postfix) with ESMTP id 6AF23237717; Wed, 2 Apr 2025 12:38:16 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=117.135.210.2 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1743597500; cv=none; b=PlWsTLxrbTLVcEyHuga68oG73LVMzEz+9JDQ3A30OlAfTZoa3gxzC0TD452KmGG5S+9KIUYoHcl6hY5d4HcxQ2t20cQvBdlWOBulIFkeOVycFVQVVkKUP+vByii9MNAJOQU4SXg4b9qJoBHGKmdKbl3ge9yP7lAlaWD9/dvOrfw= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1743597500; c=relaxed/simple; bh=Yuqvp68rdEEpleUzC6uc5JIop0Sh8kw0dPFfNujvun8=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=HlDe7DBVxC6AnHuj4xF9uGoITklTKwS0RBw2U6UBjlboSDtZ35K//CnpjE77lHUtOV3V4cCbrLr1u8Akk1/HlJJYXIfFmRBine2Evv9WIoaaV52S8uaPp+2lGsuNb5/uly4yKiHtgmxo0cyMN5YNRNAyQQn6rD+yaLe50dh1RPQ= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=163.com; spf=pass smtp.mailfrom=163.com; dkim=pass (1024-bit key) header.d=163.com header.i=@163.com header.b=ajJCLjmX; arc=none smtp.client-ip=117.135.210.2 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=163.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=163.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=163.com header.i=@163.com header.b="ajJCLjmX" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=163.com; s=s110527; h=From:Subject:Date:Message-Id:MIME-Version; bh=mVR7d PI1RpCG5sh48f+87uNK1JGB6AwPUiNiO+gfKo0=; b=ajJCLjmXKPDZ40jIzGeSq 8MjNVb0Hc3913FatmwuovcfLu1sBcgvGutnNy/SnkKj5L1AAh+hjWORlzE651GFe 6nx3CW7gzy3AudahIz9YWUFjlQBBJ2NdaATRnTHf8/af+vl195BdOBLcS6c5Eufc o6z2a2+eQOiOy114pCvu0k= Received: from localhost.localdomain (unknown []) by gzsmtp1 (Coremail) with SMTP id PCgvCgCXrkiUL+1nL3+IAA--.22499S3; Wed, 02 Apr 2025 20:37:45 +0800 (CST) From: Hans Zhang <18255117159@163.com> To: lpieralisi@kernel.org, bhelgaas@google.com Cc: kw@linux.com, manivannan.sadhasivam@linaro.org, ilpo.jarvinen@linux.intel.com, robh@kernel.org, jingoohan1@gmail.com, thomas.richard@bootlin.com, linux-pci@vger.kernel.org, linux-kernel@vger.kernel.org, Hans Zhang <18255117159@163.com> Subject: [v8 1/5] PCI: Refactor capability search into common macros Date: Wed, 2 Apr 2025 20:37:32 +0800 Message-Id: <20250402123736.55995-2-18255117159@163.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20250402123736.55995-1-18255117159@163.com> References: <20250402123736.55995-1-18255117159@163.com> Precedence: bulk X-Mailing-List: linux-pci@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-CM-TRANSID: PCgvCgCXrkiUL+1nL3+IAA--.22499S3 X-Coremail-Antispam: 1Uf129KBjvJXoWxAryxuFW7WFW3ZF4rCF4xXrb_yoWrAF1kpr 95WF1Sy395Ja129wnxZa18Krya9a97Aay29rWxGw15XFyDC3WxGF4FkFy2gFy7trZrAF13 Xw1qvFyru3ZIyF7anT9S1TB71UUUUU7qnTZGkaVYY2UrUUUUjbIjqfuFe4nvWSU5nxnvy2 9KBjDUYxBIdaVFxhVjvjDU0xZFpf9x0zR1mhrUUUUU= X-CM-SenderInfo: rpryjkyvrrlimvzbiqqrwthudrp/1tbiOhsjo2ftJvzjoQABsy Introduce PCI_FIND_NEXT_CAP_TTL and PCI_FIND_NEXT_EXT_CAPABILITY macros to consolidate duplicate PCI capability search logic found throughout the driver tree. This refactoring: 1. Eliminates code duplication in capability scanning routines 2. Provides a standardized, maintainable implementation 3. Reduces error-prone copy-paste implementations 4. Maintains identical functionality to existing code The macros abstract the low-level capability register scanning while preserving the existing PCI configuration space access patterns. They will enable future conversions of multiple capability search implementations across various drivers (e.g., PCI core, controller drivers) to use this centralized logic. Signed-off-by: Hans Zhang <18255117159@163.com> --- drivers/pci/pci.h | 81 +++++++++++++++++++++++++++++++++++ include/uapi/linux/pci_regs.h | 2 + 2 files changed, 83 insertions(+) diff --git a/drivers/pci/pci.h b/drivers/pci/pci.h index 2e9cf26a9ee9..f705b8bd3084 100644 --- a/drivers/pci/pci.h +++ b/drivers/pci/pci.h @@ -89,6 +89,87 @@ bool pcie_cap_has_lnkctl(const struct pci_dev *dev); bool pcie_cap_has_lnkctl2(const struct pci_dev *dev); bool pcie_cap_has_rtctl(const struct pci_dev *dev); +/* Standard Capability finder */ +/** + * PCI_FIND_NEXT_CAP_TTL - Find a PCI standard capability + * @read_cfg: Function pointer for reading PCI config space + * @start: Starting position to begin search + * @cap: Capability ID to find + * @args: Arguments to pass to read_cfg function + * + * Iterates through the capability list in PCI config space to find + * the specified capability. Implements TTL (time-to-live) protection + * against infinite loops. + * + * Returns: Position of the capability if found, 0 otherwise. + */ +#define PCI_FIND_NEXT_CAP_TTL(read_cfg, start, cap, args...) \ +({ \ + u8 __pos = (start); \ + int __ttl = PCI_FIND_CAP_TTL; \ + u16 __ent; \ + u8 __found_pos = 0; \ + u8 __id; \ + \ + read_cfg(args, __pos, 1, (u32 *)&__pos); \ + \ + while (__ttl--) { \ + if (__pos < PCI_STD_HEADER_SIZEOF) \ + break; \ + __pos = ALIGN_DOWN(__pos, 4); \ + read_cfg(args, __pos, 2, (u32 *)&__ent); \ + __id = FIELD_GET(PCI_CAP_ID_MASK, __ent); \ + if (__id == 0xff) \ + break; \ + if (__id == (cap)) { \ + __found_pos = __pos; \ + break; \ + } \ + __pos = FIELD_GET(PCI_CAP_LIST_NEXT_MASK, __ent); \ + } \ + __found_pos; \ +}) + +/* Extended Capability finder */ +/** + * PCI_FIND_NEXT_EXT_CAPABILITY - Find a PCI extended capability + * @read_cfg: Function pointer for reading PCI config space + * @start: Starting position to begin search (0 for initial search) + * @cap: Extended capability ID to find + * @args: Arguments to pass to read_cfg function + * + * Searches the extended capability space in PCI config registers + * for the specified capability. Implements TTL protection against + * infinite loops using a calculated maximum search count. + * + * Returns: Position of the capability if found, 0 otherwise. + */ +#define PCI_FIND_NEXT_EXT_CAPABILITY(read_cfg, start, cap, args...) \ +({ \ + u16 __pos = (start) ?: PCI_CFG_SPACE_SIZE; \ + u16 __found_pos = 0; \ + int __ttl, __ret; \ + u32 __header; \ + \ + __ttl = (PCI_CFG_SPACE_EXP_SIZE - PCI_CFG_SPACE_SIZE) / 8; \ + while (__ttl-- > 0 && __pos >= PCI_CFG_SPACE_SIZE) { \ + __ret = read_cfg(args, __pos, 4, &__header); \ + if (__ret != PCIBIOS_SUCCESSFUL) \ + break; \ + \ + if (__header == 0) \ + break; \ + \ + if (PCI_EXT_CAP_ID(__header) == (cap) && __pos != start) { \ + __found_pos = __pos; \ + break; \ + } \ + \ + __pos = PCI_EXT_CAP_NEXT(__header); \ + } \ + __found_pos; \ +}) + /* Functions internal to the PCI core code */ #ifdef CONFIG_DMI diff --git a/include/uapi/linux/pci_regs.h b/include/uapi/linux/pci_regs.h index 3445c4970e4d..a11ebbab99fc 100644 --- a/include/uapi/linux/pci_regs.h +++ b/include/uapi/linux/pci_regs.h @@ -206,6 +206,8 @@ /* 0x48-0x7f reserved */ /* Capability lists */ +#define PCI_CAP_ID_MASK 0x00ff +#define PCI_CAP_LIST_NEXT_MASK 0xff00 #define PCI_CAP_LIST_ID 0 /* Capability ID */ #define PCI_CAP_ID_PM 0x01 /* Power Management */ From patchwork Wed Apr 2 12:37:33 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Hans Zhang <18255117159@163.com> X-Patchwork-Id: 14035916 Received: from m16.mail.163.com (m16.mail.163.com [220.197.31.3]) by smtp.subspace.kernel.org (Postfix) with ESMTP id 5C19523A99C; Wed, 2 Apr 2025 12:38:20 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=220.197.31.3 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1743597503; cv=none; b=OhwhgltdM5lJz0zTCeDaZbIWDp0Z9gtXjZ6xB3WCL38adunLU0rVtZw7xctOmxEd5mNZm1nTR2mmLMmumYCDfqcqohX33QC6yTz/geCkoRsJ1jNDi2KjNROOJUkZihUTaSoe/KlWqJSpEDY9LCsjtpOkvvP5GdBEnx/OCclH51E= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1743597503; c=relaxed/simple; bh=ddtnqBOd2ODSD+XyZv/73r6EEZeGjBoXxpInKC6Gw3Y=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=NBkyMKUGHnCvJREZ+ub8f68Ur2iaNmVuyOK8vLOlmCoKi555lUoTfWPKBTfX7WjspMov1UJcFNv3qYbUTuCoswpslRcmRX1daDptbXxkG/fmBb0G+YVWiGa4vuhIt0WpeqZXSLizk4da2LT52murIW1XKr4/yz7Z2Y44lDVIVHQ= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=163.com; spf=pass smtp.mailfrom=163.com; dkim=pass (1024-bit key) header.d=163.com header.i=@163.com header.b=eEV3Z8Fc; arc=none smtp.client-ip=220.197.31.3 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=163.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=163.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=163.com header.i=@163.com header.b="eEV3Z8Fc" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=163.com; s=s110527; h=From:Subject:Date:Message-Id:MIME-Version; bh=av1Pb jZeH5TlBaSDhEWPUDcgL43N17wauAZ7YJSio9Y=; b=eEV3Z8FcQYWcOssaNZ+xc mDEvpF/Sv9iWnJbmLctSznzKfcgunn7UwncGiA9B0mu/Jrdyh/88l7uRclIMDSOE gjvfO5Dl7Rp6IhKtGqnBrM9wxvQLxWErn5PiNiqCEOTrzypoPVW3UH+ocbLbbMwW RoQFlRFIUyOjYHT+Hbaxr8= Received: from localhost.localdomain (unknown []) by gzsmtp1 (Coremail) with SMTP id PCgvCgCXrkiUL+1nL3+IAA--.22499S4; Wed, 02 Apr 2025 20:37:46 +0800 (CST) From: Hans Zhang <18255117159@163.com> To: lpieralisi@kernel.org, bhelgaas@google.com Cc: kw@linux.com, manivannan.sadhasivam@linaro.org, ilpo.jarvinen@linux.intel.com, robh@kernel.org, jingoohan1@gmail.com, thomas.richard@bootlin.com, linux-pci@vger.kernel.org, linux-kernel@vger.kernel.org, Hans Zhang <18255117159@163.com> Subject: [v8 2/5] PCI: Refactor capability search functions to eliminate code duplication Date: Wed, 2 Apr 2025 20:37:33 +0800 Message-Id: <20250402123736.55995-3-18255117159@163.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20250402123736.55995-1-18255117159@163.com> References: <20250402123736.55995-1-18255117159@163.com> Precedence: bulk X-Mailing-List: linux-pci@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-CM-TRANSID: PCgvCgCXrkiUL+1nL3+IAA--.22499S4 X-Coremail-Antispam: 1Uf129KBjvJXoWxAryxCw4UuryUJw4DJr1fJFb_yoWrKF18pF W3Aa43Ary8G3W7tw4q9ayjyw13WF9rJrWxZrWxC3sYvF12yryvyFy2ka4aqFy2grZ7WF1f X39xtan5C3WqyaDanT9S1TB71UUUUU7qnTZGkaVYY2UrUUUUjbIjqfuFe4nvWSU5nxnvy2 9KBjDUYxBIdaVFxhVjvjDU0xZFpf9x0zROzVbUUUUU= X-CM-SenderInfo: rpryjkyvrrlimvzbiqqrwthudrp/xtbBDx8jo2ftJx3gQwAAsD Refactor the PCI capability and extended capability search functions by consolidating common code patterns into reusable macros (PCI_FIND_NEXT_CAP_TTL and PCI_FIND_NEXT_EXT_CAPABILITY). The main changes include: 1. Introducing a unified config space read helper (__pci_bus_read_config). 2. Removing duplicate search logic from __pci_find_next_cap_ttl and pci_find_next_ext_capability. 3. Implementing consistent capability discovery using the new macros. 4. Simplifying HyperTransport capability lookup by leveraging the refactored code. The refactoring maintains existing functionality while reducing code duplication and improving maintainability. By centralizing the search logic, we achieve better code consistency and make future updates easier. This change has been verified to maintain backward compatibility with existing capability discovery patterns through thorough testing of PCI device enumeration and capability probing. Signed-off-by: Hans Zhang <18255117159@163.com> --- Changes since v7: https://lore.kernel.org/linux-pci/20250402042020.48681-3-18255117159@163.com - Resolve compilation errors. --- drivers/pci/pci.c | 80 ++++++++++++++--------------------------------- 1 file changed, 23 insertions(+), 57 deletions(-) diff --git a/drivers/pci/pci.c b/drivers/pci/pci.c index 869d204a70a3..f5a97f8882a6 100644 --- a/drivers/pci/pci.c +++ b/drivers/pci/pci.c @@ -423,36 +423,33 @@ static int pci_dev_str_match(struct pci_dev *dev, const char *p, return 1; } -static u8 __pci_find_next_cap_ttl(struct pci_bus *bus, unsigned int devfn, - u8 pos, int cap, int *ttl) +static int __pci_bus_read_config(void *priv, unsigned int devfn, int where, + u32 size, u32 *val) { - u8 id; - u16 ent; + struct pci_bus *bus = priv; + int ret; - pci_bus_read_config_byte(bus, devfn, pos, &pos); + if (size == 1) + ret = pci_bus_read_config_byte(bus, devfn, where, (u8 *)val); + else if (size == 2) + ret = pci_bus_read_config_word(bus, devfn, where, (u16 *)val); + else + ret = pci_bus_read_config_dword(bus, devfn, where, val); - while ((*ttl)--) { - if (pos < 0x40) - break; - pos &= ~3; - pci_bus_read_config_word(bus, devfn, pos, &ent); + return ret; +} - id = ent & 0xff; - if (id == 0xff) - break; - if (id == cap) - return pos; - pos = (ent >> 8); - } - return 0; +static u8 __pci_find_next_cap_ttl(struct pci_bus *bus, unsigned int devfn, + u8 pos, int cap) +{ + return PCI_FIND_NEXT_CAP_TTL(__pci_bus_read_config, pos, cap, bus, + devfn); } static u8 __pci_find_next_cap(struct pci_bus *bus, unsigned int devfn, u8 pos, int cap) { - int ttl = PCI_FIND_CAP_TTL; - - return __pci_find_next_cap_ttl(bus, devfn, pos, cap, &ttl); + return __pci_find_next_cap_ttl(bus, devfn, pos, cap); } u8 pci_find_next_capability(struct pci_dev *dev, u8 pos, int cap) @@ -553,42 +550,11 @@ EXPORT_SYMBOL(pci_bus_find_capability); */ u16 pci_find_next_ext_capability(struct pci_dev *dev, u16 start, int cap) { - u32 header; - int ttl; - u16 pos = PCI_CFG_SPACE_SIZE; - - /* minimum 8 bytes per capability */ - ttl = (PCI_CFG_SPACE_EXP_SIZE - PCI_CFG_SPACE_SIZE) / 8; - if (dev->cfg_size <= PCI_CFG_SPACE_SIZE) return 0; - if (start) - pos = start; - - if (pci_read_config_dword(dev, pos, &header) != PCIBIOS_SUCCESSFUL) - return 0; - - /* - * If we have no capabilities, this is indicated by cap ID, - * cap version and next pointer all being 0. - */ - if (header == 0) - return 0; - - while (ttl-- > 0) { - if (PCI_EXT_CAP_ID(header) == cap && pos != start) - return pos; - - pos = PCI_EXT_CAP_NEXT(header); - if (pos < PCI_CFG_SPACE_SIZE) - break; - - if (pci_read_config_dword(dev, pos, &header) != PCIBIOS_SUCCESSFUL) - break; - } - - return 0; + return PCI_FIND_NEXT_EXT_CAPABILITY(__pci_bus_read_config, start, cap, + dev->bus, dev->devfn); } EXPORT_SYMBOL_GPL(pci_find_next_ext_capability); @@ -648,7 +614,7 @@ EXPORT_SYMBOL_GPL(pci_get_dsn); static u8 __pci_find_next_ht_cap(struct pci_dev *dev, u8 pos, int ht_cap) { - int rc, ttl = PCI_FIND_CAP_TTL; + int rc; u8 cap, mask; if (ht_cap == HT_CAPTYPE_SLAVE || ht_cap == HT_CAPTYPE_HOST) @@ -657,7 +623,7 @@ static u8 __pci_find_next_ht_cap(struct pci_dev *dev, u8 pos, int ht_cap) mask = HT_5BIT_CAP_MASK; pos = __pci_find_next_cap_ttl(dev->bus, dev->devfn, pos, - PCI_CAP_ID_HT, &ttl); + PCI_CAP_ID_HT); while (pos) { rc = pci_read_config_byte(dev, pos + 3, &cap); if (rc != PCIBIOS_SUCCESSFUL) @@ -668,7 +634,7 @@ static u8 __pci_find_next_ht_cap(struct pci_dev *dev, u8 pos, int ht_cap) pos = __pci_find_next_cap_ttl(dev->bus, dev->devfn, pos + PCI_CAP_LIST_NEXT, - PCI_CAP_ID_HT, &ttl); + PCI_CAP_ID_HT); } return 0; From patchwork Wed Apr 2 12:37:34 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Hans Zhang <18255117159@163.com> X-Patchwork-Id: 14035912 Received: from m16.mail.163.com (m16.mail.163.com [220.197.31.4]) by smtp.subspace.kernel.org (Postfix) with ESMTP id DA0E7469D; Wed, 2 Apr 2025 12:38:14 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=220.197.31.4 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1743597497; cv=none; b=S0XmH0nGp5Og93802Df/tL7LGb/detfaHLWno4uJ1lrHfR0esdf6NDh+AIAHsNUpqBxVv8yNjkKiy18SSFhoFz2/szBV9nMPPkJHFYqu6Dklpm2MzvdJlS5X2UZqdak4WTQbyVi2VLLWgXuDSspcf+/IoTLDxxfsfd/N8VQLELg= ARC-Message-Signature: i=1; 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d=163.com; s=s110527; h=From:Subject:Date:Message-Id:MIME-Version; bh=iprjK QascAma72b8ssTYfHVklAFJft/JzeNryBFLrLc=; b=IP2AtXi+ruDFBP/1N4g7T oMu9i3Medo0Yn/4XLc6yCfnQt8+aRLxctce+5x6sMr0rDX0Dn7kzD9OohMcReS+6 ER3cFsV4SgQcuIrIWAQ1FqeMHemVnCztFvNEGO67anMZf/uqGyLA7At3QntRo+Rj ZaZ1kTNIiLit+N172USnAY= Received: from localhost.localdomain (unknown []) by gzsmtp1 (Coremail) with SMTP id PCgvCgCXrkiUL+1nL3+IAA--.22499S5; Wed, 02 Apr 2025 20:37:48 +0800 (CST) From: Hans Zhang <18255117159@163.com> To: lpieralisi@kernel.org, bhelgaas@google.com Cc: kw@linux.com, manivannan.sadhasivam@linaro.org, ilpo.jarvinen@linux.intel.com, robh@kernel.org, jingoohan1@gmail.com, thomas.richard@bootlin.com, linux-pci@vger.kernel.org, linux-kernel@vger.kernel.org, Hans Zhang <18255117159@163.com> Subject: [v8 3/5] PCI: dwc: Use common PCI host bridge APIs for finding the capabilities Date: Wed, 2 Apr 2025 20:37:34 +0800 Message-Id: <20250402123736.55995-4-18255117159@163.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20250402123736.55995-1-18255117159@163.com> References: <20250402123736.55995-1-18255117159@163.com> Precedence: bulk X-Mailing-List: linux-pci@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-CM-TRANSID: PCgvCgCXrkiUL+1nL3+IAA--.22499S5 X-Coremail-Antispam: 1Uf129KBjvJXoWxuryrKFW8KrWDCry8Jw1DJrb_yoW5Aw18pa yrAa4Fkr4rtr4Yqw4qv3ZIyF13AF9xAa47Aa97Gw1SvF12krW3K340kayaqF1IkrZF9F13 Kr4UtFyrCw1kJFDanT9S1TB71UUUUU7qnTZGkaVYY2UrUUUUjbIjqfuFe4nvWSU5nxnvy2 9KBjDUYxBIdaVFxhVjvjDU0xZFpf9x07UYApwUUUUU= X-CM-SenderInfo: rpryjkyvrrlimvzbiqqrwthudrp/1tbiWxYjo2ftKgmL8QACsc Use the PCI core is now exposing generic macros for the host bridges to search for the PCIe capabilities, make use of them in the DWC driver. Signed-off-by: Hans Zhang <18255117159@163.com> --- Changes since v7: https://lore.kernel.org/linux-pci/20250402042020.48681-4-18255117159@163.com/ - Resolve compilation errors. --- drivers/pci/controller/dwc/pcie-designware.c | 72 ++------------------ 1 file changed, 7 insertions(+), 65 deletions(-) diff --git a/drivers/pci/controller/dwc/pcie-designware.c b/drivers/pci/controller/dwc/pcie-designware.c index 145e7f579072..af6a4930f6a9 100644 --- a/drivers/pci/controller/dwc/pcie-designware.c +++ b/drivers/pci/controller/dwc/pcie-designware.c @@ -203,83 +203,25 @@ void dw_pcie_version_detect(struct dw_pcie *pci) pci->type = ver; } -/* - * These interfaces resemble the pci_find_*capability() interfaces, but these - * are for configuring host controllers, which are bridges *to* PCI devices but - * are not PCI devices themselves. - */ -static u8 __dw_pcie_find_next_cap(struct dw_pcie *pci, u8 cap_ptr, - u8 cap) +static int dw_pcie_read_cfg(void *priv, int where, int size, u32 *val) { - u8 cap_id, next_cap_ptr; - u16 reg; - - if (!cap_ptr) - return 0; - - reg = dw_pcie_readw_dbi(pci, cap_ptr); - cap_id = (reg & 0x00ff); - - if (cap_id > PCI_CAP_ID_MAX) - return 0; + struct dw_pcie *pcie = priv; - if (cap_id == cap) - return cap_ptr; + *val = dw_pcie_read_dbi(pcie, where, size); - next_cap_ptr = (reg & 0xff00) >> 8; - return __dw_pcie_find_next_cap(pci, next_cap_ptr, cap); + return PCIBIOS_SUCCESSFUL; } u8 dw_pcie_find_capability(struct dw_pcie *pci, u8 cap) { - u8 next_cap_ptr; - u16 reg; - - reg = dw_pcie_readw_dbi(pci, PCI_CAPABILITY_LIST); - next_cap_ptr = (reg & 0x00ff); - - return __dw_pcie_find_next_cap(pci, next_cap_ptr, cap); + return PCI_FIND_NEXT_CAP_TTL(dw_pcie_read_cfg, PCI_CAPABILITY_LIST, cap, + pci); } EXPORT_SYMBOL_GPL(dw_pcie_find_capability); -static u16 dw_pcie_find_next_ext_capability(struct dw_pcie *pci, u16 start, - u8 cap) -{ - u32 header; - int ttl; - int pos = PCI_CFG_SPACE_SIZE; - - /* minimum 8 bytes per capability */ - ttl = (PCI_CFG_SPACE_EXP_SIZE - PCI_CFG_SPACE_SIZE) / 8; - - if (start) - pos = start; - - header = dw_pcie_readl_dbi(pci, pos); - /* - * If we have no capabilities, this is indicated by cap ID, - * cap version and next pointer all being 0. - */ - if (header == 0) - return 0; - - while (ttl-- > 0) { - if (PCI_EXT_CAP_ID(header) == cap && pos != start) - return pos; - - pos = PCI_EXT_CAP_NEXT(header); - if (pos < PCI_CFG_SPACE_SIZE) - break; - - header = dw_pcie_readl_dbi(pci, pos); - } - - return 0; -} - u16 dw_pcie_find_ext_capability(struct dw_pcie *pci, u8 cap) { - return dw_pcie_find_next_ext_capability(pci, 0, cap); + return PCI_FIND_NEXT_EXT_CAPABILITY(dw_pcie_read_cfg, 0, cap, pci); } EXPORT_SYMBOL_GPL(dw_pcie_find_ext_capability); From patchwork Wed Apr 2 12:37:35 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Hans Zhang <18255117159@163.com> X-Patchwork-Id: 14035914 Received: from m16.mail.163.com (m16.mail.163.com [220.197.31.3]) by smtp.subspace.kernel.org (Postfix) with ESMTP id 29EBB1E50B; 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arc=none smtp.client-ip=220.197.31.3 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=163.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=163.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=163.com header.i=@163.com header.b="jwkGt0WP" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=163.com; s=s110527; h=From:Subject:Date:Message-Id:MIME-Version; bh=CoW96 e1Gmdd0kpTwykWsVW5WBGKPsLmM7zi76qOXnbA=; b=jwkGt0WPt55zHU5QzhJdP TBzkXf2OtItXw580fbx2S0E87U57hNGLts9+icypahA7F4wVWF00k1gcvYJRlHSe 06D4ll+VoJRotYGCgsqlgNRk45tc2NL6wdfAVIiUB8FNJzl1DvDiIXtEy46p7ztS Pg2oiNme9hfVk64o9VyIho= Received: from localhost.localdomain (unknown []) by gzsmtp1 (Coremail) with SMTP id PCgvCgCXrkiUL+1nL3+IAA--.22499S6; Wed, 02 Apr 2025 20:37:50 +0800 (CST) From: Hans Zhang <18255117159@163.com> To: lpieralisi@kernel.org, bhelgaas@google.com Cc: kw@linux.com, manivannan.sadhasivam@linaro.org, ilpo.jarvinen@linux.intel.com, robh@kernel.org, jingoohan1@gmail.com, thomas.richard@bootlin.com, linux-pci@vger.kernel.org, linux-kernel@vger.kernel.org, Hans Zhang <18255117159@163.com> Subject: [v8 4/5] PCI: cadence: Use common PCI host bridge APIs for finding the capabilities Date: Wed, 2 Apr 2025 20:37:35 +0800 Message-Id: <20250402123736.55995-5-18255117159@163.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20250402123736.55995-1-18255117159@163.com> References: <20250402123736.55995-1-18255117159@163.com> Precedence: bulk X-Mailing-List: linux-pci@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-CM-TRANSID: PCgvCgCXrkiUL+1nL3+IAA--.22499S6 X-Coremail-Antispam: 1Uf129KBjvJXoWxuryrAr48Cw4rur1kCF4UJwb_yoW5Cw1fpF WDGFyfCF1rJFW3uFs3Z3W5Xr13tFnay347ta92k347ZF17Cr1UGFy2gFy3tr9xKrs7Gr13 X3yDtFykKrn0yFUanT9S1TB71UUUUU7qnTZGkaVYY2UrUUUUjbIjqfuFe4nvWSU5nxnvy2 9KBjDUYxBIdaVFxhVjvjDU0xZFpf9x0ziID7hUUUUU= X-CM-SenderInfo: rpryjkyvrrlimvzbiqqrwthudrp/xtbBDwsjo2ftJx3gbQABs4 Use the PCI core is now exposing generic macros for the host bridges to search for the PCIe capabilities, make use of them in the CDNS driver. Signed-off-by: Hans Zhang <18255117159@163.com> --- Changes since v6: https://lore.kernel.org/linux-pci/20250323164852.430546-4-18255117159@163.com/ - The patch commit message were modified. Changes since v5: https://lore.kernel.org/linux-pci/20250321163803.391056-4-18255117159@163.com - Kconfig add "select PCI_HOST_HELPERS" --- drivers/pci/controller/cadence/pcie-cadence.c | 28 +++++++++++++++++++ drivers/pci/controller/cadence/pcie-cadence.h | 13 +++++++++ 2 files changed, 41 insertions(+) diff --git a/drivers/pci/controller/cadence/pcie-cadence.c b/drivers/pci/controller/cadence/pcie-cadence.c index 204e045aed8c..ca4a1a809fcb 100644 --- a/drivers/pci/controller/cadence/pcie-cadence.c +++ b/drivers/pci/controller/cadence/pcie-cadence.c @@ -7,6 +7,34 @@ #include #include "pcie-cadence.h" +#include "../../pci.h" + +static int cdns_pcie_read_cfg(void *priv, int where, int size, u32 *val) +{ + struct cdns_pcie *pcie = priv; + + if (size == 4) + *val = cdns_pcie_readl(pcie, where); + else if (size == 2) + *val = cdns_pcie_readw(pcie, where); + else if (size == 1) + *val = cdns_pcie_readb(pcie, where); + + return PCIBIOS_SUCCESSFUL; +} + +u8 cdns_pcie_find_capability(struct cdns_pcie *pcie, u8 cap) +{ + return PCI_FIND_NEXT_CAP_TTL(cdns_pcie_read_cfg, PCI_CAPABILITY_LIST, + cap, pcie); +} +EXPORT_SYMBOL_GPL(cdns_pcie_find_capability); + +u16 cdns_pcie_find_ext_capability(struct cdns_pcie *pcie, u8 cap) +{ + return PCI_FIND_NEXT_EXT_CAPABILITY(cdns_pcie_read_cfg, 0, cap, pcie); +} +EXPORT_SYMBOL_GPL(cdns_pcie_find_ext_capability); void cdns_pcie_detect_quiet_min_delay_set(struct cdns_pcie *pcie) { diff --git a/drivers/pci/controller/cadence/pcie-cadence.h b/drivers/pci/controller/cadence/pcie-cadence.h index f5eeff834ec1..dd7cb6b6b291 100644 --- a/drivers/pci/controller/cadence/pcie-cadence.h +++ b/drivers/pci/controller/cadence/pcie-cadence.h @@ -398,6 +398,16 @@ static inline u32 cdns_pcie_readl(struct cdns_pcie *pcie, u32 reg) return readl(pcie->reg_base + reg); } +static inline u32 cdns_pcie_readw(struct cdns_pcie *pcie, u32 reg) +{ + return readw(pcie->reg_base + reg); +} + +static inline u32 cdns_pcie_readb(struct cdns_pcie *pcie, u32 reg) +{ + return readb(pcie->reg_base + reg); +} + static inline u32 cdns_pcie_read_sz(void __iomem *addr, int size) { void __iomem *aligned_addr = PTR_ALIGN_DOWN(addr, 0x4); @@ -557,6 +567,9 @@ static inline int cdns_pcie_ep_setup(struct cdns_pcie_ep *ep) } #endif +u8 cdns_pcie_find_capability(struct cdns_pcie *pcie, u8 cap); +u16 cdns_pcie_find_ext_capability(struct cdns_pcie *pcie, u8 cap); + void cdns_pcie_detect_quiet_min_delay_set(struct cdns_pcie *pcie); void cdns_pcie_set_outbound_region(struct cdns_pcie *pcie, u8 busnr, u8 fn, From patchwork Wed Apr 2 12:37:36 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Hans Zhang <18255117159@163.com> X-Patchwork-Id: 14035917 Received: from m16.mail.163.com (m16.mail.163.com [117.135.210.2]) by smtp.subspace.kernel.org (Postfix) with ESMTP id E608B23BCF6; Wed, 2 Apr 2025 12:38:22 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=117.135.210.2 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1743597505; cv=none; b=JATl4shVYPo6iha8sOZSv9qcg0odP3ljGUNYTwqjg58j8w1F35YqOQl2ma15Nk3UvMvEEanrwxC6mT5rJydi6GK6mHXZVCJQxO7t7pdJavlAuSeP1BC1V3N46LMIRg1F9/OCmRUqVseLni8u35fbjZKlY6lURy43hbiJJq9ZRpI= ARC-Message-Signature: i=1; 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d=163.com; s=s110527; h=From:Subject:Date:Message-Id:MIME-Version; bh=3pdrC OxR6siQiayEEylQqqJe1i5VAX0C977IX+Taf2k=; b=J6fv3WQlJfYkAe7ZMEtTQ QqcRkOgpJbldKtmrfcHZoDbQbwYkz1UZZD7gr77M9UMSVF+6W1semVUkfHTo+etQ db86Oz/NFVDLyYx+IjsH/0r/KUNdNH+MJBy4FxaDIqnCbTGe45is5t12adAZUZ65 HwGBRvEfSAe84GWqrFr5nw= Received: from localhost.localdomain (unknown []) by gzsmtp1 (Coremail) with SMTP id PCgvCgCXrkiUL+1nL3+IAA--.22499S7; Wed, 02 Apr 2025 20:37:50 +0800 (CST) From: Hans Zhang <18255117159@163.com> To: lpieralisi@kernel.org, bhelgaas@google.com Cc: kw@linux.com, manivannan.sadhasivam@linaro.org, ilpo.jarvinen@linux.intel.com, robh@kernel.org, jingoohan1@gmail.com, thomas.richard@bootlin.com, linux-pci@vger.kernel.org, linux-kernel@vger.kernel.org, Hans Zhang <18255117159@163.com> Subject: [v8 5/5] PCI: cadence: Use cdns_pcie_find_*capability to avoid hardcode. Date: Wed, 2 Apr 2025 20:37:36 +0800 Message-Id: <20250402123736.55995-6-18255117159@163.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20250402123736.55995-1-18255117159@163.com> References: <20250402123736.55995-1-18255117159@163.com> Precedence: bulk X-Mailing-List: linux-pci@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-CM-TRANSID: PCgvCgCXrkiUL+1nL3+IAA--.22499S7 X-Coremail-Antispam: 1Uf129KBjvJXoW3JF1xAFy3Jw43GF17ur18AFb_yoWxCr4fpF W5ua4SkF40qrW7uFsrAa15ZrnxtFnIv347Aa92kw1ruF129FyUGFyIva43KF1akrs7uF17 XrWDtrsa93W3trUanT9S1TB71UUUUU7qnTZGkaVYY2UrUUUUjbIjqfuFe4nvWSU5nxnvy2 9KBjDUYxBIdaVFxhVjvjDU0xZFpf9x0ziID7hUUUUU= X-CM-SenderInfo: rpryjkyvrrlimvzbiqqrwthudrp/xtbBDw4jo2ftJx3gpgAAs3 The PCIe capability/extended capability offsets are not guaranteed to be the same across all SoCs integrating the Cadence PCIe IP. Hence, use the cdns_pcie_find_{ext}_capability() APIs for finding them. This avoids hardcoding the offsets in the driver. Signed-off-by: Hans Zhang <18255117159@163.com> --- Changes since v5~v7: - None Changes since v4: https://lore.kernel.org/linux-pci/20250321101710.371480-5-18255117159@163.com/ - The patch subject and commit message were modified. --- .../pci/controller/cadence/pcie-cadence-ep.c | 40 +++++++++++-------- drivers/pci/controller/cadence/pcie-cadence.h | 5 --- 2 files changed, 23 insertions(+), 22 deletions(-) diff --git a/drivers/pci/controller/cadence/pcie-cadence-ep.c b/drivers/pci/controller/cadence/pcie-cadence-ep.c index e0cc4560dfde..aea53ddcaf9b 100644 --- a/drivers/pci/controller/cadence/pcie-cadence-ep.c +++ b/drivers/pci/controller/cadence/pcie-cadence-ep.c @@ -19,12 +19,13 @@ static u8 cdns_pcie_get_fn_from_vfn(struct cdns_pcie *pcie, u8 fn, u8 vfn) { - u32 cap = CDNS_PCIE_EP_FUNC_SRIOV_CAP_OFFSET; u32 first_vf_offset, stride; + u16 cap; if (vfn == 0) return fn; + cap = cdns_pcie_find_ext_capability(pcie, PCI_EXT_CAP_ID_SRIOV); first_vf_offset = cdns_pcie_ep_fn_readw(pcie, fn, cap + PCI_SRIOV_VF_OFFSET); stride = cdns_pcie_ep_fn_readw(pcie, fn, cap + PCI_SRIOV_VF_STRIDE); fn = fn + first_vf_offset + ((vfn - 1) * stride); @@ -36,10 +37,11 @@ static int cdns_pcie_ep_write_header(struct pci_epc *epc, u8 fn, u8 vfn, struct pci_epf_header *hdr) { struct cdns_pcie_ep *ep = epc_get_drvdata(epc); - u32 cap = CDNS_PCIE_EP_FUNC_SRIOV_CAP_OFFSET; struct cdns_pcie *pcie = &ep->pcie; u32 reg; + u16 cap; + cap = cdns_pcie_find_ext_capability(pcie, PCI_EXT_CAP_ID_SRIOV); if (vfn > 1) { dev_err(&epc->dev, "Only Virtual Function #1 has deviceID\n"); return -EINVAL; @@ -224,9 +226,10 @@ static int cdns_pcie_ep_set_msi(struct pci_epc *epc, u8 fn, u8 vfn, u8 mmc) { struct cdns_pcie_ep *ep = epc_get_drvdata(epc); struct cdns_pcie *pcie = &ep->pcie; - u32 cap = CDNS_PCIE_EP_FUNC_MSI_CAP_OFFSET; u16 flags; + u8 cap; + cap = cdns_pcie_find_capability(pcie, PCI_CAP_ID_MSI); fn = cdns_pcie_get_fn_from_vfn(pcie, fn, vfn); /* @@ -246,9 +249,10 @@ static int cdns_pcie_ep_get_msi(struct pci_epc *epc, u8 fn, u8 vfn) { struct cdns_pcie_ep *ep = epc_get_drvdata(epc); struct cdns_pcie *pcie = &ep->pcie; - u32 cap = CDNS_PCIE_EP_FUNC_MSI_CAP_OFFSET; u16 flags, mme; + u8 cap; + cap = cdns_pcie_find_capability(pcie, PCI_CAP_ID_MSI); fn = cdns_pcie_get_fn_from_vfn(pcie, fn, vfn); /* Validate that the MSI feature is actually enabled. */ @@ -269,9 +273,10 @@ static int cdns_pcie_ep_get_msix(struct pci_epc *epc, u8 func_no, u8 vfunc_no) { struct cdns_pcie_ep *ep = epc_get_drvdata(epc); struct cdns_pcie *pcie = &ep->pcie; - u32 cap = CDNS_PCIE_EP_FUNC_MSIX_CAP_OFFSET; u32 val, reg; + u8 cap; + cap = cdns_pcie_find_capability(pcie, PCI_CAP_ID_MSIX); func_no = cdns_pcie_get_fn_from_vfn(pcie, func_no, vfunc_no); reg = cap + PCI_MSIX_FLAGS; @@ -290,9 +295,10 @@ static int cdns_pcie_ep_set_msix(struct pci_epc *epc, u8 fn, u8 vfn, { struct cdns_pcie_ep *ep = epc_get_drvdata(epc); struct cdns_pcie *pcie = &ep->pcie; - u32 cap = CDNS_PCIE_EP_FUNC_MSIX_CAP_OFFSET; u32 val, reg; + u8 cap; + cap = cdns_pcie_find_capability(pcie, PCI_CAP_ID_MSIX); fn = cdns_pcie_get_fn_from_vfn(pcie, fn, vfn); reg = cap + PCI_MSIX_FLAGS; @@ -379,11 +385,11 @@ static int cdns_pcie_ep_send_msi_irq(struct cdns_pcie_ep *ep, u8 fn, u8 vfn, u8 interrupt_num) { struct cdns_pcie *pcie = &ep->pcie; - u32 cap = CDNS_PCIE_EP_FUNC_MSI_CAP_OFFSET; u16 flags, mme, data, data_mask; - u8 msi_count; u64 pci_addr, pci_addr_mask = 0xff; + u8 msi_count, cap; + cap = cdns_pcie_find_capability(pcie, PCI_CAP_ID_MSI); fn = cdns_pcie_get_fn_from_vfn(pcie, fn, vfn); /* Check whether the MSI feature has been enabled by the PCI host. */ @@ -431,14 +437,14 @@ static int cdns_pcie_ep_map_msi_irq(struct pci_epc *epc, u8 fn, u8 vfn, u32 *msi_addr_offset) { struct cdns_pcie_ep *ep = epc_get_drvdata(epc); - u32 cap = CDNS_PCIE_EP_FUNC_MSI_CAP_OFFSET; struct cdns_pcie *pcie = &ep->pcie; u64 pci_addr, pci_addr_mask = 0xff; u16 flags, mme, data, data_mask; - u8 msi_count; + u8 msi_count, cap; int ret; int i; + cap = cdns_pcie_find_capability(pcie, PCI_CAP_ID_MSI); fn = cdns_pcie_get_fn_from_vfn(pcie, fn, vfn); /* Check whether the MSI feature has been enabled by the PCI host. */ @@ -481,16 +487,16 @@ static int cdns_pcie_ep_map_msi_irq(struct pci_epc *epc, u8 fn, u8 vfn, static int cdns_pcie_ep_send_msix_irq(struct cdns_pcie_ep *ep, u8 fn, u8 vfn, u16 interrupt_num) { - u32 cap = CDNS_PCIE_EP_FUNC_MSIX_CAP_OFFSET; u32 tbl_offset, msg_data, reg; struct cdns_pcie *pcie = &ep->pcie; struct pci_epf_msix_tbl *msix_tbl; struct cdns_pcie_epf *epf; u64 pci_addr_mask = 0xff; u64 msg_addr; + u8 bir, cap; u16 flags; - u8 bir; + cap = cdns_pcie_find_capability(pcie, PCI_CAP_ID_MSIX); epf = &ep->epf[fn]; if (vfn > 0) epf = &epf->epf[vfn - 1]; @@ -564,7 +570,9 @@ static int cdns_pcie_ep_start(struct pci_epc *epc) int max_epfs = sizeof(epc->function_num_map) * 8; int ret, epf, last_fn; u32 reg, value; + u8 cap; + cap = cdns_pcie_find_capability(pcie, PCI_CAP_ID_EXP); /* * BIT(0) is hardwired to 1, hence function 0 is always enabled * and can't be disabled anyway. @@ -588,12 +596,10 @@ static int cdns_pcie_ep_start(struct pci_epc *epc) continue; value = cdns_pcie_ep_fn_readl(pcie, epf, - CDNS_PCIE_EP_FUNC_DEV_CAP_OFFSET + - PCI_EXP_DEVCAP); + cap + PCI_EXP_DEVCAP); value &= ~PCI_EXP_DEVCAP_FLR; - cdns_pcie_ep_fn_writel(pcie, epf, - CDNS_PCIE_EP_FUNC_DEV_CAP_OFFSET + - PCI_EXP_DEVCAP, value); + cdns_pcie_ep_fn_writel(pcie, epf, cap + PCI_EXP_DEVCAP, + value); } } diff --git a/drivers/pci/controller/cadence/pcie-cadence.h b/drivers/pci/controller/cadence/pcie-cadence.h index dd7cb6b6b291..3cfef0b25988 100644 --- a/drivers/pci/controller/cadence/pcie-cadence.h +++ b/drivers/pci/controller/cadence/pcie-cadence.h @@ -125,11 +125,6 @@ */ #define CDNS_PCIE_EP_FUNC_BASE(fn) (((fn) << 12) & GENMASK(19, 12)) -#define CDNS_PCIE_EP_FUNC_MSI_CAP_OFFSET 0x90 -#define CDNS_PCIE_EP_FUNC_MSIX_CAP_OFFSET 0xb0 -#define CDNS_PCIE_EP_FUNC_DEV_CAP_OFFSET 0xc0 -#define CDNS_PCIE_EP_FUNC_SRIOV_CAP_OFFSET 0x200 - /* * Endpoint PF Registers */