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[103.229.18.19]) by smtp.gmail.com with ESMTPSA id 98e67ed59e1d1-305827d710csm1285799a91.10.2025.04.03.05.03.11 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 03 Apr 2025 05:03:14 -0700 (PDT) From: Gokul Sriram Palanisamy To: andersson@kernel.org, mathieu.poirier@linaro.org, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, konradybcio@kernel.org, quic_mmanikan@quicinc.com, linux-arm-msm@vger.kernel.org, linux-remoteproc@vger.kernel.org, devicetree@vger.kernel.org Cc: quic_srichara@quicinc.com, vignesh.viswanathan@oss.qualcomm.com, gokul.sriram.p@oss.qualcomm.com Subject: [PATCH V4 1/8] firmware: qcom_scm: ipq5332: add support to pass metadata size Date: Thu, 3 Apr 2025 17:32:57 +0530 Message-Id: <20250403120304.2345677-2-gokul.sriram.p@oss.qualcomm.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20250403120304.2345677-1-gokul.sriram.p@oss.qualcomm.com> References: <20250403120304.2345677-1-gokul.sriram.p@oss.qualcomm.com> Precedence: bulk X-Mailing-List: linux-arm-msm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-Proofpoint-GUID: Soyey6u6vukXm1LsUfpW-qTe022cujI3 X-Proofpoint-ORIG-GUID: Soyey6u6vukXm1LsUfpW-qTe022cujI3 X-Authority-Analysis: v=2.4 cv=PNAP+eqC c=1 sm=1 tr=0 ts=67ee7903 cx=c_pps a=Qgeoaf8Lrialg5Z894R3/Q==:117 a=Ou0eQOY4+eZoSc0qltEV5Q==:17 a=XR8D0OoHHMoA:10 a=COk6AnOGAAAA:8 a=EUspDBNiAAAA:8 a=uWiwPwd6ELW8fYEcJRYA:9 a=x9snwWr2DeNwDh03kgHS:22 a=TjNXssC_j7lpFel5tvFf:22 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1095,Hydra:6.0.680,FMLib:17.12.68.34 definitions=2025-04-03_05,2025-04-02_03,2024-11-22_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 spamscore=0 suspectscore=0 malwarescore=0 adultscore=0 phishscore=0 clxscore=1015 mlxscore=0 lowpriorityscore=0 impostorscore=0 mlxlogscore=999 priorityscore=1501 bulkscore=0 classifier=spam authscore=0 authtc=n/a authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.19.0-2502280000 definitions=main-2504030049 From: Manikanta Mylavarapu IPQ5332 security software running under trustzone requires metadata size. With new command support added in TrustZone that includes a size parameter, pass metadata size as well. Signed-off-by: Manikanta Mylavarapu Signed-off-by: Gokul Sriram Palanisamy Reviewed-by: Konrad Dybcio --- drivers/firmware/qcom/qcom_scm.c | 17 +++++++++++++---- drivers/firmware/qcom/qcom_scm.h | 1 + 2 files changed, 14 insertions(+), 4 deletions(-) diff --git a/drivers/firmware/qcom/qcom_scm.c b/drivers/firmware/qcom/qcom_scm.c index fc4d67e4c4a6..456e4de538b2 100644 --- a/drivers/firmware/qcom/qcom_scm.c +++ b/drivers/firmware/qcom/qcom_scm.c @@ -583,9 +583,6 @@ int qcom_scm_pas_init_image(u32 peripheral, const void *metadata, size_t size, int ret; struct qcom_scm_desc desc = { .svc = QCOM_SCM_SVC_PIL, - .cmd = QCOM_SCM_PIL_PAS_INIT_IMAGE, - .arginfo = QCOM_SCM_ARGS(2, QCOM_SCM_VAL, QCOM_SCM_RW), - .args[0] = peripheral, .owner = ARM_SMCCC_OWNER_SIP, }; struct qcom_scm_res res; @@ -617,7 +614,19 @@ int qcom_scm_pas_init_image(u32 peripheral, const void *metadata, size_t size, if (ret) goto disable_clk; - desc.args[1] = mdata_phys; + if (__qcom_scm_is_call_available(__scm->dev, QCOM_SCM_SVC_PIL, + QCOM_SCM_PIL_PAS_INIT_IMAGE_V2)) { + desc.cmd = QCOM_SCM_PIL_PAS_INIT_IMAGE_V2; + desc.arginfo = QCOM_SCM_ARGS(3, QCOM_SCM_VAL, QCOM_SCM_RW, QCOM_SCM_VAL); + desc.args[0] = peripheral; + desc.args[1] = mdata_phys; + desc.args[2] = size; + } else { + desc.cmd = QCOM_SCM_PIL_PAS_INIT_IMAGE; + desc.arginfo = QCOM_SCM_ARGS(2, QCOM_SCM_VAL, QCOM_SCM_RW); + desc.args[0] = peripheral; + desc.args[1] = mdata_phys; + } ret = qcom_scm_call(__scm->dev, &desc, &res); qcom_scm_bw_disable(); diff --git a/drivers/firmware/qcom/qcom_scm.h b/drivers/firmware/qcom/qcom_scm.h index 097369d38b84..0f40e5828a67 100644 --- a/drivers/firmware/qcom/qcom_scm.h +++ b/drivers/firmware/qcom/qcom_scm.h @@ -96,6 +96,7 @@ struct qcom_tzmem_pool *qcom_scm_get_tzmem_pool(void); #define QCOM_SCM_SVC_PIL 0x02 #define QCOM_SCM_PIL_PAS_INIT_IMAGE 0x01 +#define QCOM_SCM_PIL_PAS_INIT_IMAGE_V2 0x1a #define QCOM_SCM_PIL_PAS_MEM_SETUP 0x02 #define QCOM_SCM_PIL_PAS_AUTH_AND_RESET 0x05 #define QCOM_SCM_PIL_PAS_SHUTDOWN 0x06 From patchwork Thu Apr 3 12:02:58 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Gokul Sriram P X-Patchwork-Id: 14036858 Received: from mx0a-0031df01.pphosted.com (mx0a-0031df01.pphosted.com [205.220.168.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id BC9DF24C097 for ; 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[103.229.18.19]) by smtp.gmail.com with ESMTPSA id 98e67ed59e1d1-305827d710csm1285799a91.10.2025.04.03.05.03.14 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 03 Apr 2025 05:03:18 -0700 (PDT) From: Gokul Sriram Palanisamy To: andersson@kernel.org, mathieu.poirier@linaro.org, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, konradybcio@kernel.org, quic_mmanikan@quicinc.com, linux-arm-msm@vger.kernel.org, linux-remoteproc@vger.kernel.org, devicetree@vger.kernel.org Cc: quic_srichara@quicinc.com, vignesh.viswanathan@oss.qualcomm.com, gokul.sriram.p@oss.qualcomm.com Subject: [PATCH V4 2/8] dt-bindings: remoteproc: qcom: document hexagon based WCSS secure PIL Date: Thu, 3 Apr 2025 17:32:58 +0530 Message-Id: <20250403120304.2345677-3-gokul.sriram.p@oss.qualcomm.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20250403120304.2345677-1-gokul.sriram.p@oss.qualcomm.com> References: <20250403120304.2345677-1-gokul.sriram.p@oss.qualcomm.com> Precedence: bulk X-Mailing-List: linux-arm-msm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-Authority-Analysis: v=2.4 cv=VI/dn8PX c=1 sm=1 tr=0 ts=67ee7907 cx=c_pps a=rz3CxIlbcmazkYymdCej/Q==:117 a=Ou0eQOY4+eZoSc0qltEV5Q==:17 a=XR8D0OoHHMoA:10 a=gEfo2CItAAAA:8 a=COk6AnOGAAAA:8 a=KKAkSRfTAAAA:8 a=EUspDBNiAAAA:8 a=pS1mFShvCYhk9e5rTeIA:9 a=bFCP_H2QrGi7Okbo017w:22 a=sptkURWiP4Gy88Gu7hUp:22 a=TjNXssC_j7lpFel5tvFf:22 a=cvBusfyB2V15izCimMoJ:22 X-Proofpoint-ORIG-GUID: 1XDPnk00pMFi3_TmmcJ9F-p97XMBT3tX X-Proofpoint-GUID: 1XDPnk00pMFi3_TmmcJ9F-p97XMBT3tX X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1095,Hydra:6.0.680,FMLib:17.12.68.34 definitions=2025-04-03_05,2025-04-02_03,2024-11-22_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 spamscore=0 clxscore=1011 priorityscore=1501 mlxscore=0 adultscore=0 suspectscore=0 impostorscore=0 phishscore=0 lowpriorityscore=0 mlxlogscore=999 malwarescore=0 bulkscore=0 classifier=spam authscore=0 authtc=n/a authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.19.0-2502280000 definitions=main-2504030050 From: Manikanta Mylavarapu Add new binding document for hexagon based WCSS secure PIL. All IPQ SoCs use secure PIL. Reviewed-by: Krzysztof Kozlowski Signed-off-by: Manikanta Mylavarapu Signed-off-by: Gokul Sriram Palanisamy --- .../remoteproc/qcom,wcss-sec-pil.yaml | 146 ++++++++++++++++++ 1 file changed, 146 insertions(+) create mode 100644 Documentation/devicetree/bindings/remoteproc/qcom,wcss-sec-pil.yaml diff --git a/Documentation/devicetree/bindings/remoteproc/qcom,wcss-sec-pil.yaml b/Documentation/devicetree/bindings/remoteproc/qcom,wcss-sec-pil.yaml new file mode 100644 index 000000000000..d427470f20fd --- /dev/null +++ b/Documentation/devicetree/bindings/remoteproc/qcom,wcss-sec-pil.yaml @@ -0,0 +1,146 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/remoteproc/qcom,wcss-sec-pil.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm WCSS Secure Peripheral Image Loader + +maintainers: + - Manikanta Mylavarapu + +description: + Wireless Connectivity Subsystem (WCSS) Secure Peripheral Image Loader loads + firmware and power up QDSP6 remoteproc on the Qualcomm IPQ series SoC. + +properties: + compatible: + enum: + - qcom,ipq5332-wcss-sec-pil + - qcom,ipq5424-wcss-sec-pil + - qcom,ipq9574-wcss-sec-pil + + reg: + maxItems: 1 + + firmware-name: + items: + - description: Firmware name for the Hexagon core + - description: Firmware name for the Hexagon devicetree + + interrupts: + items: + - description: Watchdog interrupt + - description: Fatal interrupt + - description: Ready interrupt + - description: Handover interrupt + - description: Stop acknowledge interrupt + + interrupt-names: + items: + - const: wdog + - const: fatal + - const: ready + - const: handover + - const: stop-ack + + clocks: + items: + - description: sleep clock + + clock-names: + items: + - const: sleep + + mboxes: + maxItems: 1 + description: A phandle for the TMECom mailbox driver + + qcom,smem-states: + $ref: /schemas/types.yaml#/definitions/phandle-array + description: States used by the AP to signal the remote processor + items: + - description: Stop Q6 + - description: Shutdown Q6 + + qcom,smem-state-names: + description: + Names of the states used by the AP to signal the remote processor + items: + - const: stop + - const: shutdown + + memory-region: + minItems: 1 + items: + - description: Q6 reserved region + - description: Q6 dtb reserved region + + qcom,q6-dtb-info: + $ref: /schemas/types.yaml#/definitions/phandle-array + items: + - items: + - description: phandle to TCSR hardware block + - description: TCSR offset to write lower-order 32-bit physical address of dtb + - description: TCSR offset to write higher-order 32-bit physical address of dtb + - description: TCSR offset to write board machid + description: Q6 device-tree information + + glink-edge: + $ref: /schemas/remoteproc/qcom,glink-edge.yaml# + description: + Qualcomm G-Link subnode which represents communication edge, channels + and devices related to the Modem. + unevaluatedProperties: false + +required: + - compatible + - reg + - firmware-name + - interrupts + - interrupt-names + - qcom,smem-states + - qcom,smem-state-names + - memory-region + +additionalProperties: false + +examples: + - | + #include + #include + remoteproc@d100000 { + compatible = "qcom,ipq5332-wcss-sec-pil"; + reg = <0xd100000 0x4040>; + firmware-name = "ath12k/IPQ5332/hw1.0/q6_fw.mbn", + "ath12k/IPQ5332/hw1.0/qdsp6sw_dtb.mbn"; + interrupts-extended = <&intc GIC_SPI 291 IRQ_TYPE_EDGE_RISING>, + <&wcss_smp2p_in 0 IRQ_TYPE_NONE>, + <&wcss_smp2p_in 1 IRQ_TYPE_NONE>, + <&wcss_smp2p_in 2 IRQ_TYPE_NONE>, + <&wcss_smp2p_in 3 IRQ_TYPE_NONE>; + interrupt-names = "wdog", + "fatal", + "ready", + "handover", + "stop-ack"; + + clocks = <&gcc GCC_IM_SLEEP_CLK>; + clock-names = "sleep"; + + mboxes = <&tmel_qmp 0>; + qcom,smem-states = <&wcss_smp2p_out 1>, + <&wcss_smp2p_out 0>; + qcom,smem-state-names = "stop", + "shutdown"; + + memory-region = <&q6_region>, <&q6_dtb_region>; + qcom,q6-dtb-info = <&tcsr 0x1f004 0x1f008 0x1f00c>; + + glink-edge { + interrupts = ; + label = "rtr"; + qcom,remote-pid = <1>; + mboxes = <&apcs_glb 8>; + }; + }; From patchwork Thu Apr 3 12:02:59 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Gokul Sriram P X-Patchwork-Id: 14036859 Received: from mx0a-0031df01.pphosted.com (mx0a-0031df01.pphosted.com [205.220.168.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id DD9F21EF0B6 for ; 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[103.229.18.19]) by smtp.gmail.com with ESMTPSA id 98e67ed59e1d1-305827d710csm1285799a91.10.2025.04.03.05.03.18 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 03 Apr 2025 05:03:21 -0700 (PDT) From: Gokul Sriram Palanisamy To: andersson@kernel.org, mathieu.poirier@linaro.org, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, konradybcio@kernel.org, quic_mmanikan@quicinc.com, linux-arm-msm@vger.kernel.org, linux-remoteproc@vger.kernel.org, devicetree@vger.kernel.org Cc: quic_srichara@quicinc.com, vignesh.viswanathan@oss.qualcomm.com, gokul.sriram.p@oss.qualcomm.com Subject: [PATCH V4 3/8] remoteproc: qcom: add hexagon based WCSS secure PIL driver Date: Thu, 3 Apr 2025 17:32:59 +0530 Message-Id: <20250403120304.2345677-4-gokul.sriram.p@oss.qualcomm.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20250403120304.2345677-1-gokul.sriram.p@oss.qualcomm.com> References: <20250403120304.2345677-1-gokul.sriram.p@oss.qualcomm.com> Precedence: bulk X-Mailing-List: linux-arm-msm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-Authority-Analysis: v=2.4 cv=VI/dn8PX c=1 sm=1 tr=0 ts=67ee790b cx=c_pps a=vVfyC5vLCtgYJKYeQD43oA==:117 a=Ou0eQOY4+eZoSc0qltEV5Q==:17 a=XR8D0OoHHMoA:10 a=EUspDBNiAAAA:8 a=COk6AnOGAAAA:8 a=r4plcOBkgveba4xxPIQA:9 a=RVmHIydaz68A:10 a=rl5im9kqc5Lf4LNbBjHf:22 a=TjNXssC_j7lpFel5tvFf:22 X-Proofpoint-ORIG-GUID: QWQp-B6VsTZSSIp09f0H5fMkX-zKc665 X-Proofpoint-GUID: QWQp-B6VsTZSSIp09f0H5fMkX-zKc665 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1095,Hydra:6.0.680,FMLib:17.12.68.34 definitions=2025-04-03_05,2025-04-02_03,2024-11-22_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 spamscore=0 clxscore=1011 priorityscore=1501 mlxscore=0 adultscore=0 suspectscore=0 impostorscore=0 phishscore=0 lowpriorityscore=0 mlxlogscore=999 malwarescore=0 bulkscore=0 classifier=spam authscore=0 authtc=n/a authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.19.0-2502280000 definitions=main-2504030050 From: Vignesh Viswanathan Add support to bring up hexagon based WCSS using secure PIL. All IPQxxxx SoCs support secure Peripheral Image Loading (PIL). Secure PIL image is signed firmware image which only trusted software such as TrustZone (TZ) can authenticate and load. Linux kernel will send a Peripheral Authentication Service (PAS) request to TZ to authenticate and load the PIL images. This change also introduces secure firmware authentication using Trusted Management Engine-Lite (TME-L) which is supported on IPQ5424 SoC. This driver uses mailbox based PAS request to TME-L for image authentication if supported, else it will fallback to use SCM call based PAS request to TZ. In order to avoid overloading the existing WCSS driver or PAS driver, we came up with this new PAS based IPQ WCSS driver. Signed-off-by: Vignesh Viswanathan Signed-off-by: Manikanta Mylavarapu Signed-off-by: Gokul Sriram Palanisamy --- drivers/remoteproc/Kconfig | 19 ++ drivers/remoteproc/Makefile | 1 + drivers/remoteproc/qcom_q6v5_wcss_sec.c | 399 ++++++++++++++++++++++++ include/linux/remoteproc.h | 2 + 4 files changed, 421 insertions(+) create mode 100644 drivers/remoteproc/qcom_q6v5_wcss_sec.c diff --git a/drivers/remoteproc/Kconfig b/drivers/remoteproc/Kconfig index 83962a114dc9..656cbb12b54d 100644 --- a/drivers/remoteproc/Kconfig +++ b/drivers/remoteproc/Kconfig @@ -255,6 +255,25 @@ config QCOM_Q6V5_WCSS Hexagon V5 based WCSS remote processors on e.g. IPQ8074. This is a non-TrustZone wireless subsystem. +config QCOM_Q6V5_WCSS_SEC + tristate "Qualcomm Hexagon based WCSS Secure Peripheral Image Loader" + depends on OF && ARCH_QCOM + depends on QCOM_SMEM + depends on RPMSG_QCOM_GLINK_SMEM || RPMSG_QCOM_GLINK_SMEM=n + depends on RPMSG_QCOM_GLINK || RPMSG_QCOM_GLINK=n + select QCOM_MDT_LOADER + select QCOM_PIL_INFO + select QCOM_Q6V5_COMMON + select QCOM_RPROC_COMMON + select QCOM_SCM + help + Say y here to support the Qualcomm Secure Peripheral Image Loader + for the Hexagon based remote processors on e.g. IPQ5332. + + This is TrustZone wireless subsystem. The firmware is + verified and booted with the help of the Peripheral Authentication + System (PAS) in TrustZone. + config QCOM_SYSMON tristate "Qualcomm sysmon driver" depends on RPMSG diff --git a/drivers/remoteproc/Makefile b/drivers/remoteproc/Makefile index 5ff4e2fee4ab..d4971b672812 100644 --- a/drivers/remoteproc/Makefile +++ b/drivers/remoteproc/Makefile @@ -28,6 +28,7 @@ obj-$(CONFIG_QCOM_Q6V5_ADSP) += qcom_q6v5_adsp.o obj-$(CONFIG_QCOM_Q6V5_MSS) += qcom_q6v5_mss.o obj-$(CONFIG_QCOM_Q6V5_PAS) += qcom_q6v5_pas.o obj-$(CONFIG_QCOM_Q6V5_WCSS) += qcom_q6v5_wcss.o +obj-$(CONFIG_QCOM_Q6V5_WCSS_SEC) += qcom_q6v5_wcss_sec.o obj-$(CONFIG_QCOM_SYSMON) += qcom_sysmon.o obj-$(CONFIG_QCOM_WCNSS_PIL) += qcom_wcnss_pil.o qcom_wcnss_pil-y += qcom_wcnss.o diff --git a/drivers/remoteproc/qcom_q6v5_wcss_sec.c b/drivers/remoteproc/qcom_q6v5_wcss_sec.c new file mode 100644 index 000000000000..30422c6c982d --- /dev/null +++ b/drivers/remoteproc/qcom_q6v5_wcss_sec.c @@ -0,0 +1,399 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (C) 2016-2018 Linaro Ltd. + * Copyright (C) 2014 Sony Mobile Communications AB + * Copyright (c) 2012-2018 The Linux Foundation. All rights reserved. + * Copyright (c) 2024-2025 Qualcomm Innovation Center, Inc. All rights reserved. + */ +#include +#include +#include +#include +#include +#include +#include +#include + +#include "qcom_common.h" +#include "qcom_q6v5.h" +#include "qcom_pil_info.h" + +#define WCSS_CRASH_REASON 421 + +#define WCSS_PAS_ID 0x6 +#define MPD_WCSS_PAS_ID 0xd + +#define Q6_WAIT_TIMEOUT (5 * HZ) + +struct wcss_sec { + struct device *dev; + struct qcom_rproc_glink glink_subdev; + struct qcom_rproc_ssr ssr_subdev; + struct qcom_q6v5 q6; + phys_addr_t mem_phys; + phys_addr_t mem_reloc; + void *mem_region; + size_t mem_size; + const struct wcss_data *desc; + + struct mbox_client mbox_client; + struct mbox_chan *mbox_chan; + void *metadata; + size_t metadata_len; +}; + +struct wcss_data { + u32 pasid; + const char *ss_name; + bool auto_boot; + bool tmelcom; +}; + +static int wcss_sec_start(struct rproc *rproc) +{ + struct wcss_sec *wcss = rproc->priv; + struct device *dev = wcss->dev; + int ret; + + ret = qcom_q6v5_prepare(&wcss->q6); + if (ret) + return ret; + + if (!IS_ERR_OR_NULL(wcss->mbox_chan)) { + struct tmel_sec_auth tsa; + struct tmel_qmp_msg tqm; + + tsa.data = wcss->metadata; + tsa.size = wcss->metadata_len; + tsa.pas_id = wcss->desc->pasid; + tqm.msg = &tsa; + tqm.msg_id = TMEL_MSG_UID_SECBOOT_SEC_AUTH; + + ret = mbox_send_message(wcss->mbox_chan, (void *)&tqm); + if (ret < 0) { + dev_err(dev, "Failed to send message via mailbox\n"); + goto unprepare; + } + } else { + ret = qcom_scm_pas_auth_and_reset(wcss->desc->pasid); + if (ret) { + dev_err(dev, "wcss_reset failed\n"); + goto unprepare; + } + } + + ret = qcom_q6v5_wait_for_start(&wcss->q6, Q6_WAIT_TIMEOUT); + if (ret == -ETIMEDOUT) + dev_err(dev, "start timed out\n"); + +unprepare: + qcom_q6v5_unprepare(&wcss->q6); + + return ret; +} + +static int wcss_sec_stop(struct rproc *rproc) +{ + struct wcss_sec *wcss = rproc->priv; + struct device *dev = wcss->dev; + int ret; + + if (!IS_ERR_OR_NULL(wcss->mbox_chan)) { + struct tmel_sec_auth tsa = {0}; + struct tmel_qmp_msg tqm; + + tsa.pas_id = wcss->desc->pasid; + tqm.msg = &tsa; + tqm.msg_id = TMEL_MSG_UID_SECBOOT_SS_TEAR_DOWN; + + mbox_send_message(wcss->mbox_chan, (void *)&tqm); + } else { + ret = qcom_scm_pas_shutdown(wcss->desc->pasid); + if (ret) { + dev_err(dev, "not able to shutdown\n"); + return ret; + } + } + + qcom_q6v5_unprepare(&wcss->q6); + + return 0; +} + +static void *wcss_sec_da_to_va(struct rproc *rproc, u64 da, size_t len, + bool *is_iomem) +{ + struct wcss_sec *wcss = rproc->priv; + int offset; + + offset = da - wcss->mem_reloc; + if (offset < 0 || offset + len > wcss->mem_size) + return NULL; + + return wcss->mem_region + offset; +} + +static int wcss_sec_load(struct rproc *rproc, const struct firmware *fw) +{ + struct wcss_sec *wcss = rproc->priv; + struct device *dev = wcss->dev; + int ret; + + if (!IS_ERR_OR_NULL(wcss->mbox_chan)) { + wcss->metadata = qcom_mdt_read_metadata(fw, &wcss->metadata_len, + rproc->firmware, wcss->dev); + if (IS_ERR(wcss->metadata)) { + ret = PTR_ERR(wcss->metadata); + dev_err(wcss->dev, "error %d reading firmware %s metadata\n", + ret, rproc->firmware); + return ret; + } + + ret = qcom_mdt_load_no_init(wcss->dev, fw, rproc->firmware, wcss->desc->pasid, + wcss->mem_region, wcss->mem_phys, wcss->mem_size, + &wcss->mem_reloc); + if (ret) { + kfree(wcss->metadata); + return ret; + } + } else { + ret = qcom_mdt_load(dev, fw, rproc->firmware, wcss->desc->pasid, wcss->mem_region, + wcss->mem_phys, wcss->mem_size, &wcss->mem_reloc); + if (ret) + return ret; + } + + qcom_pil_info_store("wcss", wcss->mem_phys, wcss->mem_size); + + return 0; +} + +static unsigned long wcss_sec_panic(struct rproc *rproc) +{ + struct wcss_sec *wcss = rproc->priv; + + return qcom_q6v5_panic(&wcss->q6); +} + +static void wcss_sec_copy_segment(struct rproc *rproc, + struct rproc_dump_segment *segment, + void *dest, size_t offset, size_t size) +{ + struct wcss_sec *wcss = rproc->priv; + struct device *dev = wcss->dev; + + if (!segment->io_ptr) + segment->io_ptr = ioremap_wc(segment->da, segment->size); + + if (!segment->io_ptr) { + dev_err(dev, "Failed to ioremap segment %pad size 0x%zx\n", + &segment->da, segment->size); + return; + } + + if (offset + size <= segment->size) { + memcpy(dest, segment->io_ptr + offset, size); + } else { + iounmap(segment->io_ptr); + segment->io_ptr = NULL; + } +} + +static int wcss_sec_dump_segments(struct rproc *rproc, + const struct firmware *fw) +{ + struct device *dev = rproc->dev.parent; + struct reserved_mem *rmem = NULL; + struct device_node *node; + int num_segs, index; + int ret; + + /* + * Parse through additional reserved memory regions for the rproc + * and add them to the coredump segments + */ + num_segs = of_count_phandle_with_args(dev->of_node, + "memory-region", NULL); + for (index = 0; index < num_segs; index++) { + node = of_parse_phandle(dev->of_node, + "memory-region", index); + if (!node) + return -EINVAL; + + rmem = of_reserved_mem_lookup(node); + of_node_put(node); + if (!rmem) { + dev_err(dev, "unable to acquire memory-region index %d num_segs %d\n", + index, num_segs); + return -EINVAL; + } + + dev_dbg(dev, "Adding segment 0x%pa size 0x%pa", + &rmem->base, &rmem->size); + ret = rproc_coredump_add_custom_segment(rproc, + rmem->base, + rmem->size, + wcss_sec_copy_segment, + NULL); + if (ret) + return ret; + } + + return 0; +} + +static const struct rproc_ops wcss_sec_ops = { + .start = wcss_sec_start, + .stop = wcss_sec_stop, + .da_to_va = wcss_sec_da_to_va, + .load = wcss_sec_load, + .get_boot_addr = rproc_elf_get_boot_addr, + .panic = wcss_sec_panic, + .parse_fw = wcss_sec_dump_segments, +}; + +static int wcss_sec_alloc_memory_region(struct wcss_sec *wcss) +{ + struct reserved_mem *rmem = NULL; + struct device_node *node; + struct device *dev = wcss->dev; + + node = of_parse_phandle(dev->of_node, "memory-region", 0); + if (!node) { + dev_err(dev, "can't find phandle memory-region\n"); + return -EINVAL; + } + + rmem = of_reserved_mem_lookup(node); + of_node_put(node); + + if (!rmem) { + dev_err(dev, "unable to acquire memory-region\n"); + return -EINVAL; + } + + wcss->mem_phys = rmem->base; + wcss->mem_reloc = rmem->base; + wcss->mem_size = rmem->size; + wcss->mem_region = devm_ioremap_wc(dev, wcss->mem_phys, wcss->mem_size); + if (!wcss->mem_region) { + dev_err(dev, "unable to map memory region: %pa+%pa\n", + &rmem->base, &rmem->size); + return -ENOMEM; + } + + return 0; +} + +static int wcss_sec_probe(struct platform_device *pdev) +{ + struct rproc *rproc; + struct wcss_sec *wcss; + struct clk *sleep_clk; + const char *fw_name = NULL; + const struct wcss_data *desc = of_device_get_match_data(&pdev->dev); + int ret; + + ret = of_property_read_string(pdev->dev.of_node, "firmware-name", + &fw_name); + if (ret < 0) + return ret; + + rproc = devm_rproc_alloc(&pdev->dev, desc->ss_name, &wcss_sec_ops, + fw_name, sizeof(*wcss)); + if (!rproc) { + dev_err(&pdev->dev, "failed to allocate rproc\n"); + return -ENOMEM; + } + + wcss = rproc->priv; + wcss->dev = &pdev->dev; + wcss->desc = desc; + + ret = wcss_sec_alloc_memory_region(wcss); + if (ret) + return ret; + + sleep_clk = devm_clk_get_optional_enabled(&pdev->dev, "sleep"); + if (IS_ERR(sleep_clk)) + return dev_err_probe(&pdev->dev, PTR_ERR(sleep_clk), + "Failed to get sleep clock\n"); + + ret = qcom_q6v5_init(&wcss->q6, pdev, rproc, + WCSS_CRASH_REASON, NULL, NULL); + if (ret) + return ret; + + qcom_add_glink_subdev(rproc, &wcss->glink_subdev, desc->ss_name); + qcom_add_ssr_subdev(rproc, &wcss->ssr_subdev, desc->ss_name); + + rproc->auto_boot = false; + rproc->dump_conf = RPROC_COREDUMP_INLINE; + rproc_coredump_set_elf_info(rproc, ELFCLASS32, EM_NONE); + + if (desc->tmelcom) { + wcss->mbox_client.dev = wcss->dev; + wcss->mbox_client.knows_txdone = true; + wcss->mbox_client.tx_block = true; + wcss->mbox_chan = mbox_request_channel(&wcss->mbox_client, 0); + if (IS_ERR(wcss->mbox_chan)) + return dev_err_probe(wcss->dev, PTR_ERR(wcss->mbox_chan), + "mbox chan for IPC is missing\n"); + } + + ret = devm_rproc_add(&pdev->dev, rproc); + if (ret) + return ret; + + platform_set_drvdata(pdev, rproc); + + return 0; +} + +static void wcss_sec_remove(struct platform_device *pdev) +{ + struct rproc *rproc = platform_get_drvdata(pdev); + struct wcss_sec *wcss = rproc->priv; + + mbox_free_channel(wcss->mbox_chan); + qcom_remove_glink_subdev(rproc, &wcss->glink_subdev); + qcom_remove_ssr_subdev(rproc, &wcss->ssr_subdev); + qcom_q6v5_deinit(&wcss->q6); +} + +static const struct wcss_data wcss_sec_ipq5332_res_init = { + .pasid = MPD_WCSS_PAS_ID, + .ss_name = "q6wcss", +}; + +static const struct wcss_data wcss_sec_ipq5424_res_init = { + .pasid = MPD_WCSS_PAS_ID, + .ss_name = "q6wcss", + .tmelcom = true, +}; + +static const struct wcss_data wcss_sec_ipq9574_res_init = { + .pasid = WCSS_PAS_ID, + .ss_name = "q6wcss", +}; + +static const struct of_device_id wcss_sec_of_match[] = { + { .compatible = "qcom,ipq5332-wcss-sec-pil", .data = &wcss_sec_ipq5332_res_init }, + { .compatible = "qcom,ipq5424-wcss-sec-pil", .data = &wcss_sec_ipq5424_res_init }, + { .compatible = "qcom,ipq9574-wcss-sec-pil", .data = &wcss_sec_ipq9574_res_init }, + { }, +}; +MODULE_DEVICE_TABLE(of, wcss_sec_of_match); + +static struct platform_driver wcss_sec_driver = { + .probe = wcss_sec_probe, + .remove = wcss_sec_remove, + .driver = { + .name = "qcom-wcss-secure-pil", + .of_match_table = wcss_sec_of_match, + }, +}; +module_platform_driver(wcss_sec_driver); + +MODULE_DESCRIPTION("Hexagon WCSS Secure Peripheral Image Loader"); +MODULE_LICENSE("GPL"); diff --git a/include/linux/remoteproc.h b/include/linux/remoteproc.h index b4795698d8c2..7b2159853345 100644 --- a/include/linux/remoteproc.h +++ b/include/linux/remoteproc.h @@ -472,6 +472,7 @@ enum rproc_dump_mechanism { * @node: list node related to the rproc segment list * @da: device address of the segment * @size: size of the segment + * @io_ptr: ptr to store the ioremapped dump segment * @priv: private data associated with the dump_segment * @dump: custom dump function to fill device memory segment associated * with coredump @@ -483,6 +484,7 @@ struct rproc_dump_segment { dma_addr_t da; size_t size; + void *io_ptr; void *priv; void (*dump)(struct rproc *rproc, struct rproc_dump_segment *segment, void *dest, size_t offset, size_t size); From patchwork Thu Apr 3 12:03:00 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Gokul Sriram P X-Patchwork-Id: 14036860 Received: from mx0a-0031df01.pphosted.com (mx0a-0031df01.pphosted.com [205.220.168.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 417B724C07B for ; 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[103.229.18.19]) by smtp.gmail.com with ESMTPSA id 98e67ed59e1d1-305827d710csm1285799a91.10.2025.04.03.05.03.22 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 03 Apr 2025 05:03:25 -0700 (PDT) From: Gokul Sriram Palanisamy To: andersson@kernel.org, mathieu.poirier@linaro.org, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, konradybcio@kernel.org, quic_mmanikan@quicinc.com, linux-arm-msm@vger.kernel.org, linux-remoteproc@vger.kernel.org, devicetree@vger.kernel.org Cc: quic_srichara@quicinc.com, vignesh.viswanathan@oss.qualcomm.com, gokul.sriram.p@oss.qualcomm.com Subject: [PATCH V4 4/8] soc: qcom: smem: introduce qcom_smem_get_machid() Date: Thu, 3 Apr 2025 17:33:00 +0530 Message-Id: <20250403120304.2345677-5-gokul.sriram.p@oss.qualcomm.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20250403120304.2345677-1-gokul.sriram.p@oss.qualcomm.com> References: <20250403120304.2345677-1-gokul.sriram.p@oss.qualcomm.com> Precedence: bulk X-Mailing-List: linux-arm-msm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-Proofpoint-GUID: 5EINZXteLqNIn9jVVZ-egRTJ2mKTL2qv X-Proofpoint-ORIG-GUID: 5EINZXteLqNIn9jVVZ-egRTJ2mKTL2qv X-Authority-Analysis: v=2.4 cv=ZNLXmW7b c=1 sm=1 tr=0 ts=67ee790f cx=c_pps a=RP+M6JBNLl+fLTcSJhASfg==:117 a=Ou0eQOY4+eZoSc0qltEV5Q==:17 a=XR8D0OoHHMoA:10 a=EUspDBNiAAAA:8 a=jILyneK2vBiVKV3vpI8A:9 a=iS9zxrgQBfv6-_F4QbHw:22 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1095,Hydra:6.0.680,FMLib:17.12.68.34 definitions=2025-04-03_05,2025-04-02_03,2024-11-22_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 spamscore=0 lowpriorityscore=0 clxscore=1011 mlxscore=0 adultscore=0 mlxlogscore=999 priorityscore=1501 bulkscore=0 suspectscore=0 malwarescore=0 phishscore=0 impostorscore=0 classifier=spam authscore=0 authtc=n/a authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.19.0-2502280000 definitions=main-2504030050 Introduce a helper to return the machid which is used to identify the specific board variant derived from the same SoC. Signed-off-by: Gokul Sriram Palanisamy --- drivers/soc/qcom/smem.c | 26 ++++++++++++++++++++++++++ include/linux/soc/qcom/smem.h | 1 + 2 files changed, 27 insertions(+) diff --git a/drivers/soc/qcom/smem.c b/drivers/soc/qcom/smem.c index 592819701809..327f7358191d 100644 --- a/drivers/soc/qcom/smem.c +++ b/drivers/soc/qcom/smem.c @@ -827,6 +827,32 @@ int qcom_smem_get_soc_id(u32 *id) } EXPORT_SYMBOL_GPL(qcom_smem_get_soc_id); +/** + * qcom_smem_get_machid() - return the machid + * @id: On success, we return the machid here. + * + * generate machid from HW/SW build ID and return it. + * + * Return: 0 on success, negative errno on failure. + */ + +int qcom_smem_get_machid(u32 *id) +{ + struct socinfo *info; + + info = qcom_smem_get(QCOM_SMEM_HOST_ANY, SMEM_HW_SW_BUILD_ID, NULL); + if (IS_ERR(info)) + return PTR_ERR(info); + + *id = ((info->hw_plat << 24) | + (((info->plat_ver & 0xffff0000) >> 16) << 16) | + ((info->plat_ver & 0x0000ffff) << 8) | + (info->hw_plat_subtype)); + + return 0; +} +EXPORT_SYMBOL_GPL(qcom_smem_get_machid); + /** * qcom_smem_get_feature_code() - return the feature code * @code: On success, return the feature code here. diff --git a/include/linux/soc/qcom/smem.h b/include/linux/soc/qcom/smem.h index f946e3beca21..82f2e6df7853 100644 --- a/include/linux/soc/qcom/smem.h +++ b/include/linux/soc/qcom/smem.h @@ -13,6 +13,7 @@ int qcom_smem_get_free_space(unsigned host); phys_addr_t qcom_smem_virt_to_phys(void *p); int qcom_smem_get_soc_id(u32 *id); +int qcom_smem_get_machid(u32 *id); int qcom_smem_get_feature_code(u32 *code); int qcom_smem_bust_hwspin_lock_by_host(unsigned int host); From patchwork Thu Apr 3 12:03:01 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Gokul Sriram P X-Patchwork-Id: 14036861 Received: from mx0a-0031df01.pphosted.com (mx0a-0031df01.pphosted.com [205.220.168.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 8B2D324C09D for ; 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[103.229.18.19]) by smtp.gmail.com with ESMTPSA id 98e67ed59e1d1-305827d710csm1285799a91.10.2025.04.03.05.03.26 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 03 Apr 2025 05:03:29 -0700 (PDT) From: Gokul Sriram Palanisamy To: andersson@kernel.org, mathieu.poirier@linaro.org, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, konradybcio@kernel.org, quic_mmanikan@quicinc.com, linux-arm-msm@vger.kernel.org, linux-remoteproc@vger.kernel.org, devicetree@vger.kernel.org Cc: quic_srichara@quicinc.com, vignesh.viswanathan@oss.qualcomm.com, gokul.sriram.p@oss.qualcomm.com Subject: [PATCH V4 5/8] remoteproc: qcom: add support for Q6 device-tree loading Date: Thu, 3 Apr 2025 17:33:01 +0530 Message-Id: <20250403120304.2345677-6-gokul.sriram.p@oss.qualcomm.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20250403120304.2345677-1-gokul.sriram.p@oss.qualcomm.com> References: <20250403120304.2345677-1-gokul.sriram.p@oss.qualcomm.com> Precedence: bulk X-Mailing-List: linux-arm-msm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-Authority-Analysis: v=2.4 cv=Vbj3PEp9 c=1 sm=1 tr=0 ts=67ee7912 cx=c_pps a=RP+M6JBNLl+fLTcSJhASfg==:117 a=Ou0eQOY4+eZoSc0qltEV5Q==:17 a=XR8D0OoHHMoA:10 a=EUspDBNiAAAA:8 a=aTtrrYsn2t972Xo9M2sA:9 a=iS9zxrgQBfv6-_F4QbHw:22 X-Proofpoint-ORIG-GUID: wW1inIBjxtHA7PNXfGnTWY1t9Zjns6Nn X-Proofpoint-GUID: wW1inIBjxtHA7PNXfGnTWY1t9Zjns6Nn X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1095,Hydra:6.0.680,FMLib:17.12.68.34 definitions=2025-04-03_05,2025-04-02_03,2024-11-22_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 malwarescore=0 adultscore=0 suspectscore=0 clxscore=1015 mlxscore=0 phishscore=0 bulkscore=0 priorityscore=1501 spamscore=0 lowpriorityscore=0 mlxlogscore=999 impostorscore=0 classifier=spam authscore=0 authtc=n/a authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.19.0-2502280000 definitions=main-2504030050 In IPQ5332 and IPQ5424 SoCs, Q6 requires separate device-tree. Signed-off-by: Gokul Sriram Palanisamy --- drivers/remoteproc/qcom_q6v5_wcss_sec.c | 147 ++++++++++++++++++++++-- 1 file changed, 137 insertions(+), 10 deletions(-) diff --git a/drivers/remoteproc/qcom_q6v5_wcss_sec.c b/drivers/remoteproc/qcom_q6v5_wcss_sec.c index 30422c6c982d..e4cc7caebd7c 100644 --- a/drivers/remoteproc/qcom_q6v5_wcss_sec.c +++ b/drivers/remoteproc/qcom_q6v5_wcss_sec.c @@ -10,9 +10,12 @@ #include #include #include +#include #include #include +#include #include +#include #include "qcom_common.h" #include "qcom_q6v5.h" @@ -34,6 +37,18 @@ struct wcss_sec { phys_addr_t mem_reloc; void *mem_region; size_t mem_size; + + const char *dtb_firmware_name; + const struct firmware *dtb_firmware; + phys_addr_t dtb_mem_phys; + phys_addr_t dtb_mem_reloc; + void *dtb_mem_region; + size_t dtb_mem_size; + struct regmap *tcsr_map; + u32 dtb_low_offset; + u32 dtb_high_offset; + u32 machid_offset; + const struct wcss_data *desc; struct mbox_client mbox_client; @@ -46,6 +61,7 @@ struct wcss_data { u32 pasid; const char *ss_name; bool auto_boot; + const char *dtb_firmware_name; bool tmelcom; }; @@ -137,8 +153,45 @@ static int wcss_sec_load(struct rproc *rproc, const struct firmware *fw) { struct wcss_sec *wcss = rproc->priv; struct device *dev = wcss->dev; + u32 machid; int ret; + if (wcss->dtb_firmware_name) { + ret = request_firmware(&wcss->dtb_firmware, wcss->dtb_firmware_name, wcss->dev); + if (ret) { + dev_err(wcss->dev, "request_firmware failed for %s: %d\n", + wcss->dtb_firmware_name, ret); + return ret; + } + + ret = qcom_mdt_load_no_init(wcss->dev, wcss->dtb_firmware, + wcss->dtb_firmware_name, 0, wcss->dtb_mem_region, + wcss->dtb_mem_phys, wcss->dtb_mem_size, + &wcss->dtb_mem_reloc); + if (ret) + goto release_dtb_firmware; + + ret = qcom_smem_get_machid(&machid); + if (ret) { + pr_err("machid get failed, ret = %d\n", ret); + goto release_dtb_firmware; + } + + ret = regmap_write(wcss->tcsr_map, wcss->dtb_low_offset, + wcss->dtb_mem_phys & 0xFFFFFFFF); + if (ret) + goto release_dtb_firmware; + + ret = regmap_write(wcss->tcsr_map, wcss->dtb_high_offset, + wcss->dtb_mem_phys & (0xFFFFFFFF << 31)); + if (ret) + goto release_dtb_firmware; + + ret = regmap_write(wcss->tcsr_map, wcss->machid_offset, machid); + if (ret) + goto release_dtb_firmware; + } + if (!IS_ERR_OR_NULL(wcss->mbox_chan)) { wcss->metadata = qcom_mdt_read_metadata(fw, &wcss->metadata_len, rproc->firmware, wcss->dev); @@ -146,26 +199,33 @@ static int wcss_sec_load(struct rproc *rproc, const struct firmware *fw) ret = PTR_ERR(wcss->metadata); dev_err(wcss->dev, "error %d reading firmware %s metadata\n", ret, rproc->firmware); - return ret; + goto release_dtb_firmware; } ret = qcom_mdt_load_no_init(wcss->dev, fw, rproc->firmware, wcss->desc->pasid, wcss->mem_region, wcss->mem_phys, wcss->mem_size, &wcss->mem_reloc); - if (ret) { - kfree(wcss->metadata); - return ret; - } + if (ret) + goto release_metadata; } else { ret = qcom_mdt_load(dev, fw, rproc->firmware, wcss->desc->pasid, wcss->mem_region, wcss->mem_phys, wcss->mem_size, &wcss->mem_reloc); if (ret) - return ret; + goto release_dtb_firmware; } qcom_pil_info_store("wcss", wcss->mem_phys, wcss->mem_size); return 0; + +release_metadata: + if (!IS_ERR_OR_NULL(wcss->mbox_chan)) + kfree(wcss->metadata); +release_dtb_firmware: + if (wcss->dtb_firmware_name) + release_firmware(wcss->dtb_firmware); + + return ret; } static unsigned long wcss_sec_panic(struct rproc *rproc) @@ -282,6 +342,33 @@ static int wcss_sec_alloc_memory_region(struct wcss_sec *wcss) return -ENOMEM; } + if (!wcss->dtb_firmware_name) + return 0; + + node = of_parse_phandle(dev->of_node, "memory-region", 1); + if (!node) { + dev_err(dev, "can't find dtb memory-region\n"); + return -EINVAL; + } + + rmem = of_reserved_mem_lookup(node); + of_node_put(node); + + if (!rmem) { + dev_err(dev, "unable to resolve dtb memory-region\n"); + return -EINVAL; + } + + wcss->dtb_mem_phys = rmem->base; + wcss->dtb_mem_reloc = rmem->base; + wcss->dtb_mem_size = rmem->size; + wcss->dtb_mem_region = devm_ioremap_wc(dev, wcss->dtb_mem_phys, wcss->dtb_mem_size); + if (!wcss->dtb_mem_region) { + dev_err(dev, "unable to map dtb memory region: %pa+%pa\n", + &rmem->base, &rmem->size); + return -ENOMEM; + } + return 0; } @@ -291,6 +378,9 @@ static int wcss_sec_probe(struct platform_device *pdev) struct wcss_sec *wcss; struct clk *sleep_clk; const char *fw_name = NULL; + const char *dtb_fw_name = NULL; + struct of_phandle_args args; + int args_cell_cnt = 3; const struct wcss_data *desc = of_device_get_match_data(&pdev->dev); int ret; @@ -310,6 +400,33 @@ static int wcss_sec_probe(struct platform_device *pdev) wcss->dev = &pdev->dev; wcss->desc = desc; + if (desc->dtb_firmware_name) { + ret = of_property_read_string_index(pdev->dev.of_node, "firmware-name", + 1, &dtb_fw_name); + if (ret < 0) + return ret; + + if (dtb_fw_name) + wcss->dtb_firmware_name = dtb_fw_name; + + ret = of_parse_phandle_with_fixed_args(pdev->dev.of_node, "qcom,q6-dtb-info", + args_cell_cnt, 0, &args); + if (ret < 0) { + dev_err(&pdev->dev, "failed to parse qcom,q6-dtb-info\n"); + return ret; + } + + wcss->tcsr_map = syscon_node_to_regmap(args.np); + of_node_put(args.np); + if (IS_ERR(wcss->tcsr_map)) + return dev_err_probe(&pdev->dev, PTR_ERR(wcss->tcsr_map), + "unable to get syscon regmap\n"); + + wcss->dtb_low_offset = args.args[0]; + wcss->dtb_high_offset = args.args[1]; + wcss->machid_offset = args.args[2]; + } + ret = wcss_sec_alloc_memory_region(wcss); if (ret) return ret; @@ -336,18 +453,26 @@ static int wcss_sec_probe(struct platform_device *pdev) wcss->mbox_client.knows_txdone = true; wcss->mbox_client.tx_block = true; wcss->mbox_chan = mbox_request_channel(&wcss->mbox_client, 0); - if (IS_ERR(wcss->mbox_chan)) - return dev_err_probe(wcss->dev, PTR_ERR(wcss->mbox_chan), - "mbox chan for IPC is missing\n"); + if (IS_ERR(wcss->mbox_chan)) { + ret = dev_err_probe(&pdev->dev, PTR_ERR(wcss->mbox_chan), + "mbox chan for IPC is missing\n"); + goto remove_subdevs; + } } ret = devm_rproc_add(&pdev->dev, rproc); if (ret) - return ret; + goto remove_subdevs; platform_set_drvdata(pdev, rproc); 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[103.229.18.19]) by smtp.gmail.com with ESMTPSA id 98e67ed59e1d1-305827d710csm1285799a91.10.2025.04.03.05.03.29 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 03 Apr 2025 05:03:33 -0700 (PDT) From: Gokul Sriram Palanisamy To: andersson@kernel.org, mathieu.poirier@linaro.org, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, konradybcio@kernel.org, quic_mmanikan@quicinc.com, linux-arm-msm@vger.kernel.org, linux-remoteproc@vger.kernel.org, devicetree@vger.kernel.org Cc: quic_srichara@quicinc.com, vignesh.viswanathan@oss.qualcomm.com, gokul.sriram.p@oss.qualcomm.com Subject: [PATCH V4 6/8] arm64: dts: qcom: ipq5332: add nodes to bringup q6 Date: Thu, 3 Apr 2025 17:33:02 +0530 Message-Id: <20250403120304.2345677-7-gokul.sriram.p@oss.qualcomm.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20250403120304.2345677-1-gokul.sriram.p@oss.qualcomm.com> References: <20250403120304.2345677-1-gokul.sriram.p@oss.qualcomm.com> Precedence: bulk X-Mailing-List: linux-arm-msm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-Proofpoint-GUID: 9DkPDjDFeAivc4vdBe67S90Ddx_1Dmay X-Authority-Analysis: v=2.4 cv=a8Iw9VSF c=1 sm=1 tr=0 ts=67ee7916 cx=c_pps a=cmESyDAEBpBGqyK7t0alAg==:117 a=Ou0eQOY4+eZoSc0qltEV5Q==:17 a=XR8D0OoHHMoA:10 a=COk6AnOGAAAA:8 a=EUspDBNiAAAA:8 a=7PM57pxieELrpG8NSiQA:9 a=RVmHIydaz68A:10 a=1OuFwYUASf3TG4hYMiVC:22 a=TjNXssC_j7lpFel5tvFf:22 X-Proofpoint-ORIG-GUID: 9DkPDjDFeAivc4vdBe67S90Ddx_1Dmay X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1095,Hydra:6.0.680,FMLib:17.12.68.34 definitions=2025-04-03_05,2025-04-02_03,2024-11-22_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 clxscore=1015 impostorscore=0 adultscore=0 phishscore=0 priorityscore=1501 mlxscore=0 lowpriorityscore=0 suspectscore=0 bulkscore=0 mlxlogscore=932 malwarescore=0 spamscore=0 classifier=spam authscore=0 authtc=n/a authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.19.0-2502280000 definitions=main-2504030050 From: Manikanta Mylavarapu Enable nodes required for q6 remoteproc bring up. Signed-off-by: Manikanta Mylavarapu Signed-off-by: Gokul Sriram Palanisamy --- arch/arm64/boot/dts/qcom/ipq5332.dtsi | 71 ++++++++++++++++++++++++++- 1 file changed, 70 insertions(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/qcom/ipq5332.dtsi b/arch/arm64/boot/dts/qcom/ipq5332.dtsi index 69dda757925d..af0de072abd2 100644 --- a/arch/arm64/boot/dts/qcom/ipq5332.dtsi +++ b/arch/arm64/boot/dts/qcom/ipq5332.dtsi @@ -2,7 +2,7 @@ /* * IPQ5332 device tree source * - * Copyright (c) 2022-2023 Qualcomm Innovation Center, Inc. All rights reserved. + * Copyright (c) 2022-2025 Qualcomm Innovation Center, Inc. All rights reserved. */ #include @@ -146,6 +146,16 @@ smem@4a800000 { hwlocks = <&tcsr_mutex 3>; }; + + q6_region: wcss@4a900000 { + reg = <0x0 0x4a900000 0x0 0x2b00000>; + no-map; + }; + + q6_dtb_region: wcss-dtb@4d400000 { + reg = <0x0 0x4d400000 0x0 0x2000>; + no-map; + }; }; soc@0 { @@ -545,6 +555,41 @@ frame@b128000 { status = "disabled"; }; }; + + q6v5_wcss: remoteproc@d100000 { + compatible = "qcom,ipq5332-wcss-sec-pil"; + reg = <0x0d100000 0x4040>; + firmware-name = "ath12k/IPQ5332/hw1.0/q6_fw0.mbn", + "ath12k/IPQ5332/hw1.0/qdsp6sw_dtb.mbn"; + interrupts-extended = <&intc GIC_SPI 421 IRQ_TYPE_EDGE_RISING>, + <&smp2p_wcss_in 0 IRQ_TYPE_NONE>, + <&smp2p_wcss_in 1 IRQ_TYPE_NONE>, + <&smp2p_wcss_in 2 IRQ_TYPE_NONE>, + <&smp2p_wcss_in 3 IRQ_TYPE_NONE>; + interrupt-names = "wdog", + "fatal", + "ready", + "handover", + "stop-ack"; + + clocks = <&gcc GCC_IM_SLEEP_CLK>; + clock-names = "sleep"; + + qcom,smem-states = <&smp2p_wcss_out 1>, + <&smp2p_wcss_out 0>; + qcom,smem-state-names = "stop", + "shutdown"; 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[103.229.18.19]) by smtp.gmail.com with ESMTPSA id 98e67ed59e1d1-305827d710csm1285799a91.10.2025.04.03.05.03.33 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 03 Apr 2025 05:03:36 -0700 (PDT) From: Gokul Sriram Palanisamy To: andersson@kernel.org, mathieu.poirier@linaro.org, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, konradybcio@kernel.org, quic_mmanikan@quicinc.com, linux-arm-msm@vger.kernel.org, linux-remoteproc@vger.kernel.org, devicetree@vger.kernel.org Cc: quic_srichara@quicinc.com, vignesh.viswanathan@oss.qualcomm.com, gokul.sriram.p@oss.qualcomm.com Subject: [PATCH V4 7/8] arm64: dts: qcom: ipq5424: add nodes to bring up q6 Date: Thu, 3 Apr 2025 17:33:03 +0530 Message-Id: <20250403120304.2345677-8-gokul.sriram.p@oss.qualcomm.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20250403120304.2345677-1-gokul.sriram.p@oss.qualcomm.com> References: <20250403120304.2345677-1-gokul.sriram.p@oss.qualcomm.com> Precedence: bulk X-Mailing-List: linux-arm-msm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-Proofpoint-ORIG-GUID: KALlVxs5Wcxdp9bmjwkM-L9nHPEm36jG X-Authority-Analysis: v=2.4 cv=N/gpF39B c=1 sm=1 tr=0 ts=67ee791a cx=c_pps a=RP+M6JBNLl+fLTcSJhASfg==:117 a=Ou0eQOY4+eZoSc0qltEV5Q==:17 a=XR8D0OoHHMoA:10 a=EUspDBNiAAAA:8 a=Chduei3-CDLOMEben-gA:9 a=RVmHIydaz68A:10 a=iS9zxrgQBfv6-_F4QbHw:22 X-Proofpoint-GUID: KALlVxs5Wcxdp9bmjwkM-L9nHPEm36jG X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1095,Hydra:6.0.680,FMLib:17.12.68.34 definitions=2025-04-03_05,2025-04-02_03,2024-11-22_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 priorityscore=1501 clxscore=1015 adultscore=0 mlxscore=0 lowpriorityscore=0 bulkscore=0 impostorscore=0 spamscore=0 phishscore=0 suspectscore=0 mlxlogscore=811 malwarescore=0 classifier=spam authscore=0 authtc=n/a authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.19.0-2502280000 definitions=main-2504030050 Enable nodes required for q6 remoteproc bring up. Signed-off-by: Gokul Sriram Palanisamy --- arch/arm64/boot/dts/qcom/ipq5424.dtsi | 87 ++++++++++++++++++++++++++- 1 file changed, 86 insertions(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/qcom/ipq5424.dtsi b/arch/arm64/boot/dts/qcom/ipq5424.dtsi index 5d6ed2172b1b..26c297ffb602 100644 --- a/arch/arm64/boot/dts/qcom/ipq5424.dtsi +++ b/arch/arm64/boot/dts/qcom/ipq5424.dtsi @@ -3,7 +3,7 @@ * IPQ5424 device tree source * * Copyright (c) 2020-2021 The Linux Foundation. All rights reserved. - * Copyright (c) 2022-2024 Qualcomm Innovation Center, Inc. All rights reserved. + * Copyright (c) 2022-2025 Qualcomm Innovation Center, Inc. All rights reserved. */ #include @@ -149,6 +149,16 @@ smem@8a800000 { hwlocks = <&tcsr_mutex 3>; }; + + q6_region: wcss@8a900000 { + reg = <0x0 0x8a900000 0x0 0x2800000>; + no-map; + }; + + q6_dtb_region: wcss-dtb@8d100000 { + reg = <0x0 0x8d100000 0x0 0x2000>; + no-map; + }; }; soc@0 { @@ -541,6 +551,57 @@ dwc_0: usb@8a00000 { }; }; + apcs_glb: mailbox@f400004 { + compatible = "qcom,ipq5424-apcs-apps-global", + "qcom,ipq6018-apcs-apps-global"; + reg = <0 0xf400004 0 0x6000>; + #clock-cells = <1>; + #mbox-cells = <1>; + }; + + tmel_qmp: qmp@32090000 { + compatible = "qcom,ipq5424-tmel"; + reg = <0 0x32090000 0 0x2000>; + interrupts = ; + mboxes = <&apcs_glb 20>; + #mbox-cells = <1>; + }; + + q6v5_wcss: remoteproc@d100000 { + compatible = "qcom,ipq5424-wcss-sec-pil"; + reg = <0 0x0d100000 0 0x4040>; + firmware-name = "ath12k/IPQ5424/hw1.0/q6_fw0.mbn", + "ath12k/IPQ5424/hw1.0/qdsp6sw_dtb.mbn"; + interrupts-extended = <&intc GIC_SPI 508 IRQ_TYPE_EDGE_RISING>, + <&smp2p_wcss_in 0 0>, + <&smp2p_wcss_in 1 0>, + <&smp2p_wcss_in 2 0>, + <&smp2p_wcss_in 3 0>; + interrupt-names = "wdog", + "fatal", + "ready", + "handover", + "stop-ack"; + + mboxes = <&tmel_qmp 0>; + qcom,smem-states = <&smp2p_wcss_out 1>, + <&smp2p_wcss_out 0>; + qcom,smem-state-names = "stop", + "shutdown"; + + memory-region = <&q6_region>, <&q6_dtb_region>; + qcom,q6-dtb-info = <&tcsr 0x1f004 0x1f008 0x1f00c>; + + status = "okay"; + + glink-edge { + interrupts = ; + label = "rtr"; + qcom,remote-pid = <1>; + mboxes = <&apcs_glb 8>; + }; + }; + timer@f420000 { compatible = "arm,armv7-timer-mem"; reg = <0 0xf420000 0 0x1000>; @@ -724,4 +785,28 @@ timer { , ; }; + + wcss: smp2p-wcss { + compatible = "qcom,smp2p"; + qcom,smem = <435>, <428>; + + interrupt-parent = <&intc>; + interrupts = ; + + mboxes = <&apcs_glb 9>; + + qcom,local-pid = <0>; + qcom,remote-pid = <1>; + + smp2p_wcss_out: master-kernel { + qcom,entry-name = "master-kernel"; + #qcom,smem-state-cells = <1>; + }; + + smp2p_wcss_in: slave-kernel { + qcom,entry-name = "slave-kernel"; + interrupt-controller; + #interrupt-cells = <2>; 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[103.229.18.19]) by smtp.gmail.com with ESMTPSA id 98e67ed59e1d1-305827d710csm1285799a91.10.2025.04.03.05.03.37 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 03 Apr 2025 05:03:40 -0700 (PDT) From: Gokul Sriram Palanisamy To: andersson@kernel.org, mathieu.poirier@linaro.org, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, konradybcio@kernel.org, quic_mmanikan@quicinc.com, linux-arm-msm@vger.kernel.org, linux-remoteproc@vger.kernel.org, devicetree@vger.kernel.org Cc: quic_srichara@quicinc.com, vignesh.viswanathan@oss.qualcomm.com, gokul.sriram.p@oss.qualcomm.com Subject: [PATCH V4 8/8] arm64: dts: qcom: ipq9574: add nodes to bring up q6 Date: Thu, 3 Apr 2025 17:33:04 +0530 Message-Id: <20250403120304.2345677-9-gokul.sriram.p@oss.qualcomm.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20250403120304.2345677-1-gokul.sriram.p@oss.qualcomm.com> References: <20250403120304.2345677-1-gokul.sriram.p@oss.qualcomm.com> Precedence: bulk X-Mailing-List: linux-arm-msm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-Authority-Analysis: v=2.4 cv=Vbj3PEp9 c=1 sm=1 tr=0 ts=67ee791e cx=c_pps a=vVfyC5vLCtgYJKYeQD43oA==:117 a=Ou0eQOY4+eZoSc0qltEV5Q==:17 a=XR8D0OoHHMoA:10 a=COk6AnOGAAAA:8 a=EUspDBNiAAAA:8 a=nG0a804IO7H6KQc07wUA:9 a=RVmHIydaz68A:10 a=rl5im9kqc5Lf4LNbBjHf:22 a=TjNXssC_j7lpFel5tvFf:22 X-Proofpoint-ORIG-GUID: ZdxHxQ_DhsRXIhC1uAt1j5viTxe39NiC X-Proofpoint-GUID: ZdxHxQ_DhsRXIhC1uAt1j5viTxe39NiC X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1095,Hydra:6.0.680,FMLib:17.12.68.34 definitions=2025-04-03_05,2025-04-02_03,2024-11-22_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 malwarescore=0 adultscore=0 suspectscore=0 clxscore=1015 mlxscore=0 phishscore=0 bulkscore=0 priorityscore=1501 spamscore=0 lowpriorityscore=0 mlxlogscore=767 impostorscore=0 classifier=spam authscore=0 authtc=n/a authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.19.0-2502280000 definitions=main-2504030050 From: Manikanta Mylavarapu Enable nodes required for q6 remoteproc bring up. Signed-off-by: Manikanta Mylavarapu Signed-off-by: Gokul Sriram Palanisamy --- arch/arm64/boot/dts/qcom/ipq9574.dtsi | 61 ++++++++++++++++++++++++++- 1 file changed, 60 insertions(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/qcom/ipq9574.dtsi b/arch/arm64/boot/dts/qcom/ipq9574.dtsi index db69bff41afa..11a1849ec50f 100644 --- a/arch/arm64/boot/dts/qcom/ipq9574.dtsi +++ b/arch/arm64/boot/dts/qcom/ipq9574.dtsi @@ -3,7 +3,7 @@ * IPQ9574 SoC device tree source * * Copyright (c) 2020-2021 The Linux Foundation. All rights reserved. - * Copyright (c) 2023-2024, Qualcomm Innovation Center, Inc. All rights reserved. + * Copyright (c) 2023-2025, Qualcomm Innovation Center, Inc. All rights reserved. */ #include @@ -226,6 +226,11 @@ smem@4aa00000 { hwlocks = <&tcsr_mutex 3>; no-map; }; + + q6_region: wcss@4ab00000 { + reg = <0x0 0x4ab00000 0x0 0x2b00000>; + no-map; + }; }; soc: soc@0 { @@ -1473,6 +1478,36 @@ top_glue-critical { }; }; }; + + q6v5_wcss: remoteproc@cd00000 { + compatible = "qcom,ipq9574-wcss-sec-pil"; + reg = <0x0cd00000 0x4040>; + firmware-name = "ath11k/IPQ9574/hw1.0/q6_fw.mbn", + "ath11k/IPQ9574/hw1.0/qdsp6sw_dtb.mbn"; + interrupts-extended = <&intc GIC_SPI 325 IRQ_TYPE_EDGE_RISING>, + <&smp2p_wcss_in 0 IRQ_TYPE_NONE>, + <&smp2p_wcss_in 1 IRQ_TYPE_NONE>, + <&smp2p_wcss_in 2 IRQ_TYPE_NONE>, + <&smp2p_wcss_in 3 IRQ_TYPE_NONE>; + interrupt-names = "wdog", + "fatal", + "ready", + "handover", + "stop-ack"; + + qcom,smem-states = <&smp2p_wcss_out 1>, + <&smp2p_wcss_out 0>; + qcom,smem-state-names = "stop", + "shutdown"; + memory-region = <&q6_region>; + + glink-edge { + interrupts = ; + label = "rtr"; + qcom,remote-pid = <1>; + mboxes = <&apcs_glb 8>; + }; + }; }; timer { @@ -1482,4 +1517,28 @@ timer { , ; }; + + wcss: smp2p-wcss { + compatible = "qcom,smp2p"; + qcom,smem = <435>, <428>; + + interrupt-parent = <&intc>; + interrupts = ; + + mboxes = <&apcs_glb 9>; + + qcom,local-pid = <0>; + qcom,remote-pid = <1>; + + smp2p_wcss_out: master-kernel { + qcom,entry-name = "master-kernel"; + #qcom,smem-state-cells = <1>; + }; + + smp2p_wcss_in: slave-kernel { + qcom,entry-name = "slave-kernel"; + interrupt-controller; + #interrupt-cells = <2>; + }; + }; };