From patchwork Fri Apr 4 08:22:21 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Manivannan Sadhasivam X-Patchwork-Id: 14038198 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 93AC710A1F; Fri, 4 Apr 2025 08:22:30 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1743754950; cv=none; b=QlrdONJevJoL+9O9k6bKSjnxWWKGUIfD1kiBYMlF015zgkU0CMOKYB3WABS4WNBo+utvzaOa1UmbkpaXR8gmGasPjnGmzecnvW0PSSXak6vWgXwyH8nfolPbmri6DgYhtYqfT9dgYSfrKRMWA8sgfRyi+1BV9DpWs+wWaBwj+1I= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1743754950; c=relaxed/simple; bh=8w2ql223nYm+BErM3jbKkWekAvb+1IirdxYYwZl8YAY=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=bWxiW3A1iSaJgH8ahPjdm2JZjSitonzrYWq0cKSQOIyBRfCSalfYUosMy/6eNBfwPrxjVlbhDtuyxeH5h56BaNenH2KZWKBh2HBdhI/ttimcFEkgcuppUCMiEKJykIZmvRcHHXMS/rzYLmCsW1FYr9qa1LxKpjPewHvN8lgDTnA= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=eh6XwXgx; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="eh6XwXgx" Received: by smtp.kernel.org (Postfix) with ESMTPS id 0C685C4CEE5; Fri, 4 Apr 2025 08:22:30 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1743754950; bh=8w2ql223nYm+BErM3jbKkWekAvb+1IirdxYYwZl8YAY=; h=From:Date:Subject:References:In-Reply-To:To:Cc:Reply-To:From; b=eh6XwXgx7cKNxUXwPxIho+4bXpBveVNvDDkA/ph0m9rQg/+1K7OCcqv6/X9iigRQc vieRfAHJEMe2AU8Vihyvxmta0SGeEd76KY6KCs0DrQcTa5zL9K00WxNBgThU6nRean 9DE0AEbsKsBv42AUFvSvz9Bk98TLEAaMu67vQzEe6hG9vXfN6mwRfWF0yGaryBPzCk PQGwECDoCLhe85EbuulPcYlpkEvcXvarWvkqFk82hRgoE8HvddDY1EA0Jmw3H9FLml 3PWvHTLAXCVywGYniP0mgjPqG9JQH/UCrsbUA1fvCmCafxkZ9pAo5n6CFjgwehd1VA tVi7eJWuJqdJQ== Received: from aws-us-west-2-korg-lkml-1.web.codeaurora.org (localhost.localdomain [127.0.0.1]) by smtp.lore.kernel.org (Postfix) with ESMTP id F00E9C3601E; Fri, 4 Apr 2025 08:22:29 +0000 (UTC) Date: Fri, 04 Apr 2025 13:52:21 +0530 Subject: [PATCH 1/4] PCI/ERR: Remove misleading TODO regarding kernel panic Precedence: bulk X-Mailing-List: linux-pci@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20250404-pcie-reset-slot-v1-1-98952918bf90@linaro.org> References: <20250404-pcie-reset-slot-v1-0-98952918bf90@linaro.org> In-Reply-To: <20250404-pcie-reset-slot-v1-0-98952918bf90@linaro.org> To: Mahesh J Salgaonkar , Oliver O'Halloran , Bjorn Helgaas , Lorenzo Pieralisi , =?utf-8?q?Krzysztof_Wilczy?= =?utf-8?q?=C5=84ski?= , Rob Herring Cc: dingwei@marvell.com, cassel@kernel.org, Krishna Chaitanya Chundru , linuxppc-dev@lists.ozlabs.org, linux-pci@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-msm@vger.kernel.org, Manivannan Sadhasivam X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=openpgp-sha256; l=789; i=manivannan.sadhasivam@linaro.org; h=from:subject:message-id; bh=Aq+BoDTRwjfmiHKRLtODTEbwNFS8yDdFMEIJ4A/Pkz4=; b=owEBbQGS/pANAwAKAVWfEeb+kc71AcsmYgBn75bDaglwkHeKqhE9AYdkObam0SipeGIjgFjTC pJd4g4Uk5iJATMEAAEKAB0WIQRnpUMqgUjL2KRYJ5dVnxHm/pHO9QUCZ++WwwAKCRBVnxHm/pHO 9WgUCAChvFjCnq6fJcYlGvuvxyMIhUB0WLffeiqVh6Ay4cY4LA0BJMn0P0zNDsqQ29uI4ys9zW/ Cb9KhH9McHnBx4bibC2z1FV3VDtUEM40YhgFlSqdB5XHDVDc/1ZQd9Q57zNMevLyG8YmyfPD7gZ jSvBlbICm9jNYKuqgVblG45YAaBClN0wTRFGePyZmJbJvm83vnwMWACNI3Ek9cdVf5UVVensIxQ A56rmM9gaxYGrXjKY3769BDiCdL9/TV/KqDoTkz7rfOd219Kg9utVeKCKB+l1tpgYHX/vKB7Tf0 PeQCXiiajJHNhxI9l+fudLfKR/qDu+2NuRZjWCMLMIdm30GF X-Developer-Key: i=manivannan.sadhasivam@linaro.org; a=openpgp; fpr=C668AEC3C3188E4C611465E7488550E901166008 X-Endpoint-Received: by B4 Relay for manivannan.sadhasivam@linaro.org/default with auth_id=185 X-Original-From: Manivannan Sadhasivam Reply-To: manivannan.sadhasivam@linaro.org From: Manivannan Sadhasivam From: Manivannan Sadhasivam A PCI device is just another peripheral in a system. So failure to recover it, must not result in a kernel panic. So remove the TODO which is quite misleading. Signed-off-by: Manivannan Sadhasivam --- drivers/pci/pcie/err.c | 1 - 1 file changed, 1 deletion(-) diff --git a/drivers/pci/pcie/err.c b/drivers/pci/pcie/err.c index 31090770fffcc94e15ba6e89f649c6f84bfdf0d5..de6381c690f5c21f00021cdc7bde8d93a5c7db52 100644 --- a/drivers/pci/pcie/err.c +++ b/drivers/pci/pcie/err.c @@ -271,7 +271,6 @@ pci_ers_result_t pcie_do_recovery(struct pci_dev *dev, pci_uevent_ers(bridge, PCI_ERS_RESULT_DISCONNECT); - /* TODO: Should kernel panic here? */ pci_info(bridge, "device recovery failed\n"); return status; From patchwork Fri Apr 4 08:22:22 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Manivannan Sadhasivam X-Patchwork-Id: 14038199 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 93B461624E9; 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dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="AwqP+8n+" Received: by smtp.kernel.org (Postfix) with ESMTPS id 2BF84C4CEE9; Fri, 4 Apr 2025 08:22:30 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1743754950; bh=ua1AiLFy13t+lITso/yoUhh+okg9epvqJ/2iV5gE6Wk=; h=From:Date:Subject:References:In-Reply-To:To:Cc:Reply-To:From; b=AwqP+8n+2VR6cDMkt+4EkFfYl9lZqigOxSqs0YnfEWjK/qOVrTnkFcKzI+0I1+m8p 68KHfT8inDWq7PyaIpyh/WBxLhvxX4xCMkMDuFglf4Ai5OyQKj4OXHhWjkaxSaGIDq F6FR/cCspb9kuWHeGbwFb0dJI0x7TWkWqKqNO4gokQFpYHJyraWV00tfV7gR+fBcXP l1a5SzKRndJwQjq2KjgtKBUsCmiduXzdRS3TkJRLwF87BH+zfwzQmeMa/sGmx/N/xK 07KrAm2rrCFvPpicQCjZmGS2t2BEaNmEXU/0YKz+6lePKpv1dnU1XdEEl71Hpf3vxl wasL5j6dTRhRQ== Received: from aws-us-west-2-korg-lkml-1.web.codeaurora.org (localhost.localdomain [127.0.0.1]) by smtp.lore.kernel.org (Postfix) with ESMTP id 0E111C369A1; Fri, 4 Apr 2025 08:22:30 +0000 (UTC) Date: Fri, 04 Apr 2025 13:52:22 +0530 Subject: [PATCH 2/4] PCI/ERR: Add support for resetting the slot in a platforms specific way Precedence: bulk X-Mailing-List: linux-pci@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20250404-pcie-reset-slot-v1-2-98952918bf90@linaro.org> References: <20250404-pcie-reset-slot-v1-0-98952918bf90@linaro.org> In-Reply-To: <20250404-pcie-reset-slot-v1-0-98952918bf90@linaro.org> To: Mahesh J Salgaonkar , Oliver O'Halloran , Bjorn Helgaas , Lorenzo Pieralisi , =?utf-8?q?Krzysztof_Wilczy?= =?utf-8?q?=C5=84ski?= , Rob Herring Cc: dingwei@marvell.com, cassel@kernel.org, Krishna Chaitanya Chundru , linuxppc-dev@lists.ozlabs.org, linux-pci@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-msm@vger.kernel.org, Manivannan Sadhasivam X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=openpgp-sha256; l=2254; i=manivannan.sadhasivam@linaro.org; h=from:subject:message-id; bh=J1pulK/QhUxJluY/dbX4w+yX5yzsNUDKLf1Z3h6Znak=; b=owEBbQGS/pANAwAKAVWfEeb+kc71AcsmYgBn75bDRHEqWRk4266lWr88ralCgC34yIDiJDcQy 8j9qOiUwGWJATMEAAEKAB0WIQRnpUMqgUjL2KRYJ5dVnxHm/pHO9QUCZ++WwwAKCRBVnxHm/pHO 9Rq8B/9yjNScPcrhP4xoodQVe2UhQ06wX8j3FIiW/HCvPsWMdhDIXtFqRnnQJemw74T7Px8Rnpi c+ZVMPISLnO/A687KVnD3VDdzk9QBaViKfRPnVzVmTbudjSJWyHiR9EyLaAxH+hG26BSoSnbP1w aouo/8LRfXNRQlMdCh1CR7h6303yWBHTisq6wRfHyG/1lbuHN04IqZ7aflwaISj7dloF9c3uP7w o23Vh7HOHfwPK7JkrXyuY/H7xqBi77K63hN77hyDimtJiJhhR3sXumd5x0u+k2Z/YXwTuNXXnL1 LEQ8T/VGLFZZ1a7uOZqhnslwXXjmxwachAAHMA+U3CJdFmjZ X-Developer-Key: i=manivannan.sadhasivam@linaro.org; a=openpgp; fpr=C668AEC3C3188E4C611465E7488550E901166008 X-Endpoint-Received: by B4 Relay for manivannan.sadhasivam@linaro.org/default with auth_id=185 X-Original-From: Manivannan Sadhasivam Reply-To: manivannan.sadhasivam@linaro.org From: Manivannan Sadhasivam From: Manivannan Sadhasivam When the PCI error handling requires resetting the slot, reset it using the host bridge specific 'reset_slot' callback if available before calling the 'slot_reset' callback of the PCI drivers. The 'reset_slot' callback is responsible for resetting the given slot referenced by the 'pci_dev' pointer in a platform specific way and bring it back to the working state if possible. If any error occurs during the slot reset operation, relevant errno should be returned. Signed-off-by: Manivannan Sadhasivam --- drivers/pci/pcie/err.c | 15 ++++++++++----- include/linux/pci.h | 1 + 2 files changed, 11 insertions(+), 5 deletions(-) diff --git a/drivers/pci/pcie/err.c b/drivers/pci/pcie/err.c index de6381c690f5c21f00021cdc7bde8d93a5c7db52..77ce9354532afee209f658175b86e625bba8a5ee 100644 --- a/drivers/pci/pcie/err.c +++ b/drivers/pci/pcie/err.c @@ -234,11 +234,16 @@ pci_ers_result_t pcie_do_recovery(struct pci_dev *dev, } if (status == PCI_ERS_RESULT_NEED_RESET) { - /* - * TODO: Should call platform-specific - * functions to reset slot before calling - * drivers' slot_reset callbacks? - */ + if (host->reset_slot) { + ret = host->reset_slot(host, bridge); + if (ret) { + pci_err(bridge, "failed to reset slot: %d\n", + ret); + status = PCI_ERS_RESULT_DISCONNECT; + goto failed; + } + } + status = PCI_ERS_RESULT_RECOVERED; pci_dbg(bridge, "broadcast slot_reset message\n"); pci_walk_bridge(bridge, report_slot_reset, &status); diff --git a/include/linux/pci.h b/include/linux/pci.h index 0e8e3fd77e96713054388bdc82f439e51023c1bf..8d7d2a49b76cf64b4218b179cec495e0d69ddf6f 100644 --- a/include/linux/pci.h +++ b/include/linux/pci.h @@ -599,6 +599,7 @@ struct pci_host_bridge { void (*release_fn)(struct pci_host_bridge *); int (*enable_device)(struct pci_host_bridge *bridge, struct pci_dev *dev); void (*disable_device)(struct pci_host_bridge *bridge, struct pci_dev *dev); + int (*reset_slot)(struct pci_host_bridge *bridge, struct pci_dev *dev); void *release_data; unsigned int ignore_reset_delay:1; /* For entire hierarchy */ unsigned int no_ext_tags:1; /* No Extended Tags */ From patchwork Fri Apr 4 08:22:23 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Manivannan Sadhasivam X-Patchwork-Id: 14038201 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 93B021CD3F; Fri, 4 Apr 2025 08:22:30 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; 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Fri, 4 Apr 2025 08:22:30 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1743754950; bh=uR3vbNZ2a/5+D41P/XdyWl7V66Eh7lHpDnUcSa7NVQA=; h=From:Date:Subject:References:In-Reply-To:To:Cc:Reply-To:From; b=tvzWp4Mx1qLnWFezGrRkxHSvV1jdOuhS+ihabj1WTVClDpxO1TXS4NawBTeRnqqyU s5Iba0PgPBLLxiNXbDpDuLtmNO7LbNfnKLSLO3SD8JrGCFr8Ma741EjWC5MXk+wZCh Dq8PLo7QM3MOuO/uTaGh6HZsy35GgrZj0Cl/GGSpXL8VChKcTAK/ECx9rP1bcIscxv h5Cjs6s9P/dlfPPeARCEH+Mc764fzGM7B8sOSSLAqu9wZcOtYRcuAIcXNjpUcTL1q7 Sf3mXfQUzbDZMwuWr2g6wF8hm7/OCyo5pUNS3RLW01tW7Sz0rE38qmahZjqWpRY5Bh AqutnLK/9/2qw== Received: from aws-us-west-2-korg-lkml-1.web.codeaurora.org (localhost.localdomain [127.0.0.1]) by smtp.lore.kernel.org (Postfix) with ESMTP id 2BEC5C36010; Fri, 4 Apr 2025 08:22:30 +0000 (UTC) Date: Fri, 04 Apr 2025 13:52:23 +0530 Subject: [PATCH 3/4] PCI: Add link down handling for host bridges Precedence: bulk X-Mailing-List: linux-pci@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20250404-pcie-reset-slot-v1-3-98952918bf90@linaro.org> References: <20250404-pcie-reset-slot-v1-0-98952918bf90@linaro.org> In-Reply-To: <20250404-pcie-reset-slot-v1-0-98952918bf90@linaro.org> To: Mahesh J Salgaonkar , Oliver O'Halloran , Bjorn Helgaas , Lorenzo Pieralisi , =?utf-8?q?Krzysztof_Wilczy?= =?utf-8?q?=C5=84ski?= , Rob Herring Cc: dingwei@marvell.com, cassel@kernel.org, Krishna Chaitanya Chundru , linuxppc-dev@lists.ozlabs.org, linux-pci@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-msm@vger.kernel.org, Manivannan Sadhasivam X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=openpgp-sha256; l=5609; i=manivannan.sadhasivam@linaro.org; h=from:subject:message-id; bh=+ITPzeoaQcEIkq+82fVSDeyUKwuRWQPYslcPdhuwyHg=; b=owEBbQGS/pANAwAKAVWfEeb+kc71AcsmYgBn75bD4Cd8YzJEF3HRP0cKDCIO4/b18SYn1gsUN i3KX+KTt4aJATMEAAEKAB0WIQRnpUMqgUjL2KRYJ5dVnxHm/pHO9QUCZ++WwwAKCRBVnxHm/pHO 9WTMB/9GHKbl1ReNJXYGisTpWVPXDX3UXEsckCiGgo2A143UhTD0joeYs2wDWZD3CuxbGZAVj7W 8dznHcVyatwu3oFqIoRqu//qlW+ioIAT8kwSZuLhoS443XFKUwXL18BkryEKc+UaZdf4v1QGoQh JgHksuRL1YAt7nG12tWWrP1Uj2dQ4VXb/RZRP/oy7uV3HnzUNcXPsFMJjJRPl8bZOZ00YP3CsEY 53+R1Xua+9ku9CF2S54VyE0KATQ2cU9VolZkQ8rq0iFposlw50jF/yVyqOZhqkdhbgJ1OFNeXdc kdb02a9ZxCWH1z/kwPHKMFZtd00u3fMnjNVr/nNvUaITap8m X-Developer-Key: i=manivannan.sadhasivam@linaro.org; a=openpgp; fpr=C668AEC3C3188E4C611465E7488550E901166008 X-Endpoint-Received: by B4 Relay for manivannan.sadhasivam@linaro.org/default with auth_id=185 X-Original-From: Manivannan Sadhasivam Reply-To: manivannan.sadhasivam@linaro.org From: Manivannan Sadhasivam From: Manivannan Sadhasivam The PCI link, when down, needs to be recovered to bring it back. But that cannot be done in a generic way as link recovery procedure is specific to host bridges. So add a new API pci_host_handle_link_down() that could be called by the host bridge drivers when the link goes down. The API will iterate through all the slots and calls the pcie_do_recovery() function with 'pci_channel_io_frozen' as the state. This will result in the execution of the AER Fatal error handling code. Since the link down recovery is pretty much the same as AER Fatal error handling, pcie_do_recovery() helper is reused here. First the AER error_detected callback will be triggered for the bridge and the downstream devices, then the 'reset_slot' callback for the host bridge will be called to recover the link. Once that's done, resume message will be broadcasted to the bridge and the downstream devices indicating successful link recovery. In case if the AER support is not enabled in the kernel, only the 'reset_slot' callback will be called for each slots as there is no way we could inform the drivers about link recovery. Signed-off-by: Manivannan Sadhasivam --- drivers/pci/pci.h | 22 ++++++++++++++++++++++ drivers/pci/pcie/err.c | 13 ++++++++++++- drivers/pci/probe.c | 7 +++++++ include/linux/pci.h | 1 + 4 files changed, 42 insertions(+), 1 deletion(-) diff --git a/drivers/pci/pci.h b/drivers/pci/pci.h index b81e99cd4b62a3022c8b07a09f212f6888674487..7ea81d596d5f9608237f5897c5c13288d9169207 100644 --- a/drivers/pci/pci.h +++ b/drivers/pci/pci.h @@ -966,6 +966,7 @@ int pci_aer_clear_status(struct pci_dev *dev); int pci_aer_raw_clear_status(struct pci_dev *dev); void pci_save_aer_state(struct pci_dev *dev); void pci_restore_aer_state(struct pci_dev *dev); +void pcie_do_recover_slots(struct pci_host_bridge *host); #else static inline void pci_no_aer(void) { } static inline void pci_aer_init(struct pci_dev *d) { } @@ -975,6 +976,27 @@ static inline int pci_aer_clear_status(struct pci_dev *dev) { return -EINVAL; } static inline int pci_aer_raw_clear_status(struct pci_dev *dev) { return -EINVAL; } static inline void pci_save_aer_state(struct pci_dev *dev) { } static inline void pci_restore_aer_state(struct pci_dev *dev) { } +static inline void pcie_do_recover_slots(struct pci_host_bridge *host) +{ + struct pci_bus *bus = host->bus; + struct pci_dev *dev; + int ret; + + if (!host->reset_slot) { + dev_warn(&host->dev, "Missing reset_slot() callback\n"); + return; + } + + for_each_pci_bridge(dev, bus) { + ret = host->reset_slot(host, dev); + if (ret) + dev_err(&host->dev, "failed to reset slot (%s): %d\n", + pci_name(dev), ret); + else + dev_dbg(&host->dev, "recovered slot (%s)\n", + pci_name(dev)); + } +} #endif #ifdef CONFIG_ACPI diff --git a/drivers/pci/pcie/err.c b/drivers/pci/pcie/err.c index 77ce9354532afee209f658175b86e625bba8a5ee..0f86c228245ef80c5bba4433c109ec37c57f4a67 100644 --- a/drivers/pci/pcie/err.c +++ b/drivers/pci/pcie/err.c @@ -196,6 +196,7 @@ pci_ers_result_t pcie_do_recovery(struct pci_dev *dev, struct pci_dev *bridge; pci_ers_result_t status = PCI_ERS_RESULT_CAN_RECOVER; struct pci_host_bridge *host = pci_find_host_bridge(dev->bus); + int ret; /* * If the error was detected by a Root Port, Downstream Port, RCEC, @@ -219,7 +220,8 @@ pci_ers_result_t pcie_do_recovery(struct pci_dev *dev, pci_dbg(bridge, "broadcast error_detected message\n"); if (state == pci_channel_io_frozen) { pci_walk_bridge(bridge, report_frozen_detected, &status); - if (reset_subordinates(bridge) != PCI_ERS_RESULT_RECOVERED) { + if (reset_subordinates && reset_subordinates(bridge) != + PCI_ERS_RESULT_RECOVERED) { pci_warn(bridge, "subordinate device reset failed\n"); goto failed; } @@ -280,3 +282,12 @@ pci_ers_result_t pcie_do_recovery(struct pci_dev *dev, return status; } + +void pcie_do_recover_slots(struct pci_host_bridge *host) +{ + struct pci_bus *bus = host->bus; + struct pci_dev *dev; + + for_each_pci_bridge(dev, bus) + pcie_do_recovery(dev, pci_channel_io_frozen, NULL); +} diff --git a/drivers/pci/probe.c b/drivers/pci/probe.c index 364fa2a514f8a68fb18bded3259c6847d3932f8b..60ad20eea0259797e68afa7979bb1fc24b6f213b 100644 --- a/drivers/pci/probe.c +++ b/drivers/pci/probe.c @@ -3249,6 +3249,13 @@ int pci_host_probe(struct pci_host_bridge *bridge) } EXPORT_SYMBOL_GPL(pci_host_probe); +void pci_host_handle_link_down(struct pci_host_bridge *bridge) +{ + dev_info(&bridge->dev, "Recovering slots due to Link Down\n"); + pcie_do_recover_slots(bridge); +} +EXPORT_SYMBOL_GPL(pci_host_handle_link_down); + int pci_bus_insert_busn_res(struct pci_bus *b, int bus, int bus_max) { struct resource *res = &b->busn_res; diff --git a/include/linux/pci.h b/include/linux/pci.h index 8d7d2a49b76cf64b4218b179cec495e0d69ddf6f..76e977af2d524200b67f39a6d0417ee565cf5116 100644 --- a/include/linux/pci.h +++ b/include/linux/pci.h @@ -1157,6 +1157,7 @@ struct pci_bus *pci_create_root_bus(struct device *parent, int bus, struct pci_ops *ops, void *sysdata, struct list_head *resources); int pci_host_probe(struct pci_host_bridge *bridge); +void pci_host_handle_link_down(struct pci_host_bridge *bridge); int pci_bus_insert_busn_res(struct pci_bus *b, int bus, int busmax); int pci_bus_update_busn_res_end(struct pci_bus *b, int busmax); void pci_bus_release_busn_res(struct pci_bus *b); From patchwork Fri Apr 4 08:22:24 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Manivannan Sadhasivam X-Patchwork-Id: 14038202 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id BFFBB194C86; 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dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="D9ShQ6FP" Received: by smtp.kernel.org (Postfix) with ESMTPS id 4899FC4CEF0; Fri, 4 Apr 2025 08:22:30 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1743754950; bh=ffTrhsY9FJRcfVww9i0y0yxQfrwIq4gqaddUeXhlv5A=; h=From:Date:Subject:References:In-Reply-To:To:Cc:Reply-To:From; b=D9ShQ6FPlAhquV1oMV5an//O1orxi1OZg9wU398rNbW2M3N9VvAJgEOKL2J3utjoH LtND4CqPvQ3uY4FNuCwLUJo7wJlvomk/Dy8ruh00M5PEqIFeIx/tGcJe9KqQRf8XDB lwms0QcAXMnVI+t+i5NDq/jIvN03Iyy96ISpJPwU6qQGOe5pXbcZF/Xhbf9U7b7OJS ZKjfd/HgTk2XtpRw6cDnYYnjwyeNRFHxG9niMvhL2UZbuX1oA3bgnHd1wM3gwXUVPy NFPk2jVH9uJEfNEPyNmWYlDJNvrLUiG3l4NA0Nz7VnjG6eaPb29poVgL8z+U+vJVja XjS6YeDuMn3dA== Received: from aws-us-west-2-korg-lkml-1.web.codeaurora.org (localhost.localdomain [127.0.0.1]) by smtp.lore.kernel.org (Postfix) with ESMTP id 39BA7C3601E; Fri, 4 Apr 2025 08:22:30 +0000 (UTC) Date: Fri, 04 Apr 2025 13:52:24 +0530 Subject: [PATCH 4/4] PCI: qcom: Add support for resetting the slot due to link down event Precedence: bulk X-Mailing-List: linux-pci@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20250404-pcie-reset-slot-v1-4-98952918bf90@linaro.org> References: <20250404-pcie-reset-slot-v1-0-98952918bf90@linaro.org> In-Reply-To: <20250404-pcie-reset-slot-v1-0-98952918bf90@linaro.org> To: Mahesh J Salgaonkar , Oliver O'Halloran , Bjorn Helgaas , Lorenzo Pieralisi , =?utf-8?q?Krzysztof_Wilczy?= =?utf-8?q?=C5=84ski?= , Rob Herring Cc: dingwei@marvell.com, cassel@kernel.org, Krishna Chaitanya Chundru , linuxppc-dev@lists.ozlabs.org, linux-pci@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-msm@vger.kernel.org, Manivannan Sadhasivam X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=openpgp-sha256; l=6144; i=manivannan.sadhasivam@linaro.org; h=from:subject:message-id; bh=HLmverztHMHdlf6iHpfj2weCoSC+ZBfRtve4NgX9dNk=; b=owEBbQGS/pANAwAKAVWfEeb+kc71AcsmYgBn75bD4IKYNbv//nyxjS6fn8rRAv9TJ+ustu03A 5oBDvZ7iXWJATMEAAEKAB0WIQRnpUMqgUjL2KRYJ5dVnxHm/pHO9QUCZ++WwwAKCRBVnxHm/pHO 9QvcCACSocfRLEqKZDYj0W0aZt8ZpVhJGCB/hNr+d8Ytjf5Ygef2P6wt+710HTaKJwNdwjtJemr sZhT4x/YDMcUM0TpJvi5dksSBcntnglOMlNNMKN0HSfyXiDbFWK1TgO/nuvZFpvL9KeJiy4JAlm 1Ys94fK8eXXd7o/qsuIWTKIUSZT5fPgWCz11VNDSjieNKw2cZRxYiD41XxKpCwijWv+HZ95zd5X zFpKu6rnQibq6H+JASDtpXk8xg51Wd46Lb2O+7cDy7PGv8l7wBnTfyM9WTLTFA5VTmFo/kGIMID gzXXMn5zeJScJVqWdvgORCdygUDJhliN4Qi1EUQozbWJPIZu X-Developer-Key: i=manivannan.sadhasivam@linaro.org; a=openpgp; fpr=C668AEC3C3188E4C611465E7488550E901166008 X-Endpoint-Received: by B4 Relay for manivannan.sadhasivam@linaro.org/default with auth_id=185 X-Original-From: Manivannan Sadhasivam Reply-To: manivannan.sadhasivam@linaro.org From: Manivannan Sadhasivam From: Manivannan Sadhasivam The PCIe link can go down under circumstances such as the device firmware crash, link instability, etc... When that happens, the PCIe slot needs to be reset to make it operational again. Currently, the driver is not handling the link down event, due to which the users have to restart the machine to make PCIe link operational again. So fix it by detecting the link down event and adding support to resetting the slot. Since the Qcom PCIe controllers report the link down event through the 'global' IRQ, enable the link down event by setting PARF_INT_ALL_LINK_DOWN bit in PARF_INT_ALL_MASK register. Then in the case of the event, call pci_host_handle_link_down() API in the handler to let the PCI core handle the link down condition. The API will internally call, 'pci_host_bridge::reset_slot()' callback to reset the slot in a platform specific way. So implement the callback to reset the slot by first resetting the PCIe core, followed by reinitializing the resources and then finally starting the link again. Signed-off-by: Manivannan Sadhasivam --- drivers/pci/controller/dwc/pcie-qcom.c | 89 +++++++++++++++++++++++++++++++++- 1 file changed, 87 insertions(+), 2 deletions(-) diff --git a/drivers/pci/controller/dwc/pcie-qcom.c b/drivers/pci/controller/dwc/pcie-qcom.c index dc98ae63362db0422384b1879a2b9a7dc564d091..b0df108fb4f3c6a8b8290062ecb3e1c5c34ddd4c 100644 --- a/drivers/pci/controller/dwc/pcie-qcom.c +++ b/drivers/pci/controller/dwc/pcie-qcom.c @@ -55,6 +55,7 @@ #define PARF_INT_ALL_STATUS 0x224 #define PARF_INT_ALL_CLEAR 0x228 #define PARF_INT_ALL_MASK 0x22c +#define PARF_STATUS 0x230 #define PARF_SID_OFFSET 0x234 #define PARF_BDF_TRANSLATE_CFG 0x24c #define PARF_DBI_BASE_ADDR_V2 0x350 @@ -130,8 +131,11 @@ /* PARF_LTSSM register fields */ #define LTSSM_EN BIT(8) +#define SW_CLEAR_FLUSH_MODE BIT(10) +#define FLUSH_MODE BIT(11) /* PARF_INT_ALL_{STATUS/CLEAR/MASK} register fields */ +#define PARF_INT_ALL_LINK_DOWN BIT(1) #define PARF_INT_ALL_LINK_UP BIT(13) #define PARF_INT_MSI_DEV_0_7 GENMASK(30, 23) @@ -145,6 +149,9 @@ /* PARF_BDF_TO_SID_CFG fields */ #define BDF_TO_SID_BYPASS BIT(0) +/* PARF_STATUS fields */ +#define FLUSH_COMPLETED BIT(8) + /* ELBI_SYS_CTRL register fields */ #define ELBI_SYS_CTRL_LT_ENABLE BIT(0) @@ -169,6 +176,7 @@ PCIE_CAP_SLOT_POWER_LIMIT_SCALE) #define PERST_DELAY_US 1000 +#define FLUSH_TIMEOUT_US 100 #define QCOM_PCIE_CRC8_POLYNOMIAL (BIT(2) | BIT(1) | BIT(0)) @@ -274,11 +282,14 @@ struct qcom_pcie { struct icc_path *icc_cpu; const struct qcom_pcie_cfg *cfg; struct dentry *debugfs; + int global_irq; bool suspended; bool use_pm_opp; }; #define to_qcom_pcie(x) dev_get_drvdata((x)->dev) +static int qcom_pcie_reset_slot(struct pci_host_bridge *bridge, + struct pci_dev *pdev); static void qcom_ep_reset_assert(struct qcom_pcie *pcie) { @@ -1263,6 +1274,8 @@ static int qcom_pcie_host_init(struct dw_pcie_rp *pp) goto err_assert_reset; } + pp->bridge->reset_slot = qcom_pcie_reset_slot; + return 0; err_assert_reset: @@ -1300,6 +1313,73 @@ static const struct dw_pcie_host_ops qcom_pcie_dw_ops = { .post_init = qcom_pcie_host_post_init, }; +static int qcom_pcie_reset_slot(struct pci_host_bridge *bridge, + struct pci_dev *pdev) +{ + struct pci_bus *bus = bridge->bus; + struct dw_pcie_rp *pp = bus->sysdata; + struct dw_pcie *pci = to_dw_pcie_from_pp(pp); + struct qcom_pcie *pcie = to_qcom_pcie(pci); + struct device *dev = pcie->pci->dev; + u32 val; + int ret; + + /* Wait for the pending transactions to be completed */ + ret = readl_relaxed_poll_timeout(pcie->parf + PARF_STATUS, val, + val & FLUSH_COMPLETED, 10, + FLUSH_TIMEOUT_US); + if (ret) { + dev_err(dev, "Flush completion failed: %d\n", ret); + goto err_host_deinit; + } + + /* Clear the FLUSH_MODE to allow the core to be reset */ + val = readl(pcie->parf + PARF_LTSSM); + val |= SW_CLEAR_FLUSH_MODE; + writel(val, pcie->parf + PARF_LTSSM); + + /* Wait for the FLUSH_MODE to clear */ + ret = readl_relaxed_poll_timeout(pcie->parf + PARF_LTSSM, val, + !(val & FLUSH_MODE), 10, + FLUSH_TIMEOUT_US); + if (ret) { + dev_err(dev, "Flush mode clear failed: %d\n", ret); + goto err_host_deinit; + } + + qcom_pcie_host_deinit(pp); + + ret = qcom_pcie_host_init(pp); + if (ret) { + dev_err(dev, "Host init failed\n"); + return ret; + } + + ret = dw_pcie_setup_rc(pp); + if (ret) + goto err_host_deinit; + + /* + * Re-enable global IRQ events as the PARF_INT_ALL_MASK register is + * non-sticky. + */ + if (pcie->global_irq) + writel_relaxed(PARF_INT_ALL_LINK_UP | PARF_INT_ALL_LINK_DOWN | + PARF_INT_MSI_DEV_0_7, pcie->parf + PARF_INT_ALL_MASK); + + qcom_pcie_start_link(pci); + dw_pcie_wait_for_link(pci); + + dev_dbg(dev, "Slot reset completed\n"); + + return 0; + +err_host_deinit: + qcom_pcie_host_deinit(pp); + + return ret; +} + /* Qcom IP rev.: 2.1.0 Synopsys IP rev.: 4.01a */ static const struct qcom_pcie_ops ops_2_1_0 = { .get_resources = qcom_pcie_get_resources_2_1_0, @@ -1571,6 +1651,9 @@ static irqreturn_t qcom_pcie_global_irq_thread(int irq, void *data) pci_unlock_rescan_remove(); qcom_pcie_icc_opp_update(pcie); + } else if (FIELD_GET(PARF_INT_ALL_LINK_DOWN, status)) { + dev_dbg(dev, "Received Link down event\n"); + pci_host_handle_link_down(pp->bridge); } else { dev_WARN_ONCE(dev, 1, "Received unknown event. INT_STATUS: 0x%08x\n", status); @@ -1732,8 +1815,10 @@ static int qcom_pcie_probe(struct platform_device *pdev) goto err_host_deinit; } - writel_relaxed(PARF_INT_ALL_LINK_UP | PARF_INT_MSI_DEV_0_7, - pcie->parf + PARF_INT_ALL_MASK); + writel_relaxed(PARF_INT_ALL_LINK_UP | PARF_INT_ALL_LINK_DOWN | + PARF_INT_MSI_DEV_0_7, pcie->parf + PARF_INT_ALL_MASK); + + pcie->global_irq = irq; } qcom_pcie_icc_opp_update(pcie);