From patchwork Fri Apr 4 13:52:18 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Teddy Astie X-Patchwork-Id: 14038500 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.xenproject.org (lists.xenproject.org [192.237.175.120]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 1C169C36014 for ; Fri, 4 Apr 2025 13:52:34 +0000 (UTC) Received: from list by lists.xenproject.org with outflank-mailman.938259.1339186 (Exim 4.92) (envelope-from ) id 1u0hT8-0000re-Fo; Fri, 04 Apr 2025 13:52:26 +0000 X-Outflank-Mailman: Message body and most headers restored to incoming version Received: by outflank-mailman (output) from mailman id 938259.1339186; Fri, 04 Apr 2025 13:52:26 +0000 Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1u0hT8-0000rV-CI; Fri, 04 Apr 2025 13:52:26 +0000 Received: by outflank-mailman (input) for mailman id 938259; Fri, 04 Apr 2025 13:52:25 +0000 Received: from se1-gles-flk1-in.inumbo.com ([94.247.172.50] helo=se1-gles-flk1.inumbo.com) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1u0hT7-0000qo-4E for xen-devel@lists.xenproject.org; Fri, 04 Apr 2025 13:52:25 +0000 Received: from mail180-44.suw31.mandrillapp.com (mail180-44.suw31.mandrillapp.com [198.2.180.44]) by se1-gles-flk1.inumbo.com (Halon) with ESMTPS id 0630c483-115c-11f0-9ffb-bf95429c2676; Fri, 04 Apr 2025 15:52:19 +0200 (CEST) Received: from pmta11.mandrill.prod.suw01.rsglab.com (localhost [127.0.0.1]) by mail180-44.suw31.mandrillapp.com (Mailchimp) with ESMTP id 4ZTg5Z3Tbnz705mdc for ; Fri, 4 Apr 2025 13:52:18 +0000 (GMT) Received: from [37.26.189.201] by mandrillapp.com id 57e71f5af35149d8a34943717485ba4f; Fri, 04 Apr 2025 13:52:18 +0000 X-BeenThere: xen-devel@lists.xenproject.org List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Errors-To: xen-devel-bounces@lists.xenproject.org Precedence: list Sender: "Xen-devel" X-Inumbo-ID: 0630c483-115c-11f0-9ffb-bf95429c2676 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=mandrillapp.com; s=mte1; t=1743774738; x=1744044738; bh=LN9JfEv4G0O3BbLHkaCk2NpM2eltoGV6GWKw+Cf44zs=; h=From:Subject:To:Cc:Message-Id:Feedback-ID:Date:MIME-Version: Content-Type:Content-Transfer-Encoding:CC:Date:Subject:From; b=a5ykMxaXpCa50WHQ4x280jHt4pItLfA86X+HDbUIdx4HLysFvFT6KPtUnflyUgLx3 uTzg0RihgL+sx+3X7VfKmJr5PbwHkfZ4ukULNvzficqAMKE9z27usEcDjsrrSaniRJ CKTH7gs7pj47xTqOvOVmgjCNkzTWhrhe4TDRUITDJWileVQ/zzSpRXblgs5dhFOmwR vq91sk4pP3wUmrRH6SywiUN9IRYYF15A+17EJufx5i3UfYxeyI2BmEEGWl2MROdRZ7 g7NECuQebq4VbBz2tivuyHP8PrxD/g9gWbjnHB/kfHdST1yndhN1T9oasr3/iuZKto Ill9dOcpDqR/A== DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=vates.tech; s=mte1; t=1743774738; x=1744035238; i=teddy.astie@vates.tech; bh=LN9JfEv4G0O3BbLHkaCk2NpM2eltoGV6GWKw+Cf44zs=; h=From:Subject:To:Cc:Message-Id:Feedback-ID:Date:MIME-Version: Content-Type:Content-Transfer-Encoding:CC:Date:Subject:From; b=fwtG2qpa6yJq9o/L0+O2EpFr1URgCOGYsE563ESYYKLO5k3jzfNk85ZEVrGnPG0sl AawkUKMA6yks+j9dyrfYecfR/IpQSJuYcvkGDOpwMBJDNWWsIInppoZmL05b6U/jRo xXYMyIr3hoodXvqUH5bxAZvM3M8AqX0mlTx+zOtXRQrYMsrHWhdcjDJsqUT858fYFe t6YIZJH/0plj1SIiv8eyb6RA81F3lZESCQgEsyAVURV+zxP4FiIO+PS5wtuFT/S+v3 MntarkMVoGONYCGQ23zxzsLJTI6U7FCUPi6adG75nui3zY6jZntrSCVDJBif0M2zyG BL4FUyXXU2vPQ== From: "Teddy Astie" Subject: =?utf-8?q?=5BPATCH_v3_1/2=5D_x86/amd=3A_Add_guest_support_for_AMD_T?= =?utf-8?q?CE?= X-Mailer: git-send-email 2.47.2 X-Bm-Disclaimer: Yes X-Bm-Milter-Handled: 4ffbd6c1-ee69-4e1b-aabd-f977039bd3e2 X-Bm-Transport-Timestamp: 1743774737788 To: xen-devel@lists.xenproject.org Cc: "Teddy Astie" Message-Id: <2bac0ded3456e04b49b48cf0808203e76fc6a622.1743771654.git.teddy.astie@vates.tech> X-Native-Encoded: 1 X-Report-Abuse: =?utf-8?q?Please_forward_a_copy_of_this_message=2C_including?= =?utf-8?q?_all_headers=2C_to_abuse=40mandrill=2Ecom=2E_You_can_also_report_?= =?utf-8?q?abuse_here=3A_https=3A//mandrillapp=2Ecom/contact/abuse=3Fid=3D30?= =?utf-8?q?504962=2E57e71f5af35149d8a34943717485ba4f?= X-Mandrill-User: md_30504962 Feedback-ID: 30504962:30504962.20250404:md Date: Fri, 04 Apr 2025 13:52:18 +0000 MIME-Version: 1.0 AMD Translation Cache Extension is a flag that can be enabled in the EFER MSR to optimize some TLB flushes. Expose this flag to guest if supported by hardware. Only expose this feature to HAP-enabled guests. Guests with shadow paging guests have their TLB flush operations intercepted and handled separately, without taking account to this flag. PV guest follows Xen TLB flush behavior. Signed-off-by: Teddy Astie --- v3: - hide from PV guests - review commit description --- CHANGELOG.md | 1 + xen/arch/x86/hvm/hvm.c | 3 +++ xen/arch/x86/include/asm/msr-index.h | 3 ++- xen/arch/x86/pv/emul-priv-op.c | 4 ++-- xen/include/public/arch-x86/cpufeatureset.h | 1 + 5 files changed, 9 insertions(+), 3 deletions(-) diff --git a/CHANGELOG.md b/CHANGELOG.md index 8f6afa5c85..dbfecefbd4 100644 --- a/CHANGELOG.md +++ b/CHANGELOG.md @@ -18,6 +18,7 @@ The format is based on [Keep a Changelog](https://keepachangelog.com/en/1.0.0/) - Support PCI passthrough for HVM domUs when dom0 is PVH (note SR-IOV capability usage is not yet supported on PVH dom0). - Smoke tests for the FreeBSD Xen builds in Cirrus CI. + - Guest support for AMD Translation Cache Extension feature. ### Removed diff --git a/xen/arch/x86/hvm/hvm.c b/xen/arch/x86/hvm/hvm.c index 5950f3160f..184357b042 100644 --- a/xen/arch/x86/hvm/hvm.c +++ b/xen/arch/x86/hvm/hvm.c @@ -959,6 +959,9 @@ const char *hvm_efer_valid(const struct vcpu *v, uint64_t value, if ( (value & EFER_FFXSE) && !p->extd.ffxsr ) return "FFXSE without feature"; + if ( (value & EFER_TCE) && !p->extd.tce ) + return "TCE without feature"; + if ( (value & EFER_AIBRSE) && !p->extd.auto_ibrs ) return "AutoIBRS without feature"; diff --git a/xen/arch/x86/include/asm/msr-index.h b/xen/arch/x86/include/asm/msr-index.h index 22d9e76e55..d8576aec1c 100644 --- a/xen/arch/x86/include/asm/msr-index.h +++ b/xen/arch/x86/include/asm/msr-index.h @@ -200,11 +200,12 @@ #define EFER_NXE (_AC(1, ULL) << 11) /* No Execute Enable */ #define EFER_SVME (_AC(1, ULL) << 12) /* Secure Virtual Machine Enable */ #define EFER_FFXSE (_AC(1, ULL) << 14) /* Fast FXSAVE/FXRSTOR */ +#define EFER_TCE (_AC(1, ULL) << 15) /* Translation Cache Extensions */ #define EFER_AIBRSE (_AC(1, ULL) << 21) /* Automatic IBRS Enable */ #define EFER_KNOWN_MASK \ (EFER_SCE | EFER_LME | EFER_LMA | EFER_NXE | EFER_SVME | EFER_FFXSE | \ - EFER_AIBRSE) + EFER_TCE | EFER_AIBRSE) #define MSR_STAR _AC(0xc0000081, U) /* legacy mode SYSCALL target */ #define MSR_LSTAR _AC(0xc0000082, U) /* long mode SYSCALL target */ diff --git a/xen/arch/x86/pv/emul-priv-op.c b/xen/arch/x86/pv/emul-priv-op.c index 70150c2722..531228b2da 100644 --- a/xen/arch/x86/pv/emul-priv-op.c +++ b/xen/arch/x86/pv/emul-priv-op.c @@ -857,8 +857,8 @@ static uint64_t guest_efer(const struct domain *d) { uint64_t val; - /* Hide unknown bits, and unconditionally hide SVME and AIBRSE from guests. */ - val = read_efer() & EFER_KNOWN_MASK & ~(EFER_SVME | EFER_AIBRSE); + /* Hide unknown bits, and unconditionally hide SVME, TCE and AIBRSE from guests. */ + val = read_efer() & EFER_KNOWN_MASK & ~(EFER_SVME | EFER_TCE | EFER_AIBRSE); /* * Hide the 64-bit features from 32-bit guests. SCE has * vendor-dependent behaviour. diff --git a/xen/include/public/arch-x86/cpufeatureset.h b/xen/include/public/arch-x86/cpufeatureset.h index cc6e984a88..8182d2dbed 100644 --- a/xen/include/public/arch-x86/cpufeatureset.h +++ b/xen/include/public/arch-x86/cpufeatureset.h @@ -170,6 +170,7 @@ XEN_CPUFEATURE(SKINIT, 3*32+12) /* SKINIT/STGI instructions */ XEN_CPUFEATURE(WDT, 3*32+13) /* Watchdog timer */ XEN_CPUFEATURE(LWP, 3*32+15) /* Light Weight Profiling */ XEN_CPUFEATURE(FMA4, 3*32+16) /*A 4 operands MAC instructions */ +XEN_CPUFEATURE(TCE, 3*32+17) /*H Translation Cache Extension support */ XEN_CPUFEATURE(NODEID_MSR, 3*32+19) /* NodeId MSR */ XEN_CPUFEATURE(TBM, 3*32+21) /*A trailing bit manipulations */ XEN_CPUFEATURE(TOPOEXT, 3*32+22) /* topology extensions CPUID leafs */ From patchwork Fri Apr 4 13:52:18 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Teddy Astie X-Patchwork-Id: 14038499 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.xenproject.org (lists.xenproject.org [192.237.175.120]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 48703C36010 for ; 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a=rsa-sha256; c=relaxed/relaxed; d=vates.tech; s=mte1; t=1743774738; x=1744035238; i=teddy.astie@vates.tech; bh=nbTN4p4U7Kn8AweJEt9smKXgKC3x3eyXeKtnPBjIBmg=; h=From:Subject:To:Cc:Message-Id:In-Reply-To:References:Feedback-ID: Date:MIME-Version:Content-Type:Content-Transfer-Encoding:CC:Date: Subject:From; b=Qju2gM6i4JIZNVApyiSbF+v4B/KshlpMm+/9+Fqf+43GVhH7IlUIMxWxIsBQJGVbw YUA6CerpqhFSNsZ2jeHn1aqJb9WASp4Y7+qBLguuAFG6n/3v32kt7x4b5PHZxv27ms ONa6V9BhG21v2tJQwcoF/G76Ab+lrR4LCz04yR4B61Qv83kPyXtzgO0lsBepwfmGbN VxXyp1efzx0O+AMjDhXfgefLSeZIBlVJ0O/a2KF/ihWvSdCmarVygtsLt75PFU02MY +yy8zeNG2JfrH7I+LhHFChU2fhKwfU/PukQ+qajZ9sF0AfJHAkzcEKBLmvQ7B47tcg 0AtpsQvF980TA== From: "Teddy Astie" Subject: =?utf-8?q?=5BPATCH_v3_2/2=5D_x86/amd=3A_Enable_TCE_in_Xen?= X-Mailer: git-send-email 2.47.2 X-Bm-Disclaimer: Yes X-Bm-Milter-Handled: 4ffbd6c1-ee69-4e1b-aabd-f977039bd3e2 X-Bm-Transport-Timestamp: 1743774738180 To: xen-devel@lists.xenproject.org Cc: "Teddy Astie" Message-Id: <79b08632b74dc13b8c399003eb76d198cb73ac32.1743771654.git.teddy.astie@vates.tech> In-Reply-To: <2bac0ded3456e04b49b48cf0808203e76fc6a622.1743771654.git.teddy.astie@vates.tech> References: <2bac0ded3456e04b49b48cf0808203e76fc6a622.1743771654.git.teddy.astie@vates.tech> X-Native-Encoded: 1 X-Report-Abuse: =?utf-8?q?Please_forward_a_copy_of_this_message=2C_including?= =?utf-8?q?_all_headers=2C_to_abuse=40mandrill=2Ecom=2E_You_can_also_report_?= =?utf-8?q?abuse_here=3A_https=3A//mandrillapp=2Ecom/contact/abuse=3Fid=3D30?= =?utf-8?q?504962=2Eec15a1c33c95496faa2cfe236b78d41d?= X-Mandrill-User: md_30504962 Feedback-ID: 30504962:30504962.20250404:md Date: Fri, 04 Apr 2025 13:52:18 +0000 MIME-Version: 1.0 Aside exposing this flag to guests, Xen can also make use of it to reduce the cost of some TLB flushes. Enable this flag if supported by hardware. Signed-off-by: Teddy Astie --- v2: - Add changelog entry - use trampoline_efer - use cpu_has_tce instead of opencoded boot_cpu_has(X86_FEATURE_TCE) v3: - drop message - use bootsym for modifying trampoline_efer --- CHANGELOG.md | 2 +- xen/arch/x86/include/asm/cpufeature.h | 1 + xen/arch/x86/setup.c | 6 ++++++ 3 files changed, 8 insertions(+), 1 deletion(-) diff --git a/CHANGELOG.md b/CHANGELOG.md index dbfecefbd4..375905e68a 100644 --- a/CHANGELOG.md +++ b/CHANGELOG.md @@ -18,7 +18,7 @@ The format is based on [Keep a Changelog](https://keepachangelog.com/en/1.0.0/) - Support PCI passthrough for HVM domUs when dom0 is PVH (note SR-IOV capability usage is not yet supported on PVH dom0). - Smoke tests for the FreeBSD Xen builds in Cirrus CI. - - Guest support for AMD Translation Cache Extension feature. + - Guest and Xen support for AMD Translation Cache Extension feature. ### Removed diff --git a/xen/arch/x86/include/asm/cpufeature.h b/xen/arch/x86/include/asm/cpufeature.h index 05399fb9c9..ab6d07b767 100644 --- a/xen/arch/x86/include/asm/cpufeature.h +++ b/xen/arch/x86/include/asm/cpufeature.h @@ -114,6 +114,7 @@ static inline bool boot_cpu_has(unsigned int feat) #define cpu_has_xop boot_cpu_has(X86_FEATURE_XOP) #define cpu_has_skinit boot_cpu_has(X86_FEATURE_SKINIT) #define cpu_has_fma4 boot_cpu_has(X86_FEATURE_FMA4) +#define cpu_has_tce boot_cpu_has(X86_FEATURE_TCE) #define cpu_has_tbm boot_cpu_has(X86_FEATURE_TBM) /* CPUID level 0x0000000D:1.eax */ diff --git a/xen/arch/x86/setup.c b/xen/arch/x86/setup.c index d70abb7e0c..9b1924ad05 100644 --- a/xen/arch/x86/setup.c +++ b/xen/arch/x86/setup.c @@ -2008,6 +2008,12 @@ void asmlinkage __init noreturn __start_xen(void) if ( cpu_has_pku ) set_in_cr4(X86_CR4_PKE); + if ( cpu_has_tce ) + { + write_efer(read_efer() | EFER_TCE); + bootsym(trampoline_efer) |= EFER_TCE; + } + if ( opt_invpcid && cpu_has_invpcid ) use_invpcid = true;