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Sat, 05 Apr 2025 07:00:07 -0700 (PDT) Received: from server.roeck-us.net ([2600:1700:e321:62f0:da43:aeff:fecc:bfd5]) by smtp.gmail.com with ESMTPSA id 41be03b00d2f7-af9bc41c626sm3743062a12.78.2025.04.05.07.00.06 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 05 Apr 2025 07:00:06 -0700 (PDT) From: Guenter Roeck To: qemu-devel@nongnu.org Cc: Richard Henderson , Peter Maydell , Bernhard Beschow , Guenter Roeck Subject: [PATCH 1/2] hw: usb: xhci: Add property to support writing ERSTBA in high-low order Date: Sat, 5 Apr 2025 07:00:01 -0700 Message-ID: <20250405140002.3537411-2-linux@roeck-us.net> X-Mailer: git-send-email 2.45.2 In-Reply-To: <20250405140002.3537411-1-linux@roeck-us.net> References: <20250405140002.3537411-1-linux@roeck-us.net> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::42a; envelope-from=groeck7@gmail.com; helo=mail-pf1-x42a.google.com X-Spam_score_int: -16 X-Spam_score: -1.7 X-Spam_bar: - X-Spam_report: (-1.7 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_ENVFROM_END_DIGIT=0.25, FREEMAIL_FORGED_FROMDOMAIN=0.001, FREEMAIL_FROM=0.001, HEADER_FROM_DIFFERENT_DOMAINS=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org According to the XHCI specification, ERSTBA should be written in Low-High order. The Linux kernel writes the high word first. This results in an initialization failure. The following information is found in the Linux kernel commit log. [Synopsys]- The host controller was design to support ERST setting during the RUN state. But since there is a limitation in controller in supporting separate ERSTBA_HI and ERSTBA_LO programming, It is supported when the ERSTBA is programmed in 64bit, or in 32 bit mode ERSTBA_HI before ERSTBA_LO [Synopsys]- The internal initialization of event ring fetches the "Event Ring Segment Table Entry" based on the indication of ERSTBA_LO written. Add property to support writing the high word first. Signed-off-by: Guenter Roeck --- hw/usb/hcd-xhci.c | 8 +++++++- hw/usb/hcd-xhci.h | 1 + 2 files changed, 8 insertions(+), 1 deletion(-) diff --git a/hw/usb/hcd-xhci.c b/hw/usb/hcd-xhci.c index 64c3a23b9b..8c0ba569c8 100644 --- a/hw/usb/hcd-xhci.c +++ b/hw/usb/hcd-xhci.c @@ -3107,10 +3107,15 @@ static void xhci_runtime_write(void *ptr, hwaddr reg, } else { intr->erstba_low = val & 0xffffffc0; } + if (xhci->erstba_hi_lo) { + xhci_er_reset(xhci, v); + } break; case 0x14: /* ERSTBA high */ intr->erstba_high = val; - xhci_er_reset(xhci, v); + if (!xhci->erstba_hi_lo) { + xhci_er_reset(xhci, v); + } break; case 0x18: /* ERDP low */ if (val & ERDP_EHB) { @@ -3636,6 +3641,7 @@ static const Property xhci_properties[] = { DEFINE_PROP_UINT32("p3", XHCIState, numports_3, 4), DEFINE_PROP_LINK("host", XHCIState, hostOpaque, TYPE_DEVICE, DeviceState *), + DEFINE_PROP_BOOL("erstba-hi-lo", XHCIState, erstba_hi_lo, false), }; static void xhci_class_init(ObjectClass *klass, void *data) diff --git a/hw/usb/hcd-xhci.h b/hw/usb/hcd-xhci.h index 9c3974f148..cf3f074261 100644 --- a/hw/usb/hcd-xhci.h +++ b/hw/usb/hcd-xhci.h @@ -189,6 +189,7 @@ typedef struct XHCIState { uint32_t numports_3; uint32_t numintrs; uint32_t numslots; + bool erstba_hi_lo; uint32_t flags; uint32_t max_pstreams_mask; void (*intr_update)(XHCIState *s, int n, bool enable); From patchwork Sat Apr 5 14:00:02 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Guenter Roeck X-Patchwork-Id: 14039145 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 5483BC36010 for ; Sat, 5 Apr 2025 14:01:12 +0000 (UTC) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1u144E-00027P-5m; Sat, 05 Apr 2025 10:00:14 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1u144B-00025z-SJ for qemu-devel@nongnu.org; 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Sat, 05 Apr 2025 07:00:08 -0700 (PDT) Received: from server.roeck-us.net ([2600:1700:e321:62f0:da43:aeff:fecc:bfd5]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-229785bfea5sm50149875ad.54.2025.04.05.07.00.08 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 05 Apr 2025 07:00:08 -0700 (PDT) From: Guenter Roeck To: qemu-devel@nongnu.org Cc: Richard Henderson , Peter Maydell , Bernhard Beschow , Guenter Roeck Subject: [PATCH 2/2] hw/usb/hcd-dwc3: Set erstba-hi-lo property Date: Sat, 5 Apr 2025 07:00:02 -0700 Message-ID: <20250405140002.3537411-3-linux@roeck-us.net> X-Mailer: git-send-email 2.45.2 In-Reply-To: <20250405140002.3537411-1-linux@roeck-us.net> References: <20250405140002.3537411-1-linux@roeck-us.net> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::633; envelope-from=groeck7@gmail.com; helo=mail-pl1-x633.google.com X-Spam_score_int: -16 X-Spam_score: -1.7 X-Spam_bar: - X-Spam_report: (-1.7 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_ENVFROM_END_DIGIT=0.25, FREEMAIL_FORGED_FROMDOMAIN=0.001, FREEMAIL_FROM=0.001, HEADER_FROM_DIFFERENT_DOMAINS=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org The dwc3 hardware requires the ERSTBA address to be written in high-low order. From information found in the Linux kernel: [Synopsys]- The host controller was design to support ERST setting during the RUN state. But since there is a limitation in controller in supporting separate ERSTBA_HI and ERSTBA_LO programming, It is supported when the ERSTBA is programmed in 64bit, or in 32 bit mode ERSTBA_HI before ERSTBA_LO [Synopsys]- The internal initialization of event ring fetches the "Event Ring Segment Table Entry" based on the indication of ERSTBA_LO written. Inform the XHCI core to expect ERSTBA to be written in high-low order. Signed-off-by: Guenter Roeck --- hw/usb/hcd-dwc3.c | 1 + 1 file changed, 1 insertion(+) diff --git a/hw/usb/hcd-dwc3.c b/hw/usb/hcd-dwc3.c index 0bceee2712..6783d55526 100644 --- a/hw/usb/hcd-dwc3.c +++ b/hw/usb/hcd-dwc3.c @@ -603,6 +603,7 @@ static void usb_dwc3_realize(DeviceState *dev, Error **errp) SysBusDevice *sbd = SYS_BUS_DEVICE(dev); Error *err = NULL; + qdev_prop_set_bit(DEVICE(&s->sysbus_xhci), "erstba-hi-lo", true); sysbus_realize(SYS_BUS_DEVICE(&s->sysbus_xhci), &err); if (err) { error_propagate(errp, err);