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Sun, 6 Apr 2025 16:49:05 +0200 (CEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=mailbox.org; s=mail20150812; t=1743950945; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=NZfk8RedLxtNCRcmkK7zn9ngWF+gdEznqP4g7JRtTIA=; b=mfar+LwcHRFAAtIJakws9GLQUAKJL6p4GuUjpDXHMMu4dqt3G9c+ziKhT1zztKCavyQFlc oD1TuhQmpmPcU9rjJ4VWH6pJ8zVsLjcX6TCH8S0TPKQmcHJRPcfTTK6FOhyAVcf/uP7QqO uLgGtyr4+P9N+J1a4WpSZpiFqnaLX4sGd9G2HsJJsxKFIddBEWuc3/24vILjpE0IfPnyaH t0Vq7IJAWbQCLrYTlM/ms2hWtbHYisFPL6DpcCAFiZH92rOdaqTIvzQPmb/E7ZEWE5epk6 o6CUEuIgTWgvnhRk6DbiaE+heriE5R4lotjqI06vUtEbC1agTZI8kM8OHef6Aw== From: Marek Vasut DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=mailbox.org; s=mail20150812; t=1743950943; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=NZfk8RedLxtNCRcmkK7zn9ngWF+gdEznqP4g7JRtTIA=; b=Q5By991cWEpFyGc0WcGeB+yCJHOfB9nkul/mqE93eW5FDMfg/KQZfF297oATa24l5CDLQ1 LUX5MjnDhBKIAf3xaNuu3z93uwTw2TR9DRXv2KnSik0FVCyD3H1bovvd1eHnwk+SqXSy3x eBe7KADGE5MSaSRCTwrmVQ2DX9/h2bfOGyEMR0AWEXtTJ02IC8I81UC4X0hx32zdAaIvYD oPgI9hxH+IXqzyfkWv0QC2JtrOY360uQtddKP7BAsqj+0nLY3dJMfDz8u2+UWENeO09sa7 0h1s5kteuqdZGJjv0tEvmivAdfN5imZp+cXd+XzynE2+5ggj3Zr96FcJQktc1g== To: linux-arm-kernel@lists.infradead.org Cc: Marek Vasut , =?utf-8?q?Niklas_S=C3=B6d?= =?utf-8?q?erlund?= , =?utf-8?q?Krzys?= =?utf-8?q?ztof_Wilczy=C5=84ski?= , =?utf-8?b?UmFmYcWCIE1pxYJl?= =?utf-8?b?Y2tp?= , Aradhya Bhatia , Bjorn Helgaas , Conor Dooley , Geert Uytterhoeven , Heiko Stuebner , Junhao Xie , Kever Yang , Krzysztof Kozlowski , Kuninori Morimoto , Lorenzo Pieralisi , Magnus Damm , Manivannan Sadhasivam , Neil Armstrong , Rob Herring , Yoshihiro Shimoda , devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-pci@vger.kernel.org, linux-renesas-soc@vger.kernel.org Subject: [PATCH v2 1/4] dt-bindings: PCI: rcar-gen4-pci-host: Document optional aux clock Date: Sun, 6 Apr 2025 16:45:21 +0200 Message-ID: <20250406144822.21784-2-marek.vasut+renesas@mailbox.org> In-Reply-To: <20250406144822.21784-1-marek.vasut+renesas@mailbox.org> References: <20250406144822.21784-1-marek.vasut+renesas@mailbox.org> Precedence: bulk X-Mailing-List: linux-renesas-soc@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-MBO-RS-ID: dbb51fa08f898da8fea X-MBO-RS-META: k4sadesb9s9f6djnzfhmuzp6g8xxmzxa X-Rspamd-Queue-Id: 4ZVwG94DQTz9v5Q Document 'aux' clock which are used to supply the PCIe bus. This is useful in case of a hardware setup, where the PCIe controller input clock and the PCIe bus clock are supplied from the same clock synthesiser, but from different differential clock outputs: ____________ _____________ | R-Car PCIe | | PCIe device | | | | | | PCIe RX<|==================|>PCIe TX | | PCIe TX<|==================|>PCIe RX | | | | | | PCIe CLK<|======.. ..======|>PCIe CLK | '------------' || || '-------------' || || ____________ || || | 9FGV0441 | || || | | || || | CLK DIF0<|======'' || | CLK DIF1<|=========='' | CLK DIF2<| | CLK DIF3<| '------------' The clock are named 'aux' because those are one of the clock listed in Documentation/devicetree/bindings/pci/snps,dw-pcie-common.yaml which fit closest to the PCIe bus clock. According to that binding document, the 'aux' clock describe clock which supply the PMC domain, which is likely PCIe Mezzanine Card domain. Tested-by: Niklas Söderlund Signed-off-by: Marek Vasut --- NOTE: Shall we patch Documentation/devicetree/bindings/pci/snps,dw-pcie-common.yaml instead and add 'bus' clock outright ? --- Cc: "Krzysztof Wilczyński" Cc: "Rafał Miłecki" Cc: Aradhya Bhatia Cc: Bjorn Helgaas Cc: Conor Dooley Cc: Geert Uytterhoeven Cc: Heiko Stuebner Cc: Junhao Xie Cc: Kever Yang Cc: Krzysztof Kozlowski Cc: Kuninori Morimoto Cc: Lorenzo Pieralisi Cc: Magnus Damm Cc: Manivannan Sadhasivam Cc: Neil Armstrong Cc: Rob Herring Cc: Yoshihiro Shimoda Cc: devicetree@vger.kernel.org Cc: linux-kernel@vger.kernel.org Cc: linux-pci@vger.kernel.org Cc: linux-renesas-soc@vger.kernel.org --- V2: - Add TB from Niklas - Document minItems in clock-names --- .../devicetree/bindings/pci/rcar-gen4-pci-host.yaml | 9 ++++++--- 1 file changed, 6 insertions(+), 3 deletions(-) diff --git a/Documentation/devicetree/bindings/pci/rcar-gen4-pci-host.yaml b/Documentation/devicetree/bindings/pci/rcar-gen4-pci-host.yaml index bb3f843c59d91..528b916fdb99b 100644 --- a/Documentation/devicetree/bindings/pci/rcar-gen4-pci-host.yaml +++ b/Documentation/devicetree/bindings/pci/rcar-gen4-pci-host.yaml @@ -46,12 +46,15 @@ properties: - const: app clocks: - maxItems: 2 + minItems: 2 + maxItems: 3 clock-names: + minItems: 2 items: - const: core - const: ref + - const: aux power-domains: maxItems: 1 @@ -105,8 +108,8 @@ examples: , ; interrupt-names = "msi", "dma", "sft_ce", "app"; - clocks = <&cpg CPG_MOD 624>, <&pcie0_clkref>; - clock-names = "core", "ref"; + clocks = <&cpg CPG_MOD 624>, <&pcie0_clkref>, <&pcie0_clkgen>; + clock-names = "core", "ref", "aux"; power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>; resets = <&cpg 624>; reset-names = "pwr"; From patchwork Sun Apr 6 14:45:22 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Marek Vasut X-Patchwork-Id: 14039371 X-Patchwork-Delegate: geert@linux-m68k.org Received: from mout-p-202.mailbox.org (mout-p-202.mailbox.org [80.241.56.172]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id C524D374FF; Sun, 6 Apr 2025 14:49:11 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=80.241.56.172 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1743950953; 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Date: Sun, 6 Apr 2025 16:45:22 +0200 Message-ID: <20250406144822.21784-3-marek.vasut+renesas@mailbox.org> In-Reply-To: <20250406144822.21784-1-marek.vasut+renesas@mailbox.org> References: <20250406144822.21784-1-marek.vasut+renesas@mailbox.org> Precedence: bulk X-Mailing-List: linux-renesas-soc@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-MBO-RS-META: eh3cxapmdc34r7fzbija53a6retpeg3b X-MBO-RS-ID: a10c0140563f717f0d4 X-Rspamd-Queue-Id: 4ZVwGF5nR3z9tQF Add vendor prefix for Retronix Technology Inc. https://www.retronix.com.tw/en/about.html Acked-by: Krzysztof Kozlowski Reviewed-by: Geert Uytterhoeven Tested-by: Niklas Söderlund Signed-off-by: Marek Vasut --- Cc: "Krzysztof Wilczyński" Cc: "Rafał Miłecki" Cc: Aradhya Bhatia Cc: Bjorn Helgaas Cc: Conor Dooley Cc: Geert Uytterhoeven Cc: Heiko Stuebner Cc: Junhao Xie Cc: Kever Yang Cc: Krzysztof Kozlowski Cc: Kuninori Morimoto Cc: Lorenzo Pieralisi Cc: Magnus Damm Cc: Manivannan Sadhasivam Cc: Neil Armstrong Cc: Rob Herring Cc: Yoshihiro Shimoda Cc: devicetree@vger.kernel.org Cc: linux-kernel@vger.kernel.org Cc: linux-pci@vger.kernel.org Cc: linux-renesas-soc@vger.kernel.org --- V2: - Add AB from Krzysztof - Add RB from Geert - Add TB from Niklas --- Documentation/devicetree/bindings/vendor-prefixes.yaml | 2 ++ 1 file changed, 2 insertions(+) diff --git a/Documentation/devicetree/bindings/vendor-prefixes.yaml b/Documentation/devicetree/bindings/vendor-prefixes.yaml index 86f6a19b28ae2..2b1bf6709aac7 100644 --- a/Documentation/devicetree/bindings/vendor-prefixes.yaml +++ b/Documentation/devicetree/bindings/vendor-prefixes.yaml @@ -1262,6 +1262,8 @@ patternProperties: description: Renesas Electronics Corporation "^rervision,.*": description: Shenzhen Rervision Technology Co., Ltd. + "^retronix,.*": + description: Retronix Technology Inc. "^revotics,.*": description: Revolution Robotics, Inc. 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a=rsa-sha256; c=relaxed/relaxed; d=mailbox.org; s=mail20150812; t=1743950951; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=MWN4rK4Flr4QJJjckzrtsp2NO98+h/Gt6eIWZ9nsIDA=; b=oubgr8hKjDgZ/PH3IDz8tYWBGeJw7P0u1xSBXWlEeBcbpmyKUqk8/DvkWYwrw3jkxrWNeW 8NKc2lGioQDbF1ziQiitEebav5NasZXumV9xckF/5IX3egQVuEb/mLnfAaLx8Ip9V3vnXq bjmwhYJ4nkw1faGciXV+5wkGiPzSKgqGf9KwhSE3ALSkJI6mA3e1V+GdU07R1xreBWJrJV xU7f9E3F/P3hkN1U2dvl3zDgD9x0jeLy6PRM2lMoCuFcknTqP76Lu7KJFjmlGsXg0aRhii 70qA8cOf+IjwewtvkhVWYsnG9URfAL23V4gyEuCF+hnLgPD9VePJg9/mcxVRgg== To: linux-arm-kernel@lists.infradead.org Cc: Marek Vasut , Krzysztof Kozlowski , =?utf-8?q?Niklas_S?= =?utf-8?q?=C3=B6derlund?= , =?utf-8?q?Krzysztof_Wilczy=C5=84ski?= , =?utf-8?b?UmFmYcWC?= =?utf-8?b?IE1pxYJlY2tp?= , Aradhya Bhatia , Bjorn Helgaas , Conor Dooley , Geert Uytterhoeven , Heiko Stuebner , Junhao Xie , Kever Yang , Krzysztof Kozlowski , Kuninori Morimoto , Lorenzo Pieralisi , Magnus Damm , Manivannan Sadhasivam , Neil Armstrong , Rob Herring , Yoshihiro Shimoda , devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-pci@vger.kernel.org, linux-renesas-soc@vger.kernel.org Subject: [PATCH v2 3/4] dt-bindings: soc: renesas: Document Retronix R-Car V4H Sparrow Hawk board support Date: Sun, 6 Apr 2025 16:45:23 +0200 Message-ID: <20250406144822.21784-4-marek.vasut+renesas@mailbox.org> In-Reply-To: <20250406144822.21784-1-marek.vasut+renesas@mailbox.org> References: <20250406144822.21784-1-marek.vasut+renesas@mailbox.org> Precedence: bulk X-Mailing-List: linux-renesas-soc@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-MBO-RS-ID: 84dab855406a7822c6b X-MBO-RS-META: qoifthtwm14o3m7bbrkb8kt3mrqm3m4w X-Rspamd-Queue-Id: 4ZVwGK5NHKz9stN Document Retronix R-Car V4H Sparrow Hawk board based on Renesas R-Car V4H ES3.0 (R8A779G3) SoC. This is a single-board computer with single gigabit ethernet, DSI-to-eDP bridge, DSI and two CSI2 interfaces, audio codec, two CANFD ports, micro SD card slot, USB PD supply, USB 3.0 ports, M.2 Key-M slot for NVMe SSD, debug UART and JTAG. Acked-by: Krzysztof Kozlowski Tested-by: Niklas Söderlund Signed-off-by: Marek Vasut --- Cc: "Krzysztof Wilczyński" Cc: "Rafał Miłecki" Cc: Aradhya Bhatia Cc: Bjorn Helgaas Cc: Conor Dooley Cc: Geert Uytterhoeven Cc: Heiko Stuebner Cc: Junhao Xie Cc: Kever Yang Cc: Krzysztof Kozlowski Cc: Kuninori Morimoto Cc: Lorenzo Pieralisi Cc: Magnus Damm Cc: Manivannan Sadhasivam Cc: Neil Armstrong Cc: Rob Herring Cc: Yoshihiro Shimoda Cc: devicetree@vger.kernel.org Cc: linux-kernel@vger.kernel.org Cc: linux-pci@vger.kernel.org Cc: linux-renesas-soc@vger.kernel.org --- V2: - Add AB from Krzysztof - Add TB from Niklas - Rename {Renesas,Retronix} R-Car V4H Sparrow Hawk in commit message and update R-Car V4H ES3.0 to Renesas R-Car V4H ES3.0 --- Documentation/devicetree/bindings/soc/renesas/renesas.yaml | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/Documentation/devicetree/bindings/soc/renesas/renesas.yaml b/Documentation/devicetree/bindings/soc/renesas/renesas.yaml index 51a4c48eea6d7..201088277514d 100644 --- a/Documentation/devicetree/bindings/soc/renesas/renesas.yaml +++ b/Documentation/devicetree/bindings/soc/renesas/renesas.yaml @@ -375,6 +375,13 @@ properties: - renesas,r8a779g3 # ES3.x - const: renesas,r8a779g0 + - description: R-Car V4H (R8A779G3) + items: + - enum: + - retronix,sparrow-hawk # Sparrow Hawk board + - const: renesas,r8a779g3 # ES3.x + - const: renesas,r8a779g0 + - description: R-Car V4M (R8A779H0) items: - enum: From patchwork Sun Apr 6 14:45:24 2025 Content-Type: text/plain; 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Sun, 6 Apr 2025 16:49:16 +0200 (CEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=mailbox.org; s=mail20150812; t=1743950956; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=A3b/XIF0PJ90Q4tX/J4m+YV/IjnKoOJFKE8s5E9IIck=; b=VQIsi3y2jwNXoWFqwHQxFhy+GqkK9nkNkQindniAeZJn9W00X8ZUYGdYAozg2mRIRhiX7J ay/cdbtq8bqln5yG3V7DqQbrDreITKfkSUHRvhClClcakvOQp9Vl7in7GHd5FPQsjPbn4g 1A3Zlcg6ucPdh4RUl1bQ5M346vEUyZ41xPa/EE9KL4Hb53IIEBBEoxqHF46U580KYgJdJ4 W1caAki9i8U8qdwwQtKG9mI6Pn+vl/M6fjZcIHeGz0u+BdOo2C//moJSVKSFhnG7KENgVt ai8HY5Mpb8O3Vp4vBRgyTrjleTvHadz4RAknsLC/vCvrsEoMQQTzqtnP1wWUZw== From: Marek Vasut DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=mailbox.org; s=mail20150812; t=1743950954; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=A3b/XIF0PJ90Q4tX/J4m+YV/IjnKoOJFKE8s5E9IIck=; b=WlU5PGlsDArMxYBNHA6qvTKFewYRZPcW1IaLJ78oaeg9bKMVGEv7Xt0MpvzOI58jqwJNXU PBCiNiG2gs0klmJ9akcfL+Evzb+dTpPLUlBtvb1h512E2Hpbff/7mZufBTmXMIQJYLxBcB /hhmW62kZxO5zlLsm78G36uLfGGj65EnLlOwuYrlAq4W87NLevBJqZiPnonvbJJXMMiiB8 sO1DEC2h7LH4m9Z0/S8rbA0VCYDpLH96DNn66mvkypc1jZTkywV1GaTuLtmrCX3KkYXhM8 HvQNYyGPs4wLTOMG9g9rgKxSxNQ4RzO1YPrWhoLWv9zZMlKVdZyPjlbxMxCe7Q== To: linux-arm-kernel@lists.infradead.org Cc: Marek Vasut , Kuninori Morimoto , =?utf-8?q?Niklas_S?= =?utf-8?q?=C3=B6derlund?= , =?utf-8?q?Krzysztof_Wilczy=C5=84ski?= , =?utf-8?b?UmFmYcWC?= =?utf-8?b?IE1pxYJlY2tp?= , Aradhya Bhatia , Bjorn Helgaas , Conor Dooley , Geert Uytterhoeven , Heiko Stuebner , Junhao Xie , Kever Yang , Krzysztof Kozlowski , Lorenzo Pieralisi , Magnus Damm , Manivannan Sadhasivam , Neil Armstrong , Rob Herring , Yoshihiro Shimoda , devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-pci@vger.kernel.org, linux-renesas-soc@vger.kernel.org Subject: [PATCH v2 4/4] arm64: dts: renesas: r8a779g3: Add Retronix R-Car V4H Sparrow Hawk board support Date: Sun, 6 Apr 2025 16:45:24 +0200 Message-ID: <20250406144822.21784-5-marek.vasut+renesas@mailbox.org> In-Reply-To: <20250406144822.21784-1-marek.vasut+renesas@mailbox.org> References: <20250406144822.21784-1-marek.vasut+renesas@mailbox.org> Precedence: bulk X-Mailing-List: linux-renesas-soc@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-MBO-RS-ID: 0f00a90f29f97f1e66e X-MBO-RS-META: shum6gw787say6jdziwpfm9rcg1gfr8z Add Retronix R-Car V4H Sparrow Hawk board based on Renesas R-Car V4H ES3.0 (R8A779G3) SoC. This is a single-board computer with single gigabit ethernet, DSI-to-eDP bridge, DSI and two CSI2 interfaces, audio codec, two CANFD ports, micro SD card slot, USB PD supply, USB 3.0 ports, M.2 Key-M slot for NVMe SSD, debug UART and JTAG. Tested-by: Kuninori Morimoto Tested-by: Niklas Söderlund Signed-off-by: Marek Vasut --- Cc: "Krzysztof Wilczyński" Cc: "Rafał Miłecki" Cc: Aradhya Bhatia Cc: Bjorn Helgaas Cc: Conor Dooley Cc: Geert Uytterhoeven Cc: Heiko Stuebner Cc: Junhao Xie Cc: Kever Yang Cc: Krzysztof Kozlowski Cc: Kuninori Morimoto Cc: Lorenzo Pieralisi Cc: Magnus Damm Cc: Manivannan Sadhasivam Cc: Neil Armstrong Cc: Rob Herring Cc: Yoshihiro Shimoda Cc: devicetree@vger.kernel.org Cc: linux-kernel@vger.kernel.org Cc: linux-pci@vger.kernel.org Cc: linux-renesas-soc@vger.kernel.org --- V2: - Add TB from Morimoto-san - Enable pwm-fan and set PWM to full by default, to achieve maximum cooling effect unless configured otherwise. The blower fan is user supplied device, hence this default. - Add arch/arm64/boot/dts/renesas/r8a779g3-sparrow-hawk-fan-pwm.dtso to demonstrate user supplied blower fan configuration. - Add TB from Niklas - Rename pins{_,-}mdio, pins{_,-}mii, scif{_,-}clk, sd{_,-}uhs - Add serial1 = &hscif1; and serial2 = &hscif3 - Rename {Renesas,Retronix} R-Car V4H Sparrow Hawk in commit message and update R-Car V4H ES3.0 to Renesas R-Car V4H ES3.0 --- arch/arm64/boot/dts/renesas/Makefile | 4 + .../r8a779g3-sparrow-hawk-fan-pwm.dtso | 43 ++ .../dts/renesas/r8a779g3-sparrow-hawk.dts | 685 ++++++++++++++++++ 3 files changed, 732 insertions(+) create mode 100644 arch/arm64/boot/dts/renesas/r8a779g3-sparrow-hawk-fan-pwm.dtso create mode 100644 arch/arm64/boot/dts/renesas/r8a779g3-sparrow-hawk.dts diff --git a/arch/arm64/boot/dts/renesas/Makefile b/arch/arm64/boot/dts/renesas/Makefile index d25e665ee4bfb..abf3df588092c 100644 --- a/arch/arm64/boot/dts/renesas/Makefile +++ b/arch/arm64/boot/dts/renesas/Makefile @@ -94,6 +94,10 @@ dtb-$(CONFIG_ARCH_R8A779G0) += r8a779g2-white-hawk-single.dtb r8a779g2-white-hawk-single-ard-audio-da7212-dtbs := r8a779g2-white-hawk-single.dtb white-hawk-ard-audio-da7212.dtbo dtb-$(CONFIG_ARCH_R8A779G0) += r8a779g2-white-hawk-single-ard-audio-da7212.dtb +dtb-$(CONFIG_ARCH_R8A779G0) += r8a779g3-sparrow-hawk.dtb +r8a779g3-sparrow-hawk-fan-pwm-dtbs := r8a779g3-sparrow-hawk.dtb r8a779g3-sparrow-hawk-fan-pwm.dtbo +dtb-$(CONFIG_ARCH_R8A779G0) += r8a779g3-sparrow-hawk-fan-pwm.dtb + dtb-$(CONFIG_ARCH_R8A779G0) += r8a779g3-white-hawk-single.dtb r8a779g3-white-hawk-single-ard-audio-da7212-dtbs := r8a779g3-white-hawk-single.dtb white-hawk-ard-audio-da7212.dtbo dtb-$(CONFIG_ARCH_R8A779G0) += r8a779g3-white-hawk-single-ard-audio-da7212.dtb diff --git a/arch/arm64/boot/dts/renesas/r8a779g3-sparrow-hawk-fan-pwm.dtso b/arch/arm64/boot/dts/renesas/r8a779g3-sparrow-hawk-fan-pwm.dtso new file mode 100644 index 0000000000000..50d53c8d76c5b --- /dev/null +++ b/arch/arm64/boot/dts/renesas/r8a779g3-sparrow-hawk-fan-pwm.dtso @@ -0,0 +1,43 @@ +// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +/* + * Device Tree Overlay for the PWM controlled blower fan in connector J3:FAN + * on R-Car V4H ES3.0 Sparrow Hawk board + * + * Copyright (C) 2025 Marek Vasut + * + * Example usage: + * + * # Localize hwmon sysfs directory that matches the PWM fan, + * # enable the PWM fan, and configure the fan speed manually. + * r8a779g3-sparrow-hawk$ grep -H . /sys/class/hwmon/hwmon?/name + * /sys/class/hwmon/hwmon0/name:sensor1_thermal + * /sys/class/hwmon/hwmon1/name:sensor2_thermal + * /sys/class/hwmon/hwmon2/name:sensor3_thermal + * /sys/class/hwmon/hwmon3/name:sensor4_thermal + * /sys/class/hwmon/hwmon4/name:pwmfan + * ^ ^^^^^^ + * + * # Select mode 2 , enable fan PWM and regulator and keep them enabled. + * # For details, see Linux Documentation/hwmon/pwm-fan.rst + * r8a779g3-sparrow-hawk$ echo 2 > /sys/class/hwmon/hwmon4/pwm1_enable + * + * # Configure PWM fan speed in range 0..255 , 0 is stopped , 255 is full speed . + * # Fan speed 101 is about 2/5 of the PWM fan speed: + * r8a779g3-sparrow-hawk$ echo 101 > /sys/class/hwmon/hwmon4/pwm1 + */ + +/dts-v1/; +/plugin/; + +/* + * Override default PWM fan settings. For a list of available properties, + * see schema Documentation/devicetree/bindings/hwmon/pwm-fan.yaml . + */ +&fan { + /* Available cooling levels */ + cooling-levels = <0 50 100 150 200 255>; + /* Four pulses of tacho signal per one revolution */ + pulses-per-revolution = <4>; + /* PWM period: 100us ~= 10 kHz */ + pwms = <&pwm0 0 100000>; +}; diff --git a/arch/arm64/boot/dts/renesas/r8a779g3-sparrow-hawk.dts b/arch/arm64/boot/dts/renesas/r8a779g3-sparrow-hawk.dts new file mode 100644 index 0000000000000..b54d45115a856 --- /dev/null +++ b/arch/arm64/boot/dts/renesas/r8a779g3-sparrow-hawk.dts @@ -0,0 +1,685 @@ +// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +/* + * Device Tree Source for the R-Car V4H ES3.0 Sparrow Hawk board + * + * Copyright (C) 2025 Marek Vasut + */ + +/dts-v1/; +#include + +#include "r8a779g3.dtsi" + +/ { + model = "Retronix Sparrow Hawk board based on r8a779g3"; + compatible = "retronix,sparrow-hawk", "renesas,r8a779g3", + "renesas,r8a779g0"; + + aliases { + ethernet0 = &avb0; + i2c0 = &i2c0; + i2c1 = &i2c1; + i2c2 = &i2c2; + i2c3 = &i2c3; + i2c4 = &i2c4; + i2c5 = &i2c5; + serial0 = &hscif0; + serial1 = &hscif1; + serial2 = &hscif3; + spi0 = &rpc; + }; + + chosen { + bootargs = "ignore_loglevel rw root=/dev/nfs ip=on"; + stdout-path = "serial0:921600n8"; + }; + + /* Page 31 / FAN */ + fan: pwm-fan { + pinctrl-0 = <&irq4_pins>; + pinctrl-names = "default"; + compatible = "pwm-fan"; + #cooling-cells = <2>; + interrupts-extended = <&intc_ex 4 IRQ_TYPE_EDGE_FALLING>; + /* + * The fan model connected to this device can be selected + * by user. Set "cooling-levels" DT property to single 255 + * entry to force the fan PWM into constant HIGH, which + * forces the fan to spin at maximum RPM, thus providing + * maximum cooling to this device and protection against + * misconfigured PWM duty cycle to the fan. + * + * User has to configure "pwms" and "pulses-per-revolution" + * DT properties according to fan datasheet first, and then + * extend "cooling-levels = <0 m n ... 255>" property to + * achieve proper fan control compatible with fan model + * installed by user. + */ + cooling-levels = <255>; + pulses-per-revolution = <2>; + pwms = <&pwm0 0 50000>; + }; + + /* + * Page 15 / LPDDR5 + * + * This configuration listed below is for the 8 GiB board variant + * with MT62F1G64D8EK-023 WT:C LPDDR5 part populated on the board. + * + * A variant with 16 GiB MT62F2G64D8EK-023 WT:C part populated on + * the board is automatically handled by the bootloader, which + * adjusts the correct DRAM size into the memory nodes below. + */ + memory@48000000 { + device_type = "memory"; + /* first 128MB is reserved for secure area. */ + reg = <0x0 0x48000000 0x0 0x78000000>; + }; + + memory@480000000 { + device_type = "memory"; + reg = <0x4 0x80000000 0x0 0x80000000>; + }; + + memory@600000000 { + device_type = "memory"; + reg = <0x6 0x00000000 0x1 0x00000000>; + }; + + /* Page 27 / DSI to Display */ + mini-dp-con { + compatible = "dp-connector"; + label = "CN6"; + type = "full-size"; + + port { + mini_dp_con_in: endpoint { + remote-endpoint = <&sn65dsi86_out>; + }; + }; + }; + + reg_1p2v: regulator-1p2v { + compatible = "regulator-fixed"; + regulator-name = "fixed-1.2V"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + regulator-boot-on; + regulator-always-on; + }; + + reg_1p8v: regulator-1p8v { + compatible = "regulator-fixed"; + regulator-name = "fixed-1.8V"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-boot-on; + regulator-always-on; + }; + + reg_3p3v: regulator-3p3v { + compatible = "regulator-fixed"; + regulator-name = "fixed-3.3V"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-boot-on; + regulator-always-on; + }; + + /* Page 27 / DSI to Display */ + sn65dsi86_refclk: clk-x9 { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <38400000>; + }; + + /* Page 26 / PCIe.0/1 CLK */ + pcie_refclk: clk-x8 { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <25000000>; + }; + + /* Page 17 uSD-Slot */ + vcc_sdhi: regulator-vcc-sdhi { + compatible = "regulator-gpio"; + regulator-name = "SDHI VccQ"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + gpios = <&gpio8 13 GPIO_ACTIVE_HIGH>; + gpios-states = <1>; + states = <3300000 0>, <1800000 1>; + }; +}; + +/* Page 22 / Ether_AVB0 */ +&avb0 { + pinctrl-0 = <&avb0_pins>; + pinctrl-names = "default"; + phy-handle = <&avb0_phy>; + tx-internal-delay-ps = <2000>; + status = "okay"; + + mdio { + #address-cells = <1>; + #size-cells = <0>; + + avb0_phy: ethernet-phy@0 { /* KSZ9031RNXVB */ + compatible = "ethernet-phy-id0022.1622", + "ethernet-phy-ieee802.3-c22"; + rxc-skew-ps = <1500>; + reg = <0>; + /* AVB0_PHY_INT_V */ + interrupts-extended = <&gpio7 5 IRQ_TYPE_LEVEL_LOW>; + /* GP7_10/AVB0_RESETN_V */ + reset-gpios = <&gpio7 10 GPIO_ACTIVE_LOW>; + reset-assert-us = <10000>; + reset-deassert-us = <300>; + }; + }; +}; + +/* Page 28 / CANFD_IF */ +&can_clk { + clock-frequency = <40000000>; +}; + +/* Page 28 / CANFD_IF */ +&canfd { + pinctrl-0 = <&canfd3_pins>, <&canfd4_pins>, <&can_clk_pins>; + pinctrl-names = "default"; + + status = "okay"; + + channel3 { + status = "okay"; + }; + + channel4 { + status = "okay"; + }; +}; + +/* Page 27 / DSI to Display */ +&dsi1 { + status = "okay"; + + ports { + port@1 { + dsi1_out: endpoint { + remote-endpoint = <&sn65dsi86_in>; + data-lanes = <1 2 3 4>; + }; + }; + }; +}; + +/* Page 27 / DSI to Display */ +&du { + status = "okay"; +}; + +/* Page 5 / R-Car V4H_INT_I2C */ +&extal_clk { /* X3 */ + clock-frequency = <16666666>; +}; + +/* Page 5 / R-Car V4H_INT_I2C */ +&extalr_clk { /* X2 */ + clock-frequency = <32768>; +}; + +/* Page 26 / 2230 Key M M.2 */ +&gpio4 { + /* 9FGV0441 nOE inputs 0 and 1 */ + pcie-m2-oe-hog { + gpio-hog; + gpios = <21 GPIO_ACTIVE_HIGH>; + output-low; + line-name = "PCIe-CLK-nOE-M2"; + }; + + /* 9FGV0441 nOE inputs 2 and 3 */ + pcie-usb-oe-hog { + gpio-hog; + gpios = <22 GPIO_ACTIVE_HIGH>; + output-low; + line-name = "PCIe-CLK-nOE-USB"; + }; +}; + +/* Page 23 / DEBUG */ +&hscif0 { /* FTDI ADBUS[3:0] */ + pinctrl-0 = <&hscif0_pins>; + pinctrl-names = "default"; + uart-has-rtscts; + bootph-all; + + status = "okay"; +}; + +/* Page 23 / DEBUG */ +&hscif1 { /* FTDI BDBUS[3:0] */ + pinctrl-0 = <&hscif1_pins>; + pinctrl-names = "default"; + uart-has-rtscts; + + status = "okay"; +}; + +/* Page 24 / UART */ +&hscif3 { /* CN7 pins 8 (TX) and 10 (RX) */ + pinctrl-0 = <&hscif3_pins>; + pinctrl-names = "default"; + + status = "okay"; +}; + +/* Page 24 / I2C SWITCH */ +&i2c0 { + #address-cells = <1>; + #size-cells = <0>; + pinctrl-0 = <&i2c0_pins>; + pinctrl-names = "default"; + clock-frequency = <400000>; + status = "okay"; + + mux@71 { + compatible = "nxp,pca9544"; /* TCA9544 */ + reg = <0x71>; + #address-cells = <1>; + #size-cells = <0>; + vdd-supply = <®_3p3v>; + + i2c0_mux0: i2c@0 { + reg = <0>; + #address-cells = <1>; + #size-cells = <0>; + + /* Page 27 / DSI to Display */ + bridge@2c { + pinctrl-0 = <&irq0_pins>; + pinctrl-names = "default"; + + compatible = "ti,sn65dsi86"; + reg = <0x2c>; + + clocks = <&sn65dsi86_refclk>; + clock-names = "refclk"; + + interrupts-extended = <&intc_ex 0 IRQ_TYPE_LEVEL_HIGH>; + + enable-gpios = <&gpio2 1 GPIO_ACTIVE_HIGH>; + + vccio-supply = <®_1p8v>; + vpll-supply = <®_1p8v>; + vcca-supply = <®_1p2v>; + vcc-supply = <®_1p2v>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + sn65dsi86_in: endpoint { + remote-endpoint = <&dsi1_out>; + }; + }; + + port@1 { + reg = <1>; + sn65dsi86_out: endpoint { + remote-endpoint = <&mini_dp_con_in>; + }; + }; + }; + }; + }; + + i2c0_mux1: i2c@1 { + reg = <1>; + #address-cells = <1>; + #size-cells = <0>; + }; + + i2c0_mux2: i2c@2 { + reg = <2>; + #address-cells = <1>; + #size-cells = <0>; + + /* Page 26 / PCIe.0/1 CLK */ + pcie_clk: clk@68 { + compatible = "renesas,9fgv0441"; + reg = <0x68>; + clocks = <&pcie_refclk>; + #clock-cells = <1>; + }; + }; + + i2c0_mux3: i2c@3 { + reg = <3>; + #address-cells = <1>; + #size-cells = <0>; + }; + }; +}; + +/* Page 29 / CSI_IF_CN / CAM_CN0 */ +&i2c1 { + #address-cells = <1>; + #size-cells = <0>; + pinctrl-0 = <&i2c1_pins>; + pinctrl-names = "default"; +}; + +/* Page 29 / CSI_IF_CN / CAM_CN1 */ +&i2c2 { + #address-cells = <1>; + #size-cells = <0>; + pinctrl-0 = <&i2c2_pins>; + pinctrl-names = "default"; +}; + +/* Page 31 / IO_CN */ +&i2c3 { + #address-cells = <1>; + #size-cells = <0>; + pinctrl-0 = <&i2c3_pins>; + pinctrl-names = "default"; +}; + +/* Page 31 / IO_CN */ +&i2c4 { + #address-cells = <1>; + #size-cells = <0>; + pinctrl-0 = <&i2c4_pins>; + pinctrl-names = "default"; +}; + +/* Page 18 / POWER_CORE and Page 19 / POWER_PMIC */ +&i2c5 { + #address-cells = <1>; + #size-cells = <0>; + pinctrl-0 = <&i2c5_pins>; + pinctrl-names = "default"; +}; + +/* Page 17 uSD-Slot */ +&mmc0 { + pinctrl-0 = <&sd_pins>; + pinctrl-1 = <&sd_uhs_pins>; + pinctrl-names = "default", "state_uhs"; + bus-width = <4>; + cd-gpios = <&gpio3 11 GPIO_ACTIVE_LOW>; /* SD_CD */ + sd-uhs-sdr50; + sd-uhs-sdr104; + vmmc-supply = <®_3p3v>; + vqmmc-supply = <&vcc_sdhi>; + status = "okay"; +}; + +/* Page 26 / 2230 Key M M.2 */ +&pcie0_clkref { + status = "disabled"; +}; + +&pciec0 { + clocks = <&cpg CPG_MOD 624>, <&pcie_clk 0>, <&pcie_clk 1>; + clock-names = "core", "ref", "aux"; + reset-gpios = <&gpio2 2 GPIO_ACTIVE_LOW>; + status = "okay"; +}; + +/* Page 25 / PCIe to USB */ +&pcie1_clkref { + status = "disabled"; +}; + +&pciec1 { + clocks = <&cpg CPG_MOD 625>, <&pcie_clk 2>, <&pcie_clk 3>; + clock-names = "core", "ref", "aux"; + /* uPD720201 is PCIe Gen2 x1 device */ + num-lanes = <1>; + reset-gpios = <&gpio2 0 GPIO_ACTIVE_LOW>; + status = "okay"; +}; + +&pfc { + pinctrl-0 = <&scif_clk_pins>; + pinctrl-names = "default"; + + /* Page 22 / Ether_AVB0 */ + avb0_pins: avb0 { + mux { + groups = "avb0_link", "avb0_mdio", "avb0_rgmii", + "avb0_txcrefclk"; + function = "avb0"; + }; + + pins-mdio { + groups = "avb0_mdio"; + drive-strength = <21>; + }; + + pins-mii { + groups = "avb0_rgmii"; + drive-strength = <21>; + }; + + }; + + /* Page 28 / CANFD_IF */ + can_clk_pins: can-clk { + groups = "can_clk"; + function = "can_clk"; + }; + + /* Page 28 / CANFD_IF */ + canfd3_pins: canfd3 { + groups = "canfd3_data"; + function = "canfd3"; + }; + + /* Page 28 / CANFD_IF */ + canfd4_pins: canfd4 { + groups = "canfd4_data"; + function = "canfd4"; + }; + + /* Page 23 / DEBUG */ + hscif0_pins: hscif0 { + groups = "hscif0_data", "hscif0_ctrl"; + function = "hscif0"; + }; + + /* Page 23 / DEBUG */ + hscif1_pins: hscif1 { + groups = "hscif1_data_a", "hscif1_ctrl_a"; + function = "hscif1"; + }; + + /* Page 24 / UART */ + hscif3_pins: hscif3 { + groups = "hscif3_data_a"; + function = "hscif3"; + }; + + /* Page 24 / I2C SWITCH */ + i2c0_pins: i2c0 { + groups = "i2c0"; + function = "i2c0"; + }; + + /* Page 29 / CSI_IF_CN / CAM_CN0 */ + i2c1_pins: i2c1 { + groups = "i2c1"; + function = "i2c1"; + }; + + /* Page 29 / CSI_IF_CN / CAM_CN1 */ + i2c2_pins: i2c2 { + groups = "i2c2"; + function = "i2c2"; + }; + + /* Page 31 / IO_CN */ + i2c3_pins: i2c3 { + groups = "i2c3"; + function = "i2c3"; + }; + + /* Page 31 / IO_CN */ + i2c4_pins: i2c4 { + groups = "i2c4"; + function = "i2c4"; + }; + + /* Page 18 / POWER_CORE */ + i2c5_pins: i2c5 { + groups = "i2c5"; + function = "i2c5"; + }; + + /* Page 27 / DSI to Display */ + irq0_pins: irq0 { + groups = "intc_ex_irq0_a"; + function = "intc_ex"; + }; + + /* Page 31 / FAN */ + irq4_pins: irq4 { + groups = "intc_ex_irq4_b"; + function = "intc_ex"; + }; + + /* Page 31 / FAN */ + pwm0_pins: pwm0 { + groups = "pwm0"; + function = "pwm0"; + }; + + /* Page 31 / CN7 pin 12 */ + pwm1_pins: pwm1 { + groups = "pwm1_b"; + function = "pwm1"; + }; + + /* Page 31 / CN7 pin 32 */ + pwm6_pins: pwm6 { + groups = "pwm6"; + function = "pwm6"; + }; + + /* Page 31 / CN7 pin 33 */ + pwm7_pins: pwm7 { + groups = "pwm7"; + function = "pwm7"; + }; + + /* Page 16 / QSPI_FLASH */ + qspi0_pins: qspi0 { + groups = "qspi0_ctrl", "qspi0_data4"; + function = "qspi0"; + bootph-all; + }; + + /* Page 6 / SCIF_CLK_SOC_V */ + scif_clk_pins: scif-clk { + groups = "scif_clk"; + function = "scif_clk"; + }; + + /* Page 17 uSD-Slot */ + sd_pins: sd { + groups = "mmc_data4", "mmc_ctrl"; + function = "mmc"; + power-source = <3300>; + }; + + /* Page 17 uSD-Slot */ + sd_uhs_pins: sd-uhs { + groups = "mmc_data4", "mmc_ctrl"; + function = "mmc"; + power-source = <1800>; + }; +}; + +/* Page 31 / FAN */ +&pwm0 { + pinctrl-0 = <&pwm0_pins>; + pinctrl-names = "default"; + status = "okay"; +}; + +/* Page 31 / CN7 pin 12 */ +&pwm1 { + pinctrl-0 = <&pwm1_pins>; + pinctrl-names = "default"; + status = "okay"; +}; + +/* Page 31 / CN7 pin 32 */ +&pwm6 { + pinctrl-0 = <&pwm6_pins>; + pinctrl-names = "default"; + status = "okay"; +}; + +/* Page 31 / CN7 pin 33 */ +&pwm7 { + pinctrl-0 = <&pwm7_pins>; + pinctrl-names = "default"; + status = "okay"; +}; + +/* Page 16 / QSPI_FLASH */ +&rpc { + pinctrl-0 = <&qspi0_pins>; + pinctrl-names = "default"; + bootph-all; + + status = "okay"; + + flash@0 { + compatible = "spansion,s25fs512s", "jedec,spi-nor"; + reg = <0>; + spi-max-frequency = <40000000>; + spi-rx-bus-width = <4>; + spi-tx-bus-width = <4>; + bootph-all; + + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + + boot@0 { + reg = <0x0 0x1000000>; + read-only; + }; + + user@1000000 { + reg = <0x1000000 0x2f80000>; + }; + + env1@3f80000 { + reg = <0x3f80000 0x40000>; + }; + + env2@3fc0000 { + reg = <0x3fc0000 0x40000>; + }; + }; + }; +}; + +&rwdt { + timeout-sec = <60>; + status = "okay"; +}; + +/* Page 6 / SCIF_CLK_SOC_V */ +&scif_clk { /* X12 */ + clock-frequency = <24000000>; +};