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Sun, 06 Apr 2025 21:46:07 -0700 (PDT) From: Nick Chan Date: Mon, 07 Apr 2025 12:45:10 +0800 Subject: [PATCH v6 01/21] dt-bindings: arm: pmu: Add Apple A7-A11 SoC CPU PMU compatibles MIME-Version: 1.0 Message-Id: <20250407-apple-cpmu-v6-1-ae8c2f225c1f@gmail.com> References: <20250407-apple-cpmu-v6-0-ae8c2f225c1f@gmail.com> In-Reply-To: <20250407-apple-cpmu-v6-0-ae8c2f225c1f@gmail.com> To: Will Deacon , Mark Rutland , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Catalin Marinas , Sven Peter , Janne Grunau , Alyssa Rosenzweig , Neal Gompa Cc: Marc Zyngier , linux-arm-kernel@lists.infradead.org, linux-perf-users@vger.kernel.org, devicetree@vger.kernel.org, asahi@lists.linux.dev, linux-kernel@vger.kernel.org, Nick Chan , Krzysztof Kozlowski X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=openpgp-sha256; l=1102; i=towinchenmi@gmail.com; h=from:subject:message-id; bh=nvc6B3SNJrX+OFSnYkWwiXKVem6neRj112hzdXP5HLQ=; b=owEBbQKS/ZANAwAIAQHKCLemxQgkAcsmYgBn81iF5N0lEK0tQxrovFdNs6/Non4nh/+bWpI/2 VKz9Lmslc2JAjMEAAEIAB0WIQRLUnh4XJes95w8aIMBygi3psUIJAUCZ/NYhQAKCRABygi3psUI JMWXD/433zs8eXtVNbS+hSlKXj716ZiiEDJp1ttmVLgn1jlsjKilu6WTd5KwYcf8fTdw40qBb1r 6me48cGkpO1Mma+WITNcvK4rF6CgPariDwIUFIp44h2BtVNWcD6++OvABYd5C208fV1vVceHNiJ LkOjfa8LFRfbgT7hmNwUJe4ckNgLdIoKS3fTRvOf5UYRrJFbgy43MVq7TMHDMK/y5tf38xd19kB uFQjsDoLf1JqIUczkQHRXwM4ICSSckRjlRHM0hWTKydW4mTkmnDiiqv8dOMYGtBADVqN3dOiKSa /y7NQeYudBCPFkHqVN8wbE7r49ZqdOhWSFA437faxXIRhNbSvKOLUW6xg4Io6M5WUxtXHwNGuz/ PhQ0VSSWzfYsZaSc/ZSftBBIN3rR4lQCjcA0G0Gs5VcboSIdVn6mlPXwefQnb/LGqGOAGjCSGcF It/pYXIg2pxTRdAF6/djgHKjhszQY2eRwNL/TZyOLtLcRRCViqO7pgO5BUr2kzDmO90AQoCgTCd FbfJh9uY80jJ7cX+IYomb/uvd+3yRs7Ipozi3Wubbnp4o3R92epjynsmhZxUnOYhHotd+rq276K q23TiP33IPovipu7ho0nA0oSdagoxIhlnsVdtBPDkS+XzQkp52H6L0tOqezmzW6LVxvAU8GubYP x0wOe9TS7dlMmvw== X-Developer-Key: i=towinchenmi@gmail.com; a=openpgp; fpr=4B5278785C97ACF79C3C688301CA08B7A6C50824 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20250406_214608_750425_C1527594 X-CRM114-Status: UNSURE ( 9.15 ) X-CRM114-Notice: Please train this message. X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org Document the compatibles for Apple A7-A11 SoC CPU PMU. Acked-by: Krzysztof Kozlowski Signed-off-by: Nick Chan --- Documentation/devicetree/bindings/arm/pmu.yaml | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/Documentation/devicetree/bindings/arm/pmu.yaml b/Documentation/devicetree/bindings/arm/pmu.yaml index 295963a3cae799a54560557137dd6b3cf4bd00f9..3726e1b78c42f150cf1dc68a6b3aa3541517c311 100644 --- a/Documentation/devicetree/bindings/arm/pmu.yaml +++ b/Documentation/devicetree/bindings/arm/pmu.yaml @@ -22,8 +22,14 @@ properties: - apm,potenza-pmu - apple,avalanche-pmu - apple,blizzard-pmu + - apple,cyclone-pmu - apple,firestorm-pmu + - apple,fusion-pmu - apple,icestorm-pmu + - apple,monsoon-pmu + - apple,mistral-pmu + - apple,twister-pmu + - apple,typhoon-pmu - arm,armv8-pmuv3 # Only for s/w models - arm,arm1136-pmu - arm,arm1176-pmu From patchwork Mon Apr 7 04:45:11 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Nick Chan X-Patchwork-Id: 14039697 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 8FA29C36010 for ; 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Sun, 06 Apr 2025 21:46:11 -0700 (PDT) Received: from [127.0.1.1] ([59.188.211.160]) by smtp.googlemail.com with ESMTPSA id 98e67ed59e1d1-305983b9954sm7765810a91.32.2025.04.06.21.46.07 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 06 Apr 2025 21:46:10 -0700 (PDT) From: Nick Chan Date: Mon, 07 Apr 2025 12:45:11 +0800 Subject: [PATCH v6 02/21] drivers/perf: apple_m1: Only init PMUv3 remap when EL2 is available MIME-Version: 1.0 Message-Id: <20250407-apple-cpmu-v6-2-ae8c2f225c1f@gmail.com> References: <20250407-apple-cpmu-v6-0-ae8c2f225c1f@gmail.com> In-Reply-To: <20250407-apple-cpmu-v6-0-ae8c2f225c1f@gmail.com> To: Will Deacon , Mark Rutland , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Catalin Marinas , Sven Peter , Janne Grunau , Alyssa Rosenzweig , Neal Gompa Cc: Marc Zyngier , linux-arm-kernel@lists.infradead.org, linux-perf-users@vger.kernel.org, devicetree@vger.kernel.org, asahi@lists.linux.dev, linux-kernel@vger.kernel.org, Nick Chan X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; 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a=openpgp; fpr=4B5278785C97ACF79C3C688301CA08B7A6C50824 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20250406_214612_090881_1AEF6B6E X-CRM114-Status: GOOD ( 12.91 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org Skip initialization of PMUv3 remap when EL2 is not available. Initialization is harmless in EL1 but it is still a weird thing to do. Signed-off-by: Nick Chan --- drivers/perf/apple_m1_cpu_pmu.c | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-) diff --git a/drivers/perf/apple_m1_cpu_pmu.c b/drivers/perf/apple_m1_cpu_pmu.c index df9a28ba69dcfad6f33a0d18b620276b910a36ca..b800da3f7f61ffa972fcab5f24b42127f2c55ac6 100644 --- a/drivers/perf/apple_m1_cpu_pmu.c +++ b/drivers/perf/apple_m1_cpu_pmu.c @@ -646,8 +646,10 @@ static int m1_pmu_init(struct arm_pmu *cpu_pmu, u32 flags) cpu_pmu->reset = m1_pmu_reset; cpu_pmu->set_event_filter = m1_pmu_set_event_filter; - cpu_pmu->map_pmuv3_event = m1_pmu_map_pmuv3_event; - m1_pmu_init_pmceid(cpu_pmu); + if (is_hyp_mode_available()) { + cpu_pmu->map_pmuv3_event = m1_pmu_map_pmuv3_event; + m1_pmu_init_pmceid(cpu_pmu); + } bitmap_set(cpu_pmu->cntr_mask, 0, M1_PMU_NR_COUNTERS); cpu_pmu->attr_groups[ARMPMU_ATTR_GROUP_EVENTS] = &m1_pmu_events_attr_group; From patchwork Mon Apr 7 04:45:12 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Nick Chan X-Patchwork-Id: 14039698 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 2038EC36010 for ; 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a=openpgp; fpr=4B5278785C97ACF79C3C688301CA08B7A6C50824 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20250406_214615_116225_06E5735D X-CRM114-Status: GOOD ( 17.45 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org Use per-implementation event tables to allow supporting implementations with a different list of events and event affinities. Signed-off-by: Nick Chan --- drivers/perf/apple_m1_cpu_pmu.c | 65 +++++++++++++++++++++++++---------------- 1 file changed, 40 insertions(+), 25 deletions(-) diff --git a/drivers/perf/apple_m1_cpu_pmu.c b/drivers/perf/apple_m1_cpu_pmu.c index b800da3f7f61ffa972fcab5f24b42127f2c55ac6..d1bc850809993de044df8fd5d4dfc61341482ee7 100644 --- a/drivers/perf/apple_m1_cpu_pmu.c +++ b/drivers/perf/apple_m1_cpu_pmu.c @@ -43,9 +43,6 @@ * moment, we don't really need to distinguish between the two because we * know next to nothing about the events themselves, and we already have * per cpu-type PMU abstractions. - * - * If we eventually find out that the events are different across - * implementations, we'll have to introduce per cpu-type tables. */ enum m1_pmu_events { M1_PMU_PERFCTR_RETIRE_UOP = 0x1, @@ -494,11 +491,12 @@ static void m1_pmu_write_counter(struct perf_event *event, u64 value) isb(); } -static int m1_pmu_get_event_idx(struct pmu_hw_events *cpuc, - struct perf_event *event) +static int apple_pmu_get_event_idx(struct pmu_hw_events *cpuc, + struct perf_event *event, + const u16 event_affinities[M1_PMU_CFG_EVENT]) { unsigned long evtype = event->hw.config_base & M1_PMU_CFG_EVENT; - unsigned long affinity = m1_pmu_event_affinity[evtype]; + unsigned long affinity = event_affinities[evtype]; int idx; /* @@ -517,6 +515,12 @@ static int m1_pmu_get_event_idx(struct pmu_hw_events *cpuc, return -EAGAIN; } +static int m1_pmu_get_event_idx(struct pmu_hw_events *cpuc, + struct perf_event *event) +{ + return apple_pmu_get_event_idx(cpuc, event, m1_pmu_event_affinity); +} + static void m1_pmu_clear_event_idx(struct pmu_hw_events *cpuc, struct perf_event *event) { @@ -544,7 +548,8 @@ static void m1_pmu_stop(struct arm_pmu *cpu_pmu) __m1_pmu_set_mode(PMCR0_IMODE_OFF); } -static int m1_pmu_map_event(struct perf_event *event) +static int apple_pmu_map_event_47(struct perf_event *event, + const unsigned int (*perf_map)[]) { /* * Although the counters are 48bit wide, bit 47 is what @@ -552,18 +557,29 @@ static int m1_pmu_map_event(struct perf_event *event) * being 47bit wide to mimick the behaviour of the ARM PMU. */ event->hw.flags |= ARMPMU_EVT_47BIT; - return armpmu_map_event(event, &m1_pmu_perf_map, NULL, M1_PMU_CFG_EVENT); + return armpmu_map_event(event, perf_map, NULL, M1_PMU_CFG_EVENT); } -static int m2_pmu_map_event(struct perf_event *event) +static int apple_pmu_map_event_63(struct perf_event *event, + const unsigned int (*perf_map)[]) { /* - * Same deal as the above, except that M2 has 64bit counters. + * Same deal as the above, except with 64bit counters. * Which, as far as we're concerned, actually means 63 bits. * Yes, this is getting awkward. */ event->hw.flags |= ARMPMU_EVT_63BIT; - return armpmu_map_event(event, &m1_pmu_perf_map, NULL, M1_PMU_CFG_EVENT); + return armpmu_map_event(event, perf_map, NULL, M1_PMU_CFG_EVENT); +} + +static int m1_pmu_map_event(struct perf_event *event) +{ + return apple_pmu_map_event_47(event, &m1_pmu_perf_map); +} + +static int m2_pmu_map_event(struct perf_event *event) +{ + return apple_pmu_map_event_63(event, &m1_pmu_perf_map); } static int m1_pmu_map_pmuv3_event(unsigned int eventsel) @@ -624,25 +640,16 @@ static int m1_pmu_set_event_filter(struct hw_perf_event *event, return 0; } -static int m1_pmu_init(struct arm_pmu *cpu_pmu, u32 flags) +static int apple_pmu_init(struct arm_pmu *cpu_pmu) { cpu_pmu->handle_irq = m1_pmu_handle_irq; cpu_pmu->enable = m1_pmu_enable_event; cpu_pmu->disable = m1_pmu_disable_event; cpu_pmu->read_counter = m1_pmu_read_counter; cpu_pmu->write_counter = m1_pmu_write_counter; - cpu_pmu->get_event_idx = m1_pmu_get_event_idx; cpu_pmu->clear_event_idx = m1_pmu_clear_event_idx; cpu_pmu->start = m1_pmu_start; cpu_pmu->stop = m1_pmu_stop; - - if (flags & ARMPMU_EVT_47BIT) - cpu_pmu->map_event = m1_pmu_map_event; - else if (flags & ARMPMU_EVT_63BIT) - cpu_pmu->map_event = m2_pmu_map_event; - else - return WARN_ON(-EINVAL); - cpu_pmu->reset = m1_pmu_reset; cpu_pmu->set_event_filter = m1_pmu_set_event_filter; @@ -661,25 +668,33 @@ static int m1_pmu_init(struct arm_pmu *cpu_pmu, u32 flags) static int m1_pmu_ice_init(struct arm_pmu *cpu_pmu) { cpu_pmu->name = "apple_icestorm_pmu"; - return m1_pmu_init(cpu_pmu, ARMPMU_EVT_47BIT); + cpu_pmu->get_event_idx = m1_pmu_get_event_idx; + cpu_pmu->map_event = m1_pmu_map_event; + return apple_pmu_init(cpu_pmu); } static int m1_pmu_fire_init(struct arm_pmu *cpu_pmu) { cpu_pmu->name = "apple_firestorm_pmu"; - return m1_pmu_init(cpu_pmu, ARMPMU_EVT_47BIT); + cpu_pmu->get_event_idx = m1_pmu_get_event_idx; + cpu_pmu->map_event = m1_pmu_map_event; + return apple_pmu_init(cpu_pmu); } static int m2_pmu_avalanche_init(struct arm_pmu *cpu_pmu) { cpu_pmu->name = "apple_avalanche_pmu"; - return m1_pmu_init(cpu_pmu, ARMPMU_EVT_63BIT); + cpu_pmu->get_event_idx = m1_pmu_get_event_idx; + cpu_pmu->map_event = m2_pmu_map_event; + return apple_pmu_init(cpu_pmu); } static int m2_pmu_blizzard_init(struct arm_pmu *cpu_pmu) { cpu_pmu->name = "apple_blizzard_pmu"; - return m1_pmu_init(cpu_pmu, ARMPMU_EVT_63BIT); + cpu_pmu->get_event_idx = m1_pmu_get_event_idx; + cpu_pmu->map_event = m2_pmu_map_event; + return apple_pmu_init(cpu_pmu); } static const struct of_device_id m1_pmu_of_device_ids[] = { From patchwork Mon Apr 7 04:45:13 2025 Content-Type: text/plain; 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Sun, 06 Apr 2025 21:46:17 -0700 (PDT) From: Nick Chan Date: Mon, 07 Apr 2025 12:45:13 +0800 Subject: [PATCH v6 04/21] drivers/perf: apple_m1: Support a per-implementation number of counters MIME-Version: 1.0 Message-Id: <20250407-apple-cpmu-v6-4-ae8c2f225c1f@gmail.com> References: <20250407-apple-cpmu-v6-0-ae8c2f225c1f@gmail.com> In-Reply-To: <20250407-apple-cpmu-v6-0-ae8c2f225c1f@gmail.com> To: Will Deacon , Mark Rutland , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Catalin Marinas , Sven Peter , Janne Grunau , Alyssa Rosenzweig , Neal Gompa Cc: Marc Zyngier , linux-arm-kernel@lists.infradead.org, linux-perf-users@vger.kernel.org, devicetree@vger.kernel.org, asahi@lists.linux.dev, linux-kernel@vger.kernel.org, Nick Chan X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=openpgp-sha256; l=4845; i=towinchenmi@gmail.com; h=from:subject:message-id; bh=BTD9OzZ4+bVdpzPnyX6mWog1RpRVl3h0ilCKcAXUUSU=; b=owEBbQKS/ZANAwAIAQHKCLemxQgkAcsmYgBn81iGqhUUZt9nky98KDY3T1B1WYbpyDK+8m3Yx gUwHxgLQmiJAjMEAAEIAB0WIQRLUnh4XJes95w8aIMBygi3psUIJAUCZ/NYhgAKCRABygi3psUI JDKXD/4lIldbnqE1hTQRJKq40e4filHHMJC+4IZgtoHQV9zQvpGEB5y0InQPawHu8Tf2z8ghGrW rBHV/OrTcERXXaisZxR+bXTVybcA6IrSWR2xtyBbTlLv0e6p75USp3XfJ0oKhDY3ibrVizo6Hys w9Hmd5qCKxDTa0XtXAkg9/BNpxPDpvIwabca0KvcrKjtwX9s9R4/5GVu4qnSKpOprT1fphO1UyZ wld4wNY2RM/Zt4usnUnFKQkTSYgjKU6br3r84+0UPJWVzkR/6mNBZkFVJaKVvOjbhC/L8cPn5D8 Zdy5vn4MDTE9QVufxf/38RkCD66qMLaPrCylqsz5pVPWIBrJXfHK4JYgEFwjnGxnzDl+xCPUHhw oPXbMpK9+bc+QbF9fDRPWlK6hiQwBue6RdGmpByoRLuqBT9ZENx4htJz0EzIB2rxcWyTS+I01M1 z5mpVLKKeXDaGC58kG48Day4fJ3w6ielBMs3hnLwz/K9FHX7eG9N6KJHttopx90aIj1e7bbxrwF soGeVQeFJzQlZXuvncRaWzfuo6aGqiKbqvcMGtXi8kkp4c/Rjr1hxTRYIqzbNZgWVXfycklDUqh zsrgUbWygnAwU/kVcmZLGcEId7YrlqabgJaLzs9kaFcHJXzSXN2+FaapQKmEkSf1GaJWS1ZDrsw CTg+TUuCT8qrznw== X-Developer-Key: i=towinchenmi@gmail.com; a=openpgp; fpr=4B5278785C97ACF79C3C688301CA08B7A6C50824 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20250406_214618_705776_B452D07C X-CRM114-Status: GOOD ( 16.40 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org Support a per-implementation number of counters to allow adding support for implementations with less counters. Signed-off-by: Nick Chan --- drivers/perf/apple_m1_cpu_pmu.c | 31 ++++++++++++++++++++----------- 1 file changed, 20 insertions(+), 11 deletions(-) diff --git a/drivers/perf/apple_m1_cpu_pmu.c b/drivers/perf/apple_m1_cpu_pmu.c index d1bc850809993de044df8fd5d4dfc61341482ee7..c03eb7acbb66790e17967d570c71746f72e40867 100644 --- a/drivers/perf/apple_m1_cpu_pmu.c +++ b/drivers/perf/apple_m1_cpu_pmu.c @@ -20,6 +20,7 @@ #include #define M1_PMU_NR_COUNTERS 10 +#define APPLE_PMU_MAX_NR_COUNTERS 10 #define M1_PMU_CFG_EVENT GENMASK(7, 0) @@ -459,7 +460,7 @@ static irqreturn_t m1_pmu_handle_irq(struct arm_pmu *cpu_pmu) regs = get_irq_regs(); - for_each_set_bit(idx, cpu_pmu->cntr_mask, M1_PMU_NR_COUNTERS) { + for_each_set_bit(idx, cpu_pmu->cntr_mask, APPLE_PMU_MAX_NR_COUNTERS) { struct perf_event *event = cpuc->events[idx]; struct perf_sample_data data; @@ -507,7 +508,7 @@ static int apple_pmu_get_event_idx(struct pmu_hw_events *cpuc, * counting on the PMU at any given time, and by placing the * most constraining events first. */ - for_each_set_bit(idx, &affinity, M1_PMU_NR_COUNTERS) { + for_each_set_bit(idx, &affinity, APPLE_PMU_MAX_NR_COUNTERS) { if (!test_and_set_bit(idx, cpuc->used_mask)) return idx; } @@ -602,13 +603,13 @@ static void m1_pmu_init_pmceid(struct arm_pmu *pmu) } } -static void m1_pmu_reset(void *info) +static void apple_pmu_reset(void *info, u32 counters) { int i; __m1_pmu_set_mode(PMCR0_IMODE_OFF); - for (i = 0; i < M1_PMU_NR_COUNTERS; i++) { + for (i = 0; i < counters; i++) { m1_pmu_disable_counter(i); m1_pmu_disable_counter_interrupt(i); m1_pmu_write_hw_counter(0, i); @@ -617,6 +618,11 @@ static void m1_pmu_reset(void *info) isb(); } +static void m1_pmu_reset(void *info) +{ + apple_pmu_reset(info, M1_PMU_NR_COUNTERS); +} + static int m1_pmu_set_event_filter(struct hw_perf_event *event, struct perf_event_attr *attr) { @@ -640,7 +646,7 @@ static int m1_pmu_set_event_filter(struct hw_perf_event *event, return 0; } -static int apple_pmu_init(struct arm_pmu *cpu_pmu) +static int apple_pmu_init(struct arm_pmu *cpu_pmu, u32 counters) { cpu_pmu->handle_irq = m1_pmu_handle_irq; cpu_pmu->enable = m1_pmu_enable_event; @@ -650,7 +656,6 @@ static int apple_pmu_init(struct arm_pmu *cpu_pmu) cpu_pmu->clear_event_idx = m1_pmu_clear_event_idx; cpu_pmu->start = m1_pmu_start; cpu_pmu->stop = m1_pmu_stop; - cpu_pmu->reset = m1_pmu_reset; cpu_pmu->set_event_filter = m1_pmu_set_event_filter; if (is_hyp_mode_available()) { @@ -658,7 +663,7 @@ static int apple_pmu_init(struct arm_pmu *cpu_pmu) m1_pmu_init_pmceid(cpu_pmu); } - bitmap_set(cpu_pmu->cntr_mask, 0, M1_PMU_NR_COUNTERS); + bitmap_set(cpu_pmu->cntr_mask, 0, counters); cpu_pmu->attr_groups[ARMPMU_ATTR_GROUP_EVENTS] = &m1_pmu_events_attr_group; cpu_pmu->attr_groups[ARMPMU_ATTR_GROUP_FORMATS] = &m1_pmu_format_attr_group; return 0; @@ -670,7 +675,8 @@ static int m1_pmu_ice_init(struct arm_pmu *cpu_pmu) cpu_pmu->name = "apple_icestorm_pmu"; cpu_pmu->get_event_idx = m1_pmu_get_event_idx; cpu_pmu->map_event = m1_pmu_map_event; - return apple_pmu_init(cpu_pmu); + cpu_pmu->reset = m1_pmu_reset; + return apple_pmu_init(cpu_pmu, M1_PMU_NR_COUNTERS); } static int m1_pmu_fire_init(struct arm_pmu *cpu_pmu) @@ -678,7 +684,8 @@ static int m1_pmu_fire_init(struct arm_pmu *cpu_pmu) cpu_pmu->name = "apple_firestorm_pmu"; cpu_pmu->get_event_idx = m1_pmu_get_event_idx; cpu_pmu->map_event = m1_pmu_map_event; - return apple_pmu_init(cpu_pmu); + cpu_pmu->reset = m1_pmu_reset; + return apple_pmu_init(cpu_pmu, M1_PMU_NR_COUNTERS); } static int m2_pmu_avalanche_init(struct arm_pmu *cpu_pmu) @@ -686,7 +693,8 @@ static int m2_pmu_avalanche_init(struct arm_pmu *cpu_pmu) cpu_pmu->name = "apple_avalanche_pmu"; cpu_pmu->get_event_idx = m1_pmu_get_event_idx; cpu_pmu->map_event = m2_pmu_map_event; - return apple_pmu_init(cpu_pmu); + cpu_pmu->reset = m1_pmu_reset; + return apple_pmu_init(cpu_pmu, M1_PMU_NR_COUNTERS); } static int m2_pmu_blizzard_init(struct arm_pmu *cpu_pmu) @@ -694,7 +702,8 @@ static int m2_pmu_blizzard_init(struct arm_pmu *cpu_pmu) cpu_pmu->name = "apple_blizzard_pmu"; cpu_pmu->get_event_idx = m1_pmu_get_event_idx; cpu_pmu->map_event = m2_pmu_map_event; - return apple_pmu_init(cpu_pmu); + cpu_pmu->reset = m1_pmu_reset; + return apple_pmu_init(cpu_pmu, M1_PMU_NR_COUNTERS); } static const struct of_device_id m1_pmu_of_device_ids[] = { From patchwork Mon Apr 7 04:45:14 2025 Content-Type: text/plain; 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Sun, 06 Apr 2025 21:46:20 -0700 (PDT) From: Nick Chan Date: Mon, 07 Apr 2025 12:45:14 +0800 Subject: [PATCH v6 05/21] drivers/perf: apple_m1: Support configuring counters for 32-bit EL0 MIME-Version: 1.0 Message-Id: <20250407-apple-cpmu-v6-5-ae8c2f225c1f@gmail.com> References: <20250407-apple-cpmu-v6-0-ae8c2f225c1f@gmail.com> In-Reply-To: <20250407-apple-cpmu-v6-0-ae8c2f225c1f@gmail.com> To: Will Deacon , Mark Rutland , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Catalin Marinas , Sven Peter , Janne Grunau , Alyssa Rosenzweig , Neal Gompa Cc: Marc Zyngier , linux-arm-kernel@lists.infradead.org, linux-perf-users@vger.kernel.org, devicetree@vger.kernel.org, asahi@lists.linux.dev, linux-kernel@vger.kernel.org, Nick Chan X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=openpgp-sha256; l=2122; i=towinchenmi@gmail.com; h=from:subject:message-id; bh=ow2nagzt8cdbi88jV06ZnLC5cMis8xMzKWgyHSgosSQ=; b=owEBbQKS/ZANAwAIAQHKCLemxQgkAcsmYgBn81iGwNe6cSPZDJeV+M3GsJYDoPDTRilFEHJMm 2rQGNvdL0uJAjMEAAEIAB0WIQRLUnh4XJes95w8aIMBygi3psUIJAUCZ/NYhgAKCRABygi3psUI JFdaD/40iSJYdfx9SHyamIEddVIar+7DkYWcqtkWkzzjdFjSq6Ak3TgXq+p2CjsWVzYpv6vrMqN wkUbLR01ADbBmEykVR9Y0QtU5S9VAFqQX5Vfn+TFbFhK6Uuh+8mC5RllY0pIqQoEThDegeWYpSJ JhR3g8h8WP4XRZjuiw1nH0e8Ps6434D5kLgPRftpB5o5q0jFjc0D9TZ3G5GFT9Ff6sXVwqLPO7Q /Iusv7lYcBaKt4e1jwlmjSSrjMXq2V0KxFOobVCOVtVsl83igP38QkOUf/HeHnwyOMgKsyYZ4EF afHMqCOs31GPtvVmDFnKC96tFnzbu+VPFp4cXVqpMUzNM5P8JvjzR7Y9U73PGwoKNs3He827Gv6 5zsgxG3OFOlqcpg6IaDXEDBdwnlNUpCgQyn0mBUv0ENcHpQk0PDzzOmnucKmD5OJ2pQVQeb0sJ/ XQoTupZGYQLxBm1DDMIJgmNlbehuTD26BIMJ/XSHL0bUy/CMmJ2NULPB3O9qWM0TF9JJcmrMDfp ty1aG3m3O6fAFdDxu4mfj4AxNr7OgDg1jhorFf1h6HerMlSE8yj5Q9+ZI2sgZhFbP6moM+/aNa2 YEqfWn4n4QY8GvOq/ro6MkZ5LexuutJd+d2HYVvjqSyaBJTyBwVo/SzYJMLc4DBigaFHI7R5XSW h1HMGgKlDZVP8ZA== X-Developer-Key: i=towinchenmi@gmail.com; a=openpgp; fpr=4B5278785C97ACF79C3C688301CA08B7A6C50824 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20250406_214622_098847_D0340CF8 X-CRM114-Status: GOOD ( 11.89 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org Add support for configuring counters for 32-bit EL0 to allow adding support for implementations with 32-bit EL0. For documentation purposes, also add the bitmask for configuring counters for 64-bit EL3. Signed-off-by: Nick Chan --- arch/arm64/include/asm/apple_m1_pmu.h | 3 +++ drivers/perf/apple_m1_cpu_pmu.c | 6 ++++++ 2 files changed, 9 insertions(+) diff --git a/arch/arm64/include/asm/apple_m1_pmu.h b/arch/arm64/include/asm/apple_m1_pmu.h index 02e05d05851f739b985bf416f1aa3baeafd691dc..6e238043e0dc2360c4fd507dc6a0eb7e055d2d6f 100644 --- a/arch/arm64/include/asm/apple_m1_pmu.h +++ b/arch/arm64/include/asm/apple_m1_pmu.h @@ -38,8 +38,11 @@ #define SYS_IMP_APL_PMCR1_EL1 sys_reg(3, 1, 15, 1, 0) #define SYS_IMP_APL_PMCR1_EL12 sys_reg(3, 1, 15, 7, 2) +#define PMCR1_COUNT_A32_EL0_0_7 GENMASK(7, 0) #define PMCR1_COUNT_A64_EL0_0_7 GENMASK(15, 8) #define PMCR1_COUNT_A64_EL1_0_7 GENMASK(23, 16) +#define PMCR1_COUNT_A64_EL3_0_7 GENMASK(31, 24) +#define PMCR1_COUNT_A32_EL0_8_9 GENMASK(33, 32) #define PMCR1_COUNT_A64_EL0_8_9 GENMASK(41, 40) #define PMCR1_COUNT_A64_EL1_8_9 GENMASK(49, 48) diff --git a/drivers/perf/apple_m1_cpu_pmu.c b/drivers/perf/apple_m1_cpu_pmu.c index c03eb7acbb66790e17967d570c71746f72e40867..f2566a0f8d330fdc0d71ae298f16ee9700a13c23 100644 --- a/drivers/perf/apple_m1_cpu_pmu.c +++ b/drivers/perf/apple_m1_cpu_pmu.c @@ -348,10 +348,16 @@ static void __m1_pmu_configure_event_filter(unsigned int index, bool user, case 0 ... 7: user_bit = BIT(get_bit_offset(index, PMCR1_COUNT_A64_EL0_0_7)); kernel_bit = BIT(get_bit_offset(index, PMCR1_COUNT_A64_EL1_0_7)); + + if (system_supports_32bit_el0()) + user_bit |= BIT(get_bit_offset(index, PMCR1_COUNT_A32_EL0_0_7)); break; case 8 ... 9: user_bit = BIT(get_bit_offset(index - 8, PMCR1_COUNT_A64_EL0_8_9)); kernel_bit = BIT(get_bit_offset(index - 8, PMCR1_COUNT_A64_EL1_8_9)); + + if (system_supports_32bit_el0()) + user_bit |= BIT(get_bit_offset(index - 8, PMCR1_COUNT_A32_EL0_8_9)); break; default: BUG(); From patchwork Mon Apr 7 04:45:15 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Nick Chan X-Patchwork-Id: 14039702 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id C5920C36010 for ; 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a=openpgp; fpr=4B5278785C97ACF79C3C688301CA08B7A6C50824 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20250406_214625_255503_1640F63F X-CRM114-Status: GOOD ( 11.32 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org Support for implementations that deliver its interrupts in ways other than FIQ will be added, which requires a per-implementation startup function. Signed-off-by: Nick Chan --- drivers/perf/apple_m1_cpu_pmu.c | 5 ++++- 1 file changed, 4 insertions(+), 1 deletion(-) diff --git a/drivers/perf/apple_m1_cpu_pmu.c b/drivers/perf/apple_m1_cpu_pmu.c index f2566a0f8d330fdc0d71ae298f16ee9700a13c23..38fb9200369c11d0d7674bec4f350915c67352b9 100644 --- a/drivers/perf/apple_m1_cpu_pmu.c +++ b/drivers/perf/apple_m1_cpu_pmu.c @@ -660,7 +660,6 @@ static int apple_pmu_init(struct arm_pmu *cpu_pmu, u32 counters) cpu_pmu->read_counter = m1_pmu_read_counter; cpu_pmu->write_counter = m1_pmu_write_counter; cpu_pmu->clear_event_idx = m1_pmu_clear_event_idx; - cpu_pmu->start = m1_pmu_start; cpu_pmu->stop = m1_pmu_stop; cpu_pmu->set_event_filter = m1_pmu_set_event_filter; @@ -682,6 +681,7 @@ static int m1_pmu_ice_init(struct arm_pmu *cpu_pmu) cpu_pmu->get_event_idx = m1_pmu_get_event_idx; cpu_pmu->map_event = m1_pmu_map_event; cpu_pmu->reset = m1_pmu_reset; + cpu_pmu->start = m1_pmu_start; return apple_pmu_init(cpu_pmu, M1_PMU_NR_COUNTERS); } @@ -691,6 +691,7 @@ static int m1_pmu_fire_init(struct arm_pmu *cpu_pmu) cpu_pmu->get_event_idx = m1_pmu_get_event_idx; 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a=openpgp; fpr=4B5278785C97ACF79C3C688301CA08B7A6C50824 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20250406_214628_234167_DE4BA7AF X-CRM114-Status: GOOD ( 11.52 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org To support implementations with different event numbers for cycles or instruction events, event attr groups needs to be per-implementation. Signed-off-by: Nick Chan --- drivers/perf/apple_m1_cpu_pmu.c | 5 ++++- 1 file changed, 4 insertions(+), 1 deletion(-) diff --git a/drivers/perf/apple_m1_cpu_pmu.c b/drivers/perf/apple_m1_cpu_pmu.c index 38fb9200369c11d0d7674bec4f350915c67352b9..523ad37a07521692206cc438b8d777f505506c7e 100644 --- a/drivers/perf/apple_m1_cpu_pmu.c +++ b/drivers/perf/apple_m1_cpu_pmu.c @@ -669,7 +669,6 @@ static int apple_pmu_init(struct arm_pmu *cpu_pmu, u32 counters) } bitmap_set(cpu_pmu->cntr_mask, 0, counters); - cpu_pmu->attr_groups[ARMPMU_ATTR_GROUP_EVENTS] = &m1_pmu_events_attr_group; cpu_pmu->attr_groups[ARMPMU_ATTR_GROUP_FORMATS] = &m1_pmu_format_attr_group; return 0; } @@ -682,6 +681,7 @@ static int m1_pmu_ice_init(struct arm_pmu *cpu_pmu) cpu_pmu->map_event = m1_pmu_map_event; cpu_pmu->reset = m1_pmu_reset; cpu_pmu->start = m1_pmu_start; + cpu_pmu->attr_groups[ARMPMU_ATTR_GROUP_EVENTS] = &m1_pmu_events_attr_group; return apple_pmu_init(cpu_pmu, M1_PMU_NR_COUNTERS); } @@ -692,6 +692,7 @@ static int m1_pmu_fire_init(struct arm_pmu *cpu_pmu) cpu_pmu->map_event = m1_pmu_map_event; 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Sun, 06 Apr 2025 21:46:30 -0700 (PDT) Received: from [127.0.1.1] ([59.188.211.160]) by smtp.googlemail.com with ESMTPSA id 98e67ed59e1d1-305983b9954sm7765810a91.32.2025.04.06.21.46.27 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 06 Apr 2025 21:46:30 -0700 (PDT) From: Nick Chan Date: Mon, 07 Apr 2025 12:45:17 +0800 Subject: [PATCH v6 08/21] drivers/perf: apple_m1: Add Apple A7 support MIME-Version: 1.0 Message-Id: <20250407-apple-cpmu-v6-8-ae8c2f225c1f@gmail.com> References: <20250407-apple-cpmu-v6-0-ae8c2f225c1f@gmail.com> In-Reply-To: <20250407-apple-cpmu-v6-0-ae8c2f225c1f@gmail.com> To: Will Deacon , Mark Rutland , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Catalin Marinas , Sven Peter , Janne Grunau , Alyssa Rosenzweig , Neal Gompa Cc: Marc Zyngier , linux-arm-kernel@lists.infradead.org, linux-perf-users@vger.kernel.org, devicetree@vger.kernel.org, asahi@lists.linux.dev, linux-kernel@vger.kernel.org, Nick Chan X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; 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a=openpgp; fpr=4B5278785C97ACF79C3C688301CA08B7A6C50824 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20250406_214632_014351_010A9005 X-CRM114-Status: GOOD ( 16.91 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org Add support for the CPU PMU found in the Apple A7 SoC. The PMU has 8 counters and a very different event layout compared to the M1 PMU. Interrupts are delivered as IRQs instead of FIQs like on the M1. Signed-off-by: Nick Chan --- drivers/perf/apple_m1_cpu_pmu.c | 190 ++++++++++++++++++++++++++++++++++++++++ 1 file changed, 190 insertions(+) diff --git a/drivers/perf/apple_m1_cpu_pmu.c b/drivers/perf/apple_m1_cpu_pmu.c index 523ad37a07521692206cc438b8d777f505506c7e..3c03d0e99ddaf90605cb8dafa68ab8770d371a05 100644 --- a/drivers/perf/apple_m1_cpu_pmu.c +++ b/drivers/perf/apple_m1_cpu_pmu.c @@ -19,6 +19,7 @@ #include #include +#define A7_PMU_NR_COUNTERS 8 #define M1_PMU_NR_COUNTERS 10 #define APPLE_PMU_MAX_NR_COUNTERS 10 @@ -45,6 +46,143 @@ * know next to nothing about the events themselves, and we already have * per cpu-type PMU abstractions. */ + +enum a7_pmu_events { + A7_PMU_PERFCTR_INST_ALL = 0x0, + A7_PMU_PERFCTR_UNKNOWN_1 = 0x1, + A7_PMU_PERFCTR_CORE_ACTIVE_CYCLE = 0x2, + A7_PMU_PERFCTR_L2_TLB_MISS_INSTRUCTION = 0x10, + A7_PMU_PERFCTR_L2_TLB_MISS_DATA = 0x11, + A7_PMU_PERFCTR_BIU_UPSTREAM_CYCLE = 0x19, + A7_PMU_PERFCTR_BIU_DOWNSTREAM_CYCLE = 0x20, + A7_PMU_PERFCTR_L2C_AGENT_LD = 0x22, + A7_PMU_PERFCTR_L2C_AGENT_LD_MISS = 0x23, + A7_PMU_PERFCTR_L2C_AGENT_ST = 0x24, + A7_PMU_PERFCTR_L2C_AGENT_ST_MISS = 0x25, + A7_PMU_PERFCTR_SCHEDULE_UOP = 0x58, + A7_PMU_PERFCTR_MAP_REWIND = 0x61, + A7_PMU_PERFCTR_MAP_STALL = 0x62, + A7_PMU_PERFCTR_FLUSH_RESTART_OTHER_NONSPEC = 0x6e, + A7_PMU_PERFCTR_INST_A32 = 0x78, + A7_PMU_PERFCTR_INST_T32 = 0x79, + A7_PMU_PERFCTR_INST_A64 = 0x7a, + A7_PMU_PERFCTR_INST_BRANCH = 0x7b, + A7_PMU_PERFCTR_INST_BRANCH_CALL = 0x7c, + A7_PMU_PERFCTR_INST_BRANCH_RET = 0x7d, + A7_PMU_PERFCTR_INST_BRANCH_TAKEN = 0x7e, + A7_PMU_PERFCTR_INST_BRANCH_INDIR = 0x81, + A7_PMU_PERFCTR_INST_BRANCH_COND = 0x82, + A7_PMU_PERFCTR_INST_INT_LD = 0x83, + A7_PMU_PERFCTR_INST_INT_ST = 0x84, + A7_PMU_PERFCTR_INST_INT_ALU = 0x85, + A7_PMU_PERFCTR_INST_SIMD_LD = 0x86, + A7_PMU_PERFCTR_INST_SIMD_ST = 0x87, + A7_PMU_PERFCTR_INST_SIMD_ALU = 0x88, + A7_PMU_PERFCTR_INST_LDST = 0x89, + A7_PMU_PERFCTR_UNKNOWN_8d = 0x8d, + A7_PMU_PERFCTR_UNKNOWN_8e = 0x8e, + A7_PMU_PERFCTR_UNKNOWN_8f = 0x8f, + A7_PMU_PERFCTR_UNKNOWN_90 = 0x90, + A7_PMU_PERFCTR_UNKNOWN_93 = 0x93, + A7_PMU_PERFCTR_UNKNOWN_94 = 0x94, + A7_PMU_PERFCTR_UNKNOWN_95 = 0x95, + A7_PMU_PERFCTR_L1D_TLB_ACCESS = 0x96, + A7_PMU_PERFCTR_L1D_TLB_MISS = 0x97, + A7_PMU_PERFCTR_L1D_CACHE_MISS_ST = 0x98, + A7_PMU_PERFCTR_L1D_CACHE_MISS_LD = 0x99, + A7_PMU_PERFCTR_UNKNOWN_9b = 0x9b, + A7_PMU_PERFCTR_LD_UNIT_UOP = 0x9c, + A7_PMU_PERFCTR_ST_UNIT_UOP = 0x9d, + A7_PMU_PERFCTR_L1D_CACHE_WRITEBACK = 0x9e, + A7_PMU_PERFCTR_UNKNOWN_9f = 0x9f, + A7_PMU_PERFCTR_LDST_X64_UOP = 0xa7, + A7_PMU_PERFCTR_L1D_CACHE_MISS_LD_NONSPEC = 0xb4, + A7_PMU_PERFCTR_L1D_CACHE_MISS_ST_NONSPEC = 0xb5, + A7_PMU_PERFCTR_L1D_TLB_MISS_NONSPEC = 0xb6, + A7_PMU_PERFCTR_ST_MEMORY_ORDER_VIOLATION_NONSPEC = 0xb9, + A7_PMU_PERFCTR_BRANCH_COND_MISPRED_NONSPEC = 0xba, + A7_PMU_PERFCTR_BRANCH_INDIR_MISPRED_NONSPEC = 0xbb, + A7_PMU_PERFCTR_BRANCH_RET_INDIR_MISPRED_NONSPEC = 0xbd, + A7_PMU_PERFCTR_BRANCH_CALL_INDIR_MISPRED_NONSPEC = 0xbf, + A7_PMU_PERFCTR_BRANCH_MISPRED_NONSPEC = 0xc0, + A7_PMU_PERFCTR_UNKNOWN_c1 = 0xc1, + A7_PMU_PERFCTR_UNKNOWN_c4 = 0xc4, + A7_PMU_PERFCTR_UNKNOWN_c5 = 0xc5, + A7_PMU_PERFCTR_UNKNOWN_c6 = 0xc6, + A7_PMU_PERFCTR_UNKNOWN_c8 = 0xc8, + A7_PMU_PERFCTR_UNKNOWN_ca = 0xca, + A7_PMU_PERFCTR_UNKNOWN_cb = 0xcb, + A7_PMU_PERFCTR_FED_IC_MISS_DEMAND = 0xce, + A7_PMU_PERFCTR_L1I_TLB_MISS_DEMAND = 0xcf, + A7_PMU_PERFCTR_UNKNOWN_f5 = 0xf5, + A7_PMU_PERFCTR_UNKNOWN_f6 = 0xf6, + A7_PMU_PERFCTR_UNKNOWN_f7 = 0xf7, + A7_PMU_PERFCTR_UNKNOWN_f8 = 0xf8, + A7_PMU_PERFCTR_UNKNOWN_fd = 0xfd, + A7_PMU_PERFCTR_LAST = M1_PMU_CFG_EVENT, + /* + * From this point onwards, these are not actual HW events, + * but attributes that get stored in hw->config_base. + */ + A7_PMU_CFG_COUNT_USER = BIT(8), + A7_PMU_CFG_COUNT_KERNEL = BIT(9), +}; + +static const u16 a7_pmu_event_affinity[A7_PMU_PERFCTR_LAST + 1] = { + [0 ... A7_PMU_PERFCTR_LAST] = ANY_BUT_0_1, + [A7_PMU_PERFCTR_INST_ALL] = ANY_BUT_0_1 | BIT(1), + [A7_PMU_PERFCTR_UNKNOWN_1] = ONLY_5_6_7, + [A7_PMU_PERFCTR_CORE_ACTIVE_CYCLE] = ANY_BUT_0_1 | BIT(0), + [A7_PMU_PERFCTR_INST_A32] = ONLY_5_6_7, + [A7_PMU_PERFCTR_INST_T32] = ONLY_5_6_7, + [A7_PMU_PERFCTR_INST_A64] = ONLY_5_6_7, + [A7_PMU_PERFCTR_INST_BRANCH] = ONLY_5_6_7, + [A7_PMU_PERFCTR_INST_BRANCH_CALL] = ONLY_5_6_7, + [A7_PMU_PERFCTR_INST_BRANCH_RET] = ONLY_5_6_7, + [A7_PMU_PERFCTR_INST_BRANCH_TAKEN] = ONLY_5_6_7, + [A7_PMU_PERFCTR_INST_BRANCH_INDIR] = ONLY_5_6_7, + [A7_PMU_PERFCTR_INST_BRANCH_COND] = ONLY_5_6_7, + [A7_PMU_PERFCTR_INST_INT_LD] = ONLY_5_6_7, + [A7_PMU_PERFCTR_INST_INT_ST] = ONLY_5_6_7, + [A7_PMU_PERFCTR_INST_INT_ALU] = ONLY_5_6_7, + [A7_PMU_PERFCTR_INST_SIMD_LD] = ONLY_5_6_7, + [A7_PMU_PERFCTR_INST_SIMD_ST] = ONLY_5_6_7, + [A7_PMU_PERFCTR_INST_SIMD_ALU] = ONLY_5_6_7, + [A7_PMU_PERFCTR_INST_LDST] = ONLY_5_6_7, + [A7_PMU_PERFCTR_UNKNOWN_8d] = ONLY_5_6_7, + [A7_PMU_PERFCTR_UNKNOWN_8e] = ONLY_5_6_7, + [A7_PMU_PERFCTR_UNKNOWN_8f] = ONLY_5_6_7, + [A7_PMU_PERFCTR_UNKNOWN_90] = ONLY_5_6_7, + [A7_PMU_PERFCTR_UNKNOWN_93] = ONLY_5_6_7, + [A7_PMU_PERFCTR_UNKNOWN_94] = ONLY_5_6_7, + [A7_PMU_PERFCTR_UNKNOWN_95] = ONLY_5_6_7, + [A7_PMU_PERFCTR_L1D_CACHE_MISS_ST] = ONLY_5_6_7, + [A7_PMU_PERFCTR_L1D_CACHE_MISS_LD] = ONLY_5_6_7, + [A7_PMU_PERFCTR_UNKNOWN_9b] = ONLY_5_6_7, + [A7_PMU_PERFCTR_LD_UNIT_UOP] = ONLY_5_6_7, + [A7_PMU_PERFCTR_UNKNOWN_9f] = ONLY_5_6_7, + [A7_PMU_PERFCTR_L1D_CACHE_MISS_LD_NONSPEC] = ONLY_5_6_7, + [A7_PMU_PERFCTR_L1D_CACHE_MISS_ST_NONSPEC] = ONLY_5_6_7, + [A7_PMU_PERFCTR_L1D_TLB_MISS_NONSPEC] = ONLY_5_6_7, + [A7_PMU_PERFCTR_ST_MEMORY_ORDER_VIOLATION_NONSPEC] = ONLY_5_6_7, + [A7_PMU_PERFCTR_BRANCH_COND_MISPRED_NONSPEC] = ONLY_5_6_7, + [A7_PMU_PERFCTR_BRANCH_INDIR_MISPRED_NONSPEC] = ONLY_5_6_7, + [A7_PMU_PERFCTR_BRANCH_RET_INDIR_MISPRED_NONSPEC] = ONLY_5_6_7, + [A7_PMU_PERFCTR_BRANCH_CALL_INDIR_MISPRED_NONSPEC] = ONLY_5_6_7, + [A7_PMU_PERFCTR_BRANCH_MISPRED_NONSPEC] = ONLY_5_6_7, + [A7_PMU_PERFCTR_UNKNOWN_c1] = ONLY_5_6_7, + [A7_PMU_PERFCTR_UNKNOWN_c4] = ONLY_5_6_7, + [A7_PMU_PERFCTR_UNKNOWN_c5] = ONLY_5_6_7, + [A7_PMU_PERFCTR_UNKNOWN_c6] = ONLY_5_6_7, + [A7_PMU_PERFCTR_UNKNOWN_c8] = ONLY_5_6_7, + [A7_PMU_PERFCTR_UNKNOWN_ca] = ONLY_5_6_7, + [A7_PMU_PERFCTR_UNKNOWN_cb] = ONLY_5_6_7, + [A7_PMU_PERFCTR_UNKNOWN_f5] = ONLY_2_4_6, + [A7_PMU_PERFCTR_UNKNOWN_f6] = ONLY_2_4_6, + [A7_PMU_PERFCTR_UNKNOWN_f7] = ONLY_2_4_6, + [A7_PMU_PERFCTR_UNKNOWN_fd] = ONLY_2_4_6, +}; + enum m1_pmu_events { M1_PMU_PERFCTR_RETIRE_UOP = 0x1, M1_PMU_PERFCTR_CORE_ACTIVE_CYCLE = 0x2, @@ -165,6 +303,14 @@ static const u16 m1_pmu_event_affinity[M1_PMU_PERFCTR_LAST + 1] = { [M1_PMU_PERFCTR_UNKNOWN_fd] = ONLY_2_4_6, }; +static const unsigned int a7_pmu_perf_map[PERF_COUNT_HW_MAX] = { + PERF_MAP_ALL_UNSUPPORTED, + [PERF_COUNT_HW_CPU_CYCLES] = A7_PMU_PERFCTR_CORE_ACTIVE_CYCLE, + [PERF_COUNT_HW_INSTRUCTIONS] = A7_PMU_PERFCTR_INST_ALL, + [PERF_COUNT_HW_BRANCH_MISSES] = A7_PMU_PERFCTR_BRANCH_MISPRED_NONSPEC, + [PERF_COUNT_HW_BRANCH_INSTRUCTIONS] = A7_PMU_PERFCTR_INST_BRANCH +}; + static const unsigned m1_pmu_perf_map[PERF_COUNT_HW_MAX] = { PERF_MAP_ALL_UNSUPPORTED, [PERF_COUNT_HW_CPU_CYCLES] = M1_PMU_PERFCTR_CORE_ACTIVE_CYCLE, @@ -199,6 +345,17 @@ static ssize_t m1_pmu_events_sysfs_show(struct device *dev, #define M1_PMU_EVENT_ATTR(name, config) \ PMU_EVENT_ATTR_ID(name, m1_pmu_events_sysfs_show, config) +static struct attribute *a7_pmu_event_attrs[] = { + M1_PMU_EVENT_ATTR(cycles, A7_PMU_PERFCTR_CORE_ACTIVE_CYCLE), + M1_PMU_EVENT_ATTR(instructions, A7_PMU_PERFCTR_INST_ALL), + NULL, +}; + +static const struct attribute_group a7_pmu_events_attr_group = { + .name = "events", + .attrs = a7_pmu_event_attrs, +}; + static struct attribute *m1_pmu_event_attrs[] = { M1_PMU_EVENT_ATTR(cycles, M1_PMU_PERFCTR_CORE_ACTIVE_CYCLE), M1_PMU_EVENT_ATTR(instructions, M1_PMU_PERFCTR_INST_ALL), @@ -522,6 +679,12 @@ static int apple_pmu_get_event_idx(struct pmu_hw_events *cpuc, return -EAGAIN; } +static int a7_pmu_get_event_idx(struct pmu_hw_events *cpuc, + struct perf_event *event) +{ + return apple_pmu_get_event_idx(cpuc, event, a7_pmu_event_affinity); +} + static int m1_pmu_get_event_idx(struct pmu_hw_events *cpuc, struct perf_event *event) { @@ -545,6 +708,11 @@ static void __m1_pmu_set_mode(u8 mode) isb(); } +static void a7_pmu_start(struct arm_pmu *cpu_pmu) +{ + __m1_pmu_set_mode(PMCR0_IMODE_AIC); +} + static void m1_pmu_start(struct arm_pmu *cpu_pmu) { __m1_pmu_set_mode(PMCR0_IMODE_FIQ); @@ -579,6 +747,11 @@ static int apple_pmu_map_event_63(struct perf_event *event, return armpmu_map_event(event, perf_map, NULL, M1_PMU_CFG_EVENT); } +static int a7_pmu_map_event(struct perf_event *event) +{ + return apple_pmu_map_event_47(event, &a7_pmu_perf_map); +} + static int m1_pmu_map_event(struct perf_event *event) { return apple_pmu_map_event_47(event, &m1_pmu_perf_map); @@ -624,6 +797,11 @@ static void apple_pmu_reset(void *info, u32 counters) isb(); } +static void a7_pmu_reset(void *info) +{ + apple_pmu_reset(info, A7_PMU_NR_COUNTERS); +} + static void m1_pmu_reset(void *info) { apple_pmu_reset(info, M1_PMU_NR_COUNTERS); @@ -674,6 +852,17 @@ static int apple_pmu_init(struct arm_pmu *cpu_pmu, u32 counters) } /* Device driver gunk */ +static int a7_pmu_cyclone_init(struct arm_pmu *cpu_pmu) +{ + cpu_pmu->name = "apple_cyclone_pmu"; + cpu_pmu->get_event_idx = a7_pmu_get_event_idx; + cpu_pmu->map_event = a7_pmu_map_event; + cpu_pmu->reset = a7_pmu_reset; + cpu_pmu->start = a7_pmu_start; + cpu_pmu->attr_groups[ARMPMU_ATTR_GROUP_EVENTS] = &a7_pmu_events_attr_group; + return apple_pmu_init(cpu_pmu, A7_PMU_NR_COUNTERS); +} + static int m1_pmu_ice_init(struct arm_pmu *cpu_pmu) { cpu_pmu->name = "apple_icestorm_pmu"; @@ -723,6 +912,7 @@ static const struct of_device_id m1_pmu_of_device_ids[] = { { .compatible = "apple,blizzard-pmu", .data = m2_pmu_blizzard_init, }, { .compatible = "apple,icestorm-pmu", .data = m1_pmu_ice_init, }, { .compatible = "apple,firestorm-pmu", .data = m1_pmu_fire_init, }, + { .compatible = "apple,cyclone-pmu", .data = a7_pmu_cyclone_init, }, { }, }; MODULE_DEVICE_TABLE(of, m1_pmu_of_device_ids); From patchwork Mon Apr 7 04:45:18 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Nick Chan X-Patchwork-Id: 14039705 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id E3C38C36010 for ; Mon, 7 Apr 2025 05:04:09 +0000 (UTC) DKIM-Signature: v=1; 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a=openpgp; fpr=4B5278785C97ACF79C3C688301CA08B7A6C50824 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20250406_214635_224914_DBC8BA2F X-CRM114-Status: GOOD ( 13.96 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org Add support for the CPU PMU found on the Apple A8, A8X SoCs. Signed-off-by: Nick Chan --- drivers/perf/apple_m1_cpu_pmu.c | 124 ++++++++++++++++++++++++++++++++++++++++ 1 file changed, 124 insertions(+) diff --git a/drivers/perf/apple_m1_cpu_pmu.c b/drivers/perf/apple_m1_cpu_pmu.c index 3c03d0e99ddaf90605cb8dafa68ab8770d371a05..5739a85f3ae07c52f4ce91c4eda3e4bcdf91015d 100644 --- a/drivers/perf/apple_m1_cpu_pmu.c +++ b/drivers/perf/apple_m1_cpu_pmu.c @@ -28,6 +28,7 @@ #define ANY_BUT_0_1 GENMASK(9, 2) #define ONLY_2_TO_7 GENMASK(7, 2) #define ONLY_2_4_6 (BIT(2) | BIT(4) | BIT(6)) +#define ONLY_3_5_7 (BIT(3) | BIT(5) | BIT(7)) #define ONLY_5_6_7 (BIT(5) | BIT(6) | BIT(7)) /* @@ -183,6 +184,111 @@ static const u16 a7_pmu_event_affinity[A7_PMU_PERFCTR_LAST + 1] = { [A7_PMU_PERFCTR_UNKNOWN_fd] = ONLY_2_4_6, }; +enum a8_pmu_events { + A8_PMU_PERFCTR_UNKNOWN_1 = 0x1, + A8_PMU_PERFCTR_CORE_ACTIVE_CYCLE = 0x2, + A8_PMU_PERFCTR_L2_TLB_MISS_INSTRUCTION = 0xa, + A8_PMU_PERFCTR_L2_TLB_MISS_DATA = 0xb, + A8_PMU_PERFCTR_BIU_UPSTREAM_CYCLE = 0x13, + A8_PMU_PERFCTR_BIU_DOWNSTREAM_CYCLE = 0x14, + A8_PMU_PERFCTR_L2C_AGENT_LD = 0x1a, + A8_PMU_PERFCTR_L2C_AGENT_LD_MISS = 0x1b, + A8_PMU_PERFCTR_L2C_AGENT_ST = 0x1c, + A8_PMU_PERFCTR_L2C_AGENT_ST_MISS = 0x1d, + A8_PMU_PERFCTR_SCHEDULE_UOP = 0x52, + A8_PMU_PERFCTR_MAP_REWIND = 0x75, + A8_PMU_PERFCTR_MAP_STALL = 0x76, + A8_PMU_PERFCTR_MAP_INT_UOP = 0x7b, + A8_PMU_PERFCTR_MAP_LDST_UOP = 0x7c, + A8_PMU_PERFCTR_MAP_SIMD_UOP = 0x7d, + A8_PMU_PERFCTR_FLUSH_RESTART_OTHER_NONSPEC = 0x84, + A8_PMU_PERFCTR_INST_A32 = 0x8a, + A8_PMU_PERFCTR_INST_T32 = 0x8b, + A8_PMU_PERFCTR_INST_ALL = 0x8c, + A8_PMU_PERFCTR_INST_BRANCH = 0x8d, + A8_PMU_PERFCTR_INST_BRANCH_CALL = 0x8e, + A8_PMU_PERFCTR_INST_BRANCH_RET = 0x8f, + A8_PMU_PERFCTR_INST_BRANCH_TAKEN = 0x90, + A8_PMU_PERFCTR_INST_BRANCH_INDIR = 0x93, + A8_PMU_PERFCTR_INST_BRANCH_COND = 0x94, + A8_PMU_PERFCTR_INST_INT_LD = 0x95, + A8_PMU_PERFCTR_INST_INT_ST = 0x96, + A8_PMU_PERFCTR_INST_INT_ALU = 0x97, + A8_PMU_PERFCTR_INST_SIMD_LD = 0x98, + A8_PMU_PERFCTR_INST_SIMD_ST = 0x99, + A8_PMU_PERFCTR_INST_SIMD_ALU = 0x9a, + A8_PMU_PERFCTR_INST_LDST = 0x9b, + A8_PMU_PERFCTR_UNKNOWN_9c = 0x9c, + A8_PMU_PERFCTR_UNKNOWN_9f = 0x9f, + A8_PMU_PERFCTR_L1D_TLB_ACCESS = 0xa0, + A8_PMU_PERFCTR_L1D_TLB_MISS = 0xa1, + A8_PMU_PERFCTR_L1D_CACHE_MISS_ST = 0xa2, + A8_PMU_PERFCTR_L1D_CACHE_MISS_LD = 0xa3, + A8_PMU_PERFCTR_LD_UNIT_UOP = 0xa6, + A8_PMU_PERFCTR_ST_UNIT_UOP = 0xa7, + A8_PMU_PERFCTR_L1D_CACHE_WRITEBACK = 0xa8, + A8_PMU_PERFCTR_LDST_X64_UOP = 0xb1, + A8_PMU_PERFCTR_L1D_CACHE_MISS_LD_NONSPEC = 0xbf, + A8_PMU_PERFCTR_L1D_CACHE_MISS_ST_NONSPEC = 0xc0, + A8_PMU_PERFCTR_L1D_TLB_MISS_NONSPEC = 0xc1, + A8_PMU_PERFCTR_ST_MEMORY_ORDER_VIOLATION_NONSPEC = 0xc4, + A8_PMU_PERFCTR_BRANCH_COND_MISPRED_NONSPEC = 0xc5, + A8_PMU_PERFCTR_BRANCH_INDIR_MISPRED_NONSPEC = 0xc6, + A8_PMU_PERFCTR_BRANCH_RET_INDIR_MISPRED_NONSPEC = 0xc8, + A8_PMU_PERFCTR_BRANCH_CALL_INDIR_MISPRED_NONSPEC = 0xca, + A8_PMU_PERFCTR_BRANCH_MISPRED_NONSPEC = 0xcb, + A8_PMU_PERFCTR_FED_IC_MISS_DEMAND = 0xd3, + A8_PMU_PERFCTR_L1I_TLB_MISS_DEMAND = 0xd4, + A8_PMU_PERFCTR_FETCH_RESTART = 0xde, + A8_PMU_PERFCTR_UNKNOWN_f5 = 0xf5, + A8_PMU_PERFCTR_UNKNOWN_f6 = 0xf6, + A8_PMU_PERFCTR_UNKNOWN_f7 = 0xf7, + A8_PMU_PERFCTR_LAST = M1_PMU_CFG_EVENT, + + /* + * From this point onwards, these are not actual HW events, + * but attributes that get stored in hw->config_base. + */ + A8_PMU_CFG_COUNT_USER = BIT(8), + A8_PMU_CFG_COUNT_KERNEL = BIT(9), +}; + +static const u16 a8_pmu_event_affinity[A8_PMU_PERFCTR_LAST + 1] = { + [0 ... A8_PMU_PERFCTR_LAST] = ANY_BUT_0_1, + [A8_PMU_PERFCTR_UNKNOWN_1] = ONLY_5_6_7, + [A8_PMU_PERFCTR_CORE_ACTIVE_CYCLE] = ANY_BUT_0_1 | BIT(0), + [A8_PMU_PERFCTR_INST_A32] = ONLY_5_6_7, + [A8_PMU_PERFCTR_INST_T32] = ONLY_5_6_7, + [A8_PMU_PERFCTR_INST_ALL] = BIT(7) | BIT(1), + [A8_PMU_PERFCTR_INST_BRANCH] = ONLY_5_6_7, + [A8_PMU_PERFCTR_INST_BRANCH_CALL] = ONLY_5_6_7, + [A8_PMU_PERFCTR_INST_BRANCH_RET] = ONLY_5_6_7, + [A8_PMU_PERFCTR_INST_BRANCH_TAKEN] = ONLY_5_6_7, + [A8_PMU_PERFCTR_INST_BRANCH_INDIR] = ONLY_5_6_7, + [A8_PMU_PERFCTR_INST_BRANCH_COND] = ONLY_5_6_7, + [A8_PMU_PERFCTR_INST_INT_LD] = ONLY_5_6_7, + [A8_PMU_PERFCTR_INST_INT_ST] = ONLY_5_6_7, + [A8_PMU_PERFCTR_INST_INT_ALU] = ONLY_5_6_7, + [A8_PMU_PERFCTR_INST_SIMD_LD] = ONLY_5_6_7, + [A8_PMU_PERFCTR_INST_SIMD_ST] = ONLY_5_6_7, + [A8_PMU_PERFCTR_INST_SIMD_ALU] = ONLY_5_6_7, + [A8_PMU_PERFCTR_INST_LDST] = ONLY_5_6_7, + [A8_PMU_PERFCTR_UNKNOWN_9c] = ONLY_5_6_7, + [A8_PMU_PERFCTR_UNKNOWN_9f] = ONLY_5_6_7, + [A8_PMU_PERFCTR_L1D_CACHE_MISS_LD_NONSPEC] = ONLY_5_6_7, + [A8_PMU_PERFCTR_L1D_CACHE_MISS_ST_NONSPEC] = ONLY_5_6_7, + [A8_PMU_PERFCTR_L1D_TLB_MISS_NONSPEC] = ONLY_5_6_7, + [A8_PMU_PERFCTR_ST_MEMORY_ORDER_VIOLATION_NONSPEC] = ONLY_5_6_7, + [A8_PMU_PERFCTR_BRANCH_COND_MISPRED_NONSPEC] = ONLY_5_6_7, + [A8_PMU_PERFCTR_BRANCH_INDIR_MISPRED_NONSPEC] = ONLY_5_6_7, + [A8_PMU_PERFCTR_BRANCH_RET_INDIR_MISPRED_NONSPEC] = ONLY_5_6_7, + [A8_PMU_PERFCTR_BRANCH_CALL_INDIR_MISPRED_NONSPEC] = ONLY_5_6_7, + [A8_PMU_PERFCTR_BRANCH_MISPRED_NONSPEC] = ONLY_5_6_7, + [A8_PMU_PERFCTR_UNKNOWN_f5] = ANY_BUT_0_1, + [A8_PMU_PERFCTR_UNKNOWN_f6] = ONLY_3_5_7, + [A8_PMU_PERFCTR_UNKNOWN_f7] = ONLY_3_5_7, +}; + enum m1_pmu_events { M1_PMU_PERFCTR_RETIRE_UOP = 0x1, M1_PMU_PERFCTR_CORE_ACTIVE_CYCLE = 0x2, @@ -685,6 +791,12 @@ static int a7_pmu_get_event_idx(struct pmu_hw_events *cpuc, return apple_pmu_get_event_idx(cpuc, event, a7_pmu_event_affinity); } +static int a8_pmu_get_event_idx(struct pmu_hw_events *cpuc, + struct perf_event *event) +{ + return apple_pmu_get_event_idx(cpuc, event, a8_pmu_event_affinity); +} + static int m1_pmu_get_event_idx(struct pmu_hw_events *cpuc, struct perf_event *event) { @@ -863,6 +975,17 @@ static int a7_pmu_cyclone_init(struct arm_pmu *cpu_pmu) return apple_pmu_init(cpu_pmu, A7_PMU_NR_COUNTERS); } +static int a8_pmu_typhoon_init(struct arm_pmu *cpu_pmu) +{ + cpu_pmu->name = "apple_typhoon_pmu"; + cpu_pmu->get_event_idx = a8_pmu_get_event_idx; + cpu_pmu->map_event = m1_pmu_map_event; + cpu_pmu->reset = a7_pmu_reset; + cpu_pmu->start = a7_pmu_start; + cpu_pmu->attr_groups[ARMPMU_ATTR_GROUP_EVENTS] = &m1_pmu_events_attr_group; + return apple_pmu_init(cpu_pmu, A7_PMU_NR_COUNTERS); +} + static int m1_pmu_ice_init(struct arm_pmu *cpu_pmu) { cpu_pmu->name = "apple_icestorm_pmu"; @@ -912,6 +1035,7 @@ static const struct of_device_id m1_pmu_of_device_ids[] = { { .compatible = "apple,blizzard-pmu", .data = m2_pmu_blizzard_init, }, { .compatible = "apple,icestorm-pmu", .data = m1_pmu_ice_init, }, { .compatible = "apple,firestorm-pmu", .data = m1_pmu_fire_init, }, + { .compatible = "apple,typhoon-pmu", .data = a8_pmu_typhoon_init, }, { .compatible = "apple,cyclone-pmu", .data = a7_pmu_cyclone_init, }, { }, }; From patchwork Mon Apr 7 04:45:19 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Nick Chan X-Patchwork-Id: 14039706 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id D96AAC3601A for ; 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a=openpgp; fpr=4B5278785C97ACF79C3C688301CA08B7A6C50824 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20250406_214638_430248_59C52CB3 X-CRM114-Status: GOOD ( 13.39 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org Add support for CPU PMU found in the Apple A9 and A9X SoCs. Signed-off-by: Nick Chan --- drivers/perf/apple_m1_cpu_pmu.c | 121 ++++++++++++++++++++++++++++++++++++++++ 1 file changed, 121 insertions(+) diff --git a/drivers/perf/apple_m1_cpu_pmu.c b/drivers/perf/apple_m1_cpu_pmu.c index 5739a85f3ae07c52f4ce91c4eda3e4bcdf91015d..0f59a22812a424ecd442e731a5c6b5be828be77c 100644 --- a/drivers/perf/apple_m1_cpu_pmu.c +++ b/drivers/perf/apple_m1_cpu_pmu.c @@ -289,6 +289,109 @@ static const u16 a8_pmu_event_affinity[A8_PMU_PERFCTR_LAST + 1] = { [A8_PMU_PERFCTR_UNKNOWN_f7] = ONLY_3_5_7, }; + +enum a9_pmu_events { + A9_PMU_PERFCTR_UNKNOWN_1 = 0x1, + A9_PMU_PERFCTR_CORE_ACTIVE_CYCLE = 0x2, + A9_PMU_PERFCTR_L2_TLB_MISS_INSTRUCTION = 0xa, + A9_PMU_PERFCTR_L2_TLB_MISS_DATA = 0xb, + A9_PMU_PERFCTR_L2C_AGENT_LD = 0x1a, + A9_PMU_PERFCTR_L2C_AGENT_LD_MISS = 0x1b, + A9_PMU_PERFCTR_L2C_AGENT_ST = 0x1c, + A9_PMU_PERFCTR_L2C_AGENT_ST_MISS = 0x1d, + A9_PMU_PERFCTR_SCHEDULE_UOP = 0x52, + A9_PMU_PERFCTR_MAP_REWIND = 0x75, + A9_PMU_PERFCTR_MAP_STALL = 0x76, + A9_PMU_PERFCTR_MAP_INT_UOP = 0x7c, + A9_PMU_PERFCTR_MAP_LDST_UOP = 0x7d, + A9_PMU_PERFCTR_MAP_SIMD_UOP = 0x7e, + A9_PMU_PERFCTR_FLUSH_RESTART_OTHER_NONSPEC = 0x84, + A9_PMU_PERFCTR_INST_ALL = 0x8c, + A9_PMU_PERFCTR_INST_BRANCH = 0x8d, + A9_PMU_PERFCTR_INST_BRANCH_CALL = 0x8e, + A9_PMU_PERFCTR_INST_BRANCH_RET = 0x8f, + A9_PMU_PERFCTR_INST_BRANCH_TAKEN = 0x90, + A9_PMU_PERFCTR_INST_BRANCH_INDIR = 0x93, + A9_PMU_PERFCTR_INST_BRANCH_COND = 0x94, + A9_PMU_PERFCTR_INST_INT_LD = 0x95, + A9_PMU_PERFCTR_INST_INT_ST = 0x96, + A9_PMU_PERFCTR_INST_INT_ALU = 0x97, + A9_PMU_PERFCTR_INST_SIMD_LD = 0x98, + A9_PMU_PERFCTR_INST_SIMD_ST = 0x99, + A9_PMU_PERFCTR_INST_SIMD_ALU = 0x9a, + A9_PMU_PERFCTR_INST_LDST = 0x9b, + A9_PMU_PERFCTR_INST_BARRIER = 0x9c, + A9_PMU_PERFCTR_UNKNOWN_9f = 0x9f, + A9_PMU_PERFCTR_L1D_TLB_ACCESS = 0xa0, + A9_PMU_PERFCTR_L1D_TLB_MISS = 0xa1, + A9_PMU_PERFCTR_L1D_CACHE_MISS_ST = 0xa2, + A9_PMU_PERFCTR_L1D_CACHE_MISS_LD = 0xa3, + A9_PMU_PERFCTR_LD_UNIT_UOP = 0xa6, + A9_PMU_PERFCTR_ST_UNIT_UOP = 0xa7, + A9_PMU_PERFCTR_L1D_CACHE_WRITEBACK = 0xa8, + A9_PMU_PERFCTR_LDST_X64_UOP = 0xb1, + A9_PMU_PERFCTR_ATOMIC_OR_EXCLUSIVE_SUCC = 0xb3, + A9_PMU_PERFCTR_ATOMIC_OR_EXCLUSIVE_FAIL = 0xb4, + A9_PMU_PERFCTR_L1D_CACHE_MISS_LD_NONSPEC = 0xbf, + A9_PMU_PERFCTR_L1D_CACHE_MISS_ST_NONSPEC = 0xc0, + A9_PMU_PERFCTR_L1D_TLB_MISS_NONSPEC = 0xc1, + A9_PMU_PERFCTR_ST_MEMORY_ORDER_VIOLATION_NONSPEC = 0xc4, + A9_PMU_PERFCTR_BRANCH_COND_MISPRED_NONSPEC = 0xc5, + A9_PMU_PERFCTR_BRANCH_INDIR_MISPRED_NONSPEC = 0xc6, + A9_PMU_PERFCTR_BRANCH_RET_INDIR_MISPRED_NONSPEC = 0xc8, + A9_PMU_PERFCTR_BRANCH_CALL_INDIR_MISPRED_NONSPEC = 0xca, + A9_PMU_PERFCTR_BRANCH_MISPRED_NONSPEC = 0xcb, + A9_PMU_PERFCTR_FED_IC_MISS_DEMAND = 0xd3, + A9_PMU_PERFCTR_L1I_TLB_MISS_DEMAND = 0xd4, + A9_PMU_PERFCTR_MAP_DISPATCH_BUBBLE = 0xd6, + A9_PMU_PERFCTR_FETCH_RESTART = 0xde, + A9_PMU_PERFCTR_ST_NT_UOP = 0xe5, + A9_PMU_PERFCTR_LD_NT_UOP = 0xe6, + A9_PMU_PERFCTR_UNKNOWN_f6 = 0xf6, + A9_PMU_PERFCTR_UNKNOWN_f7 = 0xf7, + A9_PMU_PERFCTR_LAST = M1_PMU_CFG_EVENT, + + /* + * From this point onwards, these are not actual HW events, + * but attributes that get stored in hw->config_base. + */ + A9_PMU_CFG_COUNT_USER = BIT(8), + A9_PMU_CFG_COUNT_KERNEL = BIT(9), +}; + +static const u16 a9_pmu_event_affinity[A9_PMU_PERFCTR_LAST + 1] = { + [0 ... A9_PMU_PERFCTR_LAST] = ANY_BUT_0_1, + [A9_PMU_PERFCTR_UNKNOWN_1] = BIT(7), + [A9_PMU_PERFCTR_CORE_ACTIVE_CYCLE] = ANY_BUT_0_1 | BIT(0), + [A9_PMU_PERFCTR_INST_ALL] = BIT(7) | BIT(1), + [A9_PMU_PERFCTR_INST_BRANCH] = ONLY_5_6_7, + [A9_PMU_PERFCTR_INST_BRANCH_CALL] = ONLY_5_6_7, + [A9_PMU_PERFCTR_INST_BRANCH_RET] = ONLY_5_6_7, + [A9_PMU_PERFCTR_INST_BRANCH_TAKEN] = ONLY_5_6_7, + [A9_PMU_PERFCTR_INST_BRANCH_INDIR] = ONLY_5_6_7, + [A9_PMU_PERFCTR_INST_BRANCH_COND] = ONLY_5_6_7, + [A9_PMU_PERFCTR_INST_INT_LD] = ONLY_5_6_7, + [A9_PMU_PERFCTR_INST_INT_ST] = ONLY_5_6_7, + [A9_PMU_PERFCTR_INST_INT_ALU] = BIT(7), + [A9_PMU_PERFCTR_INST_SIMD_LD] = ONLY_5_6_7, + [A9_PMU_PERFCTR_INST_SIMD_ST] = ONLY_5_6_7, + [A9_PMU_PERFCTR_INST_SIMD_ALU] = BIT(7), + [A9_PMU_PERFCTR_INST_LDST] = ONLY_5_6_7, + [A9_PMU_PERFCTR_INST_BARRIER] = ONLY_5_6_7, + [A9_PMU_PERFCTR_UNKNOWN_9f] = BIT(7), + [A9_PMU_PERFCTR_L1D_CACHE_MISS_LD_NONSPEC] = ONLY_5_6_7, + [A9_PMU_PERFCTR_L1D_CACHE_MISS_ST_NONSPEC] = ONLY_5_6_7, + [A9_PMU_PERFCTR_L1D_TLB_MISS_NONSPEC] = ONLY_5_6_7, + [A9_PMU_PERFCTR_ST_MEMORY_ORDER_VIOLATION_NONSPEC] = ONLY_5_6_7, + [A9_PMU_PERFCTR_BRANCH_COND_MISPRED_NONSPEC] = ONLY_5_6_7, + [A9_PMU_PERFCTR_BRANCH_INDIR_MISPRED_NONSPEC] = ONLY_5_6_7, + [A9_PMU_PERFCTR_BRANCH_RET_INDIR_MISPRED_NONSPEC] = ONLY_5_6_7, + [A9_PMU_PERFCTR_BRANCH_CALL_INDIR_MISPRED_NONSPEC] = ONLY_5_6_7, + [A9_PMU_PERFCTR_BRANCH_MISPRED_NONSPEC] = ONLY_5_6_7, + [A9_PMU_PERFCTR_UNKNOWN_f6] = ONLY_3_5_7, + [A9_PMU_PERFCTR_UNKNOWN_f7] = ONLY_3_5_7, +}; + enum m1_pmu_events { M1_PMU_PERFCTR_RETIRE_UOP = 0x1, M1_PMU_PERFCTR_CORE_ACTIVE_CYCLE = 0x2, @@ -797,6 +900,12 @@ static int a8_pmu_get_event_idx(struct pmu_hw_events *cpuc, return apple_pmu_get_event_idx(cpuc, event, a8_pmu_event_affinity); } +static int a9_pmu_get_event_idx(struct pmu_hw_events *cpuc, + struct perf_event *event) +{ + return apple_pmu_get_event_idx(cpuc, event, a9_pmu_event_affinity); +} + static int m1_pmu_get_event_idx(struct pmu_hw_events *cpuc, struct perf_event *event) { @@ -986,6 +1095,17 @@ static int a8_pmu_typhoon_init(struct arm_pmu *cpu_pmu) return apple_pmu_init(cpu_pmu, A7_PMU_NR_COUNTERS); } +static int a9_pmu_twister_init(struct arm_pmu *cpu_pmu) +{ + cpu_pmu->name = "apple_twister_pmu"; + cpu_pmu->get_event_idx = a9_pmu_get_event_idx; + cpu_pmu->map_event = m1_pmu_map_event; + cpu_pmu->reset = a7_pmu_reset; + cpu_pmu->start = a7_pmu_start; + cpu_pmu->attr_groups[ARMPMU_ATTR_GROUP_EVENTS] = &m1_pmu_events_attr_group; + return apple_pmu_init(cpu_pmu, A7_PMU_NR_COUNTERS); +} + static int m1_pmu_ice_init(struct arm_pmu *cpu_pmu) { cpu_pmu->name = "apple_icestorm_pmu"; @@ -1035,6 +1155,7 @@ static const struct of_device_id m1_pmu_of_device_ids[] = { { .compatible = "apple,blizzard-pmu", .data = m2_pmu_blizzard_init, }, { .compatible = "apple,icestorm-pmu", .data = m1_pmu_ice_init, }, { .compatible = "apple,firestorm-pmu", .data = m1_pmu_fire_init, }, + { .compatible = "apple,twister-pmu", .data = a9_pmu_twister_init, }, { .compatible = "apple,typhoon-pmu", .data = a8_pmu_typhoon_init, }, { .compatible = "apple,cyclone-pmu", .data = a7_pmu_cyclone_init, }, { }, From patchwork Mon Apr 7 04:45:20 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Nick Chan X-Patchwork-Id: 14039707 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 5F14BC36010 for ; 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Sun, 06 Apr 2025 21:46:40 -0700 (PDT) Received: from [127.0.1.1] ([59.188.211.160]) by smtp.googlemail.com with ESMTPSA id 98e67ed59e1d1-305983b9954sm7765810a91.32.2025.04.06.21.46.37 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 06 Apr 2025 21:46:40 -0700 (PDT) From: Nick Chan Date: Mon, 07 Apr 2025 12:45:20 +0800 Subject: [PATCH v6 11/21] drivers/perf: apple_m1: Add Apple A10/A10X/T2 Support MIME-Version: 1.0 Message-Id: <20250407-apple-cpmu-v6-11-ae8c2f225c1f@gmail.com> References: <20250407-apple-cpmu-v6-0-ae8c2f225c1f@gmail.com> In-Reply-To: <20250407-apple-cpmu-v6-0-ae8c2f225c1f@gmail.com> To: Will Deacon , Mark Rutland , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Catalin Marinas , Sven Peter , Janne Grunau , Alyssa Rosenzweig , Neal Gompa Cc: Marc Zyngier , linux-arm-kernel@lists.infradead.org, linux-perf-users@vger.kernel.org, devicetree@vger.kernel.org, asahi@lists.linux.dev, linux-kernel@vger.kernel.org, Nick Chan X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; 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a=openpgp; fpr=4B5278785C97ACF79C3C688301CA08B7A6C50824 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20250406_214641_743816_D39A568D X-CRM114-Status: GOOD ( 13.24 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org Add support for the CPU PMU found in the Apple A10, A10X, T2 SoCs. Signed-off-by: Nick Chan --- drivers/perf/apple_m1_cpu_pmu.c | 127 ++++++++++++++++++++++++++++++++++++++++ 1 file changed, 127 insertions(+) diff --git a/drivers/perf/apple_m1_cpu_pmu.c b/drivers/perf/apple_m1_cpu_pmu.c index 0f59a22812a424ecd442e731a5c6b5be828be77c..4f65ca4ea24157bced11d42a4cbbad5f2dd23d4a 100644 --- a/drivers/perf/apple_m1_cpu_pmu.c +++ b/drivers/perf/apple_m1_cpu_pmu.c @@ -392,6 +392,115 @@ static const u16 a9_pmu_event_affinity[A9_PMU_PERFCTR_LAST + 1] = { [A9_PMU_PERFCTR_UNKNOWN_f7] = ONLY_3_5_7, }; +enum a10_pmu_events { + A10_PMU_PERFCTR_RETIRE_UOP = 0x1, + A10_PMU_PERFCTR_CORE_ACTIVE_CYCLE = 0x2, + A10_PMU_PERFCTR_L2_TLB_MISS_INSTRUCTION = 0xa, + A10_PMU_PERFCTR_L2_TLB_MISS_DATA = 0xb, + A10_PMU_PERFCTR_L2C_AGENT_LD = 0x1a, + A10_PMU_PERFCTR_L2C_AGENT_LD_MISS = 0x1b, + A10_PMU_PERFCTR_L2C_AGENT_ST = 0x1c, + A10_PMU_PERFCTR_L2C_AGENT_ST_MISS = 0x1d, + A10_PMU_PERFCTR_SCHEDULE_UOP = 0x52, + A10_PMU_PERFCTR_MAP_REWIND = 0x75, + A10_PMU_PERFCTR_MAP_STALL = 0x76, + A10_PMU_PERFCTR_MAP_INT_UOP = 0x7c, + A10_PMU_PERFCTR_MAP_LDST_UOP = 0x7d, + A10_PMU_PERFCTR_MAP_SIMD_UOP = 0x7e, + A10_PMU_PERFCTR_FLUSH_RESTART_OTHER_NONSPEC = 0x84, + A10_PMU_PERFCTR_INST_ALL = 0x8c, + A10_PMU_PERFCTR_INST_BRANCH = 0x8d, + A10_PMU_PERFCTR_INST_BRANCH_CALL = 0x8e, + A10_PMU_PERFCTR_INST_BRANCH_RET = 0x8f, + A10_PMU_PERFCTR_INST_BRANCH_TAKEN = 0x90, + A10_PMU_PERFCTR_INST_BRANCH_INDIR = 0x93, + A10_PMU_PERFCTR_INST_BRANCH_COND = 0x94, + A10_PMU_PERFCTR_INST_INT_LD = 0x95, + A10_PMU_PERFCTR_INST_INT_ST = 0x96, + A10_PMU_PERFCTR_INST_INT_ALU = 0x97, + A10_PMU_PERFCTR_INST_SIMD_LD = 0x98, + A10_PMU_PERFCTR_INST_SIMD_ST = 0x99, + A10_PMU_PERFCTR_INST_SIMD_ALU = 0x9a, + A10_PMU_PERFCTR_INST_LDST = 0x9b, + A10_PMU_PERFCTR_INST_BARRIER = 0x9c, + A10_PMU_PERFCTR_UNKNOWN_9f = 0x9f, + A10_PMU_PERFCTR_L1D_TLB_ACCESS = 0xa0, + A10_PMU_PERFCTR_L1D_TLB_MISS = 0xa1, + A10_PMU_PERFCTR_L1D_CACHE_MISS_ST = 0xa2, + A10_PMU_PERFCTR_L1D_CACHE_MISS_LD = 0xa3, + A10_PMU_PERFCTR_LD_UNIT_UOP = 0xa6, + A10_PMU_PERFCTR_ST_UNIT_UOP = 0xa7, + A10_PMU_PERFCTR_L1D_CACHE_WRITEBACK = 0xa8, + A10_PMU_PERFCTR_LDST_X64_UOP = 0xb1, + A10_PMU_PERFCTR_ATOMIC_OR_EXCLUSIVE_SUCC = 0xb3, + A10_PMU_PERFCTR_ATOMIC_OR_EXCLUSIVE_FAIL = 0xb4, + A10_PMU_PERFCTR_L1D_CACHE_MISS_LD_NONSPEC = 0xbf, + A10_PMU_PERFCTR_L1D_CACHE_MISS_ST_NONSPEC = 0xc0, + A10_PMU_PERFCTR_L1D_TLB_MISS_NONSPEC = 0xc1, + A10_PMU_PERFCTR_ST_MEMORY_ORDER_VIOLATION_NONSPEC = 0xc4, + A10_PMU_PERFCTR_BRANCH_COND_MISPRED_NONSPEC = 0xc5, + A10_PMU_PERFCTR_BRANCH_INDIR_MISPRED_NONSPEC = 0xc6, + A10_PMU_PERFCTR_BRANCH_RET_INDIR_MISPRED_NONSPEC = 0xc8, + A10_PMU_PERFCTR_BRANCH_CALL_INDIR_MISPRED_NONSPEC = 0xca, + A10_PMU_PERFCTR_BRANCH_MISPRED_NONSPEC = 0xcb, + A10_PMU_PERFCTR_FED_IC_MISS_DEMAND = 0xd3, + A10_PMU_PERFCTR_L1I_TLB_MISS_DEMAND = 0xd4, + A10_PMU_PERFCTR_MAP_DISPATCH_BUBBLE = 0xd6, + A10_PMU_PERFCTR_L1I_CACHE_MISS_DEMAND = 0xdb, + A10_PMU_PERFCTR_FETCH_RESTART = 0xde, + A10_PMU_PERFCTR_ST_NT_UOP = 0xe5, + A10_PMU_PERFCTR_LD_NT_UOP = 0xe6, + A10_PMU_PERFCTR_UNKNOWN_f5 = 0xf5, + A10_PMU_PERFCTR_UNKNOWN_f6 = 0xf6, + A10_PMU_PERFCTR_UNKNOWN_f7 = 0xf7, + A10_PMU_PERFCTR_UNKNOWN_f8 = 0xf8, + A10_PMU_PERFCTR_UNKNOWN_fd = 0xfd, + A10_PMU_PERFCTR_LAST = M1_PMU_CFG_EVENT, + + /* + * From this point onwards, these are not actual HW events, + * but attributes that get stored in hw->config_base. + */ + A10_PMU_CFG_COUNT_USER = BIT(8), + A10_PMU_CFG_COUNT_KERNEL = BIT(9), +}; + +static const u16 a10_pmu_event_affinity[A10_PMU_PERFCTR_LAST + 1] = { + [0 ... A10_PMU_PERFCTR_LAST] = ANY_BUT_0_1, + [A10_PMU_PERFCTR_RETIRE_UOP] = BIT(7), + [A10_PMU_PERFCTR_CORE_ACTIVE_CYCLE] = ANY_BUT_0_1 | BIT(0), + [A10_PMU_PERFCTR_INST_ALL] = BIT(7) | BIT(1), + [A10_PMU_PERFCTR_INST_BRANCH] = ONLY_5_6_7, + [A10_PMU_PERFCTR_INST_BRANCH_CALL] = ONLY_5_6_7, + [A10_PMU_PERFCTR_INST_BRANCH_RET] = ONLY_5_6_7, + [A10_PMU_PERFCTR_INST_BRANCH_TAKEN] = ONLY_5_6_7, + [A10_PMU_PERFCTR_INST_BRANCH_INDIR] = ONLY_5_6_7, + [A10_PMU_PERFCTR_INST_BRANCH_COND] = ONLY_5_6_7, + [A10_PMU_PERFCTR_INST_INT_LD] = ONLY_5_6_7, + [A10_PMU_PERFCTR_INST_INT_ST] = ONLY_5_6_7, + [A10_PMU_PERFCTR_INST_INT_ALU] = BIT(7), + [A10_PMU_PERFCTR_INST_SIMD_LD] = ONLY_5_6_7, + [A10_PMU_PERFCTR_INST_SIMD_ST] = ONLY_5_6_7, + [A10_PMU_PERFCTR_INST_SIMD_ALU] = BIT(7), + [A10_PMU_PERFCTR_INST_LDST] = ONLY_5_6_7, + [A10_PMU_PERFCTR_INST_BARRIER] = ONLY_5_6_7, + [A10_PMU_PERFCTR_UNKNOWN_9f] = BIT(7), + [A10_PMU_PERFCTR_L1D_CACHE_MISS_LD_NONSPEC] = ONLY_5_6_7, + [A10_PMU_PERFCTR_L1D_CACHE_MISS_ST_NONSPEC] = ONLY_5_6_7, + [A10_PMU_PERFCTR_L1D_TLB_MISS_NONSPEC] = ONLY_5_6_7, + [A10_PMU_PERFCTR_ST_MEMORY_ORDER_VIOLATION_NONSPEC] = ONLY_5_6_7, + [A10_PMU_PERFCTR_BRANCH_COND_MISPRED_NONSPEC] = ONLY_5_6_7, + [A10_PMU_PERFCTR_BRANCH_INDIR_MISPRED_NONSPEC] = ONLY_5_6_7, + [A10_PMU_PERFCTR_BRANCH_RET_INDIR_MISPRED_NONSPEC] = ONLY_5_6_7, + [A10_PMU_PERFCTR_BRANCH_CALL_INDIR_MISPRED_NONSPEC] = ONLY_5_6_7, + [A10_PMU_PERFCTR_BRANCH_MISPRED_NONSPEC] = ONLY_5_6_7, + [A10_PMU_PERFCTR_UNKNOWN_f5] = ONLY_2_4_6, + [A10_PMU_PERFCTR_UNKNOWN_f6] = ONLY_2_4_6, + [A10_PMU_PERFCTR_UNKNOWN_f7] = ONLY_2_4_6, + [A10_PMU_PERFCTR_UNKNOWN_f8] = ONLY_2_TO_7, + [A10_PMU_PERFCTR_UNKNOWN_fd] = ONLY_2_4_6, +}; + enum m1_pmu_events { M1_PMU_PERFCTR_RETIRE_UOP = 0x1, M1_PMU_PERFCTR_CORE_ACTIVE_CYCLE = 0x2, @@ -906,6 +1015,12 @@ static int a9_pmu_get_event_idx(struct pmu_hw_events *cpuc, return apple_pmu_get_event_idx(cpuc, event, a9_pmu_event_affinity); } +static int a10_pmu_get_event_idx(struct pmu_hw_events *cpuc, + struct perf_event *event) +{ + return apple_pmu_get_event_idx(cpuc, event, a10_pmu_event_affinity); +} + static int m1_pmu_get_event_idx(struct pmu_hw_events *cpuc, struct perf_event *event) { @@ -1106,6 +1221,17 @@ static int a9_pmu_twister_init(struct arm_pmu *cpu_pmu) return apple_pmu_init(cpu_pmu, A7_PMU_NR_COUNTERS); } +static int a10_pmu_fusion_init(struct arm_pmu *cpu_pmu) +{ + cpu_pmu->name = "apple_fusion_pmu"; + cpu_pmu->get_event_idx = a10_pmu_get_event_idx; + cpu_pmu->map_event = m1_pmu_map_event; + cpu_pmu->reset = m1_pmu_reset; + cpu_pmu->start = a7_pmu_start; + cpu_pmu->attr_groups[ARMPMU_ATTR_GROUP_EVENTS] = &m1_pmu_events_attr_group; + return apple_pmu_init(cpu_pmu, M1_PMU_NR_COUNTERS); +} + static int m1_pmu_ice_init(struct arm_pmu *cpu_pmu) { cpu_pmu->name = "apple_icestorm_pmu"; @@ -1155,6 +1281,7 @@ static const struct of_device_id m1_pmu_of_device_ids[] = { { .compatible = "apple,blizzard-pmu", .data = m2_pmu_blizzard_init, }, { .compatible = "apple,icestorm-pmu", .data = m1_pmu_ice_init, }, { .compatible = "apple,firestorm-pmu", .data = m1_pmu_fire_init, }, + { .compatible = "apple,fusion-pmu", .data = a10_pmu_fusion_init, }, { .compatible = "apple,twister-pmu", .data = a9_pmu_twister_init, }, { .compatible = "apple,typhoon-pmu", .data = a8_pmu_typhoon_init, }, { .compatible = "apple,cyclone-pmu", .data = a7_pmu_cyclone_init, }, From patchwork Mon Apr 7 04:45:21 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Nick Chan X-Patchwork-Id: 14039708 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id EBB49C36010 for ; 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Sun, 06 Apr 2025 21:46:44 -0700 (PDT) Received: from [127.0.1.1] ([59.188.211.160]) by smtp.googlemail.com with ESMTPSA id 98e67ed59e1d1-305983b9954sm7765810a91.32.2025.04.06.21.46.41 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 06 Apr 2025 21:46:43 -0700 (PDT) From: Nick Chan Date: Mon, 07 Apr 2025 12:45:21 +0800 Subject: [PATCH v6 12/21] drivers/perf: apple_m1: Add Apple A11 Support MIME-Version: 1.0 Message-Id: <20250407-apple-cpmu-v6-12-ae8c2f225c1f@gmail.com> References: <20250407-apple-cpmu-v6-0-ae8c2f225c1f@gmail.com> In-Reply-To: <20250407-apple-cpmu-v6-0-ae8c2f225c1f@gmail.com> To: Will Deacon , Mark Rutland , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Catalin Marinas , Sven Peter , Janne Grunau , Alyssa Rosenzweig , Neal Gompa Cc: Marc Zyngier , linux-arm-kernel@lists.infradead.org, linux-perf-users@vger.kernel.org, devicetree@vger.kernel.org, asahi@lists.linux.dev, linux-kernel@vger.kernel.org, Nick Chan X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; 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a=openpgp; fpr=4B5278785C97ACF79C3C688301CA08B7A6C50824 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20250406_214645_092152_F446BB32 X-CRM114-Status: GOOD ( 13.29 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org Add support for the CPU PMU found attached to the performance and efficiency cores of the Apple A11 SoCs. This PMU can deliver its interrupt via IRQ or FIQ. Use FIQ as that is faster. Signed-off-by: Nick Chan --- drivers/perf/apple_m1_cpu_pmu.c | 137 ++++++++++++++++++++++++++++++++++++++++ 1 file changed, 137 insertions(+) diff --git a/drivers/perf/apple_m1_cpu_pmu.c b/drivers/perf/apple_m1_cpu_pmu.c index 4f65ca4ea24157bced11d42a4cbbad5f2dd23d4a..365b4ecaedb180fe88f15c675c44e2f5ac916c25 100644 --- a/drivers/perf/apple_m1_cpu_pmu.c +++ b/drivers/perf/apple_m1_cpu_pmu.c @@ -501,6 +501,113 @@ static const u16 a10_pmu_event_affinity[A10_PMU_PERFCTR_LAST + 1] = { [A10_PMU_PERFCTR_UNKNOWN_fd] = ONLY_2_4_6, }; +enum a11_pmu_events { + A11_PMU_PERFCTR_RETIRE_UOP = 0x1, + A11_PMU_PERFCTR_CORE_ACTIVE_CYCLE = 0x2, + A11_PMU_PERFCTR_L2_TLB_MISS_INSTRUCTION = 0xa, + A11_PMU_PERFCTR_L2_TLB_MISS_DATA = 0xb, + A11_PMU_PERFCTR_SCHEDULE_UOP = 0x52, + A11_PMU_PERFCTR_MAP_REWIND = 0x75, + A11_PMU_PERFCTR_MAP_STALL = 0x76, + A11_PMU_PERFCTR_MAP_INT_UOP = 0x7c, + A11_PMU_PERFCTR_MAP_LDST_UOP = 0x7d, + A11_PMU_PERFCTR_MAP_SIMD_UOP = 0x7e, + A11_PMU_PERFCTR_FLUSH_RESTART_OTHER_NONSPEC = 0x84, + A11_PMU_PERFCTR_INST_A32 = 0x8a, + A11_PMU_PERFCTR_INST_T32 = 0x8b, + A11_PMU_PERFCTR_INST_ALL = 0x8c, + A11_PMU_PERFCTR_INST_BRANCH = 0x8d, + A11_PMU_PERFCTR_INST_BRANCH_CALL = 0x8e, + A11_PMU_PERFCTR_INST_BRANCH_RET = 0x8f, + A11_PMU_PERFCTR_INST_BRANCH_TAKEN = 0x90, + A11_PMU_PERFCTR_INST_BRANCH_INDIR = 0x93, + A11_PMU_PERFCTR_INST_BRANCH_COND = 0x94, + A11_PMU_PERFCTR_INST_INT_LD = 0x95, + A11_PMU_PERFCTR_INST_INT_ST = 0x96, + A11_PMU_PERFCTR_INST_INT_ALU = 0x97, + A11_PMU_PERFCTR_INST_SIMD_LD = 0x98, + A11_PMU_PERFCTR_INST_SIMD_ST = 0x99, + A11_PMU_PERFCTR_INST_SIMD_ALU = 0x9a, + A11_PMU_PERFCTR_INST_LDST = 0x9b, + A11_PMU_PERFCTR_INST_BARRIER = 0x9c, + A11_PMU_PERFCTR_UNKNOWN_9f = 0x9f, + A11_PMU_PERFCTR_L1D_TLB_ACCESS = 0xa0, + A11_PMU_PERFCTR_L1D_TLB_MISS = 0xa1, + A11_PMU_PERFCTR_L1D_CACHE_MISS_ST = 0xa2, + A11_PMU_PERFCTR_L1D_CACHE_MISS_LD = 0xa3, + A11_PMU_PERFCTR_LD_UNIT_UOP = 0xa6, + A11_PMU_PERFCTR_ST_UNIT_UOP = 0xa7, + A11_PMU_PERFCTR_L1D_CACHE_WRITEBACK = 0xa8, + A11_PMU_PERFCTR_LDST_X64_UOP = 0xb1, + A11_PMU_PERFCTR_ATOMIC_OR_EXCLUSIVE_SUCC = 0xb3, + A11_PMU_PERFCTR_ATOMIC_OR_EXCLUSIVE_FAIL = 0xb4, + A11_PMU_PERFCTR_L1D_CACHE_MISS_LD_NONSPEC = 0xbf, + A11_PMU_PERFCTR_L1D_CACHE_MISS_ST_NONSPEC = 0xc0, + A11_PMU_PERFCTR_L1D_TLB_MISS_NONSPEC = 0xc1, + A11_PMU_PERFCTR_ST_MEMORY_ORDER_VIOLATION_NONSPEC = 0xc4, + A11_PMU_PERFCTR_BRANCH_COND_MISPRED_NONSPEC = 0xc5, + A11_PMU_PERFCTR_BRANCH_INDIR_MISPRED_NONSPEC = 0xc6, + A11_PMU_PERFCTR_BRANCH_RET_INDIR_MISPRED_NONSPEC = 0xc8, + A11_PMU_PERFCTR_BRANCH_CALL_INDIR_MISPRED_NONSPEC = 0xca, + A11_PMU_PERFCTR_BRANCH_MISPRED_NONSPEC = 0xcb, + A11_PMU_PERFCTR_FED_IC_MISS_DEMAND = 0xd3, + A11_PMU_PERFCTR_L1I_TLB_MISS_DEMAND = 0xd4, + A11_PMU_PERFCTR_MAP_DISPATCH_BUBBLE = 0xd6, + A11_PMU_PERFCTR_L1I_CACHE_MISS_DEMAND = 0xdb, + A11_PMU_PERFCTR_FETCH_RESTART = 0xde, + A11_PMU_PERFCTR_ST_NT_UOP = 0xe5, + A11_PMU_PERFCTR_LD_NT_UOP = 0xe6, + A11_PMU_PERFCTR_UNKNOWN_f5 = 0xf5, + A11_PMU_PERFCTR_UNKNOWN_f6 = 0xf6, + A11_PMU_PERFCTR_UNKNOWN_f7 = 0xf7, + A11_PMU_PERFCTR_UNKNOWN_f8 = 0xf8, + A11_PMU_PERFCTR_UNKNOWN_fd = 0xfd, + A11_PMU_PERFCTR_LAST = M1_PMU_CFG_EVENT, + + /* + * From this point onwards, these are not actual HW events, + * but attributes that get stored in hw->config_base. + */ + A11_PMU_CFG_COUNT_USER = BIT(8), + A11_PMU_CFG_COUNT_KERNEL = BIT(9), +}; + +static const u16 a11_pmu_event_affinity[A11_PMU_PERFCTR_LAST + 1] = { + [0 ... A11_PMU_PERFCTR_LAST] = ANY_BUT_0_1, + [A11_PMU_PERFCTR_RETIRE_UOP] = BIT(7), + [A11_PMU_PERFCTR_CORE_ACTIVE_CYCLE] = ANY_BUT_0_1 | BIT(0), + [A11_PMU_PERFCTR_INST_ALL] = BIT(7) | BIT(1), + [A11_PMU_PERFCTR_INST_BRANCH] = ONLY_5_6_7, + [A11_PMU_PERFCTR_INST_BRANCH_CALL] = ONLY_5_6_7, + [A11_PMU_PERFCTR_INST_BRANCH_RET] = ONLY_5_6_7, + [A11_PMU_PERFCTR_INST_BRANCH_TAKEN] = ONLY_5_6_7, + [A11_PMU_PERFCTR_INST_BRANCH_INDIR] = ONLY_5_6_7, + [A11_PMU_PERFCTR_INST_BRANCH_COND] = ONLY_5_6_7, + [A11_PMU_PERFCTR_INST_INT_LD] = ONLY_5_6_7, + [A11_PMU_PERFCTR_INST_INT_ST] = ONLY_5_6_7, + [A11_PMU_PERFCTR_INST_INT_ALU] = BIT(7), + [A11_PMU_PERFCTR_INST_SIMD_LD] = ONLY_5_6_7, + [A11_PMU_PERFCTR_INST_SIMD_ST] = ONLY_5_6_7, + [A11_PMU_PERFCTR_INST_SIMD_ALU] = BIT(7), + [A11_PMU_PERFCTR_INST_LDST] = ONLY_5_6_7, + [A11_PMU_PERFCTR_INST_BARRIER] = ONLY_5_6_7, + [A11_PMU_PERFCTR_UNKNOWN_9f] = BIT(7), + [A11_PMU_PERFCTR_L1D_CACHE_MISS_LD_NONSPEC] = ONLY_5_6_7, + [A11_PMU_PERFCTR_L1D_CACHE_MISS_ST_NONSPEC] = ONLY_5_6_7, + [A11_PMU_PERFCTR_L1D_TLB_MISS_NONSPEC] = ONLY_5_6_7, + [A11_PMU_PERFCTR_ST_MEMORY_ORDER_VIOLATION_NONSPEC] = ONLY_5_6_7, + [A11_PMU_PERFCTR_BRANCH_COND_MISPRED_NONSPEC] = ONLY_5_6_7, + [A11_PMU_PERFCTR_BRANCH_INDIR_MISPRED_NONSPEC] = ONLY_5_6_7, + [A11_PMU_PERFCTR_BRANCH_RET_INDIR_MISPRED_NONSPEC] = ONLY_5_6_7, + [A11_PMU_PERFCTR_BRANCH_CALL_INDIR_MISPRED_NONSPEC] = ONLY_5_6_7, + [A11_PMU_PERFCTR_BRANCH_MISPRED_NONSPEC] = ONLY_5_6_7, + [A11_PMU_PERFCTR_UNKNOWN_f5] = ONLY_2_4_6, + [A11_PMU_PERFCTR_UNKNOWN_f6] = ONLY_2_4_6, + [A11_PMU_PERFCTR_UNKNOWN_f7] = ONLY_2_4_6, + [A11_PMU_PERFCTR_UNKNOWN_f8] = ONLY_2_TO_7, + [A11_PMU_PERFCTR_UNKNOWN_fd] = ONLY_2_4_6, +}; + enum m1_pmu_events { M1_PMU_PERFCTR_RETIRE_UOP = 0x1, M1_PMU_PERFCTR_CORE_ACTIVE_CYCLE = 0x2, @@ -1021,6 +1128,12 @@ static int a10_pmu_get_event_idx(struct pmu_hw_events *cpuc, return apple_pmu_get_event_idx(cpuc, event, a10_pmu_event_affinity); } +static int a11_pmu_get_event_idx(struct pmu_hw_events *cpuc, + struct perf_event *event) +{ + return apple_pmu_get_event_idx(cpuc, event, a11_pmu_event_affinity); +} + static int m1_pmu_get_event_idx(struct pmu_hw_events *cpuc, struct perf_event *event) { @@ -1232,6 +1345,28 @@ static int a10_pmu_fusion_init(struct arm_pmu *cpu_pmu) return apple_pmu_init(cpu_pmu, M1_PMU_NR_COUNTERS); } +static int a11_pmu_monsoon_init(struct arm_pmu *cpu_pmu) +{ + cpu_pmu->name = "apple_monsoon_pmu"; + cpu_pmu->get_event_idx = a11_pmu_get_event_idx; + cpu_pmu->map_event = m1_pmu_map_event; + cpu_pmu->reset = m1_pmu_reset; + cpu_pmu->start = m1_pmu_start; + cpu_pmu->attr_groups[ARMPMU_ATTR_GROUP_EVENTS] = &m1_pmu_events_attr_group; + return apple_pmu_init(cpu_pmu, M1_PMU_NR_COUNTERS); +} + +static int a11_pmu_mistral_init(struct arm_pmu *cpu_pmu) +{ + cpu_pmu->name = "apple_mistral_pmu"; + cpu_pmu->get_event_idx = a11_pmu_get_event_idx; + cpu_pmu->map_event = m1_pmu_map_event; + cpu_pmu->reset = m1_pmu_reset; + cpu_pmu->start = m1_pmu_start; + cpu_pmu->attr_groups[ARMPMU_ATTR_GROUP_EVENTS] = &m1_pmu_events_attr_group; + return apple_pmu_init(cpu_pmu, M1_PMU_NR_COUNTERS); +} + static int m1_pmu_ice_init(struct arm_pmu *cpu_pmu) { cpu_pmu->name = "apple_icestorm_pmu"; @@ -1281,6 +1416,8 @@ static const struct of_device_id m1_pmu_of_device_ids[] = { { .compatible = "apple,blizzard-pmu", .data = m2_pmu_blizzard_init, }, { .compatible = "apple,icestorm-pmu", .data = m1_pmu_ice_init, }, { .compatible = "apple,firestorm-pmu", .data = m1_pmu_fire_init, }, + { .compatible = "apple,monsoon-pmu", .data = a11_pmu_monsoon_init, }, + { .compatible = "apple,mistral-pmu", .data = a11_pmu_mistral_init, }, { .compatible = "apple,fusion-pmu", .data = a10_pmu_fusion_init, }, { .compatible = "apple,twister-pmu", .data = a9_pmu_twister_init, }, { .compatible = "apple,typhoon-pmu", .data = a8_pmu_typhoon_init, }, From patchwork Mon Apr 7 04:45:22 2025 Content-Type: text/plain; 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Sun, 06 Apr 2025 21:46:47 -0700 (PDT) From: Nick Chan Date: Mon, 07 Apr 2025 12:45:22 +0800 Subject: [PATCH v6 13/21] arm64: dts: apple: s5l8960x: Add CPU PMU nodes MIME-Version: 1.0 Message-Id: <20250407-apple-cpmu-v6-13-ae8c2f225c1f@gmail.com> References: <20250407-apple-cpmu-v6-0-ae8c2f225c1f@gmail.com> In-Reply-To: <20250407-apple-cpmu-v6-0-ae8c2f225c1f@gmail.com> To: Will Deacon , Mark Rutland , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Catalin Marinas , Sven Peter , Janne Grunau , Alyssa Rosenzweig , Neal Gompa Cc: Marc Zyngier , linux-arm-kernel@lists.infradead.org, linux-perf-users@vger.kernel.org, devicetree@vger.kernel.org, asahi@lists.linux.dev, linux-kernel@vger.kernel.org, Nick Chan X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=openpgp-sha256; l=914; i=towinchenmi@gmail.com; h=from:subject:message-id; bh=LZ5pN5iqWz3OCuzIiw27nZWBzYhm/oPtBhWwt5qbJRc=; b=owEBbQKS/ZANAwAIAQHKCLemxQgkAcsmYgBn81iHZej07K4cgcyZGTeJm6SSKprUs+DfbEz1O QRY0WyIqpeJAjMEAAEIAB0WIQRLUnh4XJes95w8aIMBygi3psUIJAUCZ/NYhwAKCRABygi3psUI JPJND/oCRoiuuMx0WjE436hra0n7lRJ23QGEwbuaKRrYxUzTehmLsZZZNAikViX1e9FoBgFDURz IT7+8f9AAZ3QHy8hpjGht8u31siCvpoj5i9rp9juEBzUgqG3bOyavFIalzGTYGqZC0QWdNFhNz/ adg/FayUYDvgET64rIwipHx2mL2/rnCK43cINTtE9+ZAuksw/BHs3gfVzj9GRbEC5rhbPYhQxXX jiTuVbAhcPpuM4vcbIc9zG5rjsldL+P2jPzxwskJAlIat/wizYYaB03wlaPnx8yVNtvHZ9pDV9G b6+2+U5E+0nIbwwu5rbtKr+kcHcN15EhGab0q/xpiDpRCjaS2/OLM9XtNFGnW9Rk8CYrZc6+L+S ezXJvhp4dSFRHyFvM5V0fqiAb5u8qWVUrLSLrStpPQT0Y3IUyH+RGQ3v5Ar/G4Kng9kCoEqjJNi B7f9DM+aH9LjFbRGqVEFaxNlxRo+22tpJ6rG3/MPCS2Pv/L4zi/WwmB734iKMEAXTHzz3faJuH2 S4dueUw8aqrxVWXkai92CxaEQSVEVJ3cSXhofEh3e6J9lVSar9FgVeq4XoTi2B0UUVvBOeAUgYt 8C1YjgpdhFlo6T0GLP5nondqLtcbyjiI/hSGhum9P15PA8LpcTvu21Rjz2wMJANHebZn4rMiJZD Zr6HOVJPunwWpEQ== X-Developer-Key: i=towinchenmi@gmail.com; a=openpgp; fpr=4B5278785C97ACF79C3C688301CA08B7A6C50824 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20250406_214648_123590_A1F7C40D X-CRM114-Status: UNSURE ( 9.72 ) X-CRM114-Notice: Please train this message. X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org Add CPU PMU nodes for Apple A7 SoC. Signed-off-by: Nick Chan --- arch/arm64/boot/dts/apple/s5l8960x.dtsi | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/arch/arm64/boot/dts/apple/s5l8960x.dtsi b/arch/arm64/boot/dts/apple/s5l8960x.dtsi index d820b0e430507f681a5f2aa13a498be98080e1db..62d528d4b7204af28b66a90d68e27e1c78e2df26 100644 --- a/arch/arm64/boot/dts/apple/s5l8960x.dtsi +++ b/arch/arm64/boot/dts/apple/s5l8960x.dtsi @@ -138,6 +138,14 @@ timer { interrupts = , ; }; + + pmu { + compatible = "apple,cyclone-pmu"; + interrupt-parent = <&aic>; + interrupts = , + ; + interrupt-affinity = <&cpu0 &cpu1>; + }; }; #include "s5l8960x-pmgr.dtsi" From patchwork Mon Apr 7 04:45:23 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Nick Chan X-Patchwork-Id: 14039712 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 4BDF3C36010 for ; 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a=openpgp; fpr=4B5278785C97ACF79C3C688301CA08B7A6C50824 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20250406_214651_756540_92111FF2 X-CRM114-Status: UNSURE ( 9.72 ) X-CRM114-Notice: Please train this message. X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org Add CPU PMU nodes for Apple A8 SoC. Signed-off-by: Nick Chan --- arch/arm64/boot/dts/apple/t7000.dtsi | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/arch/arm64/boot/dts/apple/t7000.dtsi b/arch/arm64/boot/dts/apple/t7000.dtsi index 85a34dc7bc01088167d33d7b7e1cdb78161c46d8..f1415f50cb150ce1d33999c817243c3dc9184199 100644 --- a/arch/arm64/boot/dts/apple/t7000.dtsi +++ b/arch/arm64/boot/dts/apple/t7000.dtsi @@ -193,6 +193,14 @@ timer { interrupts = , ; }; + + pmu { + compatible = "apple,typhoon-pmu"; + interrupt-parent = <&aic>; + interrupts = , + ; + interrupt-affinity = <&cpu0 &cpu1>; + }; }; #include "t7000-pmgr.dtsi" From patchwork Mon Apr 7 04:45:24 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Nick Chan X-Patchwork-Id: 14039713 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 50213C36010 for ; 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X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org Add CPU PMU nodes for Apple A8X SoC. Signed-off-by: Nick Chan --- arch/arm64/boot/dts/apple/t7001.dtsi | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/arch/arm64/boot/dts/apple/t7001.dtsi b/arch/arm64/boot/dts/apple/t7001.dtsi index 8e2c67e19c4167fc6639458ce79588e153336603..fca0a100dfd7b29086735d36fec0db51144da456 100644 --- a/arch/arm64/boot/dts/apple/t7001.dtsi +++ b/arch/arm64/boot/dts/apple/t7001.dtsi @@ -183,6 +183,15 @@ timer { interrupts = , ; }; + + pmu { + compatible = "apple,typhoon-pmu"; + interrupt-parent = <&aic>; + interrupts = , + , + ; + interrupt-affinity = <&cpu0 &cpu1 &cpu2>; + }; }; #include "t7001-pmgr.dtsi" From patchwork Mon Apr 7 04:45:25 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Nick Chan X-Patchwork-Id: 14039719 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 3DF9BC3601E for ; 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X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org Add CPU PMU nodes for Apple A9 SoC. Signed-off-by: Nick Chan --- arch/arm64/boot/dts/apple/s800-0-3.dtsi | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/arch/arm64/boot/dts/apple/s800-0-3.dtsi b/arch/arm64/boot/dts/apple/s800-0-3.dtsi index c0e9ae45627c8150bc0ddcdc1e6ab65d52fa7219..56ac6e7f3803a16beacc74764262b02c75a96fce 100644 --- a/arch/arm64/boot/dts/apple/s800-0-3.dtsi +++ b/arch/arm64/boot/dts/apple/s800-0-3.dtsi @@ -167,6 +167,14 @@ timer { interrupts = , ; }; + + pmu { + compatible = "apple,twister-pmu"; + interrupt-parent = <&aic>; + interrupts = , + ; + interrupt-affinity = <&cpu0 &cpu1>; + }; }; #include "s800-0-3-pmgr.dtsi" From patchwork Mon Apr 7 04:45:26 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Nick Chan X-Patchwork-Id: 14039714 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 2A62AC36010 for ; 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X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org Add CPU PMU nodes for Apple A9X SoC. Signed-off-by: Nick Chan --- arch/arm64/boot/dts/apple/s8001.dtsi | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/arch/arm64/boot/dts/apple/s8001.dtsi b/arch/arm64/boot/dts/apple/s8001.dtsi index d56d49c048bbf55e5f2edf40f6fd1fcff6342a9f..33760c60a9189df5491256f81db7f413cada27a7 100644 --- a/arch/arm64/boot/dts/apple/s8001.dtsi +++ b/arch/arm64/boot/dts/apple/s8001.dtsi @@ -209,6 +209,14 @@ timer { interrupts = , ; }; + + pmu { + compatible = "apple,twister-pmu"; + interrupt-parent = <&aic>; + interrupts = , + ; + interrupt-affinity = <&cpu0 &cpu1>; + }; }; #include "s8001-pmgr.dtsi" From patchwork Mon Apr 7 04:45:27 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Nick Chan X-Patchwork-Id: 14039715 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 93E6AC36010 for ; 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a=openpgp; fpr=4B5278785C97ACF79C3C688301CA08B7A6C50824 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20250406_214704_938928_3ED85621 X-CRM114-Status: UNSURE ( 9.72 ) X-CRM114-Notice: Please train this message. X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org Add CPU PMU nodes for Apple A10 SoC. Signed-off-by: Nick Chan --- arch/arm64/boot/dts/apple/t8010.dtsi | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/arch/arm64/boot/dts/apple/t8010.dtsi b/arch/arm64/boot/dts/apple/t8010.dtsi index 17e294bd7c44c7961cc3ba0ec5f4178840d5b9c6..cbffc84480379cb476d5caaecce91f746e862354 100644 --- a/arch/arm64/boot/dts/apple/t8010.dtsi +++ b/arch/arm64/boot/dts/apple/t8010.dtsi @@ -243,6 +243,14 @@ timer { interrupts = , ; }; + + pmu { + compatible = "apple,fusion-pmu"; + interrupt-parent = <&aic>; + interrupts = , + ; + interrupt-affinity = <&cpu0 &cpu1>; + }; }; #include "t8010-pmgr.dtsi" From patchwork Mon Apr 7 04:45:28 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Nick Chan X-Patchwork-Id: 14039716 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 01C31C36010 for ; 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X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org Add CPU PMU nodse for Apple A10X SoC. Signed-off-by: Nick Chan --- arch/arm64/boot/dts/apple/t8011.dtsi | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/arch/arm64/boot/dts/apple/t8011.dtsi b/arch/arm64/boot/dts/apple/t8011.dtsi index 5b280c896b760dc8b759bf38dae79060e34dfc19..7fb3ab738f67583d9a19a542bf36ab2806268d55 100644 --- a/arch/arm64/boot/dts/apple/t8011.dtsi +++ b/arch/arm64/boot/dts/apple/t8011.dtsi @@ -237,6 +237,15 @@ timer { interrupts = , ; }; + + pmu { + compatible = "apple,fusion-pmu"; + interrupt-parent = <&aic>; + interrupts = , + , + ; + interrupt-affinity = <&cpu0 &cpu1 &cpu2>; + }; }; #include "t8011-pmgr.dtsi" From patchwork Mon Apr 7 04:45:29 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Nick Chan X-Patchwork-Id: 14039717 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 5B45CC36010 for ; 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a=openpgp; fpr=4B5278785C97ACF79C3C688301CA08B7A6C50824 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20250406_214711_637564_028E3536 X-CRM114-Status: UNSURE ( 9.72 ) X-CRM114-Notice: Please train this message. X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org Add CPU PMU nodes for Apple T2 SoC. Signed-off-by: Nick Chan --- arch/arm64/boot/dts/apple/t8012.dtsi | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/arch/arm64/boot/dts/apple/t8012.dtsi b/arch/arm64/boot/dts/apple/t8012.dtsi index 42df2f51ad7be4c4533e76d18e49a9a747b6b7a8..d79ed754c68dd89fc8c52887e6dcbbce04fe126b 100644 --- a/arch/arm64/boot/dts/apple/t8012.dtsi +++ b/arch/arm64/boot/dts/apple/t8012.dtsi @@ -276,6 +276,14 @@ timer { interrupts = , ; }; + + pmu { + compatible = "apple,fusion-pmu"; + interrupt-parent = <&aic>; + interrupts = , + ; + interrupt-affinity = <&cpu0 &cpu1>; + }; }; #include "t8012-pmgr.dtsi" From patchwork Mon Apr 7 04:45:30 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Nick Chan X-Patchwork-Id: 14039718 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id ABE8BC3601A for ; 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a=openpgp; fpr=4B5278785C97ACF79C3C688301CA08B7A6C50824 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20250406_214714_869800_50DFD6CE X-CRM114-Status: UNSURE ( 9.67 ) X-CRM114-Notice: Please train this message. X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org Add CPU PMU nodes for Apple A11 SoC. Signed-off-by: Nick Chan --- arch/arm64/boot/dts/apple/t8015.dtsi | 24 ++++++++++++++++++++++++ 1 file changed, 24 insertions(+) diff --git a/arch/arm64/boot/dts/apple/t8015.dtsi b/arch/arm64/boot/dts/apple/t8015.dtsi index 4d54afcecd50b50ed1fd386ccfc46c373e190e6b..e838b65ea63eef9c198032ee87e63dae282141dc 100644 --- a/arch/arm64/boot/dts/apple/t8015.dtsi +++ b/arch/arm64/boot/dts/apple/t8015.dtsi @@ -252,6 +252,18 @@ aic: interrupt-controller@232100000 { #interrupt-cells = <3>; interrupt-controller; power-domains = <&ps_aic>; + + affinities { + e-core-pmu-affinity { + apple,fiq-index = ; + cpus = <&cpu_e0 &cpu_e1 &cpu_e2 &cpu_e3>; + }; + + p-core-pmu-affinity { + apple,fiq-index = ; + cpus = <&cpu_p0 &cpu_p1>; + }; + }; }; pmgr: power-management@232000000 { @@ -380,6 +392,18 @@ timer { interrupts = , ; }; + + pmu-e { + compatible = "apple,mistral-pmu"; + interrupt-parent = <&aic>; + interrupts = ; + }; + + pmu-p { + compatible = "apple,monsoon-pmu"; + interrupt-parent = <&aic>; + interrupts = ; + }; }; #include "t8015-pmgr.dtsi"