From patchwork Mon Apr 7 12:38:46 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ze Huang X-Patchwork-Id: 14040410 Received: from mail-m155101.qiye.163.com (mail-m155101.qiye.163.com [101.71.155.101]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 10AD2245028; Mon, 7 Apr 2025 12:39:42 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=101.71.155.101 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1744029587; cv=none; b=jhMVmLIVgmahhfhJxPXmbnUuRZSfhYmyX9/sa1Qz0VkIKHijE//KN/P8UR/EJXIJONYX+oY7PB0Wz58jPUFBoC+MS7/BKAko1T6Mb8wyTIV30V01IiebVIEr+mNOWIGF5b9Kfc43CiQqRIjSeB93y1x349dZkyIfuW4hNTs2m2Y= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1744029587; c=relaxed/simple; bh=06AK6QCzrNsaSeCaNUjtkIsTuO5Ff1yFycP5j8rIQ+U=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=SMxhPrsD5KaGBsVHx8ddsNVALggF3q5LT8iBXKhzKD5SSq5pMfks8nwaV0a/JJHdM2dBeKHcoPOAjJyVjSDr7c00Ns4++aWdFbEYheGc0ctgJCaWdKmcWyP8RbCu07FpPWLEgCakMadEdHFYhH0ax9QOXzYCDj2wB1c4g3gz+X8= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=whut.edu.cn; spf=pass smtp.mailfrom=whut.edu.cn; arc=none smtp.client-ip=101.71.155.101 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=whut.edu.cn Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=whut.edu.cn Received: from [127.0.0.1] (gy-adaptive-ssl-proxy-2-entmail-virt205.gy.ntes [27.18.106.237]) by smtp.qiye.163.com (Hmail) with ESMTP id 10ef566e8; Mon, 7 Apr 2025 20:39:33 +0800 (GMT+08:00) From: Ze Huang Date: Mon, 07 Apr 2025 20:38:46 +0800 Subject: [PATCH 1/7] dt-bindings: phy: spacemit: add K1 USB2 PHY Precedence: bulk X-Mailing-List: linux-usb@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20250407-b4-k1-usb3-v3-2-v1-1-bf0bcc41c9ba@whut.edu.cn> References: <20250407-b4-k1-usb3-v3-2-v1-0-bf0bcc41c9ba@whut.edu.cn> In-Reply-To: <20250407-b4-k1-usb3-v3-2-v1-0-bf0bcc41c9ba@whut.edu.cn> To: Vinod Koul , Kishon Vijay Abraham I , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Yixun Lan , Ze Huang , Greg Kroah-Hartman , Philipp Zabel , Thinh Nguyen , Paul Walmsley , Palmer Dabbelt , Albert Ou , Alexandre Ghiti Cc: linux-phy@lists.infradead.org, devicetree@vger.kernel.org, linux-riscv@lists.infradead.org, spacemit@lists.linux.dev, linux-kernel@vger.kernel.org, linux-usb@vger.kernel.org X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1744029565; l=1364; i=huangze@whut.edu.cn; s=20250325; h=from:subject:message-id; bh=06AK6QCzrNsaSeCaNUjtkIsTuO5Ff1yFycP5j8rIQ+U=; b=+MH2aDlKTFotCOTZXikiqGkLorQrDwaSqn6wMYfOjPhCwXXNRPWZ4rUwPOHEo5CemkiEoQK8/ o+aENhF7C6LAR018bXmzp9EpK+1oTekInmDmnqqe1Ep5K/78fjSMTK4 X-Developer-Key: i=huangze@whut.edu.cn; a=ed25519; pk=C3zfn/kH6oMJickaXBa8dxTZO68EBiD93F+tAenboRA= X-HM-Spam-Status: e1kfGhgUHx5ZQUpXWQgPGg8OCBgUHx5ZQUlOS1dZFg8aDwILHllBWSg2Ly tZV1koWUFITzdXWS1ZQUlXWQ8JGhUIEh9ZQVkaGUtOVkpLTEofGEJLS0NKSFYeHw5VEwETFhoSFy QUDg9ZV1kYEgtZQVlJTFVKQ1VKS01VSUhMWVdZFhoPEhUdFFlBWU9LSFVKS0lPT09LVUpLS1VLWQ Y+ X-HM-Tid: 0a96104362f403a1kunm10ef566e8 X-HM-MType: 10 X-HM-Sender-Digest: e1kMHhlZQR0aFwgeV1kSHx4VD1lBWUc6Pyo6OCo5AjJKF0wOEhUuGjM9 LSNPCzNVSlVKTE9PS0lCTkNLTUpJVTMWGhIXVRMOGhUcAR47DBMOD1UeHw5VGBVFWVdZEgtZQVlJ TFVKQ1VKS01VSUhMWVdZCAFZQUlCQkI3Bg++ Add support for USB2 PHY found on SpacemiT K1 SoC. Signed-off-by: Ze Huang Reviewed-by: Rob Herring (Arm) --- .../devicetree/bindings/phy/spacemit,usb2-phy.yaml | 40 ++++++++++++++++++++++ 1 file changed, 40 insertions(+) diff --git a/Documentation/devicetree/bindings/phy/spacemit,usb2-phy.yaml b/Documentation/devicetree/bindings/phy/spacemit,usb2-phy.yaml new file mode 100644 index 0000000000000000000000000000000000000000..ea999cff9c250b144dd049e5ac3c084b22bd56ea --- /dev/null +++ b/Documentation/devicetree/bindings/phy/spacemit,usb2-phy.yaml @@ -0,0 +1,40 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/phy/spacemit,usb2-phy.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: SpacemiT K1 SoC USB 2.0 PHY + +maintainers: + - Ze Huang + +properties: + compatible: + const: spacemit,k1-usb2-phy + + reg: + maxItems: 1 + + clocks: + maxItems: 1 + + "#phy-cells": + const: 0 + +required: + - compatible + - reg + - clocks + - "#phy-cells" + +additionalProperties: false + +examples: + - | + usb-phy@c09c0000 { + compatible = "spacemit,k1-usb2-phy"; + reg = <0xc09c0000 0x200>; + clocks = <&syscon_apmu 15>; + #phy-cells = <0>; + }; From patchwork Mon Apr 7 12:38:47 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ze Huang X-Patchwork-Id: 14040411 Received: from mail-m49198.qiye.163.com (mail-m49198.qiye.163.com [45.254.49.198]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id B58522505D2; Mon, 7 Apr 2025 12:39:50 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=45.254.49.198 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1744029594; cv=none; b=Y1b1w/4xpK7Aphr1eJe3tNa/B5jVEhv5Fq5NsYMaKMQpH9xDFz/XEcOKQF/xEmu4IZt1WE6PgEOuPqM/j7RnFuJhOdckv7M9mA1NUz1/lKfdQeQuNTbKqvqadbF2bA0lGX7r9a7kwEr2umtStUA5mUvachx5xtHEGN2Bg//U1OU= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1744029594; c=relaxed/simple; bh=aQ1UuXr0QokrlXqm1mkiZkV7xA2Eksfk8+Uzf96R36c=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=hXjvY0p1+qhGJCtW8Rq3jXkbYEfOds6hXmIO5LTniKd9tfDpN+Tld5NHyFRExV6u48X2azrfTfeQ+NpWh62wukZAkysa/fgzB7fJdY2zled+89Ffs++ImvxuyDaw9aa8y2If5vOOmn9FpM6iu9JC9Pp+eyYta6gNgtpGvgX/YuI= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=whut.edu.cn; spf=pass smtp.mailfrom=whut.edu.cn; arc=none smtp.client-ip=45.254.49.198 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=whut.edu.cn Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=whut.edu.cn Received: from [127.0.0.1] (gy-adaptive-ssl-proxy-2-entmail-virt205.gy.ntes [27.18.106.237]) by smtp.qiye.163.com (Hmail) with ESMTP id 10ef566ea; Mon, 7 Apr 2025 20:39:41 +0800 (GMT+08:00) From: Ze Huang Date: Mon, 07 Apr 2025 20:38:47 +0800 Subject: [PATCH 2/7] dt-bindings: phy: spacemit: add K1 PCIe/USB3 combo PHY Precedence: bulk X-Mailing-List: linux-usb@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20250407-b4-k1-usb3-v3-2-v1-2-bf0bcc41c9ba@whut.edu.cn> References: <20250407-b4-k1-usb3-v3-2-v1-0-bf0bcc41c9ba@whut.edu.cn> In-Reply-To: <20250407-b4-k1-usb3-v3-2-v1-0-bf0bcc41c9ba@whut.edu.cn> To: Vinod Koul , Kishon Vijay Abraham I , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Yixun Lan , Ze Huang , Greg Kroah-Hartman , Philipp Zabel , Thinh Nguyen , Paul Walmsley , Palmer Dabbelt , Albert Ou , Alexandre Ghiti Cc: linux-phy@lists.infradead.org, devicetree@vger.kernel.org, linux-riscv@lists.infradead.org, spacemit@lists.linux.dev, linux-kernel@vger.kernel.org, linux-usb@vger.kernel.org X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1744029565; l=1859; i=huangze@whut.edu.cn; s=20250325; h=from:subject:message-id; bh=aQ1UuXr0QokrlXqm1mkiZkV7xA2Eksfk8+Uzf96R36c=; b=iMysvMhswOHuOw6sKRzqorGENfr+yTpZptaidrXYdi4w2snquFxjPfw6h6dM82qFxBLQizPTZ NbnC3H8zupuBJID1VwH0D5gukeZERLrOc3xRJXuKBGdTkg6G+dddYbS X-Developer-Key: i=huangze@whut.edu.cn; a=ed25519; pk=C3zfn/kH6oMJickaXBa8dxTZO68EBiD93F+tAenboRA= X-HM-Spam-Status: e1kfGhgUHx5ZQUpXWQgPGg8OCBgUHx5ZQUlOS1dZFg8aDwILHllBWSg2Ly tZV1koWUFITzdXWS1ZQUlXWQ8JGhUIEh9ZQVlDGkgfVklPGUJOTx1JHkodT1YeHw5VEwETFhoSFy QUDg9ZV1kYEgtZQVlJTFVKQ1VKS01VSUhMWVdZFhoPEhUdFFlBWU9LSFVKS0hKTkxOVUpLS1VKQk tLWQY+ X-HM-Tid: 0a961043805603a1kunm10ef566ea X-HM-MType: 10 X-HM-Sender-Digest: e1kMHhlZQR0aFwgeV1kSHx4VD1lBWUc6PxA6Dzo*NjJMD0wKKBVNGjhM GRUaCi5VSlVKTE9PS0lCTkNDSk9OVTMWGhIXVRMOGhUcAR47DBMOD1UeHw5VGBVFWVdZEgtZQVlJ TFVKQ1VKS01VSUhMWVdZCAFZQUhOS043Bg++ Introduce support for SpacemiT K1 PCIe/USB3 combo PHY controller. PCIe portA and USB3 controller share this phy, only one of them can work at any given application scenario. Signed-off-by: Ze Huang --- .../bindings/phy/spacemit,k1-combphy.yaml | 53 ++++++++++++++++++++++ 1 file changed, 53 insertions(+) diff --git a/Documentation/devicetree/bindings/phy/spacemit,k1-combphy.yaml b/Documentation/devicetree/bindings/phy/spacemit,k1-combphy.yaml new file mode 100644 index 0000000000000000000000000000000000000000..450157b65410b27129603ea1f3523776a1b0a75e --- /dev/null +++ b/Documentation/devicetree/bindings/phy/spacemit,k1-combphy.yaml @@ -0,0 +1,53 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/phy/spacemit,k1-combphy.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Spacemit K1 PCIe/USB3 PHY + +maintainers: + - Ze Huang + +description: + Combo PHY on SpacemiT K1 SoC.PCIe port A and USB3 controller share this + phy, only one of PCIe port A and USB3 port can work at any given application + scenario. + +properties: + compatible: + const: spacemit,k1-combphy + + reg: + maxItems: 2 + + reg-names: + items: + - const: phy_ctrl + - const: phy_sel + + resets: + maxItems: 1 + + "#phy-cells": + const: 1 + +required: + - compatible + - reg + - reg-names + - resets + - "#phy-cells" + +additionalProperties: false + +examples: + - | + phy@c0b10000 { + compatible = "spacemit,k1-combphy"; + reg = <0xc0b10000 0x800>, + <0xd4282910 0x400>; + reg-names = "phy_ctrl", "phy_sel"; + resets = <&syscon_apmu 19>; + #phy-cells = <1>; + }; From patchwork Mon Apr 7 12:38:48 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ze Huang X-Patchwork-Id: 14040412 Received: from mail-m155101.qiye.163.com (mail-m155101.qiye.163.com [101.71.155.101]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 04A7024889F; Mon, 7 Apr 2025 12:39:57 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=101.71.155.101 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1744029603; cv=none; b=AzqgSY0vB8zXz7myfKU1/TunMfc+2yCPHBbuyeVub+2fiR1o8faKfEiPl1fF5FPhgNLooTcpLPuqcipH17bSKDe6BiyLuG+WQ/iZDKMbYNLFBjmG4tJ0TGO3cVbgU9z7mtb0HjQWMbURzX5JUbACYuaN4t1yFQ7Z1UhFPNq6+x4= ARC-Message-Signature: i=1; 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Signed-off-by: Ze Huang --- .../devicetree/bindings/usb/spacemit,k1-dwc3.yaml | 78 ++++++++++++++++++++++ 1 file changed, 78 insertions(+) diff --git a/Documentation/devicetree/bindings/usb/spacemit,k1-dwc3.yaml b/Documentation/devicetree/bindings/usb/spacemit,k1-dwc3.yaml new file mode 100644 index 0000000000000000000000000000000000000000..40ce3fd1330d5f371ec69155c237e10a65a9d8f4 --- /dev/null +++ b/Documentation/devicetree/bindings/usb/spacemit,k1-dwc3.yaml @@ -0,0 +1,78 @@ +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/usb/spacemit,k1-dwc3.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: SpacemiT K1 SuperSpeed DWC3 USB SoC Controller Glue + +maintainers: + - Ze Huang + +properties: + compatible: + const: spacemit,k1-dwc3 + + ranges: + maxItems: 1 + + clocks: + maxItems: 1 + + resets: + maxItems: 1 + + interrupts: + maxItems: 1 + + interconnects: + description: + On SpacemiT K1, USB performs DMA through bus other than parent DT node. + The 'interconnects' property explicitly describes this path, ensuring + correct address translation. + + interconnect-names: + const: dma-mem + + # optional + vbus-supply: + description: A phandle to the regulator supplying the VBUS voltage. + +patternProperties: + '^usb@': + $ref: snps,dwc3.yaml# + +additionalProperties: false + +required: + - compatible + - ranges + - clocks + - resets + - interrupts + - interconnects + - interconnect-names + +examples: + - | + usb@c0a00000 { + compatible = "spacemit,k1-dwc3"; + clocks = <&syscon_apmu 16>; + interrupts = <149>; + interconnects = <&dram_range0>; + interconnect-names = "dma-mem"; + ranges = <0x0 0xc0a00000 0x10000>; + resets = <&syscon_apmu 8>; + #address-cells = <1>; + #size-cells = <1>; + status = "disabled"; + + usb@0 { + compatible = "snps,dwc3"; + reg = <0x0 0x0 0x0 0x10000>; + interrupt-parent = <&plic>; + interrupts = <125>; + phys = <&usb_phy2>, <&usb_phy3 2>; + phy-names = "usb2-phy", "usb3-phy"; + }; + }; From patchwork Mon Apr 7 12:38:49 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ze Huang X-Patchwork-Id: 14040413 Received: from mail-m155101.qiye.163.com (mail-m155101.qiye.163.com [101.71.155.101]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id DFF7B24E4A8; Mon, 7 Apr 2025 12:40:05 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=101.71.155.101 ARC-Seal: i=1; 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spf=pass smtp.mailfrom=whut.edu.cn Received: from [127.0.0.1] (gy-adaptive-ssl-proxy-2-entmail-virt205.gy.ntes [27.18.106.237]) by smtp.qiye.163.com (Hmail) with ESMTP id 10ef566f5; Mon, 7 Apr 2025 20:39:56 +0800 (GMT+08:00) From: Ze Huang Date: Mon, 07 Apr 2025 20:38:49 +0800 Subject: [PATCH 4/7] phy: spacemit: support K1 USB2.0 PHY controller Precedence: bulk X-Mailing-List: linux-usb@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20250407-b4-k1-usb3-v3-2-v1-4-bf0bcc41c9ba@whut.edu.cn> References: <20250407-b4-k1-usb3-v3-2-v1-0-bf0bcc41c9ba@whut.edu.cn> In-Reply-To: <20250407-b4-k1-usb3-v3-2-v1-0-bf0bcc41c9ba@whut.edu.cn> To: Vinod Koul , Kishon Vijay Abraham I , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Yixun Lan , Ze Huang , Greg Kroah-Hartman , Philipp Zabel , Thinh Nguyen , Paul Walmsley , Palmer Dabbelt , Albert Ou , Alexandre Ghiti Cc: linux-phy@lists.infradead.org, devicetree@vger.kernel.org, linux-riscv@lists.infradead.org, spacemit@lists.linux.dev, linux-kernel@vger.kernel.org, linux-usb@vger.kernel.org X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; 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Signed-off-by: Ze Huang --- drivers/phy/Kconfig | 1 + drivers/phy/Makefile | 1 + drivers/phy/spacemit/Kconfig | 12 ++++ drivers/phy/spacemit/Makefile | 2 + drivers/phy/spacemit/phy-k1-usb2.c | 132 +++++++++++++++++++++++++++++++++++++ 5 files changed, 148 insertions(+) diff --git a/drivers/phy/Kconfig b/drivers/phy/Kconfig index 8d58efe998ec5fd50054eed2c90d6ecce6bd5dd8..fca589aa7926eb5bce14e99785cf32cf0395202e 100644 --- a/drivers/phy/Kconfig +++ b/drivers/phy/Kconfig @@ -114,6 +114,7 @@ source "drivers/phy/renesas/Kconfig" source "drivers/phy/rockchip/Kconfig" source "drivers/phy/samsung/Kconfig" source "drivers/phy/socionext/Kconfig" +source "drivers/phy/spacemit/Kconfig" source "drivers/phy/st/Kconfig" source "drivers/phy/starfive/Kconfig" source "drivers/phy/sunplus/Kconfig" diff --git a/drivers/phy/Makefile b/drivers/phy/Makefile index e281442acc752820fe0bd638dfe38986a37c2a78..05993ff8a15daf7e2583b5f9b9b37ac584a30609 100644 --- a/drivers/phy/Makefile +++ b/drivers/phy/Makefile @@ -34,6 +34,7 @@ obj-y += allwinner/ \ rockchip/ \ samsung/ \ socionext/ \ + spacemit/ \ st/ \ starfive/ \ sunplus/ \ diff --git a/drivers/phy/spacemit/Kconfig b/drivers/phy/spacemit/Kconfig new file mode 100644 index 0000000000000000000000000000000000000000..f0c2a33f53cc810e71c6140ae957aa68a2b6ff0c --- /dev/null +++ b/drivers/phy/spacemit/Kconfig @@ -0,0 +1,12 @@ +# SPDX-License-Identifier: GPL-2.0-only +# +# Phy drivers for SpacemiT platforms +# +config PHY_SPACEMIT_K1_USB2 + tristate "SpacemiT K1 USB 2.0 PHY support" + depends on USB || USB_GADGET + depends on ARCH_SPACEMIT || COMPILE_TEST + select USB_PHY + help + Enable this to support K1 USB 2.0 PHY driver. This driver takes care of + enabling and clock setup and will be used by K1 udc/ehci/otg driver. diff --git a/drivers/phy/spacemit/Makefile b/drivers/phy/spacemit/Makefile new file mode 100644 index 0000000000000000000000000000000000000000..fec0b425a948541b39b814caef0b05e1e002d92f --- /dev/null +++ b/drivers/phy/spacemit/Makefile @@ -0,0 +1,2 @@ +# SPDX-License-Identifier: GPL-2.0-only +obj-$(CONFIG_PHY_SPACEMIT_K1_USB2) += phy-k1-usb2.o diff --git a/drivers/phy/spacemit/phy-k1-usb2.c b/drivers/phy/spacemit/phy-k1-usb2.c new file mode 100644 index 0000000000000000000000000000000000000000..acbf6a0ebad0ee6b53cc7fd89bad4780c7b7cab5 --- /dev/null +++ b/drivers/phy/spacemit/phy-k1-usb2.c @@ -0,0 +1,132 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * SpacemiT K1 USB 2.0 PHY driver + * + * Copyright (C) 2025 SpacemiT (Hangzhou) Technology Co. Ltd + * Copyright (C) 2025 Ze Huang + */ + +#include +#include +#include +#include + +#define USB2_PHY_REG01 0x04 +#define USB2_PHY_REG01_VAL 0x60ef +#define USB2_PHY_REG01_PLL_IS_READY BIT(0) +#define USB2_PHY_REG04 0x10 +#define USB2_PHY_REG04_AUTO_CLEAR_DIS BIT(2) +#define USB2_PHY_REG0D 0x34 +#define USB2_PHY_REG0D_VAL 0x1c +#define USB2_PHY_REG26 0x98 +#define USB2_PHY_REG26_VAL 0xbec4 + +#define USB2D_CTRL_RESET_TIME_MS 50 + +struct spacemit_usb2phy { + struct phy *phy; + struct clk *clk; + void __iomem *base; +}; + +static int spacemit_usb2phy_init(struct phy *phy) +{ + struct spacemit_usb2phy *sphy = phy_get_drvdata(phy); + void __iomem *base = sphy->base; + u32 val; + int ret; + + ret = clk_prepare_enable(sphy->clk); + if (ret) { + dev_err(&phy->dev, "failed to enable clock\n"); + return ret; + } + + /* + * make sure the usb controller is not under reset process before + * any configuration + */ + usleep_range(150, 200); + writel(USB2_PHY_REG26_VAL, base + USB2_PHY_REG26); /* 24M ref clk */ + + ret = read_poll_timeout(readl, val, (val & USB2_PHY_REG01_PLL_IS_READY), + 500, USB2D_CTRL_RESET_TIME_MS * 1000, true, + base + USB2_PHY_REG01); + if (ret) { + dev_err(&phy->dev, "wait PHY_REG01[PLLREADY] timeout\n"); + return ret; + } + + /* release usb2 phy internal reset and enable clock gating */ + writel(USB2_PHY_REG01_VAL, base + USB2_PHY_REG01); + writel(USB2_PHY_REG0D_VAL, base + USB2_PHY_REG0D); + + /* auto clear host disc */ + val = readl(base + USB2_PHY_REG04); + val |= USB2_PHY_REG04_AUTO_CLEAR_DIS; + writel(val, base + USB2_PHY_REG04); + + return 0; +} + +static int spacemit_usb2phy_exit(struct phy *phy) +{ + struct spacemit_usb2phy *sphy = phy_get_drvdata(phy); + + clk_disable_unprepare(sphy->clk); + + return 0; +} + +static const struct phy_ops spacemit_usb_phy_ops = { + .init = spacemit_usb2phy_init, + .exit = spacemit_usb2phy_exit, + .owner = THIS_MODULE, +}; + +static int spacemit_usb2phy_probe(struct platform_device *pdev) +{ + struct phy_provider *phy_provider; + struct device *dev = &pdev->dev; + struct spacemit_usb2phy *sphy; + + sphy = devm_kzalloc(dev, sizeof(*sphy), GFP_KERNEL); + if (!sphy) + return -ENOMEM; + + sphy->clk = devm_clk_get_prepared(&pdev->dev, NULL); + if (IS_ERR(sphy->clk)) + return dev_err_probe(dev, PTR_ERR(sphy->clk), "Failed to get clock\n"); + + sphy->base = devm_platform_ioremap_resource(pdev, 0); + if (IS_ERR(sphy->base)) + return PTR_ERR(sphy->base); + + sphy->phy = devm_phy_create(dev, NULL, &spacemit_usb_phy_ops); + if (IS_ERR(sphy->phy)) + return dev_err_probe(dev, PTR_ERR(sphy->phy), "Failed to create phy\n"); + + phy_set_drvdata(sphy->phy, sphy); + phy_provider = devm_of_phy_provider_register(dev, of_phy_simple_xlate); + + return PTR_ERR_OR_ZERO(phy_provider); +} + +static const struct of_device_id spacemit_usb2phy_dt_match[] = { + { .compatible = "spacemit,k1-usb2-phy", }, + { /* sentinal */ } +}; +MODULE_DEVICE_TABLE(of, spacemit_usb2phy_dt_match); + +static struct platform_driver spacemit_usb2_phy_driver = { + .probe = spacemit_usb2phy_probe, + .driver = { + .name = "spacemit-usb2-phy", + .owner = THIS_MODULE, + .of_match_table = spacemit_usb2phy_dt_match, + }, +}; +module_platform_driver(spacemit_usb2_phy_driver); + +MODULE_DESCRIPTION("Spacemit USB 2.0 PHY driver"); +MODULE_LICENSE("GPL"); From patchwork Mon Apr 7 12:38:50 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ze Huang X-Patchwork-Id: 14040414 Received: from mail-m49198.qiye.163.com (mail-m49198.qiye.163.com [45.254.49.198]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 721BC24E4A8; Mon, 7 Apr 2025 12:40:13 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=45.254.49.198 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1744029615; cv=none; b=u/YPJsw9cYZEDKrU/15fa1Oa+0E4PnvXQR95PVH9dg1OQ2vH/9N16XDqzd1cw4n7S05bp4DCuN3M+w+mT8wsipVMpEsHoCIlsWOha1avBuj/PYirtrEFpQN+LTwKwlkA80r23U1xeoMDuVCzVrorvZw9Q4G3DHvJzPz+RlkKVNE= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1744029615; c=relaxed/simple; bh=weOX7YCw5xIedh/25Gtq1Ysk0phP2EJksDYzN4El25E=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=q67o8qXDgNdcbPKj3Zx67YkQjX9j7LXMVftmnKfvuFZxdy+uCOULxzWiJWoqoJWkEa/tpqXSSqQcJZX4l6kAO+5iNNqUL8iHg18UZzm9bQxKseXrAcQ+uuQrVm7yVrV2VjW/YEDohcwwNT8EH+/BN1HSP+e8yecOzu0RBoYYy+0= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=whut.edu.cn; spf=pass smtp.mailfrom=whut.edu.cn; arc=none smtp.client-ip=45.254.49.198 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=whut.edu.cn Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=whut.edu.cn Received: from [127.0.0.1] (gy-adaptive-ssl-proxy-2-entmail-virt205.gy.ntes [27.18.106.237]) by smtp.qiye.163.com (Hmail) with ESMTP id 10ef566f8; Mon, 7 Apr 2025 20:40:04 +0800 (GMT+08:00) From: Ze Huang Date: Mon, 07 Apr 2025 20:38:50 +0800 Subject: [PATCH 5/7] phy: spacemit: add USB3 support for K1 PCIe/USB3 combo PHY Precedence: bulk X-Mailing-List: linux-usb@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20250407-b4-k1-usb3-v3-2-v1-5-bf0bcc41c9ba@whut.edu.cn> References: <20250407-b4-k1-usb3-v3-2-v1-0-bf0bcc41c9ba@whut.edu.cn> In-Reply-To: <20250407-b4-k1-usb3-v3-2-v1-0-bf0bcc41c9ba@whut.edu.cn> To: Vinod Koul , Kishon Vijay Abraham I , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Yixun Lan , Ze Huang , Greg Kroah-Hartman , Philipp Zabel , Thinh Nguyen , Paul Walmsley , Palmer Dabbelt , Albert Ou , Alexandre Ghiti Cc: linux-phy@lists.infradead.org, devicetree@vger.kernel.org, linux-riscv@lists.infradead.org, spacemit@lists.linux.dev, linux-kernel@vger.kernel.org, linux-usb@vger.kernel.org X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; 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Currently, only USB mode is supported; PCIe support is not included in this change. Signed-off-by: Ze Huang --- drivers/phy/spacemit/Kconfig | 8 ++ drivers/phy/spacemit/Makefile | 1 + drivers/phy/spacemit/phy-k1-combphy.c | 229 ++++++++++++++++++++++++++++++++++ 3 files changed, 238 insertions(+) diff --git a/drivers/phy/spacemit/Kconfig b/drivers/phy/spacemit/Kconfig index f0c2a33f53cc810e71c6140ae957aa68a2b6ff0c..12749aba756329cf64fb9199055ba484fe05f3ab 100644 --- a/drivers/phy/spacemit/Kconfig +++ b/drivers/phy/spacemit/Kconfig @@ -10,3 +10,11 @@ config PHY_SPACEMIT_K1_USB2 help Enable this to support K1 USB 2.0 PHY driver. This driver takes care of enabling and clock setup and will be used by K1 udc/ehci/otg driver. + +config PHY_SPACEMIT_K1_COMBPHY + tristate "SpacemiT K1 PCIe/USB3 combo PHY support" + depends on OF + select GENERIC_PHY + default ARCH_SPACEMIT && USB_DWC3_SPACEMIT + help + USB3/PCIe Combo PHY Support for SpacemiT K1 SoC diff --git a/drivers/phy/spacemit/Makefile b/drivers/phy/spacemit/Makefile index fec0b425a948541b39b814caef0b05e1e002d92f..1fd0c65f2c5cd10ea2f70e43e62c70588d1ffae9 100644 --- a/drivers/phy/spacemit/Makefile +++ b/drivers/phy/spacemit/Makefile @@ -1,2 +1,3 @@ # SPDX-License-Identifier: GPL-2.0-only +obj-$(CONFIG_PHY_SPACEMIT_K1_COMBPHY) += phy-k1-combphy.o obj-$(CONFIG_PHY_SPACEMIT_K1_USB2) += phy-k1-usb2.o diff --git a/drivers/phy/spacemit/phy-k1-combphy.c b/drivers/phy/spacemit/phy-k1-combphy.c new file mode 100644 index 0000000000000000000000000000000000000000..a4b6e77fc2b4eb5d2c45d4e76294083509a3fc9d --- /dev/null +++ b/drivers/phy/spacemit/phy-k1-combphy.c @@ -0,0 +1,229 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Spacemit K1 PCIE/USB3 PHY driver + * + * Copyright (C) 2025 SpacemiT (Hangzhou) Technology Co. Ltd + * Copyright (C) 2025 Ze Huang + */ + +#include +#include +#include +#include +#include +#include +#include + +#define COMBPHY_USB_REG1 0x68 +#define COMBPHY_USB_REG1_VAL 0x00 +#define COMBPHY_USB_REG2 0x48 +#define COMBPHY_USB_REG2_VAL 0x603a2276 +#define COMBPHY_USB_REG3 0x08 +#define COMBPHY_USB_REG3_VAL 0x97c +#define COMBPHY_USB_REG4 0x18 +#define COMBPHY_USB_REG4_VAL 0x00 +#define COMBPHY_USB_PLL_REG 0x08 +#define COMBPHY_USB_PLL_MASK 0x01 +#define COMBPHY_USB_PLL_VAL 0x01 + +#define COMBPHY_MODE_SEL BIT(3) +#define COMBPHY_WAIT_TIMEOUT 1000 + +struct spacemit_combphy_priv { + struct device *dev; + struct phy *phy; + struct reset_control *phy_rst; + void __iomem *phy_ctrl; + void __iomem *phy_sel; + u8 type; +}; + +static void spacemit_reg_update(void __iomem *reg, u32 offset, u32 mask, u32 val) +{ + u32 tmp; + + tmp = readl(reg + offset); + tmp = (tmp & ~(mask)) | val; + writel(tmp, reg + offset); +} + +static int spacemit_combphy_wait_ready(struct spacemit_combphy_priv *priv, + u32 offset, u32 mask, u32 val) +{ + u32 reg_val; + int ret = 0; + + ret = read_poll_timeout(readl, reg_val, (reg_val & mask) == val, + 1000, COMBPHY_WAIT_TIMEOUT * 1000, false, + priv->phy_ctrl + offset); + + return ret; +} + +static int spacemit_combphy_set_mode(struct spacemit_combphy_priv *priv) +{ + int ret = 0; + + switch (priv->type) { + case PHY_TYPE_USB3: + spacemit_reg_update(priv->phy_sel, 0, 0, COMBPHY_MODE_SEL); + break; + default: + dev_err(priv->dev, "PHY type %x not supported\n", priv->type); + ret = -EINVAL; + break; + } + + return ret; +} + +static int spacemit_combphy_init_usb(struct spacemit_combphy_priv *priv) +{ + void __iomem *base = priv->phy_ctrl; + int ret; + + writel(COMBPHY_USB_REG1_VAL, base + COMBPHY_USB_REG1); + writel(COMBPHY_USB_REG2_VAL, base + COMBPHY_USB_REG2); + writel(COMBPHY_USB_REG3_VAL, base + COMBPHY_USB_REG3); + writel(COMBPHY_USB_REG4_VAL, base + COMBPHY_USB_REG4); + + ret = spacemit_combphy_wait_ready(priv, COMBPHY_USB_PLL_REG, + COMBPHY_USB_PLL_MASK, + COMBPHY_USB_PLL_VAL); + if (ret) + dev_err(priv->dev, "USB3 PHY init timeout!\n"); + + return ret; +} + +static int spacemit_combphy_init(struct phy *phy) +{ + struct spacemit_combphy_priv *priv = phy_get_drvdata(phy); + int ret; + + ret = spacemit_combphy_set_mode(priv); + if (ret) { + dev_err(priv->dev, "failed to set mode for PHY type %x\n", + priv->type); + goto out; + } + + ret = reset_control_deassert(priv->phy_rst); + if (ret) { + dev_err(priv->dev, "failed to deassert rst\n"); + goto err_rst; + } + + switch (priv->type) { + case PHY_TYPE_USB3: + ret = spacemit_combphy_init_usb(priv); + break; + default: + dev_err(priv->dev, "PHY type %x not supported\n", priv->type); + ret = -EINVAL; + break; + } + + if (ret) + goto err_rst; + + return 0; + +err_rst: + reset_control_assert(priv->phy_rst); +out: + return ret; +} + +static int spacemit_combphy_exit(struct phy *phy) +{ + struct spacemit_combphy_priv *priv = phy_get_drvdata(phy); + + reset_control_assert(priv->phy_rst); + + return 0; +} + +static struct phy *spacemit_combphy_xlate(struct device *dev, + const struct of_phandle_args *args) +{ + struct spacemit_combphy_priv *priv = dev_get_drvdata(dev); + + if (args->args_count != 1) { + dev_err(dev, "invalid number of arguments\n"); + return ERR_PTR(-EINVAL); + } + + if (priv->type != PHY_NONE && priv->type != args->args[0]) + dev_warn(dev, "PHY type %d is selected to override %d\n", + args->args[0], priv->type); + + priv->type = args->args[0]; + + if (args->args_count > 1) + dev_dbg(dev, "combo phy idx: %d selected", args->args[1]); + + return priv->phy; +} + +static const struct phy_ops spacemit_combphy_ops = { + .init = spacemit_combphy_init, + .exit = spacemit_combphy_exit, + .owner = THIS_MODULE, +}; + +static int spacemit_combphy_probe(struct platform_device *pdev) +{ + struct spacemit_combphy_priv *priv; + struct phy_provider *phy_provider; + struct device *dev = &pdev->dev; + + priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL); + if (!priv) + return -ENOMEM; + + priv->phy_ctrl = devm_platform_ioremap_resource_byname(pdev, "phy_ctrl"); + if (IS_ERR(priv->phy_ctrl)) + return PTR_ERR(priv->phy_ctrl); + + priv->phy_sel = devm_platform_ioremap_resource_byname(pdev, "phy_sel"); + if (IS_ERR(priv->phy_sel)) + return PTR_ERR(priv->phy_sel); + + priv->type = PHY_NONE; + priv->dev = dev; + + priv->phy_rst = devm_reset_control_get(dev, NULL); + if (IS_ERR(priv->phy_rst)) + return dev_err_probe(dev, PTR_ERR(priv->phy_rst), + "failed to get phy reset\n"); + + priv->phy = devm_phy_create(dev, NULL, &spacemit_combphy_ops); + if (IS_ERR(priv->phy)) + return dev_err_probe(dev, PTR_ERR(priv->phy), + "failed to create combphy\n"); + + dev_set_drvdata(dev, priv); + phy_set_drvdata(priv->phy, priv); + phy_provider = devm_of_phy_provider_register(dev, spacemit_combphy_xlate); + + return PTR_ERR_OR_ZERO(phy_provider); +} + +static const struct of_device_id spacemit_combphy_of_match[] = { + { .compatible = "spacemit,k1-combphy", }, + { /* sentinel */ } +}; +MODULE_DEVICE_TABLE(of, spacemit_combphy_of_match); + +static struct platform_driver spacemit_combphy_driver = { + .probe = spacemit_combphy_probe, + .driver = { + .name = "spacemit-k1-combphy", + .of_match_table = spacemit_combphy_of_match, + }, +}; +module_platform_driver(spacemit_combphy_driver); + +MODULE_DESCRIPTION("Spacemit PCIE/USB3.0 COMBO PHY driver"); +MODULE_LICENSE("GPL"); From patchwork Mon Apr 7 12:38:51 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ze Huang X-Patchwork-Id: 14040415 Received: from mail-m49197.qiye.163.com (mail-m49197.qiye.163.com [45.254.49.197]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id B24AA2505CE; Mon, 7 Apr 2025 12:40:21 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=45.254.49.197 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1744029624; cv=none; b=n5T5+3+EJ/wy3/lMkfwfC1tD71V4e42EfoWpAFXITUheDm2Xa8umVg5lAkmcvagu6Z2mTL47uC9Bq0ZBiuQbLtDjIu9cm/Wc2N00VB1mQAT7qmpFyJLzMZ6AhB0QJN4Sdh3aB7I/OTBHTbPKyjWReXrFNGN6HJDaFPlCv2TmreA= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1744029624; c=relaxed/simple; bh=Fd/9MKedec8AShJy/y3d+yVIscBZfEuehyAXjlgnTKA=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=sms2ToXkOBJyVKecCC0mNoQRbS/sxkC7xYRTpcguH+nwjBshZ6+EnXxc62TcGmzju3Ssb10bp6i0qzW2L3lYKWOtGhtrssSFHnNZbdAeUK0I8bQcfXTX7r2YfcEWwBpILBnrmR2+Cf4XB5+6JvI7ImbNABi5vY905zroNHUNb2Y= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=whut.edu.cn; spf=pass smtp.mailfrom=whut.edu.cn; arc=none smtp.client-ip=45.254.49.197 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=whut.edu.cn Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=whut.edu.cn Received: from [127.0.0.1] (gy-adaptive-ssl-proxy-2-entmail-virt205.gy.ntes [27.18.106.237]) by smtp.qiye.163.com (Hmail) with ESMTP id 10f021904; Mon, 7 Apr 2025 20:40:12 +0800 (GMT+08:00) From: Ze Huang Date: Mon, 07 Apr 2025 20:38:51 +0800 Subject: [PATCH 6/7] usb: dwc3: add spacemit dwc3 glue layer driver Precedence: bulk X-Mailing-List: linux-usb@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20250407-b4-k1-usb3-v3-2-v1-6-bf0bcc41c9ba@whut.edu.cn> References: <20250407-b4-k1-usb3-v3-2-v1-0-bf0bcc41c9ba@whut.edu.cn> In-Reply-To: <20250407-b4-k1-usb3-v3-2-v1-0-bf0bcc41c9ba@whut.edu.cn> To: Vinod Koul , Kishon Vijay Abraham I , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Yixun Lan , Ze Huang , Greg Kroah-Hartman , Philipp Zabel , Thinh Nguyen , Paul Walmsley , Palmer Dabbelt , Albert Ou , Alexandre Ghiti Cc: linux-phy@lists.infradead.org, devicetree@vger.kernel.org, linux-riscv@lists.infradead.org, spacemit@lists.linux.dev, linux-kernel@vger.kernel.org, linux-usb@vger.kernel.org X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; 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The driver manages clock, reset and interrupt resource. Signed-off-by: Ze Huang --- drivers/usb/dwc3/Kconfig | 7 +++ drivers/usb/dwc3/Makefile | 1 + drivers/usb/dwc3/dwc3-spacemit.c | 127 +++++++++++++++++++++++++++++++++++++++ 3 files changed, 135 insertions(+) diff --git a/drivers/usb/dwc3/Kconfig b/drivers/usb/dwc3/Kconfig index 310d182e10b50b253d7e5a51674806e6ec442a2a..3c30680fa4f83565fc03c6800e867c6ced0fe101 100644 --- a/drivers/usb/dwc3/Kconfig +++ b/drivers/usb/dwc3/Kconfig @@ -189,4 +189,11 @@ config USB_DWC3_RTK or dual-role mode. Say 'Y' or 'M' if you have such device. +config USB_DWC3_SPACEMIT + tristate "Spacemit Platforms" + default USB_DWC3 + help + Support SPACEMIT platforms with DesignWare Core USB3 IP. + Say 'Y' or 'M' here if you have one such device + endif diff --git a/drivers/usb/dwc3/Makefile b/drivers/usb/dwc3/Makefile index 124eda2522d9c1f4caab222ec9770d0deaf655fc..61a87765c0c591e0a53c33b5a6544db056166f96 100644 --- a/drivers/usb/dwc3/Makefile +++ b/drivers/usb/dwc3/Makefile @@ -56,3 +56,4 @@ obj-$(CONFIG_USB_DWC3_IMX8MP) += dwc3-imx8mp.o obj-$(CONFIG_USB_DWC3_XILINX) += dwc3-xilinx.o obj-$(CONFIG_USB_DWC3_OCTEON) += dwc3-octeon.o obj-$(CONFIG_USB_DWC3_RTK) += dwc3-rtk.o +obj-$(CONFIG_USB_DWC3_SPACEMIT) += dwc3-spacemit.o diff --git a/drivers/usb/dwc3/dwc3-spacemit.c b/drivers/usb/dwc3/dwc3-spacemit.c new file mode 100644 index 0000000000000000000000000000000000000000..4574ad3b34a200ffe999c7da61b74c2ef33c0483 --- /dev/null +++ b/drivers/usb/dwc3/dwc3-spacemit.c @@ -0,0 +1,127 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * dwc3-spacemit.c - Spacemit DWC3 Specific Glue layer + * + * Copyright (C) 2025 SpacemiT (Hangzhou) Technology Co. Ltd + * + * Author: Wilson + * Contributor: Ze Huang + */ + +#include +#include +#include +#include +#include +#include + +struct dwc3_spacemit { + struct device *dev; + struct clk *clk; + struct reset_control *reset; +}; + +static int dwc3_spacemit_init(struct dwc3_spacemit *data) +{ + struct device *dev = data->dev; + int ret = 0; + + data->reset = devm_reset_control_get(dev, NULL); + if (IS_ERR(data->reset)) + return dev_err_probe(dev, PTR_ERR(data->reset), "failed to get reset\n"); + + ret = reset_control_assert(data->reset); + if (ret) + return dev_err_probe(dev, ret, "failed to assert reset\n"); + + usleep_range(10, 20); + + ret = reset_control_deassert(data->reset); + if (ret) + return dev_err_probe(dev, ret, "failed to deassert reset\n"); + + return 0; +} + +static int dwc3_spacemit_probe(struct platform_device *pdev) +{ + struct device *dev = &pdev->dev; + struct device_node *node = dev->of_node; + struct dwc3_spacemit *spacemit; + int ret; + + spacemit = devm_kzalloc(dev, sizeof(*spacemit), GFP_KERNEL); + if (!spacemit) + return -ENOMEM; + + spacemit->dev = dev; + + platform_set_drvdata(pdev, spacemit); + + spacemit->clk = devm_clk_get_enabled(dev, NULL); + if (IS_ERR(spacemit->clk)) + return dev_err_probe(dev, PTR_ERR(spacemit->clk), "Failed to get clock\n"); + + ret = dwc3_spacemit_init(spacemit); + if (ret) + return dev_err_probe(dev, ret, "failed to init SpacemiT USB3 glue\n"); + + ret = of_platform_populate(node, NULL, NULL, dev); + if (ret) + dev_err_probe(dev, ret, "failed to add dwc3 core\n"); + + return 0; +} + +static void dwc3_spacemit_remove(struct platform_device *pdev) +{ + of_platform_depopulate(&pdev->dev); +} + +static const struct of_device_id spacemit_dwc3_match[] = { + { .compatible = "spacemit,k1-dwc3", }, + { /* sentinel */ } +}; +MODULE_DEVICE_TABLE(of, spacemit_dwc3_match); + +#ifdef CONFIG_PM_SLEEP +static int dwc3_spacemit_suspend(struct device *dev) +{ + struct dwc3_spacemit *spacemit = dev_get_drvdata(dev); + + clk_disable_unprepare(spacemit->clk); + + return 0; +} + +static int dwc3_spacemit_resume(struct device *dev) +{ + struct dwc3_spacemit *spacemit = dev_get_drvdata(dev); + int ret; + + ret = clk_prepare_enable(spacemit->clk); + + return ret; +} + +static const struct dev_pm_ops dwc3_spacemit_dev_pm_ops = { + SET_SYSTEM_SLEEP_PM_OPS(dwc3_spacemit_suspend, dwc3_spacemit_resume) +}; +#endif /* CONFIG_PM_SLEEP */ + +static struct platform_driver dwc3_spacemit_driver = { + .probe = dwc3_spacemit_probe, + .remove = dwc3_spacemit_remove, + .driver = { + .name = "spacemit-dwc3", + .of_match_table = spacemit_dwc3_match, +#ifdef CONFIG_PM_SLEEP + .pm = &dwc3_spacemit_dev_pm_ops, +#endif /* CONFIG_PM_SLEEP */ + }, +}; +module_platform_driver(dwc3_spacemit_driver); + +MODULE_AUTHOR("Wilson "); +MODULE_LICENSE("GPL"); +MODULE_DESCRIPTION("DesignWare USB3 Spacemit Glue Layer"); From patchwork Mon Apr 7 12:38:52 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ze Huang X-Patchwork-Id: 14040416 Received: from mail-m49197.qiye.163.com (mail-m49197.qiye.163.com [45.254.49.197]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id A38B624BCFD; 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dmarc=pass (p=none dis=none) header.from=whut.edu.cn Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=whut.edu.cn Received: from [127.0.0.1] (gy-adaptive-ssl-proxy-2-entmail-virt205.gy.ntes [27.18.106.237]) by smtp.qiye.163.com (Hmail) with ESMTP id 10f021907; Mon, 7 Apr 2025 20:40:19 +0800 (GMT+08:00) From: Ze Huang Date: Mon, 07 Apr 2025 20:38:52 +0800 Subject: [PATCH 7/7] riscv: dts: spacemit: add usb3.0 support for K1 Precedence: bulk X-Mailing-List: linux-usb@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20250407-b4-k1-usb3-v3-2-v1-7-bf0bcc41c9ba@whut.edu.cn> References: <20250407-b4-k1-usb3-v3-2-v1-0-bf0bcc41c9ba@whut.edu.cn> In-Reply-To: <20250407-b4-k1-usb3-v3-2-v1-0-bf0bcc41c9ba@whut.edu.cn> To: Vinod Koul , Kishon Vijay Abraham I , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Yixun Lan , Ze Huang , Greg Kroah-Hartman , Philipp Zabel , Thinh Nguyen , Paul Walmsley , Palmer Dabbelt , Albert Ou , Alexandre Ghiti Cc: linux-phy@lists.infradead.org, devicetree@vger.kernel.org, linux-riscv@lists.infradead.org, spacemit@lists.linux.dev, linux-kernel@vger.kernel.org, linux-usb@vger.kernel.org X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1744029565; l=4966; i=huangze@whut.edu.cn; s=20250325; h=from:subject:message-id; bh=9b/CmXLUb4oO7usHoGG4t62ZEhc9XM1xbRBgYVUAIi8=; b=3KOUzEqgq3ngS8e6srGkEQ9llihvefBkIa8EYXsF8TW74OrzSONs6LXCSRXUK8I5VWyz1+N0r I7ecfweIWlhCt+kdQHfdPCR10sWfIpcv4hO+OU7QGL2NcGBdLp1l/yG X-Developer-Key: i=huangze@whut.edu.cn; a=ed25519; pk=C3zfn/kH6oMJickaXBa8dxTZO68EBiD93F+tAenboRA= X-HM-Spam-Status: e1kfGhgUHx5ZQUpXWQgPGg8OCBgUHx5ZQUlOS1dZFg8aDwILHllBWSg2Ly tZV1koWUFITzdXWS1ZQUlXWQ8JGhUIEh9ZQVlDQksaVh4dTRhKGBlKQxgYH1YeHw5VEwETFhoSFy QUDg9ZV1kYEgtZQVlJTFVKQ1VKS01VSUhMWVdZFhoPEhUdFFlBWU9LSFVKS0lPT09LVUpLS1VLWQ Y+ X-HM-Tid: 0a96104417d303a1kunm10f021907 X-HM-MType: 10 X-HM-Sender-Digest: e1kMHhlZQR0aFwgeV1kSHx4VD1lBWUc6KzI6Mww4DDIBH0wMKBcDGjMo OCwaCkxVSlVKTE9PS0lCTUlMSkNKVTMWGhIXVRMOGhUcAR47DBMOD1UeHw5VGBVFWVdZEgtZQVlJ TFVKQ1VKS01VSUhMWVdZCAFZQU1NS043Bg++ Add USB 3.0 support for the SpacemiT K1 SoC, including the following components: - USB 2.0 PHY node (usb_phy2) - USB 3.0 combo PHY node (usb_phy3) - USB 3.0 host controller (dwc3 glue + core) - USB 3.0 hub and vbus regulator (usb3_vhub, usb3_vbus) - DRAM interconnect node for USB DMA ("dma-mem") The `usb3_vbus` and `usb3_vhub` regulator node provides a fixed 5V supply to power the onboard USB 3.0 hub and usb vbus. On K1, some DMA transfers from devices to memory use separate buses with different DMA address translation rules from the parent node. We express this relationship through the interconnects node("dma-mem"). Signed-off-by: Ze Huang --- arch/riscv/boot/dts/spacemit/k1-bananapi-f3.dts | 55 +++++++++++++++++++++++++ arch/riscv/boot/dts/spacemit/k1.dtsi | 52 +++++++++++++++++++++++ 2 files changed, 107 insertions(+) diff --git a/arch/riscv/boot/dts/spacemit/k1-bananapi-f3.dts b/arch/riscv/boot/dts/spacemit/k1-bananapi-f3.dts index 816ef1bc358ec490aff184d5915d680dbd9f00cb..9353432f171fc895fdd465654bc8166a1bc65e0b 100644 --- a/arch/riscv/boot/dts/spacemit/k1-bananapi-f3.dts +++ b/arch/riscv/boot/dts/spacemit/k1-bananapi-f3.dts @@ -28,6 +28,25 @@ led1 { default-state = "on"; }; }; + + usb3_vhub: regulator-vhub-5v { + compatible = "regulator-fixed"; + regulator-name = "USB30_VHUB"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + gpio = <&gpio K1_GPIO(123) GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + + usb3_vbus: regulator-vbus-5v { + compatible = "regulator-fixed"; + regulator-name = "USB30_VBUS"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + regulator-always-on; + gpio = <&gpio K1_GPIO(97) GPIO_ACTIVE_HIGH>; + enable-active-high; + }; }; &uart0 { @@ -35,3 +54,39 @@ &uart0 { pinctrl-0 = <&uart0_2_cfg>; status = "okay"; }; + +&usb3_phy0 { + status = "okay"; +}; + +&usb3_phy1 { + status = "okay"; +}; + +&usb3 { + status = "okay"; + vbus-supply = <&usb3_vbus>; + + usb@0 { + dr_mode = "host"; + phy_type = "utmi"; + snps,hsphy_interface = "utmi"; + snps,dis_enblslpm_quirk; + snps,dis-u1u2-quirk; + snps,dis-u2-freeclk-exists-quirk; + snps,dis-del-phy-power-chg-quirk; + snps,dis_u2_susphy_quirk; + snps,dis_u3_susphy_quirk; + snps,dis_rxdet_inp3_quirk; + snps,xhci-trb-ent-quirk; + #address-cells = <1>; + #size-cells = <0>; + + hub@1 { + compatible = "usb2109,817"; + reg = <0x1>; + vdd-supply = <&usb3_vhub>; + reset-gpios = <&gpio K1_GPIO(124) GPIO_ACTIVE_LOW>; + }; + }; +}; diff --git a/arch/riscv/boot/dts/spacemit/k1.dtsi b/arch/riscv/boot/dts/spacemit/k1.dtsi index dc675f7e9b131256c50e2ca4ff347ae54e4b62ae..be3648cdcecd715e656fb8bde8a434ace752c012 100644 --- a/arch/riscv/boot/dts/spacemit/k1.dtsi +++ b/arch/riscv/boot/dts/spacemit/k1.dtsi @@ -4,6 +4,8 @@ */ #include +#include +#include /dts-v1/; / { @@ -350,6 +352,14 @@ soc { dma-noncoherent; ranges; + dram_range0: dram_range@0 { + #address-cells = <2>; + #size-cells = <2>; + dma-ranges = <0x0 0x00000000 0x0 0x00000000 0x0 0x80000000>; + #interconnect-cells = <0>; + status = "okay"; + }; + syscon_rcpu: system-controller@c0880000 { compatible = "spacemit,k1-syscon-rcpu"; reg = <0x0 0xc0880000 0x0 0x2048>; @@ -362,6 +372,48 @@ syscon_rcpu2: system-controller@c0888000 { #reset-cells = <1>; }; + usb3: usb@c0a00000 { + compatible = "spacemit,k1-dwc3"; + clocks = <&syscon_apmu CLK_USB30>; + clock-names = "usbdrd30"; + interrupt-parent = <&plic>; + interrupts = <149>; + interconnects = <&dram_range0>; + interconnect-names = "dma-mem"; + ranges = <0x0 0x0 0x0 0xc0a00000 0x0 0x10000>; + resets = <&syscon_apmu RESET_USB3_0>; + #address-cells = <2>; + #size-cells = <2>; + status = "disabled"; + + usb@0 { + compatible = "snps,dwc3"; + reg = <0x0 0x0 0x0 0x10000>; + interrupt-parent = <&plic>; + interrupts = <125>; + phys = <&usb3_phy0>, <&usb3_phy1 PHY_TYPE_USB3>; + phy-names = "usb2-phy", "usb3-phy"; + }; + }; + + usb3_phy0: usb-phy@0xc0a30000 { + compatible = "spacemit,k1-usb2-phy"; + reg = <0x0 0xc0a30000 0x0 0x200>; + clocks = <&syscon_apmu CLK_USB30>; + #phy-cells = <0>; + status = "disabled"; + }; + + usb3_phy1: combphy@c0b10000 { + compatible = "spacemit,k1-combphy"; + reg = <0x0 0xc0b10000 0x0 0x800>, + <0x0 0xd4282910 0x0 0x400>; + reg-names = "phy_ctrl", "phy_sel"; + resets = <&syscon_apmu RESET_PCIE0>; + #phy-cells = <1>; + status = "disabled"; + }; + syscon_apbc: system-control@d4015000 { compatible = "spacemit,k1-syscon-apbc"; reg = <0x0 0xd4015000 0x0 0x1000>;