From patchwork Mon Apr 7 14:23:49 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: "Borah, Chaitanya Kumar" X-Patchwork-Id: 14040887 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 158D4C36010 for ; Mon, 7 Apr 2025 14:39:15 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 9AB4D10E4B3; Mon, 7 Apr 2025 14:39:14 +0000 (UTC) Authentication-Results: gabe.freedesktop.org; dkim=pass (2048-bit key; unprotected) header.d=intel.com header.i=@intel.com header.b="MCzCERqN"; dkim-atps=neutral Received: from mgamail.intel.com (mgamail.intel.com [192.198.163.19]) by gabe.freedesktop.org (Postfix) with ESMTPS id 4234210E4B3; Mon, 7 Apr 2025 14:39:13 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1744036753; x=1775572753; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=jxbtKbwMC7KcLaDZ206XXWtVvEAwSlmfPx1myL0UYC8=; b=MCzCERqN2p5Lshe/+2wCfoTBq6TVANhnAGlMU68tG/fttGDkiNuBTrwy YLKQwdQ9Ba7dTpgm+TKkeSLJXl9XeMsjIo24PZuMYaddmsFIaOAe+FRPL 6SDr+0g2CJ/M9jy87dmndYM7+hQUqG+BiLpHuTw/7/w1QjpZhw/4zwTQj CdrmasHGi0eotmoAAyPhzSOyfUwXBdk04vaxo3gFFoY9f3VNE4sUtxrQL Ix+0A16ZwA+b7horv4UlmZBcyjPa792bJJZcbvnpj3OfNTDJsT/PiFh11 iLum+dj+j36Jd89+MU8wO9OXoOuA/voj/0mpmHYj1h5DIvRzirlkUW1mj w==; X-CSE-ConnectionGUID: RBzrj73OTNSy6rl0R4yjQQ== X-CSE-MsgGUID: If844/HQSWaN5CL6K3uHDg== X-IronPort-AV: E=McAfee;i="6700,10204,11397"; a="44572406" X-IronPort-AV: E=Sophos;i="6.15,194,1739865600"; d="scan'208";a="44572406" Received: from fmviesa001.fm.intel.com ([10.60.135.141]) by fmvoesa113.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 07 Apr 2025 07:39:13 -0700 X-CSE-ConnectionGUID: q2pixgbwSd6DpyibfdH1Sw== X-CSE-MsgGUID: TLeWw3F7T6mhY0HAE8PmYQ== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.15,194,1739865600"; d="scan'208";a="158963633" Received: from dut-2a59.iind.intel.com ([10.190.239.113]) by fmviesa001.fm.intel.com with ESMTP; 07 Apr 2025 07:39:11 -0700 From: Chaitanya Kumar Borah To: intel-xe@lists.freedesktop.org, intel-gfx@lists.freedesktop.org Cc: ville.syrjala@linux.intel.com, uma.shankar@intel.com, chaitanya.kumar.borah@intel.com, animesh.manna@intel.com Subject: [PATCH 01/11] drm/i915/dsb: Extract intel_dsb_ins_align() Date: Mon, 7 Apr 2025 19:53:49 +0530 Message-Id: <20250407142359.1398410-2-chaitanya.kumar.borah@intel.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20250407142359.1398410-1-chaitanya.kumar.borah@intel.com> References: <20250407142359.1398410-1-chaitanya.kumar.borah@intel.com> MIME-Version: 1.0 X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" From: Ville Syrjälä Extract the code that alings the next instruction to the next QW boundary into a small helper. I'll have some more uses for this later. Also explain why we don't have to zero out the extra DW. Signed-off-by: Ville Syrjälä --- drivers/gpu/drm/i915/display/intel_dsb.c | 16 ++++++++++++++-- 1 file changed, 14 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_dsb.c b/drivers/gpu/drm/i915/display/intel_dsb.c index 0ddcdedf5453..c166e02b8af0 100644 --- a/drivers/gpu/drm/i915/display/intel_dsb.c +++ b/drivers/gpu/drm/i915/display/intel_dsb.c @@ -228,13 +228,25 @@ static bool is_dsb_busy(struct intel_display *display, enum pipe pipe, return intel_de_read_fw(display, DSB_CTRL(pipe, dsb_id)) & DSB_STATUS_BUSY; } +static void intel_dsb_ins_align(struct intel_dsb *dsb) +{ + /* + * Every instruction should be 8 byte aligned. + * + * The only way to get unaligned free_pos is via + * intel_dsb_reg_write_indexed() which already + * makes sure the next dword is zeroed, so no need + * to clear it here. + */ + dsb->free_pos = ALIGN(dsb->free_pos, 2); +} + static void intel_dsb_emit(struct intel_dsb *dsb, u32 ldw, u32 udw) { if (!assert_dsb_has_room(dsb)) return; - /* Every instruction should be 8 byte aligned. */ - dsb->free_pos = ALIGN(dsb->free_pos, 2); + intel_dsb_ins_align(dsb); dsb->ins_start_offset = dsb->free_pos; dsb->ins[0] = ldw; From patchwork Mon Apr 7 14:23:50 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: "Borah, Chaitanya Kumar" X-Patchwork-Id: 14040888 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 19743C369A2 for ; Mon, 7 Apr 2025 14:39:17 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id A839010E4B6; Mon, 7 Apr 2025 14:39:16 +0000 (UTC) Authentication-Results: gabe.freedesktop.org; dkim=pass (2048-bit key; unprotected) header.d=intel.com header.i=@intel.com header.b="nqhJT4Ld"; dkim-atps=neutral Received: from mgamail.intel.com (mgamail.intel.com [192.198.163.19]) by gabe.freedesktop.org (Postfix) with ESMTPS id 52D0A10E4AE; Mon, 7 Apr 2025 14:39:15 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1744036755; x=1775572755; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=+f2VD6I1HJb49xVuDR0quwpQ60KE9eLOLMy6x8GhTRE=; b=nqhJT4LdMjFgC32UeDUjCmNVoUwmdvzRer9wPgefVKcluMFsulmCNoD7 xkENJenu/9pSLgmOMa3HqNhdFcMkSdaIiW7wSKFm+dQsWP7OoiSmWCdoF wp05hY7wGd+9D6zrOWCvpgokgMdFVA0r42def4PN95zdP7OsMg3fpx5SA uhRRRq8sdKOVNPVzOwsdMn5jjKvEqYSLrU39AxkNY0gMycZMoF8KcjVxN q12sZDnKDb8lKeRpy/8IW7rR1HVzkgIA1V+mLmu5zM4TiIS0Qm3NVjC1d rx4f+rM84XP8Ty6Xa8VSdw9cDeImAkyn2CsiitOSt42jHhgOMDnVWXzuP Q==; X-CSE-ConnectionGUID: jeXX42gXQ5S02cykSGQp2A== X-CSE-MsgGUID: Rwh/fWHKRo2bHhpvH3uQ1w== X-IronPort-AV: E=McAfee;i="6700,10204,11397"; a="44572409" X-IronPort-AV: E=Sophos;i="6.15,194,1739865600"; d="scan'208";a="44572409" Received: from fmviesa001.fm.intel.com ([10.60.135.141]) by fmvoesa113.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 07 Apr 2025 07:39:15 -0700 X-CSE-ConnectionGUID: /N11PhcZSVOPNF2N3BBngQ== X-CSE-MsgGUID: YuE8JhwsRwC4jKdndCAbyA== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.15,194,1739865600"; d="scan'208";a="158963646" Received: from dut-2a59.iind.intel.com ([10.190.239.113]) by fmviesa001.fm.intel.com with ESMTP; 07 Apr 2025 07:39:13 -0700 From: Chaitanya Kumar Borah To: intel-xe@lists.freedesktop.org, intel-gfx@lists.freedesktop.org Cc: ville.syrjala@linux.intel.com, uma.shankar@intel.com, chaitanya.kumar.borah@intel.com, animesh.manna@intel.com Subject: [PATCH 02/11] drm/i915/dsb: Extract assert_dsb_tail_is_aligned() Date: Mon, 7 Apr 2025 19:53:50 +0530 Message-Id: <20250407142359.1398410-3-chaitanya.kumar.borah@intel.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20250407142359.1398410-1-chaitanya.kumar.borah@intel.com> References: <20250407142359.1398410-1-chaitanya.kumar.borah@intel.com> MIME-Version: 1.0 X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" From: Ville Syrjälä Extract the DSB tail alignment checks into helper. We already have two uses of this, and soo we'll get a third. Signed-off-by: Ville Syrjälä --- drivers/gpu/drm/i915/display/intel_dsb.c | 19 +++++++++++++++---- 1 file changed, 15 insertions(+), 4 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_dsb.c b/drivers/gpu/drm/i915/display/intel_dsb.c index c166e02b8af0..08e3bbea1a67 100644 --- a/drivers/gpu/drm/i915/display/intel_dsb.c +++ b/drivers/gpu/drm/i915/display/intel_dsb.c @@ -204,6 +204,15 @@ static bool assert_dsb_has_room(struct intel_dsb *dsb) crtc->base.base.id, crtc->base.name, dsb->id); } +static bool assert_dsb_tail_is_aligned(struct intel_dsb *dsb) +{ + struct intel_crtc *crtc = dsb->crtc; + struct intel_display *display = to_intel_display(crtc->base.dev); + + return !drm_WARN_ON(display->drm, + !IS_ALIGNED(dsb->free_pos * 4, CACHELINE_BYTES)); +} + static void intel_dsb_dump(struct intel_dsb *dsb) { struct intel_crtc *crtc = dsb->crtc; @@ -621,10 +630,11 @@ static void _intel_dsb_chain(struct intel_atomic_state *state, if (drm_WARN_ON(display->drm, dsb->id == chained_dsb->id)) return; - tail = chained_dsb->free_pos * 4; - if (drm_WARN_ON(display->drm, !IS_ALIGNED(tail, CACHELINE_BYTES))) + if (!assert_dsb_tail_is_aligned(chained_dsb)) return; + tail = chained_dsb->free_pos * 4; + intel_dsb_reg_write(dsb, DSB_CTRL(pipe, chained_dsb->id), ctrl | DSB_ENABLE); @@ -695,10 +705,11 @@ static void _intel_dsb_commit(struct intel_dsb *dsb, u32 ctrl, enum pipe pipe = crtc->pipe; u32 tail; - tail = dsb->free_pos * 4; - if (drm_WARN_ON(display->drm, !IS_ALIGNED(tail, CACHELINE_BYTES))) + if (!assert_dsb_tail_is_aligned(dsb)) return; + tail = dsb->free_pos * 4; + if (is_dsb_busy(display, pipe, dsb->id)) { drm_err(display->drm, "[CRTC:%d:%s] DSB %d is busy\n", crtc->base.base.id, crtc->base.name, dsb->id); From patchwork Mon Apr 7 14:23:51 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: "Borah, Chaitanya Kumar" X-Patchwork-Id: 14040889 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id F3848C369A3 for ; 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X-CSE-ConnectionGUID: kn7HBtVSSL2K9ujiG0unew== X-CSE-MsgGUID: s9SsoSKGSiGHYibFTc9sPA== X-IronPort-AV: E=McAfee;i="6700,10204,11397"; a="44572413" X-IronPort-AV: E=Sophos;i="6.15,194,1739865600"; d="scan'208";a="44572413" Received: from fmviesa001.fm.intel.com ([10.60.135.141]) by fmvoesa113.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 07 Apr 2025 07:39:17 -0700 X-CSE-ConnectionGUID: lJ+cWvDrRV25IIr5UDtC8g== X-CSE-MsgGUID: Lttk/nseRMq/wbNnhRPjYw== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.15,194,1739865600"; d="scan'208";a="158963656" Received: from dut-2a59.iind.intel.com ([10.190.239.113]) by fmviesa001.fm.intel.com with ESMTP; 07 Apr 2025 07:39:15 -0700 From: Chaitanya Kumar Borah To: intel-xe@lists.freedesktop.org, intel-gfx@lists.freedesktop.org Cc: ville.syrjala@linux.intel.com, uma.shankar@intel.com, chaitanya.kumar.borah@intel.com, animesh.manna@intel.com Subject: [PATCH 03/11] drm/i915/dsb: Extract intel_dsb_{head,tail}() Date: Mon, 7 Apr 2025 19:53:51 +0530 Message-Id: <20250407142359.1398410-4-chaitanya.kumar.borah@intel.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20250407142359.1398410-1-chaitanya.kumar.borah@intel.com> References: <20250407142359.1398410-1-chaitanya.kumar.borah@intel.com> MIME-Version: 1.0 X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" From: Ville Syrjälä Extract the code that calculates the DSB_HEAD/TAIL register values into small helpers. We already have two copies of this, and soon there will be a third. Signed-off-by: Ville Syrjälä --- drivers/gpu/drm/i915/display/intel_dsb.c | 24 ++++++++++++++---------- 1 file changed, 14 insertions(+), 10 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_dsb.c b/drivers/gpu/drm/i915/display/intel_dsb.c index 08e3bbea1a67..0de15e3a9a56 100644 --- a/drivers/gpu/drm/i915/display/intel_dsb.c +++ b/drivers/gpu/drm/i915/display/intel_dsb.c @@ -237,6 +237,16 @@ static bool is_dsb_busy(struct intel_display *display, enum pipe pipe, return intel_de_read_fw(display, DSB_CTRL(pipe, dsb_id)) & DSB_STATUS_BUSY; } +static unsigned int intel_dsb_head(struct intel_dsb *dsb) +{ + return intel_dsb_buffer_ggtt_offset(&dsb->dsb_buf); +} + +static unsigned int intel_dsb_tail(struct intel_dsb *dsb) +{ + return intel_dsb_buffer_ggtt_offset(&dsb->dsb_buf) + dsb->free_pos * 4; +} + static void intel_dsb_ins_align(struct intel_dsb *dsb) { /* @@ -625,7 +635,6 @@ static void _intel_dsb_chain(struct intel_atomic_state *state, struct intel_display *display = to_intel_display(state->base.dev); struct intel_crtc *crtc = dsb->crtc; enum pipe pipe = crtc->pipe; - u32 tail; if (drm_WARN_ON(display->drm, dsb->id == chained_dsb->id)) return; @@ -633,8 +642,6 @@ static void _intel_dsb_chain(struct intel_atomic_state *state, if (!assert_dsb_tail_is_aligned(chained_dsb)) return; - tail = chained_dsb->free_pos * 4; - intel_dsb_reg_write(dsb, DSB_CTRL(pipe, chained_dsb->id), ctrl | DSB_ENABLE); @@ -655,10 +662,10 @@ static void _intel_dsb_chain(struct intel_atomic_state *state, } intel_dsb_reg_write(dsb, DSB_HEAD(pipe, chained_dsb->id), - intel_dsb_buffer_ggtt_offset(&chained_dsb->dsb_buf)); + intel_dsb_head(chained_dsb)); intel_dsb_reg_write(dsb, DSB_TAIL(pipe, chained_dsb->id), - intel_dsb_buffer_ggtt_offset(&chained_dsb->dsb_buf) + tail); + intel_dsb_tail(chained_dsb)); if (ctrl & DSB_WAIT_FOR_VBLANK) { /* @@ -703,13 +710,10 @@ static void _intel_dsb_commit(struct intel_dsb *dsb, u32 ctrl, struct intel_crtc *crtc = dsb->crtc; struct intel_display *display = to_intel_display(crtc->base.dev); enum pipe pipe = crtc->pipe; - u32 tail; if (!assert_dsb_tail_is_aligned(dsb)) return; - tail = dsb->free_pos * 4; - if (is_dsb_busy(display, pipe, dsb->id)) { drm_err(display->drm, "[CRTC:%d:%s] DSB %d is busy\n", crtc->base.base.id, crtc->base.name, dsb->id); @@ -727,7 +731,7 @@ static void _intel_dsb_commit(struct intel_dsb *dsb, u32 ctrl, dsb_error_int_en(display) | DSB_PROG_INT_EN); intel_de_write_fw(display, DSB_HEAD(pipe, dsb->id), - intel_dsb_buffer_ggtt_offset(&dsb->dsb_buf)); + intel_dsb_head(dsb)); if (hw_dewake_scanline >= 0) { int diff, position; @@ -749,7 +753,7 @@ static void _intel_dsb_commit(struct intel_dsb *dsb, u32 ctrl, } intel_de_write_fw(display, DSB_TAIL(pipe, dsb->id), - intel_dsb_buffer_ggtt_offset(&dsb->dsb_buf) + tail); + intel_dsb_tail(dsb)); } /** From patchwork Mon Apr 7 14:23:52 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: "Borah, Chaitanya Kumar" X-Patchwork-Id: 14040890 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 0A63FC36010 for ; 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X-CSE-ConnectionGUID: nvIHeEtFQE+UBEC5bG5TBA== X-CSE-MsgGUID: fa9IQPFLQgW25OeTH1zDPQ== X-IronPort-AV: E=McAfee;i="6700,10204,11397"; a="44572417" X-IronPort-AV: E=Sophos;i="6.15,194,1739865600"; d="scan'208";a="44572417" Received: from fmviesa001.fm.intel.com ([10.60.135.141]) by fmvoesa113.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 07 Apr 2025 07:39:20 -0700 X-CSE-ConnectionGUID: vd4Bc4QbRqOUJ4g/DK6Low== X-CSE-MsgGUID: 2/AL+MakR9OZYkFPPd8+Mg== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.15,194,1739865600"; d="scan'208";a="158963673" Received: from dut-2a59.iind.intel.com ([10.190.239.113]) by fmviesa001.fm.intel.com with ESMTP; 07 Apr 2025 07:39:17 -0700 From: Chaitanya Kumar Borah To: intel-xe@lists.freedesktop.org, intel-gfx@lists.freedesktop.org Cc: ville.syrjala@linux.intel.com, uma.shankar@intel.com, chaitanya.kumar.borah@intel.com, animesh.manna@intel.com Subject: [PATCH 04/11] drm/i915/dsb: Implement intel_dsb_gosub() Date: Mon, 7 Apr 2025 19:53:52 +0530 Message-Id: <20250407142359.1398410-5-chaitanya.kumar.borah@intel.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20250407142359.1398410-1-chaitanya.kumar.borah@intel.com> References: <20250407142359.1398410-1-chaitanya.kumar.borah@intel.com> MIME-Version: 1.0 X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" From: Ville Syrjälä Add support for the new GOSUB DSB instruction (available on ptl+), which instructs the DSB to jump to a different buffer, executie the commands there, and then return execution to the next instruction in the original buffer. There are a few alignment related workarounds that need to be dealt with when emitting GOSUB instruction. v2: Right shift head and tail pointer passed to gosub command (chaitanya) Signed-off-by: Ville Syrjälä --- drivers/gpu/drm/i915/display/intel_dsb.c | 52 ++++++++++++++++++++++++ drivers/gpu/drm/i915/display/intel_dsb.h | 2 + 2 files changed, 54 insertions(+) diff --git a/drivers/gpu/drm/i915/display/intel_dsb.c b/drivers/gpu/drm/i915/display/intel_dsb.c index 0de15e3a9a56..2cda6fc7857b 100644 --- a/drivers/gpu/drm/i915/display/intel_dsb.c +++ b/drivers/gpu/drm/i915/display/intel_dsb.c @@ -93,6 +93,9 @@ struct intel_dsb { /* see DSB_REG_VALUE_MASK */ #define DSB_OPCODE_POLL 0xA /* see DSB_REG_VALUE_MASK */ +#define DSB_OPCODE_GOSUB 0xC /* ptl+ */ +#define DSB_GOSUB_HEAD_SHIFT 26 +#define DSB_GOSUB_TAIL_SHIFT 0 static bool pre_commit_is_vrr_active(struct intel_atomic_state *state, struct intel_crtc *crtc) @@ -533,6 +536,55 @@ static void intel_dsb_align_tail(struct intel_dsb *dsb) dsb->free_pos = aligned_tail / 4; } +static void intel_dsb_gosub_align(struct intel_dsb *dsb) +{ + u32 aligned_tail, tail; + + intel_dsb_ins_align(dsb); + + tail = dsb->free_pos * 4; + aligned_tail = ALIGN(tail, CACHELINE_BYTES); + + /* + * "The GOSUB instruction cannot be placed in + * cacheline QW slot 6 or 7 (numbered 0-7)" + */ + if (aligned_tail - tail <= 2 * 8) + intel_dsb_buffer_memset(&dsb->dsb_buf, dsb->free_pos, 0, + aligned_tail - tail); + + dsb->free_pos = aligned_tail / 4; +} + +void intel_dsb_gosub(struct intel_dsb *dsb, + struct intel_dsb *sub_dsb) +{ + struct intel_crtc *crtc = dsb->crtc; + struct intel_display *display = to_intel_display(crtc->base.dev); + u64 head_tail; + + if (drm_WARN_ON(display->drm, dsb->id != sub_dsb->id)) + return; + + if (!assert_dsb_tail_is_aligned(sub_dsb)) + return; + + intel_dsb_gosub_align(dsb); + + head_tail = ((u64)(intel_dsb_head(sub_dsb) >> 6) << DSB_GOSUB_HEAD_SHIFT) | + ((u64)(intel_dsb_tail(sub_dsb) >> 6) << DSB_GOSUB_TAIL_SHIFT); + + intel_dsb_emit(dsb, lower_32_bits(head_tail), + (DSB_OPCODE_GOSUB << DSB_OPCODE_SHIFT) | + upper_32_bits(head_tail)); + + /* + * "NOTE: the instructions within the cacheline + * FOLLOWING the GOSUB instruction must be NOPs." + */ + intel_dsb_align_tail(dsb); +} + void intel_dsb_finish(struct intel_dsb *dsb) { struct intel_crtc *crtc = dsb->crtc; diff --git a/drivers/gpu/drm/i915/display/intel_dsb.h b/drivers/gpu/drm/i915/display/intel_dsb.h index e843c52bf97c..8b2cf0a7b7e6 100644 --- a/drivers/gpu/drm/i915/display/intel_dsb.h +++ b/drivers/gpu/drm/i915/display/intel_dsb.h @@ -57,6 +57,8 @@ void intel_dsb_vblank_evade(struct intel_atomic_state *state, void intel_dsb_poll(struct intel_dsb *dsb, i915_reg_t reg, u32 mask, u32 val, int wait_us, int count); +void intel_dsb_gosub(struct intel_dsb *dsb, + struct intel_dsb *sub_dsb); void intel_dsb_chain(struct intel_atomic_state *state, struct intel_dsb *dsb, struct intel_dsb *chained_dsb, From patchwork Mon Apr 7 14:23:53 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Borah, Chaitanya Kumar" X-Patchwork-Id: 14040891 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 11667C369A2 for ; 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X-CSE-ConnectionGUID: oAShbt0HRGWdettHMhFm9w== X-CSE-MsgGUID: n5D5ASswRYykmRZ4BTzljg== X-IronPort-AV: E=McAfee;i="6700,10204,11397"; a="44572423" X-IronPort-AV: E=Sophos;i="6.15,194,1739865600"; d="scan'208";a="44572423" Received: from fmviesa001.fm.intel.com ([10.60.135.141]) by fmvoesa113.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 07 Apr 2025 07:39:22 -0700 X-CSE-ConnectionGUID: 7/ZTOKDRSdKp4g4hUQUw1g== X-CSE-MsgGUID: +jDoXracRm2jEymzCP8FTw== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.15,194,1739865600"; d="scan'208";a="158963692" Received: from dut-2a59.iind.intel.com ([10.190.239.113]) by fmviesa001.fm.intel.com with ESMTP; 07 Apr 2025 07:39:20 -0700 From: Chaitanya Kumar Borah To: intel-xe@lists.freedesktop.org, intel-gfx@lists.freedesktop.org Cc: ville.syrjala@linux.intel.com, uma.shankar@intel.com, chaitanya.kumar.borah@intel.com, animesh.manna@intel.com Subject: [PATCH 05/11] drm/i915/dsb: add intel_dsb_gosub_finish() Date: Mon, 7 Apr 2025 19:53:53 +0530 Message-Id: <20250407142359.1398410-6-chaitanya.kumar.borah@intel.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20250407142359.1398410-1-chaitanya.kumar.borah@intel.com> References: <20250407142359.1398410-1-chaitanya.kumar.borah@intel.com> MIME-Version: 1.0 X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" A DSB buffer which will be used for GOSUB execution does not need the DEWAKE mechanism but still need to be 64 bit aligned. Add helper to finish preparation of a dsb buffer to be executed with GOSUB instruction. Signed-off-by: Chaitanya Kumar Borah --- drivers/gpu/drm/i915/display/intel_dsb.c | 7 +++++++ drivers/gpu/drm/i915/display/intel_dsb.h | 1 + 2 files changed, 8 insertions(+) diff --git a/drivers/gpu/drm/i915/display/intel_dsb.c b/drivers/gpu/drm/i915/display/intel_dsb.c index 2cda6fc7857b..bffa02a0442c 100644 --- a/drivers/gpu/drm/i915/display/intel_dsb.c +++ b/drivers/gpu/drm/i915/display/intel_dsb.c @@ -585,6 +585,13 @@ void intel_dsb_gosub(struct intel_dsb *dsb, intel_dsb_align_tail(dsb); } +void intel_dsb_gosub_finish(struct intel_dsb *dsb) +{ + intel_dsb_align_tail(dsb); + + intel_dsb_buffer_flush_map(&dsb->dsb_buf); +} + void intel_dsb_finish(struct intel_dsb *dsb) { struct intel_crtc *crtc = dsb->crtc; diff --git a/drivers/gpu/drm/i915/display/intel_dsb.h b/drivers/gpu/drm/i915/display/intel_dsb.h index 8b2cf0a7b7e6..6900acd603b8 100644 --- a/drivers/gpu/drm/i915/display/intel_dsb.h +++ b/drivers/gpu/drm/i915/display/intel_dsb.h @@ -31,6 +31,7 @@ struct intel_dsb *intel_dsb_prepare(struct intel_atomic_state *state, enum intel_dsb_id dsb_id, unsigned int max_cmds); void intel_dsb_finish(struct intel_dsb *dsb); +void intel_dsb_gosub_finish(struct intel_dsb *dsb); void intel_dsb_cleanup(struct intel_dsb *dsb); void intel_dsb_reg_write(struct intel_dsb *dsb, i915_reg_t reg, u32 val); From patchwork Mon Apr 7 14:23:54 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Borah, Chaitanya Kumar" X-Patchwork-Id: 14040892 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 4D5D6C36010 for ; Mon, 7 Apr 2025 14:39:25 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id E097610E4B0; Mon, 7 Apr 2025 14:39:24 +0000 (UTC) Authentication-Results: gabe.freedesktop.org; dkim=pass (2048-bit key; unprotected) header.d=intel.com header.i=@intel.com header.b="hntl0RhL"; dkim-atps=neutral Received: from mgamail.intel.com (mgamail.intel.com [192.198.163.19]) by gabe.freedesktop.org (Postfix) with ESMTPS id EAD9B10E4BD; Mon, 7 Apr 2025 14:39:23 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1744036764; x=1775572764; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=usMAJ2Mxv0bBhPq+ePDSN2aPARo9WUXUse2/mLugf0w=; b=hntl0RhLyjWrEmqwN2R3tta4SeE4O5p+tuROpr44qhmMGRXwt0WumxHJ 5MrGyui/u1PRfQraeRsAc5KoipwFa9Hqbwh3XIe++HUlD0lz32J5N4Hj4 HQO/q4+Q2erQ0eOYggfhjRg1O0EodFTw6Y7+5XKGOrWVE474FZB3rIHV/ 9jehT6fnBlCJBSrNVhb506wDRQeILc/NCwkYxEAjlfwwcYbhby1zJMWW1 NQ9kaM/QBeNb45GBCd8chXHFQcFdl8nKlWrmC+G2x8Gb9edyNbOVc/zu2 d0FuTSluV+BiiRZ3XPXicAESsrTmxHFTQ6gyYB1Xc+cHCyCVizleA9OPx w==; X-CSE-ConnectionGUID: mepeHiqBQdKhKYJKYZs/VQ== X-CSE-MsgGUID: I+lpwoa3TpSiA8uobuLiIg== X-IronPort-AV: E=McAfee;i="6700,10204,11397"; a="44572427" X-IronPort-AV: E=Sophos;i="6.15,194,1739865600"; d="scan'208";a="44572427" Received: from fmviesa001.fm.intel.com ([10.60.135.141]) by fmvoesa113.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 07 Apr 2025 07:39:24 -0700 X-CSE-ConnectionGUID: wfIdsJjSR06Qbwp9dqav2w== X-CSE-MsgGUID: 9djreVpFRt2Mnv2fCWmTng== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.15,194,1739865600"; d="scan'208";a="158963704" Received: from dut-2a59.iind.intel.com ([10.190.239.113]) by fmviesa001.fm.intel.com with ESMTP; 07 Apr 2025 07:39:22 -0700 From: Chaitanya Kumar Borah To: intel-xe@lists.freedesktop.org, intel-gfx@lists.freedesktop.org Cc: ville.syrjala@linux.intel.com, uma.shankar@intel.com, chaitanya.kumar.borah@intel.com, animesh.manna@intel.com Subject: [PATCH 06/11] drm/i915/dsb: Add support for GOSUB interrupt Date: Mon, 7 Apr 2025 19:53:54 +0530 Message-Id: <20250407142359.1398410-7-chaitanya.kumar.borah@intel.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20250407142359.1398410-1-chaitanya.kumar.borah@intel.com> References: <20250407142359.1398410-1-chaitanya.kumar.borah@intel.com> MIME-Version: 1.0 X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" DSB raises an interrupt when there is a nested GOSUB command or illegal Head/Tail. Add support to log such errors in the DSB interrupt handler. Signed-off-by: Chaitanya Kumar Borah --- drivers/gpu/drm/i915/display/intel_dsb.c | 5 ++++- drivers/gpu/drm/i915/display/intel_dsb_regs.h | 2 ++ 2 files changed, 6 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/i915/display/intel_dsb.c b/drivers/gpu/drm/i915/display/intel_dsb.c index bffa02a0442c..da58f1c821c3 100644 --- a/drivers/gpu/drm/i915/display/intel_dsb.c +++ b/drivers/gpu/drm/i915/display/intel_dsb.c @@ -787,7 +787,7 @@ static void _intel_dsb_commit(struct intel_dsb *dsb, u32 ctrl, intel_de_write_fw(display, DSB_INTERRUPT(pipe, dsb->id), dsb_error_int_status(display) | DSB_PROG_INT_STATUS | - dsb_error_int_en(display) | DSB_PROG_INT_EN); + dsb_error_int_en(display) | DSB_PROG_INT_EN | DSB_GOSUB_INT_EN); intel_de_write_fw(display, DSB_HEAD(pipe, dsb->id), intel_dsb_head(dsb)); @@ -980,4 +980,7 @@ void intel_dsb_irq_handler(struct intel_display *display, if (errors & DSB_POLL_ERR_INT_STATUS) drm_err(display->drm, "[CRTC:%d:%s] DSB %d poll error\n", crtc->base.base.id, crtc->base.name, dsb_id); + if (errors & DSB_GOSUB_INT_STATUS) + drm_err(display->drm, "[CRTC:%d:%s] DSB %d gosub int error\n", + crtc->base.base.id, crtc->base.name, dsb_id); } diff --git a/drivers/gpu/drm/i915/display/intel_dsb_regs.h b/drivers/gpu/drm/i915/display/intel_dsb_regs.h index cb6e0e5624a6..230104f36145 100644 --- a/drivers/gpu/drm/i915/display/intel_dsb_regs.h +++ b/drivers/gpu/drm/i915/display/intel_dsb_regs.h @@ -51,11 +51,13 @@ #define DSB_RESET_SM_STATE_MASK REG_GENMASK(5, 4) #define DSB_RUN_SM_STATE_MASK REG_GENMASK(2, 0) #define DSB_INTERRUPT(pipe, id) _MMIO(DSBSL_INSTANCE(pipe, id) + 0x28) +#define DSB_GOSUB_INT_EN REG_BIT(21) /* ptl+ */ #define DSB_ATS_FAULT_INT_EN REG_BIT(20) /* mtl+ */ #define DSB_GTT_FAULT_INT_EN REG_BIT(19) #define DSB_RSPTIMEOUT_INT_EN REG_BIT(18) #define DSB_POLL_ERR_INT_EN REG_BIT(17) #define DSB_PROG_INT_EN REG_BIT(16) +#define DSB_GOSUB_INT_STATUS REG_BIT(5) /* ptl+ */ #define DSB_ATS_FAULT_INT_STATUS REG_BIT(4) /* mtl+ */ #define DSB_GTT_FAULT_INT_STATUS REG_BIT(3) #define DSB_RSPTIMEOUT_INT_STATUS REG_BIT(2) From patchwork Mon Apr 7 14:23:55 2025 Content-Type: text/plain; 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d="scan'208";a="158963720" Received: from dut-2a59.iind.intel.com ([10.190.239.113]) by fmviesa001.fm.intel.com with ESMTP; 07 Apr 2025 07:39:24 -0700 From: Chaitanya Kumar Borah To: intel-xe@lists.freedesktop.org, intel-gfx@lists.freedesktop.org Cc: ville.syrjala@linux.intel.com, uma.shankar@intel.com, chaitanya.kumar.borah@intel.com, animesh.manna@intel.com Subject: [PATCH 07/11] drm/i915: s/dsb_color_vblank/dsb_color Date: Mon, 7 Apr 2025 19:53:55 +0530 Message-Id: <20250407142359.1398410-8-chaitanya.kumar.borah@intel.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20250407142359.1398410-1-chaitanya.kumar.borah@intel.com> References: <20250407142359.1398410-1-chaitanya.kumar.borah@intel.com> MIME-Version: 1.0 X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" With double buffer gamma registers in the mix, we need not wait for vblank to execute gamma writes through dsb. Before we implement that s/dsb_color_vblank/dsb_color. Signed-off-by: Chaitanya Kumar Borah Reviewed-by: Ville Syrjälä --- drivers/gpu/drm/i915/display/intel_atomic.c | 4 +- drivers/gpu/drm/i915/display/intel_color.c | 38 +++++++++---------- drivers/gpu/drm/i915/display/intel_display.c | 10 ++--- .../drm/i915/display/intel_display_types.h | 2 +- 4 files changed, 27 insertions(+), 27 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_atomic.c b/drivers/gpu/drm/i915/display/intel_atomic.c index e83feca5c9c9..f85edb374c97 100644 --- a/drivers/gpu/drm/i915/display/intel_atomic.c +++ b/drivers/gpu/drm/i915/display/intel_atomic.c @@ -274,7 +274,7 @@ intel_crtc_duplicate_state(struct drm_crtc *crtc) crtc_state->do_async_flip = false; crtc_state->fb_bits = 0; crtc_state->update_planes = 0; - crtc_state->dsb_color_vblank = NULL; + crtc_state->dsb_color = NULL; crtc_state->dsb_commit = NULL; crtc_state->use_dsb = false; @@ -310,7 +310,7 @@ intel_crtc_destroy_state(struct drm_crtc *crtc, { struct intel_crtc_state *crtc_state = to_intel_crtc_state(state); - drm_WARN_ON(crtc->dev, crtc_state->dsb_color_vblank); + drm_WARN_ON(crtc->dev, crtc_state->dsb_color); drm_WARN_ON(crtc->dev, crtc_state->dsb_commit); __drm_atomic_helper_crtc_destroy_state(&crtc_state->uapi); diff --git a/drivers/gpu/drm/i915/display/intel_color.c b/drivers/gpu/drm/i915/display/intel_color.c index 98dddf72c0eb..bb2da3a53e9c 100644 --- a/drivers/gpu/drm/i915/display/intel_color.c +++ b/drivers/gpu/drm/i915/display/intel_color.c @@ -1339,8 +1339,8 @@ static void ilk_lut_write(const struct intel_crtc_state *crtc_state, { struct intel_display *display = to_intel_display(crtc_state); - if (crtc_state->dsb_color_vblank) - intel_dsb_reg_write(crtc_state->dsb_color_vblank, reg, val); + if (crtc_state->dsb_color) + intel_dsb_reg_write(crtc_state->dsb_color, reg, val); else intel_de_write_fw(display, reg, val); } @@ -1350,8 +1350,8 @@ static void ilk_lut_write_indexed(const struct intel_crtc_state *crtc_state, { struct intel_display *display = to_intel_display(crtc_state); - if (crtc_state->dsb_color_vblank) - intel_dsb_reg_write_indexed(crtc_state->dsb_color_vblank, reg, val); + if (crtc_state->dsb_color) + intel_dsb_reg_write_indexed(crtc_state->dsb_color, reg, val); else intel_de_write_fw(display, reg, val); } @@ -1389,7 +1389,7 @@ static void ilk_load_lut_8(const struct intel_crtc_state *crtc_state, for (i = 0; i < 256; i++) { ilk_lut_write(crtc_state, LGC_PALETTE(pipe, i), i9xx_lut_8(&lut[i])); - if (crtc_state->dsb_color_vblank) + if (crtc_state->dsb_color) ilk_lut_write(crtc_state, LGC_PALETTE(pipe, i), i9xx_lut_8(&lut[i])); } @@ -1917,7 +1917,7 @@ void intel_color_load_luts(const struct intel_crtc_state *crtc_state) { struct intel_display *display = to_intel_display(crtc_state); - if (crtc_state->dsb_color_vblank) + if (crtc_state->dsb_color) return; display->funcs.color->load_luts(crtc_state); @@ -1982,39 +1982,39 @@ void intel_color_prepare_commit(struct intel_atomic_state *state, if (!crtc_state->pre_csc_lut && !crtc_state->post_csc_lut) return; - crtc_state->dsb_color_vblank = intel_dsb_prepare(state, crtc, INTEL_DSB_1, 1024); - if (!crtc_state->dsb_color_vblank) + crtc_state->dsb_color = intel_dsb_prepare(state, crtc, INTEL_DSB_1, 1024); + if (!crtc_state->dsb_color) return; display->funcs.color->load_luts(crtc_state); if (crtc_state->use_dsb) { - intel_vrr_send_push(crtc_state->dsb_color_vblank, crtc_state); - intel_dsb_wait_vblank_delay(state, crtc_state->dsb_color_vblank); - intel_vrr_check_push_sent(crtc_state->dsb_color_vblank, crtc_state); - intel_dsb_interrupt(crtc_state->dsb_color_vblank); + intel_vrr_send_push(crtc_state->dsb_color, crtc_state); + intel_dsb_wait_vblank_delay(state, crtc_state->dsb_color); + intel_vrr_check_push_sent(crtc_state->dsb_color, crtc_state); + intel_dsb_interrupt(crtc_state->dsb_color); } - intel_dsb_finish(crtc_state->dsb_color_vblank); + intel_dsb_finish(crtc_state->dsb_color); } void intel_color_cleanup_commit(struct intel_crtc_state *crtc_state) { - if (crtc_state->dsb_color_vblank) { - intel_dsb_cleanup(crtc_state->dsb_color_vblank); - crtc_state->dsb_color_vblank = NULL; + if (crtc_state->dsb_color) { + intel_dsb_cleanup(crtc_state->dsb_color); + crtc_state->dsb_color = NULL; } } void intel_color_wait_commit(const struct intel_crtc_state *crtc_state) { - if (crtc_state->dsb_color_vblank) - intel_dsb_wait(crtc_state->dsb_color_vblank); + if (crtc_state->dsb_color) + intel_dsb_wait(crtc_state->dsb_color); } bool intel_color_uses_dsb(const struct intel_crtc_state *crtc_state) { - return crtc_state->dsb_color_vblank; + return crtc_state->dsb_color; } static bool intel_can_preload_luts(struct intel_atomic_state *state, diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c index dc7517da2ed5..69c1790199d3 100644 --- a/drivers/gpu/drm/i915/display/intel_display.c +++ b/drivers/gpu/drm/i915/display/intel_display.c @@ -7182,7 +7182,7 @@ static void intel_atomic_dsb_finish(struct intel_atomic_state *state, struct intel_crtc_state *new_crtc_state = intel_atomic_get_new_crtc_state(state, crtc); - if (!new_crtc_state->use_dsb && !new_crtc_state->dsb_color_vblank) + if (!new_crtc_state->use_dsb && !new_crtc_state->dsb_color) return; /* @@ -7229,7 +7229,7 @@ static void intel_atomic_dsb_finish(struct intel_atomic_state *state, skl_detach_scalers(new_crtc_state->dsb_commit, new_crtc_state); - if (!new_crtc_state->dsb_color_vblank) { + if (!new_crtc_state->dsb_color) { intel_dsb_wait_vblanks(new_crtc_state->dsb_commit, 1); intel_vrr_send_push(new_crtc_state->dsb_commit, new_crtc_state); @@ -7239,9 +7239,9 @@ static void intel_atomic_dsb_finish(struct intel_atomic_state *state, } } - if (new_crtc_state->dsb_color_vblank) + if (new_crtc_state->dsb_color) intel_dsb_chain(state, new_crtc_state->dsb_commit, - new_crtc_state->dsb_color_vblank, true); + new_crtc_state->dsb_color, true); intel_dsb_finish(new_crtc_state->dsb_commit); } @@ -7430,7 +7430,7 @@ static void intel_atomic_commit_tail(struct intel_atomic_state *state) * * FIXME get rid of this funny new->old swapping */ - old_crtc_state->dsb_color_vblank = fetch_and_zero(&new_crtc_state->dsb_color_vblank); + old_crtc_state->dsb_color = fetch_and_zero(&new_crtc_state->dsb_color); old_crtc_state->dsb_commit = fetch_and_zero(&new_crtc_state->dsb_commit); } diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h b/drivers/gpu/drm/i915/display/intel_display_types.h index 367b53a9eae2..99244c2449d4 100644 --- a/drivers/gpu/drm/i915/display/intel_display_types.h +++ b/drivers/gpu/drm/i915/display/intel_display_types.h @@ -1292,7 +1292,7 @@ struct intel_crtc_state { enum transcoder mst_master_transcoder; /* For DSB based pipe updates */ - struct intel_dsb *dsb_color_vblank, *dsb_commit; + struct intel_dsb *dsb_color, *dsb_commit; bool use_dsb; u32 psr2_man_track_ctl; From patchwork Mon Apr 7 14:23:56 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Borah, Chaitanya Kumar" X-Patchwork-Id: 14040894 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 79C14C369A3 for ; Mon, 7 Apr 2025 14:39:30 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 0A98F10E4C0; Mon, 7 Apr 2025 14:39:30 +0000 (UTC) Authentication-Results: gabe.freedesktop.org; dkim=pass (2048-bit key; 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a="44572445" X-IronPort-AV: E=Sophos;i="6.15,194,1739865600"; d="scan'208";a="44572445" Received: from fmviesa001.fm.intel.com ([10.60.135.141]) by fmvoesa113.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 07 Apr 2025 07:39:28 -0700 X-CSE-ConnectionGUID: VkGtgCaBTJikoHW2gjfr0Q== X-CSE-MsgGUID: yIquvMXfSAyZLTQNldoM/w== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.15,194,1739865600"; d="scan'208";a="158963739" Received: from dut-2a59.iind.intel.com ([10.190.239.113]) by fmviesa001.fm.intel.com with ESMTP; 07 Apr 2025 07:39:26 -0700 From: Chaitanya Kumar Borah To: intel-xe@lists.freedesktop.org, intel-gfx@lists.freedesktop.org Cc: ville.syrjala@linux.intel.com, uma.shankar@intel.com, chaitanya.kumar.borah@intel.com, animesh.manna@intel.com Subject: [PATCH 08/11] drm/i915: use GOSUB to program doubled buffered LUT registers Date: Mon, 7 Apr 2025 19:53:56 +0530 Message-Id: <20250407142359.1398410-9-chaitanya.kumar.borah@intel.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20250407142359.1398410-1-chaitanya.kumar.borah@intel.com> References: <20250407142359.1398410-1-chaitanya.kumar.borah@intel.com> MIME-Version: 1.0 X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" With addition of double buffered GAMMA registers in PTL, we can now program them in the active region. Use GOSUB instruction of DSB to program them. It is done in the following steps: 1. intel_color_prepare_commit() - If the platform supports, prepare a dsb instance (dsb_color) hooked to DSB0. - Add all the register write instructions to dsb_color through the load_lut() hook - Do not add the vrr_send_push() logic to the buffer as it should be taken care by dsb_commit instance of DSB0 - Finish preparation of the buffer by aligning it to 64 bit 2. intel_atomic_dsb_finish() - Add the gosub instruction into the dsb_commit instance of DSB0 using intel_dsb_gosub() - If needed, add the vrr_send_push() logic to dsb_commit after it Signed-off-by: Chaitanya Kumar Borah --- drivers/gpu/drm/i915/display/intel_color.c | 13 ++++++++--- drivers/gpu/drm/i915/display/intel_display.c | 22 ++++++++++++++++--- .../drm/i915/display/intel_display_device.h | 1 + 3 files changed, 30 insertions(+), 6 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_color.c b/drivers/gpu/drm/i915/display/intel_color.c index bb2da3a53e9c..49429404bd82 100644 --- a/drivers/gpu/drm/i915/display/intel_color.c +++ b/drivers/gpu/drm/i915/display/intel_color.c @@ -1982,20 +1982,27 @@ void intel_color_prepare_commit(struct intel_atomic_state *state, if (!crtc_state->pre_csc_lut && !crtc_state->post_csc_lut) return; - crtc_state->dsb_color = intel_dsb_prepare(state, crtc, INTEL_DSB_1, 1024); + if (HAS_DOUBLE_BUFFERED_LUT(display)) + crtc_state->dsb_color = intel_dsb_prepare(state, crtc, INTEL_DSB_0, 1024); + else + crtc_state->dsb_color = intel_dsb_prepare(state, crtc, INTEL_DSB_1, 1024); + if (!crtc_state->dsb_color) return; display->funcs.color->load_luts(crtc_state); - if (crtc_state->use_dsb) { + if (crtc_state->use_dsb && !HAS_DOUBLE_BUFFERED_LUT(display)) { intel_vrr_send_push(crtc_state->dsb_color, crtc_state); intel_dsb_wait_vblank_delay(state, crtc_state->dsb_color); intel_vrr_check_push_sent(crtc_state->dsb_color, crtc_state); intel_dsb_interrupt(crtc_state->dsb_color); } - intel_dsb_finish(crtc_state->dsb_color); + if (HAS_DOUBLE_BUFFERED_LUT(display)) + intel_dsb_gosub_finish(crtc_state->dsb_color); + else + intel_dsb_finish(crtc_state->dsb_color); } void intel_color_cleanup_commit(struct intel_crtc_state *crtc_state) diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c index 69c1790199d3..85e28b4c9e66 100644 --- a/drivers/gpu/drm/i915/display/intel_display.c +++ b/drivers/gpu/drm/i915/display/intel_display.c @@ -7239,9 +7239,25 @@ static void intel_atomic_dsb_finish(struct intel_atomic_state *state, } } - if (new_crtc_state->dsb_color) - intel_dsb_chain(state, new_crtc_state->dsb_commit, - new_crtc_state->dsb_color, true); + if (new_crtc_state->dsb_color) { + if (HAS_DOUBLE_BUFFERED_LUT(display)) { + intel_dsb_gosub(new_crtc_state->dsb_commit, + new_crtc_state->dsb_color); + + if (new_crtc_state->use_dsb) { + intel_dsb_wait_vblanks(new_crtc_state->dsb_commit, 1); + + intel_vrr_send_push(new_crtc_state->dsb_commit, new_crtc_state); + intel_dsb_wait_vblank_delay(state, new_crtc_state->dsb_commit); + intel_vrr_check_push_sent(new_crtc_state->dsb_commit, + new_crtc_state); + intel_dsb_interrupt(new_crtc_state->dsb_commit); + } + } else { + intel_dsb_chain(state, new_crtc_state->dsb_commit, + new_crtc_state->dsb_color, true); + } + } intel_dsb_finish(new_crtc_state->dsb_commit); } diff --git a/drivers/gpu/drm/i915/display/intel_display_device.h b/drivers/gpu/drm/i915/display/intel_display_device.h index 368b0d3417c2..14943b47824b 100644 --- a/drivers/gpu/drm/i915/display/intel_display_device.h +++ b/drivers/gpu/drm/i915/display/intel_display_device.h @@ -157,6 +157,7 @@ struct intel_display_platforms { #define HAS_DMC(__display) (DISPLAY_RUNTIME_INFO(__display)->has_dmc) #define HAS_DMC_WAKELOCK(__display) (DISPLAY_VER(__display) >= 20) #define HAS_DOUBLE_BUFFERED_M_N(__display) (DISPLAY_VER(__display) >= 9 || (__display)->platform.broadwell) +#define HAS_DOUBLE_BUFFERED_LUT(__display) (DISPLAY_VER(__display) >= 30) #define HAS_DOUBLE_WIDE(__display) (DISPLAY_VER(__display) < 4) #define HAS_DP20(__display) ((__display)->platform.dg2 || DISPLAY_VER(__display) >= 14) #define HAS_DPT(__display) (DISPLAY_VER(__display) >= 13) From patchwork Mon Apr 7 14:23:57 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Borah, Chaitanya Kumar" X-Patchwork-Id: 14040895 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 9273DC369A2 for ; Mon, 7 Apr 2025 14:39:31 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 2536010E4B5; Mon, 7 Apr 2025 14:39:31 +0000 (UTC) Authentication-Results: gabe.freedesktop.org; dkim=pass (2048-bit key; unprotected) header.d=intel.com header.i=@intel.com header.b="Sd12agiE"; dkim-atps=neutral Received: from mgamail.intel.com (mgamail.intel.com [192.198.163.19]) by gabe.freedesktop.org (Postfix) with ESMTPS id 8F64F10E4B5; Mon, 7 Apr 2025 14:39:30 +0000 (UTC) DKIM-Signature: v=1; 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d="scan'208";a="158963752" Received: from dut-2a59.iind.intel.com ([10.190.239.113]) by fmviesa001.fm.intel.com with ESMTP; 07 Apr 2025 07:39:28 -0700 From: Chaitanya Kumar Borah To: intel-xe@lists.freedesktop.org, intel-gfx@lists.freedesktop.org Cc: ville.syrjala@linux.intel.com, uma.shankar@intel.com, chaitanya.kumar.borah@intel.com, animesh.manna@intel.com Subject: [PATCH 09/11] drm/i915: Program DB LUT registers before vblank Date: Mon, 7 Apr 2025 19:53:57 +0530 Message-Id: <20250407142359.1398410-10-chaitanya.kumar.borah@intel.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20250407142359.1398410-1-chaitanya.kumar.borah@intel.com> References: <20250407142359.1398410-1-chaitanya.kumar.borah@intel.com> MIME-Version: 1.0 X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" Double Buffered LUT registers can be programmed in the active region. This patch implements the MMIO path for it. Program the registers after evading vblank. The HW latches on to the registers after delayed vblank. It takes around 1024 cdclk cycles(~one scanline) for this. Following assumptions have been made while making this change - Current vblank evasion time is sufficient for programming the LUT registers. - Current guardband calculation would be sufficient for the HW to latch on to the new values Signed-off-by: Chaitanya Kumar Borah --- drivers/gpu/drm/i915/display/intel_display.c | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c index 85e28b4c9e66..df9c992d2939 100644 --- a/drivers/gpu/drm/i915/display/intel_display.c +++ b/drivers/gpu/drm/i915/display/intel_display.c @@ -6725,10 +6725,12 @@ static void intel_pre_update_crtc(struct intel_atomic_state *state, static void intel_update_crtc(struct intel_atomic_state *state, struct intel_crtc *crtc) { + struct intel_display *display = to_intel_display(crtc); const struct intel_crtc_state *old_crtc_state = intel_atomic_get_old_crtc_state(state, crtc); struct intel_crtc_state *new_crtc_state = intel_atomic_get_new_crtc_state(state, crtc); + bool modeset = intel_crtc_needs_modeset(new_crtc_state); if (new_crtc_state->use_dsb) { intel_crtc_prepare_vblank_event(new_crtc_state, &crtc->dsb_event); @@ -6738,6 +6740,12 @@ static void intel_update_crtc(struct intel_atomic_state *state, /* Perform vblank evasion around commit operation */ intel_pipe_update_start(state, crtc); + if (!modeset && + intel_crtc_needs_color_update(new_crtc_state) && + !new_crtc_state->dsb_color && + HAS_DOUBLE_BUFFERED_LUT(display)) + intel_color_load_luts(new_crtc_state); + if (new_crtc_state->dsb_commit) intel_dsb_commit(new_crtc_state->dsb_commit, false); From patchwork Mon Apr 7 14:23:58 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Borah, Chaitanya Kumar" X-Patchwork-Id: 14040896 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id B9133C3601E for ; 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X-CSE-ConnectionGUID: EcuUNDIuRoWhUHA+2ryUOw== X-CSE-MsgGUID: gj5AzSqFRMWF6m4jY4EASg== X-IronPort-AV: E=McAfee;i="6700,10204,11397"; a="44572469" X-IronPort-AV: E=Sophos;i="6.15,194,1739865600"; d="scan'208";a="44572469" Received: from fmviesa001.fm.intel.com ([10.60.135.141]) by fmvoesa113.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 07 Apr 2025 07:39:32 -0700 X-CSE-ConnectionGUID: +YZsQvMGS+mNV1ZVNNTGOA== X-CSE-MsgGUID: nF/o7gh0QwKZW+0bcWnMkg== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.15,194,1739865600"; d="scan'208";a="158963769" Received: from dut-2a59.iind.intel.com ([10.190.239.113]) by fmviesa001.fm.intel.com with ESMTP; 07 Apr 2025 07:39:30 -0700 From: Chaitanya Kumar Borah To: intel-xe@lists.freedesktop.org, intel-gfx@lists.freedesktop.org Cc: ville.syrjala@linux.intel.com, uma.shankar@intel.com, chaitanya.kumar.borah@intel.com, animesh.manna@intel.com Subject: [PATCH 10/11] drm/i915/color: Do not pre-load LUTs with DB registers Date: Mon, 7 Apr 2025 19:53:58 +0530 Message-Id: <20250407142359.1398410-11-chaitanya.kumar.borah@intel.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20250407142359.1398410-1-chaitanya.kumar.borah@intel.com> References: <20250407142359.1398410-1-chaitanya.kumar.borah@intel.com> MIME-Version: 1.0 X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" Since Double Buffered LUT registers can be written in active region no need to preload them. Signed-off-by: Chaitanya Kumar Borah --- drivers/gpu/drm/i915/display/intel_color.c | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/drivers/gpu/drm/i915/display/intel_color.c b/drivers/gpu/drm/i915/display/intel_color.c index 49429404bd82..ba2b2498d1da 100644 --- a/drivers/gpu/drm/i915/display/intel_color.c +++ b/drivers/gpu/drm/i915/display/intel_color.c @@ -2027,9 +2027,13 @@ bool intel_color_uses_dsb(const struct intel_crtc_state *crtc_state) static bool intel_can_preload_luts(struct intel_atomic_state *state, struct intel_crtc *crtc) { + struct intel_display *display = to_intel_display(state); const struct intel_crtc_state *old_crtc_state = intel_atomic_get_old_crtc_state(state, crtc); + if (HAS_DOUBLE_BUFFERED_LUT(display)) + return false; + return !old_crtc_state->post_csc_lut && !old_crtc_state->pre_csc_lut; } From patchwork Mon Apr 7 14:23:59 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Borah, Chaitanya Kumar" X-Patchwork-Id: 14040897 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 2A147C36010 for ; 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X-CSE-ConnectionGUID: 35ZrDxK4SDC+mh+9ayE/qg== X-CSE-MsgGUID: na6tAPrSS/qiO5X9aL1mag== X-IronPort-AV: E=McAfee;i="6700,10204,11397"; a="44572491" X-IronPort-AV: E=Sophos;i="6.15,194,1739865600"; d="scan'208";a="44572491" Received: from fmviesa001.fm.intel.com ([10.60.135.141]) by fmvoesa113.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 07 Apr 2025 07:39:34 -0700 X-CSE-ConnectionGUID: fWrMIrPsQvCzXQDyLFQayg== X-CSE-MsgGUID: J4e+oP8mSGmt/h++sLH8xQ== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.15,194,1739865600"; d="scan'208";a="158963785" Received: from dut-2a59.iind.intel.com ([10.190.239.113]) by fmviesa001.fm.intel.com with ESMTP; 07 Apr 2025 07:39:32 -0700 From: Chaitanya Kumar Borah To: intel-xe@lists.freedesktop.org, intel-gfx@lists.freedesktop.org Cc: ville.syrjala@linux.intel.com, uma.shankar@intel.com, chaitanya.kumar.borah@intel.com, animesh.manna@intel.com Subject: [PATCH 11/11] drm/i915: Disable updating of LUT values during vblank Date: Mon, 7 Apr 2025 19:53:59 +0530 Message-Id: <20250407142359.1398410-12-chaitanya.kumar.borah@intel.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20250407142359.1398410-1-chaitanya.kumar.borah@intel.com> References: <20250407142359.1398410-1-chaitanya.kumar.borah@intel.com> MIME-Version: 1.0 X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" Do not schedule vblank worker for LUT update if the registers are double buffered Signed-off-by: Chaitanya Kumar Borah --- drivers/gpu/drm/i915/display/intel_crtc.c | 5 ++++- 1 file changed, 4 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/i915/display/intel_crtc.c b/drivers/gpu/drm/i915/display/intel_crtc.c index 5b2603ef2ff7..fd6d52712462 100644 --- a/drivers/gpu/drm/i915/display/intel_crtc.c +++ b/drivers/gpu/drm/i915/display/intel_crtc.c @@ -418,10 +418,13 @@ int intel_crtc_get_pipe_from_crtc_id_ioctl(struct drm_device *dev, void *data, static bool intel_crtc_needs_vblank_work(const struct intel_crtc_state *crtc_state) { + struct intel_display *display = to_intel_display(crtc_state); + return crtc_state->hw.active && !crtc_state->preload_luts && !intel_crtc_needs_modeset(crtc_state) && - intel_crtc_needs_color_update(crtc_state) && + (intel_crtc_needs_color_update(crtc_state) && + !HAS_DOUBLE_BUFFERED_LUT(display)) && !intel_color_uses_dsb(crtc_state) && !crtc_state->use_dsb; }