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pr=C From: Ayan Kumar Halder To: CC: Ayan Kumar Halder , Stefano Stabellini , Julien Grall , Bertrand Marquis , Michal Orzel , "Volodymyr Babchuk" Subject: [PATCH v5 1/3] xen/arm: Move some of the functions to common file Date: Mon, 7 Apr 2025 19:44:41 +0100 Message-ID: <20250407184443.1790995-2-ayan.kumar.halder@amd.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20250407184443.1790995-1-ayan.kumar.halder@amd.com> References: <20250407184443.1790995-1-ayan.kumar.halder@amd.com> MIME-Version: 1.0 Received-SPF: None (SATLEXMB04.amd.com: ayan.kumar.halder@amd.com does not designate permitted sender hosts) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: BN1PEPF0000468D:EE_|CH2PR12MB9517:EE_ X-MS-Office365-Filtering-Correlation-Id: 4ae83a01-6e8d-4689-554e-08dd760448af X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|376014|36860700013|1800799024|82310400026; X-Microsoft-Antispam-Message-Info: YIupwtHFGsMiZTJEqUMc3STQd2TqKQPbs9zjQ9lfzai4NTW962yB3hnDcti0GMPA9pgVjOarbY4ubZh+9veqDRm4u+A/6mKWkl482taWHhnxc3IOYr/9Ug3oEZZWW99woCKDW50ceB2qdu/vOvKcmi5PAUXEYhx41uaPnX6Fpo0GXbjZymJfl/brnQTSJccNfyXFTd/gF3EV0g7Z1OnheJQ1O1qtVmhPThs21Ff45OFDZV+M0SfwTsxedt68mpcDUJSvTqpgcRxRR9qHEZpfjRCbgog7pk6sNba6U5RAasglzs985Qwfqrwx9m+j0ohkKrFkDx0ekYPtFzyeePJbQQYENK9dX/aUWFQ5X3Fu5x/SVJtLNkPJB2+JQru4FbFcHR8mUUqE90TNwbMPpZwwizLbL67MBtMNBj+7cGzIMo+SF7ovN6MJO2Cf/WQO3HPGO5S/IMh76GDuZHjiav/w+OC64t9s3DsV9X7apE/4+WnqZlnvLWy6UVhXqfURBZ5nH79E/2tTb6ZHCDA67cLUVdrPiYreDURRaidRn5TRPjf4INm1rkOlpbUO+glDOypV6iYuif+sAyw+NX9qve6hrb+uWfkKALeiz3lyDeFasrZfi4W5TtG+HVHhdlzJG9nvZpnBz9BpQ020f8cSontn1IZaGpWBNjiU0pyMvxAmOS84pePBEjp9oRLEYGY0i8dk3Cn1LbZilPRIO1kqx0FHNhjjk/s6bFGN7KBRtaVQf8eQ01cr8LbHt3fmpB+9zXuJg2SrujDFP8LVQ3oXbqGh8WjrEeGPEX/FrMDtcBzq3tPVuA0y7MhlwO9V60suGJot1Sh5tBgASjvtmewo4IBPG2b0iq+26bVDgooPXXVFAYphLefs1Hv3Y6rmZo9mkFdMCL0QLVqQHp9xrtdQBy792Aw5LZBXg5SeimhbU1BVJac7pM9HvOSEH41N6GeSXXGFxoADUh7sqRTQKYR/Na1QWIoTlcbyL/f55etS6+f0Ul2Uz6ePSFw7ibPOpfSNpyfm7lRF6GB9VmdOts7ieZHLutnnbND3rFG4RCBAPBhREs88MTRiO6vBDljw1TckLk5t9A3z8GBy/u29f0zQlQBCds1KJjIhlnCWrHMN11fzj2lO2OOzNc8reINMcVPPjJZ+qAGh1TNYYZHMeluAFu9lfSSNUXIFGoaYIKv9VyJZKe8sJLN9tm3cW9okWXmgAsIoTQ2Zqo23VfPz+jqD8mQfiBPnMTvKIdU4ZVaPJAUCMcqlUtQSjg3xqqUYmZOEsti7oxL9RBFGXdWG8mE1lIL3UEQfrMYrgmU/RQ++1CXPSpKoE8wAOqNluHzEbj9gjgIGtHDlkiYOa8g5ICRiYIcwHlRF4j5kQSevavt7I2Ti02TcL/iNbi8BLL6PwC5gkfPU6x3a/VzdfjXB7pf5KJxMH+xOE3erQRQj23v55FKLpGVLcVCE/7gpeEiJPZEC5m0HpA2PstjHV5iNb4xOIsrM1zPydeGQU+DXlhUuzPQk1Gw= X-Forefront-Antispam-Report: CIP:165.204.84.17;CTRY:US;LANG:en;SCL:1;SRV:;IPV:CAL;SFV:NSPM;H:SATLEXMB04.amd.com;PTR:InfoDomainNonexistent;CAT:NONE;SFS:(13230040)(376014)(36860700013)(1800799024)(82310400026);DIR:OUT;SFP:1101; X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 07 Apr 2025 18:44:52.7446 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 4ae83a01-6e8d-4689-554e-08dd760448af X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: BN1PEPF0000468D.namprd05.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: CH2PR12MB9517 Added a new file common.inc to hold the common earlyboot MPU regions configurations across arm64 and arm32. prepare_xen_region, fail_insufficient_regions() will be used by both arm32 and arm64. Thus, they have been moved to common.inc. *_PRBAR are moved to arm64/sysregs.h. *_PRLAR are moved to common.inc as they are common between arm32 and arm64. Introduce WRITE_SYSREG_ASM to write to the system registers from the common asm file. Signed-off-by: Ayan Kumar Halder Reviewed-by: Luca Fancellu --- Changes from v1 - 1. enable_mpu() now sets HMAIR{0,1} registers. This is similar to what is being done in enable_mmu(). All the mm related configurations happen in this function. 2. Fixed some typos. v2 - 1. Extracted the arm64 head.S functions/macros in a common file. v3 - 1. Moved *_PRLAR are moved to prepare_xen_region.inc 2. enable_boot_cpu_mm() is preserved in mpu/head.S. 3. STORE_SYSREG is renamed as WRITE_SYSREG_ASM() 4. LOAD_SYSREG is removed. 5. No need to save/restore lr in enable_boot_cpu_mm(). IOW, keep it as it was in the original code. v4 - 1. Rename prepare_xen_region.inc to common.inc 2. enable_secondary_cpu_mm() is moved back to mpu/head.S. xen/arch/arm/arm64/mpu/head.S | 78 +---------------------- xen/arch/arm/include/asm/arm64/sysregs.h | 11 ++++ xen/arch/arm/include/asm/mpu/common.inc | 79 ++++++++++++++++++++++++ 3 files changed, 91 insertions(+), 77 deletions(-) create mode 100644 xen/arch/arm/include/asm/mpu/common.inc diff --git a/xen/arch/arm/arm64/mpu/head.S b/xen/arch/arm/arm64/mpu/head.S index ed01993d85..4d76a3166e 100644 --- a/xen/arch/arm/arm64/mpu/head.S +++ b/xen/arch/arm/arm64/mpu/head.S @@ -3,83 +3,7 @@ * Start-of-day code for an Armv8-R MPU system. */ -#include -#include - -/* Backgroud region enable/disable */ -#define SCTLR_ELx_BR BIT(17, UL) - -#define REGION_TEXT_PRBAR 0x38 /* SH=11 AP=10 XN=00 */ -#define REGION_RO_PRBAR 0x3A /* SH=11 AP=10 XN=10 */ -#define REGION_DATA_PRBAR 0x32 /* SH=11 AP=00 XN=10 */ -#define REGION_DEVICE_PRBAR 0x22 /* SH=10 AP=00 XN=10 */ - -#define REGION_NORMAL_PRLAR 0x0f /* NS=0 ATTR=111 EN=1 */ -#define REGION_DEVICE_PRLAR 0x09 /* NS=0 ATTR=100 EN=1 */ - -/* - * Macro to prepare and set a EL2 MPU memory region. - * We will also create an according MPU memory region entry, which - * is a structure of pr_t, in table \prmap. - * - * sel: region selector - * base: reg storing base address - * limit: reg storing limit address - * prbar: store computed PRBAR_EL2 value - * prlar: store computed PRLAR_EL2 value - * maxcount: maximum number of EL2 regions supported - * attr_prbar: PRBAR_EL2-related memory attributes. If not specified it will be - * REGION_DATA_PRBAR - * attr_prlar: PRLAR_EL2-related memory attributes. If not specified it will be - * REGION_NORMAL_PRLAR - * - * Preserves \maxcount - * Output: - * \sel: Next available region selector index. - * Clobbers \base, \limit, \prbar, \prlar - * - * Note that all parameters using registers should be distinct. - */ -.macro prepare_xen_region, sel, base, limit, prbar, prlar, maxcount, attr_prbar=REGION_DATA_PRBAR, attr_prlar=REGION_NORMAL_PRLAR - /* Check if the region is empty */ - cmp \base, \limit - beq 1f - - /* Check if the number of regions exceeded the count specified in MPUIR_EL2 */ - cmp \sel, \maxcount - bge fail_insufficient_regions - - /* Prepare value for PRBAR_EL2 reg and preserve it in \prbar.*/ - and \base, \base, #MPU_REGION_MASK - mov \prbar, #\attr_prbar - orr \prbar, \prbar, \base - - /* Limit address should be inclusive */ - sub \limit, \limit, #1 - and \limit, \limit, #MPU_REGION_MASK - mov \prlar, #\attr_prlar - orr \prlar, \prlar, \limit - - msr PRSELR_EL2, \sel - isb - msr PRBAR_EL2, \prbar - msr PRLAR_EL2, \prlar - dsb sy - isb - - add \sel, \sel, #1 - -1: -.endm - -/* - * Failure caused due to insufficient MPU regions. - */ -FUNC_LOCAL(fail_insufficient_regions) - PRINT("- Selected MPU region is above the implemented number in MPUIR_EL2 -\r\n") -1: wfe - b 1b -END(fail_insufficient_regions) +#include /* * Enable EL2 MPU and data cache diff --git a/xen/arch/arm/include/asm/arm64/sysregs.h b/xen/arch/arm/include/asm/arm64/sysregs.h index b593e4028b..3ee3715430 100644 --- a/xen/arch/arm/include/asm/arm64/sysregs.h +++ b/xen/arch/arm/include/asm/arm64/sysregs.h @@ -462,6 +462,15 @@ #define ZCR_ELx_LEN_SIZE 9 #define ZCR_ELx_LEN_MASK 0x1ff +#define REGION_TEXT_PRBAR 0x38 /* SH=11 AP=10 XN=00 */ +#define REGION_RO_PRBAR 0x3A /* SH=11 AP=10 XN=10 */ +#define REGION_DATA_PRBAR 0x32 /* SH=11 AP=00 XN=10 */ +#define REGION_DEVICE_PRBAR 0x22 /* SH=10 AP=00 XN=10 */ + +#define WRITE_SYSREG_ASM(v, name) "msr " __stringify(name,) #v; + +#ifndef __ASSEMBLY__ + /* Access to system registers */ #define WRITE_SYSREG64(v, name) do { \ @@ -481,6 +490,8 @@ #define WRITE_SYSREG_LR(v, index) WRITE_SYSREG(v, ICH_LR_REG(index)) #define READ_SYSREG_LR(index) READ_SYSREG(ICH_LR_REG(index)) +#endif /* __ASSEMBLY__ */ + #endif /* _ASM_ARM_ARM64_SYSREGS_H */ /* diff --git a/xen/arch/arm/include/asm/mpu/common.inc b/xen/arch/arm/include/asm/mpu/common.inc new file mode 100644 index 0000000000..47868a1526 --- /dev/null +++ b/xen/arch/arm/include/asm/mpu/common.inc @@ -0,0 +1,79 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include +#include + +/* Backgroud region enable/disable */ +#define SCTLR_ELx_BR BIT(17, UL) + +#define REGION_NORMAL_PRLAR 0x0f /* NS=0 ATTR=111 EN=1 */ +#define REGION_DEVICE_PRLAR 0x09 /* NS=0 ATTR=100 EN=1 */ + +/* + * Macro to prepare and set a EL2 MPU memory region. + * We will also create an according MPU memory region entry, which + * is a structure of pr_t, in table \prmap. + * + * sel: region selector + * base: reg storing base address + * limit: reg storing limit address + * prbar: store computed PRBAR_EL2 value + * prlar: store computed PRLAR_EL2 value + * maxcount: maximum number of EL2 regions supported + * attr_prbar: PRBAR_EL2-related memory attributes. If not specified it will be + * REGION_DATA_PRBAR + * attr_prlar: PRLAR_EL2-related memory attributes. If not specified it will be + * REGION_NORMAL_PRLAR + * + * Preserves maxcount + * Output: + * sel: Next available region selector index. + * Clobbers base, limit, prbar, prlar + * + * Note that all parameters using registers should be distinct. + */ +.macro prepare_xen_region, sel, base, limit, prbar, prlar, maxcount, attr_prbar=REGION_DATA_PRBAR, attr_prlar=REGION_NORMAL_PRLAR + /* Check if the region is empty */ + cmp \base, \limit + beq 1f + + /* Check if the number of regions exceeded the count specified in MPUIR_EL2 */ + cmp \sel, \maxcount + bge fail_insufficient_regions + + /* Prepare value for PRBAR_EL2 reg and preserve it in \prbar.*/ + and \base, \base, #MPU_REGION_MASK + mov \prbar, #\attr_prbar + orr \prbar, \prbar, \base + + /* Limit address should be inclusive */ + sub \limit, \limit, #1 + and \limit, \limit, #MPU_REGION_MASK + mov \prlar, #\attr_prlar + orr \prlar, \prlar, \limit + + WRITE_SYSREG_ASM(\sel, PRSELR_EL2) + isb + WRITE_SYSREG_ASM(\prbar, PRBAR_EL2) + WRITE_SYSREG_ASM(\prlar, PRLAR_EL2) + dsb sy + isb + + add \sel, \sel, #1 + +1: +.endm + +/* Failure caused due to insufficient MPU regions. */ +FUNC_LOCAL(fail_insufficient_regions) + PRINT("- Selected MPU region is above the implemented number in MPUIR_EL2 -\r\n") +1: wfe + b 1b +END(fail_insufficient_regions) + +/* + * Local variables: + * mode: ASM + * indent-tabs-mode: nil + * End: + */ From patchwork Mon Apr 7 18:44:42 2025 Content-Type: text/plain; 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pr=C From: Ayan Kumar Halder To: CC: Ayan Kumar Halder , Stefano Stabellini , Julien Grall , Bertrand Marquis , Michal Orzel , "Volodymyr Babchuk" Subject: [PATCH v5 2/3] xen/arm32: Create the same boot-time MPU regions as arm64 Date: Mon, 7 Apr 2025 19:44:42 +0100 Message-ID: <20250407184443.1790995-3-ayan.kumar.halder@amd.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20250407184443.1790995-1-ayan.kumar.halder@amd.com> References: <20250407184443.1790995-1-ayan.kumar.halder@amd.com> MIME-Version: 1.0 Received-SPF: None (SATLEXMB03.amd.com: ayan.kumar.halder@amd.com does not designate permitted sender hosts) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: BN3PEPF0000B076:EE_|CY8PR12MB7315:EE_ X-MS-Office365-Filtering-Correlation-Id: ce74ec89-9b62-48eb-658d-08dd76044868 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|1800799024|82310400026|376014|36860700013; X-Microsoft-Antispam-Message-Info: wr64JjUUN4jmxqpVvLq6G8R0p+cFgyVn9ppz7HyR/lZcGv6lmG7CUQaZ3EytESnvhq9FlnBVaxQgMvaEFe/iN3N0AO68juJuAGB5O2So6b/7b0Vt4oJrsO22z6IopH879MwxmMvBs0h5h+KNC42hPaG9E15opPaS6S5o359CNkkPY/5YHBpjGS2oR3X8/fhGd441NSECU7LbOTeu+H0cfsdIpbwuhmoPvg2rcsHmXrfX5ZaJ005/ZTyjFII9YJPCSCAOOnRUw7FBVphAhBLdd5A6D0STbscmtg/1jBsfTSEIJ9/GnX3RKWM0jAf19OLDkqpguwzLtujH3J1a+dVAiDnH0ZUAD9FHTJSzXQ56CKiF2a3sIaof1Fg3S/o1OYvMVHQjgtPBVu+YGEADNX3oROjW+/F0MTMfzTXegep3JBJyxsm6zXGpLet2gG4ELb+YTCDr+YThBZHBF2H00yyVLKNXRR3/ecfUKIsB51yxbnJuF4/lMA+Q+UTi3baC0swTh/2o8DWpfAh4LsbMB6KPdmhq+0W/A1Y0ntjm4AWDb+alv0WcCuGLr/bPGVg8jEiemu2g3aMCrI3bAMU/V4sE898spi+Xoe32rbXWc3o6XPO+BT+1ThI2jeW+i2N3or0JtgEHoL64gNjY3NtDP2pnC869C4GUOo2F159NNfeO5By0uRQ9axe6Et9U/ejBHbZL0z3T8T4Q73mYiPZtRtreAN4nMkCjTOKE/K5l9vLabzBIZ0QGRxpsjAyAT5xl5A3EQGozPHBXgDBGVRzJ7X/j8sagf3dTGe7p2ScQlp8ngq5bShKf4gQxlUk6z403jhaUgKeiijCvDlMMlhlLMnh9rfwfn5DHx/fReLJtqJfY1VIarxqoTRfBaRTJzHjyRtA9LO4wzcaDcAIrg5mrbll15BRxuxrjCoIoHqgszOvMug3Gr6nvC2QTQO2VkhZ78KTgVrdvyyTCzbAUtwNEjWPJoq6c5PCTcrvJff3gF4om0hAbyFQAEdL3P1Hkep3er8hTmV6S+oFchNm7VS1iACjKetHLHhteq6WLDv71YRuFs79FmmQd/Rbc0q8K1r33bPXpvUDqvmrrumU/TGsQaK3vsYoB+hQoqaOiFpnMWShh5BMOHA/dbvD7oxxDPToz4sBjPTybRuUx5MOtVhcnvSUIr0Ppp1WnwBZUquwHD1blCicsupSH6MOa/zr0AWrSbN7it5LO+5YMBI6gjpE7AKWM931VjK/bcYEo511zs0SiJtyApX1YSFZqvfVR9OmDeRFYmyrercUO0wFw+1lQTtj5ZBHjqYZvzuNdSWxCIW5lHJIz/HVTB9qg7z/GiAlaJVTo9/tg6rDFKUC4vnUCVZ0L7eXOfmLX0oNQajJB1Xc0sBCnPLbTr5xWegoFK2nvzyoElSK/XnVXq9xtIVtF+wUwJ5CQgpDOamcCri80KniA4dwPTbh+DMoHz3xK31ozXALLqUP9fsRJWTjpIjLcC8zuqA== X-Forefront-Antispam-Report: CIP:165.204.84.17;CTRY:US;LANG:en;SCL:1;SRV:;IPV:CAL;SFV:NSPM;H:SATLEXMB03.amd.com;PTR:InfoDomainNonexistent;CAT:NONE;SFS:(13230040)(1800799024)(82310400026)(376014)(36860700013);DIR:OUT;SFP:1101; X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 07 Apr 2025 18:44:52.2757 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: ce74ec89-9b62-48eb-658d-08dd76044868 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB03.amd.com] X-MS-Exchange-CrossTenant-AuthSource: BN3PEPF0000B076.namprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: CY8PR12MB7315 We have created the same boot-time MPU protection regions as Armv8-R AArch64. Also, we have defined *_PRBAR macros for arm32. The only difference from arm64 is that XN is 1-bit for arm32. The macros have been defined in mpu/cpregs.h. Also defined WRITE_SYSREG_ASM() to write to system registers in assembly. Signed-off-by: Ayan Kumar Halder Reviewed-by: Luca Fancellu --- Changes from v1 - 1. enable_mpu() now sets HMAIR{0,1} registers. This is similar to what is being done in enable_mmu(). All the mm related configurations happen in this function. 2. Fixed some typos. v2 - 1. Include the common prepare_xen_region.inc in head.S. 2. Define LOAD_SYSREG()/STORE_SYSREG() for arm32. v3 - 1. Rename STORE_SYSREG() as WRITE_SYSREG_ASM() 2. enable_boot_cpu_mm() is defined in head.S v4 - 1. *_PRBAR is moved to arm32/sysregs.h. 2. MPU specific CP15 system registers are defined in mpu/cpregs.h. xen/arch/arm/arm32/Makefile | 1 + xen/arch/arm/arm32/mpu/Makefile | 1 + xen/arch/arm/arm32/mpu/head.S | 101 +++++++++++++++++++++++ xen/arch/arm/include/asm/arm32/sysregs.h | 7 ++ xen/arch/arm/include/asm/cpregs.h | 4 + xen/arch/arm/include/asm/mpu/cpregs.h | 24 ++++++ 6 files changed, 138 insertions(+) create mode 100644 xen/arch/arm/arm32/mpu/Makefile create mode 100644 xen/arch/arm/arm32/mpu/head.S create mode 100644 xen/arch/arm/include/asm/mpu/cpregs.h diff --git a/xen/arch/arm/arm32/Makefile b/xen/arch/arm/arm32/Makefile index 40a2b4803f..537969d753 100644 --- a/xen/arch/arm/arm32/Makefile +++ b/xen/arch/arm/arm32/Makefile @@ -1,5 +1,6 @@ obj-y += lib/ obj-$(CONFIG_MMU) += mmu/ +obj-$(CONFIG_MPU) += mpu/ obj-$(CONFIG_EARLY_PRINTK) += debug.o obj-y += domctl.o diff --git a/xen/arch/arm/arm32/mpu/Makefile b/xen/arch/arm/arm32/mpu/Makefile new file mode 100644 index 0000000000..3340058c08 --- /dev/null +++ b/xen/arch/arm/arm32/mpu/Makefile @@ -0,0 +1 @@ +obj-y += head.o diff --git a/xen/arch/arm/arm32/mpu/head.S b/xen/arch/arm/arm32/mpu/head.S new file mode 100644 index 0000000000..84e9f1f8ec --- /dev/null +++ b/xen/arch/arm/arm32/mpu/head.S @@ -0,0 +1,101 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Start-of-day code for an Armv8-R MPU system. + */ + +#include +#include +#include + +/* + * Set up the memory attribute type tables and enable EL2 MPU and data cache. + * If the Background region is enabled, then the MPU uses the default memory + * map as the Background region for generating the memory + * attributes when MPU is disabled. + * Since the default memory map of the Armv8-R AArch32 architecture is + * IMPLEMENTATION DEFINED, we intend to turn off the Background region here. + * + * Clobbers r0 - r1 + */ +FUNC_LOCAL(enable_mpu) + /* Set up memory attribute type tables */ + mov_w r0, MAIR0VAL + mov_w r1, MAIR1VAL + mcr CP32(r0, HMAIR0) + mcr CP32(r1, HMAIR1) + + mrc CP32(r0, HSCTLR) + bic r0, r0, #SCTLR_ELx_BR /* Disable Background region */ + orr r0, r0, #SCTLR_Axx_ELx_M /* Enable MPU */ + orr r0, r0, #SCTLR_Axx_ELx_C /* Enable D-cache */ + mcr CP32(r0, HSCTLR) + isb + + ret +END(enable_mpu) + +/* + * Maps the various sections of Xen (described in xen.lds.S) as different MPU + * regions. + * + * Clobbers r0 - r5 + * + */ +FUNC(enable_boot_cpu_mm) + /* Get the number of regions specified in MPUIR_EL2 */ + mrc CP32(r5, MPUIR_EL2) + and r5, r5, #NUM_MPU_REGIONS_MASK + + /* x0: region sel */ + mov r0, #0 + /* Xen text section. */ + mov_w r1, _stext + mov_w r2, _etext + prepare_xen_region r0, r1, r2, r3, r4, r5, attr_prbar=REGION_TEXT_PRBAR + + /* Xen read-only data section. */ + mov_w r1, _srodata + mov_w r2, _erodata + prepare_xen_region r0, r1, r2, r3, r4, r5, attr_prbar=REGION_RO_PRBAR + + /* Xen read-only after init and data section. (RW data) */ + mov_w r1, __ro_after_init_start + mov_w r2, __init_begin + prepare_xen_region r0, r1, r2, r3, r4, r5 + + /* Xen code section. */ + mov_w r1, __init_begin + mov_w r2, __init_data_begin + prepare_xen_region r0, r1, r2, r3, r4, r5, attr_prbar=REGION_TEXT_PRBAR + + /* Xen data and BSS section. */ + mov_w r1, __init_data_begin + mov_w r2, __bss_end + prepare_xen_region r0, r1, r2, r3, r4, r5 + +#ifdef CONFIG_EARLY_PRINTK + /* Xen early UART section. */ + mov_w r1, CONFIG_EARLY_UART_BASE_ADDRESS + mov_w r2, (CONFIG_EARLY_UART_BASE_ADDRESS + CONFIG_EARLY_UART_SIZE) + prepare_xen_region r0, r1, r2, r3, r4, r5, attr_prbar=REGION_DEVICE_PRBAR, attr_prlar=REGION_DEVICE_PRLAR +#endif + + b enable_mpu +END(enable_boot_cpu_mm) + +/* + * We don't yet support secondary CPUs bring-up. Implement a dummy helper to + * please the common code. + */ +FUNC(enable_secondary_cpu_mm) + PRINT("- SMP not enabled yet -\r\n") +1: wfe + b 1b +END(enable_secondary_cpu_mm) + +/* + * Local variables: + * mode: ASM + * indent-tabs-mode: nil + * End: + */ diff --git a/xen/arch/arm/include/asm/arm32/sysregs.h b/xen/arch/arm/include/asm/arm32/sysregs.h index 22871999af..a90d1610a1 100644 --- a/xen/arch/arm/include/asm/arm32/sysregs.h +++ b/xen/arch/arm/include/asm/arm32/sysregs.h @@ -20,6 +20,13 @@ * uses r0 as a placeholder register. */ #define CMD_CP32(name...) "mcr " __stringify(CP32(r0, name)) ";" +#define REGION_TEXT_PRBAR 0x18 /* SH=11 AP=10 XN=0 */ +#define REGION_RO_PRBAR 0x1D /* SH=11 AP=10 XN=1 */ +#define REGION_DATA_PRBAR 0x19 /* SH=11 AP=00 XN=1 */ +#define REGION_DEVICE_PRBAR 0x11 /* SH=10 AP=00 XN=1 */ + +#define WRITE_SYSREG_ASM(v, name) mcr CP32(v, name) + #ifndef __ASSEMBLY__ /* C wrappers */ diff --git a/xen/arch/arm/include/asm/cpregs.h b/xen/arch/arm/include/asm/cpregs.h index aec9e8f329..6019a2cbdd 100644 --- a/xen/arch/arm/include/asm/cpregs.h +++ b/xen/arch/arm/include/asm/cpregs.h @@ -1,6 +1,10 @@ #ifndef __ASM_ARM_CPREGS_H #define __ASM_ARM_CPREGS_H +#ifdef CONFIG_MPU +#include +#endif + /* * AArch32 Co-processor registers. * diff --git a/xen/arch/arm/include/asm/mpu/cpregs.h b/xen/arch/arm/include/asm/mpu/cpregs.h new file mode 100644 index 0000000000..6b20c7ceae --- /dev/null +++ b/xen/arch/arm/include/asm/mpu/cpregs.h @@ -0,0 +1,24 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef __ASM_ARM_MPU_CPREGS_H +#define __ASM_ARM_MPU_CPREGS_H + +/* CP15 CR0: MPU Type Register */ +#define HMPUIR p15,4,c0,c0,4 + +/* CP15 CR6: MPU Protection Region Base/Limit/Select Address Register */ +#define HPRSELR p15,4,c6,c2,1 +#define PRBAR_EL2 p15,4,c6,c3,0 +#define PRLAR_EL2 p15,4,c6,c8,1 + +#define MPUIR_EL2 HMPUIR +#define PRSELR_EL2 HPRSELR + +#endif /* __ASM_ARM_MPU_CPREGS_H */ + +/* + * Local variables: + * mode: ASM + * indent-tabs-mode: nil + * End: + */ From patchwork Mon Apr 7 18:44:43 2025 Content-Type: text/plain; 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pr=C From: Ayan Kumar Halder To: CC: Ayan Kumar Halder , Stefano Stabellini , Julien Grall , Bertrand Marquis , Michal Orzel , "Volodymyr Babchuk" Subject: [PATCH v5 3/3] xen/arm32: mpu: Stubs to build MPU for arm32 Date: Mon, 7 Apr 2025 19:44:43 +0100 Message-ID: <20250407184443.1790995-4-ayan.kumar.halder@amd.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20250407184443.1790995-1-ayan.kumar.halder@amd.com> References: <20250407184443.1790995-1-ayan.kumar.halder@amd.com> MIME-Version: 1.0 Received-SPF: None (SATLEXMB05.amd.com: ayan.kumar.halder@amd.com does not designate permitted sender hosts) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: BN1PEPF0000468D:EE_|MW4PR12MB6849:EE_ X-MS-Office365-Filtering-Correlation-Id: c2d73e46-4fa3-49cb-3911-08dd76044a2f X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|1800799024|82310400026|376014|36860700013; X-Microsoft-Antispam-Message-Info: iDVF+btuffi2xe7KCw8hZTfKL21e4GVzLbtZ1oAqfaV4OrMEzie0J/xdySLWXYnAK0pnrGC4rf7rtyVfRrc6+jjfUqapR33J7LsVPqJPImsTAQn4R/KI6JDvWn3sTR++z3gpTE0YMd2VFeAe9w9nwv6lQAieyAF+k24SU43TwLwKlxMH1IGPWnl2OwR4q/QSi/OgGS/sSnfuJcO2/xCNoTn9IOeksIcAbLGDWNNn+5NVjZvsAKmbrMjnDFWJaFcYxEZVnmilC/8dYMx/4M1a0neTLut9uoOMpkkqqciWr64R4MiYsGjBXITewf5Qh2yuzAFr10FtVVqPpI7GMNMgdlqXh/SO8NEC1GCNkE9iCbwE/jQiOoaB+hbhvuwr+cgnS1adChbWtKOT33mnIt+akoq7dI7XElCD/kYfHzahfNnQTmT1arDCTMA5paugril3tzn+GmbIbRbNOFREqKrfQdsYsG6T8bw53Do4efnAiid17poyFDJTGm0kFDj8hHAP6xKRu6mb5a9EY/SbEelKrodC08EoPuwnvopafgzQTihDdt9DRp2w1nbkivAgyw5PU/Bp1qlMnvlBm4HvCvA1boO2TTysYBCemvgAcfq193oVfQtFLxfoawdU61bXC3NuvuL54G8yHTTHarIU8t7r9nhw+odcGIku4t5y8yhrC71GSEk6qkCWn03/43XTVKTEH3nkMLgSY4267jFv2sNIy1cJFf2RodKppsjg3NN1G6jB2wwajJLpdi4nQ9cBgafLkiYG8he7m5NQwW40OFV3ybvYeyf5rRct5AQbTGCnsi2tWkWp2I46JDD0J0Z0ZvD6B+cI3xpsR1cuPdKKK83gaL3876HUQ3cLeubpvfueJ27fi/veT9KDBzxs/odDy/dH6psNsquIzOFgZVJcfPHKmzm2cZHdPgFezflapxOo+ztWVd2e2qylzLxZ8dHcZIkIbN4kiZKNNlH+PoC6NUctdV3lPLn0cV7zBpWaB+zorMV+hcWFm2O8th3LBabTESjnQGXms46i7vCMgvO6XTlcMaICfBWoVWQUPXNXStdmENnHxCIANh1dE+FkEZ6KQyFwLuA0sfhn/6Hu/hIU18+sQS1zlUrECf6RcwGN9nU639UWYW+W8NtXth21FRaYmzNzHZXxgse1F2z/xzflBnz2F1dEOge7otgXSIMXRixHGixEQut05erIwpX8AuypP6awF1q8eWDHao5bQzvJ/7ONe7WWFbQ0XrrCNybi6AJopprXBRjyLr34EQnLPq+t7hSC+s58C0FnTCYEHCZKGMf0nicLn9AT1iO3zqZ3528Lop76aLUiDnTSvLsJ2yayQ7qDBkwYA0DzHlbFgo9ZMVDuzYLuHXy1q82xPXtTTDQL0vPqSK8LhreHBgW95SBpPjeSiNDgFGV51pHO2sItwVZ1jTO+ax/m3jUD1DM5WNres7sTHEXJwgaNipSGiTaifPMsm4+RBAWC6RhcE8SLHotPMS2zcN2DgPGvkCzTYrpY6pc= X-Forefront-Antispam-Report: CIP:165.204.84.17;CTRY:US;LANG:en;SCL:1;SRV:;IPV:CAL;SFV:NSPM;H:SATLEXMB04.amd.com;PTR:InfoDomainNonexistent;CAT:NONE;SFS:(13230040)(1800799024)(82310400026)(376014)(36860700013);DIR:OUT;SFP:1101; X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 07 Apr 2025 18:44:55.2612 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: c2d73e46-4fa3-49cb-3911-08dd76044a2f X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: BN1PEPF0000468D.namprd05.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: MW4PR12MB6849 Add stubs to enable compilation Signed-off-by: Ayan Kumar Halder Reviewed-by: Luca Fancellu --- Changes from :- v1, v2 - 1. New patch introduced in v3. 2. Should be applied on top of https://patchwork.kernel.org/project/xen-devel/cover/20250316192445.2376484-1-luca.fancellu@arm.com/ v3 - 1. Add stubs for map_domain_page() and similar functions. 2. 'BUG_ON("unimplemented")' is kept in all the stubs. v4 - 1. is_xen_heap_mfn() macros are defined across mpu/mm.h (ARM32 specific) , mmu/mm.h (ARM32 specific) and asm/mm.h (ARM64 specific) 2. s/(void*)0/NULL xen/arch/arm/arm32/mpu/Makefile | 2 ++ xen/arch/arm/arm32/mpu/p2m.c | 18 ++++++++++++++ xen/arch/arm/arm32/mpu/smpboot.c | 23 +++++++++++++++++ xen/arch/arm/include/asm/mm.h | 9 +------ xen/arch/arm/include/asm/mmu/mm.h | 9 +++++++ xen/arch/arm/include/asm/mpu/mm.h | 5 ++++ xen/arch/arm/mpu/Makefile | 1 + xen/arch/arm/mpu/domain_page.c | 41 +++++++++++++++++++++++++++++++ 8 files changed, 100 insertions(+), 8 deletions(-) create mode 100644 xen/arch/arm/arm32/mpu/p2m.c create mode 100644 xen/arch/arm/arm32/mpu/smpboot.c create mode 100644 xen/arch/arm/mpu/domain_page.c diff --git a/xen/arch/arm/arm32/mpu/Makefile b/xen/arch/arm/arm32/mpu/Makefile index 3340058c08..38797f28af 100644 --- a/xen/arch/arm/arm32/mpu/Makefile +++ b/xen/arch/arm/arm32/mpu/Makefile @@ -1 +1,3 @@ obj-y += head.o +obj-y += smpboot.o +obj-y += p2m.o diff --git a/xen/arch/arm/arm32/mpu/p2m.c b/xen/arch/arm/arm32/mpu/p2m.c new file mode 100644 index 0000000000..df8de5c7d8 --- /dev/null +++ b/xen/arch/arm/arm32/mpu/p2m.c @@ -0,0 +1,18 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include +#include + +void __init setup_virt_paging(void) +{ + BUG_ON("unimplemented"); +} + +/* + * Local variables: + * mode: C + * c-file-style: "BSD" + * c-basic-offset: 4 + * indent-tabs-mode: nil + * End: + */ diff --git a/xen/arch/arm/arm32/mpu/smpboot.c b/xen/arch/arm/arm32/mpu/smpboot.c new file mode 100644 index 0000000000..3f3e54294e --- /dev/null +++ b/xen/arch/arm/arm32/mpu/smpboot.c @@ -0,0 +1,23 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include + +int prepare_secondary_mm(int cpu) +{ + BUG_ON("unimplemented"); + return -EINVAL; +} + +void update_boot_mapping(bool enable) +{ + BUG_ON("unimplemented"); +} + +/* + * Local variables: + * mode: C + * c-file-style: "BSD" + * c-basic-offset: 4 + * indent-tabs-mode: nil + * End: + */ diff --git a/xen/arch/arm/include/asm/mm.h b/xen/arch/arm/include/asm/mm.h index fbffaccef4..5b67c0f8bb 100644 --- a/xen/arch/arm/include/asm/mm.h +++ b/xen/arch/arm/include/asm/mm.h @@ -170,14 +170,7 @@ struct page_info #define _PGC_need_scrub _PGC_allocated #define PGC_need_scrub PGC_allocated -#ifdef CONFIG_ARM_32 -#define is_xen_heap_page(page) is_xen_heap_mfn(page_to_mfn(page)) -#define is_xen_heap_mfn(mfn) ({ \ - unsigned long mfn_ = mfn_x(mfn); \ - (mfn_ >= mfn_x(directmap_mfn_start) && \ - mfn_ < mfn_x(directmap_mfn_end)); \ -}) -#else +#ifdef CONFIG_ARM_64 #define is_xen_heap_page(page) ((page)->count_info & PGC_xen_heap) #define is_xen_heap_mfn(mfn) \ (mfn_valid(mfn) && is_xen_heap_page(mfn_to_page(mfn))) diff --git a/xen/arch/arm/include/asm/mmu/mm.h b/xen/arch/arm/include/asm/mmu/mm.h index caba987edc..9b98d12b07 100644 --- a/xen/arch/arm/include/asm/mmu/mm.h +++ b/xen/arch/arm/include/asm/mmu/mm.h @@ -21,6 +21,15 @@ extern unsigned long directmap_base_pdx; #define frame_table ((struct page_info *)FRAMETABLE_VIRT_START) +#ifdef CONFIG_ARM_32 +#define is_xen_heap_page(page) is_xen_heap_mfn(page_to_mfn(page)) +#define is_xen_heap_mfn(mfn) ({ \ + unsigned long mfn_ = mfn_x(mfn); \ + (mfn_ >= mfn_x(directmap_mfn_start) && \ + mfn_ < mfn_x(directmap_mfn_end)); \ +}) +#endif + #define virt_to_maddr(va) ({ \ vaddr_t va_ = (vaddr_t)(va); \ (paddr_t)((va_to_par(va_) & PADDR_MASK & PAGE_MASK) | (va_ & ~PAGE_MASK)); \ diff --git a/xen/arch/arm/include/asm/mpu/mm.h b/xen/arch/arm/include/asm/mpu/mm.h index 86f33d9836..bfd840fa5d 100644 --- a/xen/arch/arm/include/asm/mpu/mm.h +++ b/xen/arch/arm/include/asm/mpu/mm.h @@ -13,6 +13,11 @@ extern struct page_info *frame_table; #define virt_to_maddr(va) ((paddr_t)((vaddr_t)(va) & PADDR_MASK)) +#ifdef CONFIG_ARM_32 +#define is_xen_heap_page(page) ({ BUG_ON("unimplemented"); false; }) +#define is_xen_heap_mfn(mfn) ({ BUG_ON("unimplemented"); false; }) +#endif + /* On MPU systems there is no translation, ma == va. */ static inline void *maddr_to_virt(paddr_t ma) { diff --git a/xen/arch/arm/mpu/Makefile b/xen/arch/arm/mpu/Makefile index 21bbc517b5..ff221011d5 100644 --- a/xen/arch/arm/mpu/Makefile +++ b/xen/arch/arm/mpu/Makefile @@ -2,3 +2,4 @@ obj-y += mm.o obj-y += p2m.o obj-y += setup.init.o obj-y += vmap.o +obj-$(CONFIG_ARM_32) += domain_page.o diff --git a/xen/arch/arm/mpu/domain_page.c b/xen/arch/arm/mpu/domain_page.c new file mode 100644 index 0000000000..8859b24e04 --- /dev/null +++ b/xen/arch/arm/mpu/domain_page.c @@ -0,0 +1,41 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ +#include + +void *map_domain_page_global(mfn_t mfn) +{ + BUG_ON("unimplemented"); + return NULL; +} + +/* Map a page of domheap memory */ +void *map_domain_page(mfn_t mfn) +{ + BUG_ON("unimplemented"); + return NULL; +} + +/* Release a mapping taken with map_domain_page() */ +void unmap_domain_page(const void *ptr) +{ + BUG_ON("unimplemented"); +} + +mfn_t domain_page_map_to_mfn(const void *ptr) +{ + BUG_ON("unimplemented"); + return INVALID_MFN; +} + +void unmap_domain_page_global(const void *va) +{ + BUG_ON("unimplemented"); +} + +/* + * Local variables: + * mode: C + * c-file-style: "BSD" + * c-basic-offset: 4 + * indent-tabs-mode: nil + * End: + */