From patchwork Tue Apr 8 11:38:44 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Biju Das X-Patchwork-Id: 14042900 X-Patchwork-Delegate: geert@linux-m68k.org Received: from relmlie6.idc.renesas.com (relmlor2.renesas.com [210.160.252.172]) by smtp.subspace.kernel.org (Postfix) with ESMTP id 61DF7224AEB; Tue, 8 Apr 2025 11:39:04 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=210.160.252.172 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1744112347; cv=none; b=jXZYpBRRO0QWzICKl/2FGGnkBXfxH3OUWCrBhg+RNrsrjAVT4LT/CgfQX5LwP/Qxgg25qzrPoyt5oeVASoDOlatIWbfOX0/Yr2NIw2OlCA6XQTJCn2cqEPu1Nht4tRlRDx/oq+uxrSSG7R7Efwhw3NizJBEmcHHGuo6+BWOmUl8= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1744112347; c=relaxed/simple; bh=DmzYSBaT+APlAEbVRu5H2i1KNPpf919Spcd3i7iVAPQ=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=o7ucp4ffWcmGVmd4pBiSGBeafbKXCHL8JKoFxMedSpcWispsjo/e69MkwZULv1bXEhiHCFmNvP86IJtvysRSrAPSdzACfS9dV45Qr1+sX12MBcdtR2Ed53LZB7+vfaYiQcgQ8rXqXsWGlxtnUAYG3TqsjeYsX5bvYnseeUF5pYc= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=bp.renesas.com; spf=pass smtp.mailfrom=bp.renesas.com; arc=none smtp.client-ip=210.160.252.172 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=bp.renesas.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=bp.renesas.com X-CSE-ConnectionGUID: mctjavbuTgSdEHT9aWPPaA== X-CSE-MsgGUID: RnVG+koLTyaC3NSMe1p67w== Received: from unknown (HELO relmlir5.idc.renesas.com) ([10.200.68.151]) by relmlie6.idc.renesas.com with ESMTP; 08 Apr 2025 20:38:58 +0900 Received: from localhost.localdomain (unknown [10.226.92.125]) by relmlir5.idc.renesas.com (Postfix) with ESMTP id B54D7401324C; Tue, 8 Apr 2025 20:38:55 +0900 (JST) From: Biju Das To: geert+renesas@glider.be, mturquette@baylibre.com, sboyd@kernel.org Cc: biju.das.au@gmail.com, linux-renesas-soc@vger.kernel.org, linux-clk@vger.kernel.org, prabhakar.mahadev-lad.rj@bp.renesas.com, Biju Das Subject: [PATCH v2 1/2] clk: renesas: r9a09g047: Add support for xspi mux and divider Date: Tue, 8 Apr 2025 12:38:44 +0100 Message-ID: <20250408113845.130950-2-biju.das.jz@bp.renesas.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250408113845.130950-1-biju.das.jz@bp.renesas.com> References: <20250408113845.130950-1-biju.das.jz@bp.renesas.com> Precedence: bulk X-Mailing-List: linux-renesas-soc@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 The mux smux2_xspi_clk{0,1} used for selecting spi and spix2 clocks and pllcm33_xspi divider to select different clock rates. Add support for both. Signed-off-by: Biju Das --- v1->v2: * Updated LAST_DT_CORE_CLK macro * Replaced DEF_SDIV->DEF_CSDIV macro * Added spi_clk_spi as core clk * Updated CSDIV0_DIVCTL3 macro. This patch depend upon [1] https://lore.kernel.org/all/20250401143537.224047-2-biju.das.jz@bp.renesas.com/ [2] https://lore.kernel.org/all/20250407165202.197570-4-prabhakar.mahadev-lad.rj@bp.renesas.com/ --- drivers/clk/renesas/r9a09g047-cpg.c | 28 +++++++++++++++++++++++++++- drivers/clk/renesas/rzv2h-cpg.h | 3 +++ 2 files changed, 30 insertions(+), 1 deletion(-) diff --git a/drivers/clk/renesas/r9a09g047-cpg.c b/drivers/clk/renesas/r9a09g047-cpg.c index 7b9311af603e..741ee025ce02 100644 --- a/drivers/clk/renesas/r9a09g047-cpg.c +++ b/drivers/clk/renesas/r9a09g047-cpg.c @@ -16,7 +16,7 @@ enum clk_ids { /* Core Clock Outputs exported to DT */ - LAST_DT_CORE_CLK = R9A09G047_IOTOP_0_SHCLK, + LAST_DT_CORE_CLK = R9A09G047_SPI_CLK_SPI, /* External Input Clocks */ CLK_AUDIO_EXTAL, @@ -31,7 +31,13 @@ enum clk_ids { CLK_PLLVDO, /* Internal Core Clocks */ + CLK_PLLCM33_DIV3, + CLK_PLLCM33_DIV4, + CLK_PLLCM33_DIV5, CLK_PLLCM33_DIV16, + CLK_SMUX2_XSPI_CLK0, + CLK_SMUX2_XSPI_CLK1, + CLK_PLLCM33_XSPI, CLK_PLLCLN_DIV2, CLK_PLLCLN_DIV8, CLK_PLLCLN_DIV16, @@ -60,6 +66,14 @@ static const struct clk_div_table dtable_2_4[] = { {0, 0}, }; +static const struct clk_div_table dtable_2_16[] = { + {0, 2}, + {1, 4}, + {2, 8}, + {3, 16}, + {0, 0}, +}; + static const struct clk_div_table dtable_2_64[] = { {0, 2}, {1, 4}, @@ -69,6 +83,10 @@ static const struct clk_div_table dtable_2_64[] = { {0, 0}, }; +/* Mux clock tables */ +static const char * const smux2_xspi_clk0[] = { ".pllcm33_div3", ".pllcm33_div4" }; +static const char * const smux2_xspi_clk1[] = { ".smux2_xspi_clk0", ".pllcm33_div5" }; + static const struct cpg_core_clk r9a09g047_core_clks[] __initconst = { /* External Clock Inputs */ DEF_INPUT("audio_extal", CLK_AUDIO_EXTAL), @@ -83,8 +101,15 @@ static const struct cpg_core_clk r9a09g047_core_clks[] __initconst = { DEF_FIXED(".pllvdo", CLK_PLLVDO, CLK_QEXTAL, 105, 2), /* Internal Core Clocks */ + DEF_FIXED(".pllcm33_div3", CLK_PLLCM33_DIV3, CLK_PLLCM33, 1, 3), + DEF_FIXED(".pllcm33_div4", CLK_PLLCM33_DIV4, CLK_PLLCM33, 1, 4), + DEF_FIXED(".pllcm33_div5", CLK_PLLCM33_DIV5, CLK_PLLCM33, 1, 5), DEF_FIXED(".pllcm33_div16", CLK_PLLCM33_DIV16, CLK_PLLCM33, 1, 16), + DEF_SMUX(".smux2_xspi_clk0", CLK_SMUX2_XSPI_CLK0, SSEL1_SELCTL2, smux2_xspi_clk0), + DEF_SMUX(".smux2_xspi_clk1", CLK_SMUX2_XSPI_CLK1, SSEL1_SELCTL3, smux2_xspi_clk1), + DEF_CSDIV(".pllcm33_xspi", CLK_PLLCM33_XSPI, CLK_SMUX2_XSPI_CLK1, CSDIV0_DIVCTL3, + dtable_2_16), DEF_FIXED(".pllcln_div2", CLK_PLLCLN_DIV2, CLK_PLLCLN, 1, 2), DEF_FIXED(".pllcln_div8", CLK_PLLCLN_DIV8, CLK_PLLCLN, 1, 8), DEF_FIXED(".pllcln_div16", CLK_PLLCLN_DIV16, CLK_PLLCLN, 1, 16), @@ -108,6 +133,7 @@ static const struct cpg_core_clk r9a09g047_core_clks[] __initconst = { DEF_DDIV("ca55_0_coreclk3", R9A09G047_CA55_0_CORECLK3, CLK_PLLCA55, CDDIV1_DIVCTL3, dtable_1_8), DEF_FIXED("iotop_0_shclk", R9A09G047_IOTOP_0_SHCLK, CLK_PLLCM33_DIV16, 1, 1), + DEF_FIXED("spi_clk_spi", R9A09G047_SPI_CLK_SPI, CLK_PLLCM33_XSPI, 1, 2), }; static const struct rzv2h_mod_clk r9a09g047_mod_clks[] __initconst = { diff --git a/drivers/clk/renesas/rzv2h-cpg.h b/drivers/clk/renesas/rzv2h-cpg.h index e730179d92aa..dd75a3682b19 100644 --- a/drivers/clk/renesas/rzv2h-cpg.h +++ b/drivers/clk/renesas/rzv2h-cpg.h @@ -116,11 +116,14 @@ struct smuxed { #define CSDIV0_DIVCTL0 DDIV_PACK(CPG_CSDIV0, 0, 2, CSDIV_NO_MON) #define CSDIV0_DIVCTL1 DDIV_PACK(CPG_CSDIV0, 4, 2, CSDIV_NO_MON) +#define CSDIV0_DIVCTL3 DDIV_PACK_NO_RMW(CPG_CSDIV0, 12, 2, CSDIV_NO_MON) #define SSEL0_SELCTL2 SMUX_PACK(CPG_SSEL0, 8, 1) #define SSEL0_SELCTL3 SMUX_PACK(CPG_SSEL0, 12, 1) #define SSEL1_SELCTL0 SMUX_PACK(CPG_SSEL1, 0, 1) #define SSEL1_SELCTL1 SMUX_PACK(CPG_SSEL1, 4, 1) +#define SSEL1_SELCTL2 SMUX_PACK(CPG_SSEL1, 8, 1) +#define SSEL1_SELCTL3 SMUX_PACK(CPG_SSEL1, 12, 1) #define BUS_MSTOP_IDX_MASK GENMASK(31, 16) #define BUS_MSTOP_BITS_MASK GENMASK(15, 0) From patchwork Tue Apr 8 11:38:45 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Biju Das X-Patchwork-Id: 14042901 X-Patchwork-Delegate: geert@linux-m68k.org Received: from relmlie6.idc.renesas.com (relmlor2.renesas.com [210.160.252.172]) by smtp.subspace.kernel.org (Postfix) with ESMTP id 3AAA0224AEB; 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dmarc=pass (p=none dis=none) header.from=bp.renesas.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=bp.renesas.com X-CSE-ConnectionGUID: +bJbOWRNRNeQso5jtz6dIg== X-CSE-MsgGUID: 1I/VSMtsTv2505k4r/ZwgQ== Received: from unknown (HELO relmlir5.idc.renesas.com) ([10.200.68.151]) by relmlie6.idc.renesas.com with ESMTP; 08 Apr 2025 20:39:00 +0900 Received: from localhost.localdomain (unknown [10.226.92.125]) by relmlir5.idc.renesas.com (Postfix) with ESMTP id 99B3B40138ED; Tue, 8 Apr 2025 20:38:58 +0900 (JST) From: Biju Das To: geert+renesas@glider.be, mturquette@baylibre.com, sboyd@kernel.org Cc: biju.das.au@gmail.com, linux-renesas-soc@vger.kernel.org, linux-clk@vger.kernel.org, prabhakar.mahadev-lad.rj@bp.renesas.com, Biju Das Subject: [PATCH v2 2/2] clk: renesas: r9a09g047: Add XSPI clock/reset Date: Tue, 8 Apr 2025 12:38:45 +0100 Message-ID: <20250408113845.130950-3-biju.das.jz@bp.renesas.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250408113845.130950-1-biju.das.jz@bp.renesas.com> References: <20250408113845.130950-1-biju.das.jz@bp.renesas.com> Precedence: bulk X-Mailing-List: linux-renesas-soc@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Add XSPI clock and reset entries. Signed-off-by: Biju Das --- v1->v2: * spi_clk_spix2 is handled as module clock with RPM. * Dropped CDDIV0_DIVCTL1 as it is already merged in clk tree. --- drivers/clk/renesas/r9a09g047-cpg.c | 11 +++++++++++ 1 file changed, 11 insertions(+) diff --git a/drivers/clk/renesas/r9a09g047-cpg.c b/drivers/clk/renesas/r9a09g047-cpg.c index 741ee025ce02..d3d1ce39db8e 100644 --- a/drivers/clk/renesas/r9a09g047-cpg.c +++ b/drivers/clk/renesas/r9a09g047-cpg.c @@ -35,6 +35,7 @@ enum clk_ids { CLK_PLLCM33_DIV4, CLK_PLLCM33_DIV5, CLK_PLLCM33_DIV16, + CLK_PLLCM33_GEAR, CLK_SMUX2_XSPI_CLK0, CLK_SMUX2_XSPI_CLK1, CLK_PLLCM33_XSPI, @@ -106,6 +107,8 @@ static const struct cpg_core_clk r9a09g047_core_clks[] __initconst = { DEF_FIXED(".pllcm33_div5", CLK_PLLCM33_DIV5, CLK_PLLCM33, 1, 5), DEF_FIXED(".pllcm33_div16", CLK_PLLCM33_DIV16, CLK_PLLCM33, 1, 16), + DEF_DDIV(".pllcm33_gear", CLK_PLLCM33_GEAR, CLK_PLLCM33_DIV4, CDDIV0_DIVCTL1, dtable_2_64), + DEF_SMUX(".smux2_xspi_clk0", CLK_SMUX2_XSPI_CLK0, SSEL1_SELCTL2, smux2_xspi_clk0), DEF_SMUX(".smux2_xspi_clk1", CLK_SMUX2_XSPI_CLK1, SSEL1_SELCTL3, smux2_xspi_clk1), DEF_CSDIV(".pllcm33_xspi", CLK_PLLCM33_XSPI, CLK_SMUX2_XSPI_CLK1, CSDIV0_DIVCTL3, @@ -179,6 +182,12 @@ static const struct rzv2h_mod_clk r9a09g047_mod_clks[] __initconst = { BUS_MSTOP(10, BIT(14))), DEF_MOD("canfd_0_clkc", CLK_PLLCLN_DIV20, 9, 14, 4, 30, BUS_MSTOP(10, BIT(14))), + DEF_MOD("spi_hclk", CLK_PLLCM33_GEAR, 9, 15, 4, 31, + BUS_MSTOP(4, BIT(5))), + DEF_MOD("spi_aclk", CLK_PLLCM33_GEAR, 10, 0, 5, 0, + BUS_MSTOP(4, BIT(5))), + DEF_MOD_NO_PM("spi_clk_spix2", CLK_PLLCM33_XSPI, 10, 1, 5, 2, + BUS_MSTOP(4, BIT(5))), DEF_MOD("sdhi_0_imclk", CLK_PLLCLN_DIV8, 10, 3, 5, 3, BUS_MSTOP(8, BIT(2))), DEF_MOD("sdhi_0_imclk2", CLK_PLLCLN_DIV8, 10, 4, 5, 4, @@ -233,6 +242,8 @@ static const struct rzv2h_reset r9a09g047_resets[] __initconst = { DEF_RST(10, 0, 4, 17), /* RIIC_8_MRST */ DEF_RST(10, 1, 4, 18), /* CANFD_0_RSTP_N */ DEF_RST(10, 2, 4, 19), /* CANFD_0_RSTC_N */ + DEF_RST(10, 3, 4, 20), /* SPI_HRESETN */ + DEF_RST(10, 4, 4, 21), /* SPI_ARESETN */ DEF_RST(10, 7, 4, 24), /* SDHI_0_IXRST */ DEF_RST(10, 8, 4, 25), /* SDHI_1_IXRST */ DEF_RST(10, 9, 4, 26), /* SDHI_2_IXRST */