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Signed-off-by: Oleksii Kurochko Reviewed-by: Jan Beulich --- xen/arch/riscv/include/asm/time.h | 6 ++++++ xen/arch/riscv/stubs.c | 5 ----- xen/arch/riscv/time.c | 7 +++++++ 3 files changed, 13 insertions(+), 5 deletions(-) diff --git a/xen/arch/riscv/include/asm/time.h b/xen/arch/riscv/include/asm/time.h index e8d9ffec57..0f6aa99ab1 100644 --- a/xen/arch/riscv/include/asm/time.h +++ b/xen/arch/riscv/include/asm/time.h @@ -3,6 +3,7 @@ #define ASM__RISCV__TIME_H #include +#include #include #include @@ -23,6 +24,11 @@ static inline cycles_t get_cycles(void) return csr_read(CSR_TIME); } +static inline s_time_t ticks_to_ns(uint64_t ticks) +{ + return muldiv64(ticks, SECONDS(1), 1000 * cpu_khz); +} + void preinit_xen_time(void); #endif /* ASM__RISCV__TIME_H */ diff --git a/xen/arch/riscv/stubs.c b/xen/arch/riscv/stubs.c index a1d64534cd..83416d3350 100644 --- a/xen/arch/riscv/stubs.c +++ b/xen/arch/riscv/stubs.c @@ -27,11 +27,6 @@ nodemask_t __read_mostly node_online_map = { { [0] = 1UL } }; /* time.c */ -s_time_t get_s_time(void) -{ - BUG_ON("unimplemented"); -} - int reprogram_timer(s_time_t timeout) { BUG_ON("unimplemented"); diff --git a/xen/arch/riscv/time.c b/xen/arch/riscv/time.c index 905bb13eb4..81e06781f8 100644 --- a/xen/arch/riscv/time.c +++ b/xen/arch/riscv/time.c @@ -4,10 +4,17 @@ #include #include #include +#include unsigned long __ro_after_init cpu_khz; /* CPU clock frequency in kHz. */ uint64_t __ro_after_init boot_clock_cycles; +s_time_t get_s_time(void) +{ + uint64_t ticks = get_cycles() - boot_clock_cycles; + return ticks_to_ns(ticks); +} + /* Set up the timer on the boot CPU (early init function) */ static void __init preinit_dt_xen_time(void) { From patchwork Tue Apr 8 15:57:06 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Oleksii Kurochko X-Patchwork-Id: 14043251 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.xenproject.org (lists.xenproject.org [192.237.175.120]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 10472C369A4 for ; Tue, 8 Apr 2025 15:57:38 +0000 (UTC) Received: from list by lists.xenproject.org with outflank-mailman.942502.1341658 (Exim 4.92) (envelope-from ) id 1u2BKL-00054s-05; Tue, 08 Apr 2025 15:57:29 +0000 X-Outflank-Mailman: Message body and most headers restored to incoming version Received: by outflank-mailman (output) from mailman id 942502.1341658; Tue, 08 Apr 2025 15:57:28 +0000 Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1u2BKK-00054C-Oe; Tue, 08 Apr 2025 15:57:28 +0000 Received: by outflank-mailman (input) for mailman id 942502; Tue, 08 Apr 2025 15:57:28 +0000 Received: from se1-gles-flk1-in.inumbo.com ([94.247.172.50] helo=se1-gles-flk1.inumbo.com) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1u2BKK-0004Yq-2s for xen-devel@lists.xenproject.org; Tue, 08 Apr 2025 15:57:28 +0000 Received: from mail-ej1-x633.google.com (mail-ej1-x633.google.com [2a00:1450:4864:20::633]) by se1-gles-flk1.inumbo.com (Halon) with ESMTPS id 2abb371a-1492-11f0-9ffb-bf95429c2676; Tue, 08 Apr 2025 17:57:26 +0200 (CEST) Received: by mail-ej1-x633.google.com with SMTP id a640c23a62f3a-abbd96bef64so1115126066b.3 for ; Tue, 08 Apr 2025 08:57:26 -0700 (PDT) Received: from fedora.. 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Drop DEFINE_PER_CPU(unsigned int, cpu_id) from stubs.c as this variable isn't expected to be used in RISC-V at all. Move declaration of cpu_{possible,online,present}_map from stubs.c to smpboot.c as now smpboot.c is now introduced. Other defintions keep in stubs.c as they are not initialized and not needed, at the moment. Signed-off-by: Oleksii Kurochko --- xen/arch/riscv/Makefile | 1 + xen/arch/riscv/include/asm/smp.h | 2 ++ xen/arch/riscv/setup.c | 2 ++ xen/arch/riscv/smpboot.c | 15 +++++++++++++++ xen/arch/riscv/stubs.c | 6 ------ 5 files changed, 20 insertions(+), 6 deletions(-) create mode 100644 xen/arch/riscv/smpboot.c diff --git a/xen/arch/riscv/Makefile b/xen/arch/riscv/Makefile index 0c6c4a38a3..f551bf32a2 100644 --- a/xen/arch/riscv/Makefile +++ b/xen/arch/riscv/Makefile @@ -10,6 +10,7 @@ obj-y += sbi.o obj-y += setup.o obj-y += shutdown.o obj-y += smp.o +obj-y += smpboot.o obj-y += stubs.o obj-y += time.o obj-y += traps.o diff --git a/xen/arch/riscv/include/asm/smp.h b/xen/arch/riscv/include/asm/smp.h index 5e170b57b3..188c033718 100644 --- a/xen/arch/riscv/include/asm/smp.h +++ b/xen/arch/riscv/include/asm/smp.h @@ -26,6 +26,8 @@ static inline void set_cpuid_to_hartid(unsigned long cpuid, void setup_tp(unsigned int cpuid); +void smp_clear_cpu_maps(void); + #endif /* diff --git a/xen/arch/riscv/setup.c b/xen/arch/riscv/setup.c index 4e416f6e44..7f68f3f5b7 100644 --- a/xen/arch/riscv/setup.c +++ b/xen/arch/riscv/setup.c @@ -72,6 +72,8 @@ void __init noreturn start_xen(unsigned long bootcpu_id, remove_identity_mapping(); + smp_clear_cpu_maps(); + set_processor_id(0); set_cpuid_to_hartid(0, bootcpu_id); diff --git a/xen/arch/riscv/smpboot.c b/xen/arch/riscv/smpboot.c new file mode 100644 index 0000000000..0f4dcc28e1 --- /dev/null +++ b/xen/arch/riscv/smpboot.c @@ -0,0 +1,15 @@ +#include +#include + +cpumask_t cpu_online_map; +cpumask_t cpu_present_map; +cpumask_t cpu_possible_map; + +void __init smp_clear_cpu_maps(void) +{ + cpumask_clear(&cpu_possible_map); + cpumask_clear(&cpu_online_map); + cpumask_set_cpu(0, &cpu_possible_map); + cpumask_set_cpu(0, &cpu_online_map); + cpumask_copy(&cpu_present_map, &cpu_possible_map); +} diff --git a/xen/arch/riscv/stubs.c b/xen/arch/riscv/stubs.c index 83416d3350..fdcf91054e 100644 --- a/xen/arch/riscv/stubs.c +++ b/xen/arch/riscv/stubs.c @@ -11,12 +11,6 @@ /* smpboot.c */ -cpumask_t cpu_online_map; -cpumask_t cpu_present_map; -cpumask_t cpu_possible_map; - -/* ID of the PCPU we're running on */ -DEFINE_PER_CPU(unsigned int, cpu_id); /* XXX these seem awfully x86ish... */ /* representing HT siblings of each logical CPU */ DEFINE_PER_CPU_READ_MOSTLY(cpumask_var_t, cpu_sibling_mask); From patchwork Tue Apr 8 15:57:07 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Oleksii Kurochko X-Patchwork-Id: 14043250 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.xenproject.org (lists.xenproject.org [192.237.175.120]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id E7F97C369A2 for ; Tue, 8 Apr 2025 15:57:36 +0000 (UTC) Received: from list by lists.xenproject.org with outflank-mailman.942501.1341652 (Exim 4.92) (envelope-from ) id 1u2BKK-00052S-LZ; Tue, 08 Apr 2025 15:57:28 +0000 X-Outflank-Mailman: Message body and most headers restored to incoming version Received: by outflank-mailman (output) from mailman id 942501.1341652; Tue, 08 Apr 2025 15:57:28 +0000 Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1u2BKK-00052G-Hu; Tue, 08 Apr 2025 15:57:28 +0000 Received: by outflank-mailman (input) for mailman id 942501; Tue, 08 Apr 2025 15:57:28 +0000 Received: from se1-gles-sth1-in.inumbo.com ([159.253.27.254] helo=se1-gles-sth1.inumbo.com) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1u2BKK-0004Yr-2j for xen-devel@lists.xenproject.org; Tue, 08 Apr 2025 15:57:28 +0000 Received: from mail-ed1-x52d.google.com (mail-ed1-x52d.google.com [2a00:1450:4864:20::52d]) by se1-gles-sth1.inumbo.com (Halon) with ESMTPS id 2b5b3c4e-1492-11f0-9eaa-5ba50f476ded; Tue, 08 Apr 2025 17:57:27 +0200 (CEST) Received: by mail-ed1-x52d.google.com with SMTP id 4fb4d7f45d1cf-5e61da95244so9512345a12.2 for ; Tue, 08 Apr 2025 08:57:27 -0700 (PDT) Received: from fedora.. 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Therefore, accesses to regular main memory regions that are concurrently accessed by external devices can also use the standard synchronization mechanisms. Implementations that do not conform to the Unix Platform Specification and/or in which devices do not access memory coherently will need to use mechanisms (which are currently platform-specific or device-specific) to enforce coherency. I/O regions in the address space should be considered non-cacheable regions in the PMAs for those regions. Such regions can be considered coherent by the PMA if they are not cached by any agent. ``` and [1]: ``` The current riscv linux implementation requires SOC system to support memory coherence between all I/O devices and CPUs. But some SOC systems cannot maintain the coherence and they need support cache clean/invalid operations to synchronize data. Current implementation is no problem with SiFive FU540, because FU540 keeps all IO devices and DMA master devices coherence with CPU. But to a traditional SOC vendor, it may already have a stable non-coherency SOC system, the need is simply to replace the CPU with RV CPU and rebuild the whole system with IO-coherency is very expensive. ``` and the fact that all known ( to me ) CPUs that support the H-extension and that ones is going to be supported by Xen have memory coherency between all I/O devices and CPUs, so it is currently safe to use the PAGE_HYPERVISOR attribute. However, in cases where a platform does not support memory coherency, it should support CMO extensions and Svpbmt. In this scenario, updates to ioremap will be necessary. For now, a compilation error will be generated to ensure that the need to update ioremap() is not overlooked. [1] https://patchwork.kernel.org/project/linux-riscv/patch/1555947870-23014-1-git-send-email-guoren@kernel.org/ Signed-off-by: Oleksii Kurochko --- xen/arch/riscv/Kconfig | 12 ++++++++++++ xen/arch/riscv/pt.c | 19 +++++++++++++++++++ 2 files changed, 31 insertions(+) diff --git a/xen/arch/riscv/Kconfig b/xen/arch/riscv/Kconfig index d882e0a059..27086cca9c 100644 --- a/xen/arch/riscv/Kconfig +++ b/xen/arch/riscv/Kconfig @@ -15,6 +15,18 @@ config ARCH_DEFCONFIG string default "arch/riscv/configs/tiny64_defconfig" +config HAS_SVPBMT + bool + help + This config enables usage of Svpbmt ISA-extension ( Supervisor-mode: + page-based memory types). + + The memory type for a page contains a combination of attributes + that indicate the cacheability, idempotency, and ordering + properties for access to that page. + + The Svpbmt extension is only available on 64-bit cpus. + menu "Architecture Features" source "arch/Kconfig" diff --git a/xen/arch/riscv/pt.c b/xen/arch/riscv/pt.c index 857619d48d..e2f49e2f97 100644 --- a/xen/arch/riscv/pt.c +++ b/xen/arch/riscv/pt.c @@ -7,6 +7,7 @@ #include #include #include +#include #include #include @@ -548,3 +549,21 @@ void clear_fixmap(unsigned int map) FIXMAP_ADDR(map) + PAGE_SIZE) != 0 ) BUG(); } + +void *ioremap(paddr_t pa, size_t len) +{ + mfn_t mfn = _mfn(PFN_DOWN(pa)); + unsigned int offs = pa & (PAGE_SIZE - 1); + unsigned int nr = PFN_UP(offs + len); + +#ifdef CONFIG_HAS_SVPBMT + #error "an introduction of PAGE_HYPERVISOR_IOREMAP is needed for __vmap()" +#endif + + void *ptr = __vmap(&mfn, nr, 1, 1, PAGE_HYPERVISOR, VMAP_DEFAULT); + + if ( !ptr ) + return NULL; + + return ptr + offs; +} From patchwork Tue Apr 8 15:57:08 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Oleksii Kurochko X-Patchwork-Id: 14043254 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.xenproject.org (lists.xenproject.org [192.237.175.120]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 39698C369A7 for ; Tue, 8 Apr 2025 15:57:38 +0000 (UTC) Received: from list by lists.xenproject.org with outflank-mailman.942503.1341672 (Exim 4.92) (envelope-from ) id 1u2BKN-0005Zh-64; Tue, 08 Apr 2025 15:57:31 +0000 X-Outflank-Mailman: Message body and most headers restored to incoming version Received: by outflank-mailman (output) from mailman id 942503.1341672; Tue, 08 Apr 2025 15:57:31 +0000 Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1u2BKN-0005ZV-1Y; Tue, 08 Apr 2025 15:57:31 +0000 Received: by outflank-mailman (input) for mailman id 942503; Tue, 08 Apr 2025 15:57:29 +0000 Received: from se1-gles-sth1-in.inumbo.com ([159.253.27.254] helo=se1-gles-sth1.inumbo.com) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1u2BKL-0004Yr-4O for xen-devel@lists.xenproject.org; Tue, 08 Apr 2025 15:57:29 +0000 Received: from mail-ej1-x635.google.com (mail-ej1-x635.google.com [2a00:1450:4864:20::635]) by se1-gles-sth1.inumbo.com (Halon) with ESMTPS id 2bf79871-1492-11f0-9eaa-5ba50f476ded; Tue, 08 Apr 2025 17:57:28 +0200 (CEST) Received: by mail-ej1-x635.google.com with SMTP id a640c23a62f3a-ac29fd22163so995725366b.3 for ; Tue, 08 Apr 2025 08:57:28 -0700 (PDT) Received: from fedora.. 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Currently, this function initializes the irq_desc[] array, which stores IRQ descriptors containing various information about each IRQ, such as the type of hardware handling, whether the IRQ is disabled, etc. The initialization is basic at this point and includes setting IRQ_TYPE_INVALID as the IRQ type, assigning the IRQ number ( which is just a consequent index of irq_desc[] array ) to desc->irq, and setting desc->action to NULL. Additionally, the function init_irq_data() is introduced to initialize the IRQ descriptors for all IRQs in the system. Also, define IRQ_TYPE_* which are the same as the existing device tree definitions for convenience. Signed-off-by: Oleksii Kurochko --- xen/arch/riscv/Makefile | 1 + xen/arch/riscv/include/asm/irq.h | 24 +++++++++++++++++ xen/arch/riscv/irq.c | 44 ++++++++++++++++++++++++++++++++ xen/arch/riscv/setup.c | 3 +++ xen/arch/riscv/stubs.c | 5 ---- 5 files changed, 72 insertions(+), 5 deletions(-) create mode 100644 xen/arch/riscv/irq.c diff --git a/xen/arch/riscv/Makefile b/xen/arch/riscv/Makefile index f551bf32a2..457e8e88a4 100644 --- a/xen/arch/riscv/Makefile +++ b/xen/arch/riscv/Makefile @@ -3,6 +3,7 @@ obj-y += cpufeature.o obj-$(CONFIG_EARLY_PRINTK) += early_printk.o obj-y += entry.o obj-y += intc.o +obj-y += irq.o obj-y += mm.o obj-y += pt.o obj-$(CONFIG_RISCV_64) += riscv64/ diff --git a/xen/arch/riscv/include/asm/irq.h b/xen/arch/riscv/include/asm/irq.h index 2a48da2651..8f936b7d01 100644 --- a/xen/arch/riscv/include/asm/irq.h +++ b/xen/arch/riscv/include/asm/irq.h @@ -3,6 +3,28 @@ #define ASM__RISCV__IRQ_H #include +#include + +#define NR_IRQS 1024 + +/* + * TODO: Should IRQ_TYPE_* be moved to xen/irq.h and wrapped into + * #ifdef CONFIG_HAS_DEVICE_TREE? + */ +/* + * These defines correspond to the Xen internal representation of the + * IRQ types. We choose to make them the same as the existing device + * tree definitions for convenience. + */ +#define IRQ_TYPE_NONE DT_IRQ_TYPE_NONE +#define IRQ_TYPE_EDGE_RISING DT_IRQ_TYPE_EDGE_RISING +#define IRQ_TYPE_EDGE_FALLING DT_IRQ_TYPE_EDGE_FALLING +#define IRQ_TYPE_EDGE_BOTH DT_IRQ_TYPE_EDGE_BOTH +#define IRQ_TYPE_LEVEL_HIGH DT_IRQ_TYPE_LEVEL_HIGH +#define IRQ_TYPE_LEVEL_LOW DT_IRQ_TYPE_LEVEL_LOW +#define IRQ_TYPE_LEVEL_MASK DT_IRQ_TYPE_LEVEL_MASK +#define IRQ_TYPE_SENSE_MASK DT_IRQ_TYPE_SENSE_MASK +#define IRQ_TYPE_INVALID DT_IRQ_TYPE_INVALID /* TODO */ #define nr_irqs 0U @@ -25,6 +47,8 @@ static inline void arch_move_irqs(struct vcpu *v) BUG_ON("unimplemented"); } +void init_IRQ(void); + #endif /* ASM__RISCV__IRQ_H */ /* diff --git a/xen/arch/riscv/irq.c b/xen/arch/riscv/irq.c new file mode 100644 index 0000000000..99b8f2095e --- /dev/null +++ b/xen/arch/riscv/irq.c @@ -0,0 +1,44 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +/* + * RISC-V Trap handlers + * + * Copyright (c) 2024 Vates + */ + +#include +#include +#include + +static irq_desc_t irq_desc[NR_IRQS]; + +int arch_init_one_irq_desc(struct irq_desc *desc) +{ + desc->arch.type = IRQ_TYPE_INVALID; + return 0; +} + +static int __init init_irq_data(void) +{ + int irq; + + for ( irq = 0; irq < NR_IRQS; irq++ ) + { + struct irq_desc *desc = irq_to_desc(irq); + int rc = init_one_irq_desc(desc); + + if ( rc ) + return rc; + + desc->irq = irq; + desc->action = NULL; + } + + return 0; +} + +void __init init_IRQ(void) +{ + if ( init_irq_data() < 0 ) + panic("initialization of IRQ data failed\n"); +} diff --git a/xen/arch/riscv/setup.c b/xen/arch/riscv/setup.c index 7f68f3f5b7..a3189697da 100644 --- a/xen/arch/riscv/setup.c +++ b/xen/arch/riscv/setup.c @@ -6,6 +6,7 @@ #include #include #include +#include #include #include #include @@ -127,6 +128,8 @@ void __init noreturn start_xen(unsigned long bootcpu_id, panic("Booting using ACPI isn't supported\n"); } + init_IRQ(); + riscv_fill_hwcap(); preinit_xen_time(); diff --git a/xen/arch/riscv/stubs.c b/xen/arch/riscv/stubs.c index fdcf91054e..e396b67cd3 100644 --- a/xen/arch/riscv/stubs.c +++ b/xen/arch/riscv/stubs.c @@ -107,11 +107,6 @@ void irq_ack_none(struct irq_desc *desc) BUG_ON("unimplemented"); } -int arch_init_one_irq_desc(struct irq_desc *desc) -{ - BUG_ON("unimplemented"); -} - void smp_send_state_dump(unsigned int cpu) { BUG_ON("unimplemented"); From patchwork Tue Apr 8 15:57:09 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Oleksii Kurochko X-Patchwork-Id: 14043255 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.xenproject.org (lists.xenproject.org [192.237.175.120]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 89F9DC369A2 for ; Tue, 8 Apr 2025 15:57:42 +0000 (UTC) Received: from list by lists.xenproject.org with outflank-mailman.942505.1341682 (Exim 4.92) (envelope-from ) id 1u2BKP-0005rm-Di; Tue, 08 Apr 2025 15:57:33 +0000 X-Outflank-Mailman: Message body and most headers restored to incoming version Received: by outflank-mailman (output) from mailman id 942505.1341682; Tue, 08 Apr 2025 15:57:33 +0000 Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1u2BKP-0005rf-Ab; Tue, 08 Apr 2025 15:57:33 +0000 Received: by outflank-mailman (input) for mailman id 942505; Tue, 08 Apr 2025 15:57:31 +0000 Received: from se1-gles-flk1-in.inumbo.com ([94.247.172.50] helo=se1-gles-flk1.inumbo.com) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1u2BKN-0004Yq-IU for xen-devel@lists.xenproject.org; Tue, 08 Apr 2025 15:57:31 +0000 Received: from mail-ej1-x634.google.com (mail-ej1-x634.google.com [2a00:1450:4864:20::634]) by se1-gles-flk1.inumbo.com (Halon) with ESMTPS id 2ccb0e72-1492-11f0-9ffb-bf95429c2676; Tue, 08 Apr 2025 17:57:29 +0200 (CEST) Received: by mail-ej1-x634.google.com with SMTP id a640c23a62f3a-ac25520a289so1006060566b.3 for ; Tue, 08 Apr 2025 08:57:29 -0700 (PDT) Received: from fedora.. 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Introduce dt_irq_xlate and initialize with aplic_irq_xlate() as it is used by dt_device_get_irq() which is called by platform_get_irq(). Co-developed-by: Romain Caritey Signed-off-by: Oleksii Kurochko --- xen/arch/riscv/aplic.c | 19 +++++++++++++++ xen/arch/riscv/include/asm/irq.h | 3 +++ xen/arch/riscv/irq.c | 41 ++++++++++++++++++++++++++++++++ 3 files changed, 63 insertions(+) diff --git a/xen/arch/riscv/aplic.c b/xen/arch/riscv/aplic.c index caba8f8993..6dc040af6f 100644 --- a/xen/arch/riscv/aplic.c +++ b/xen/arch/riscv/aplic.c @@ -11,6 +11,7 @@ #include #include +#include #include #include @@ -21,6 +22,22 @@ static struct intc_info __ro_after_init aplic_info = { .hw_version = INTC_APLIC, }; +static int aplic_irq_xlate(const uint32_t *intspec, unsigned int intsize, + unsigned int *out_hwirq, + unsigned int *out_type) +{ + if ( intsize < 2 ) + return -EINVAL; + + /* Mapping 1:1 */ + *out_hwirq = intspec[0]; + + if ( out_type ) + *out_type = intspec[1] & IRQ_TYPE_SENSE_MASK; + + return 0; +} + static int __init aplic_preinit(struct dt_device_node *node, const void *dat) { if ( aplic_info.node ) @@ -35,6 +52,8 @@ static int __init aplic_preinit(struct dt_device_node *node, const void *dat) aplic_info.node = node; + dt_irq_xlate = aplic_irq_xlate; + return 0; } diff --git a/xen/arch/riscv/include/asm/irq.h b/xen/arch/riscv/include/asm/irq.h index 8f936b7d01..ff1c95e0be 100644 --- a/xen/arch/riscv/include/asm/irq.h +++ b/xen/arch/riscv/include/asm/irq.h @@ -47,6 +47,9 @@ static inline void arch_move_irqs(struct vcpu *v) BUG_ON("unimplemented"); } +struct dt_device_node; +int platform_get_irq(const struct dt_device_node *device, int index); + void init_IRQ(void); #endif /* ASM__RISCV__IRQ_H */ diff --git a/xen/arch/riscv/irq.c b/xen/arch/riscv/irq.c index 99b8f2095e..c332e000c4 100644 --- a/xen/arch/riscv/irq.c +++ b/xen/arch/riscv/irq.c @@ -7,11 +7,52 @@ */ #include +#include +#include #include #include static irq_desc_t irq_desc[NR_IRQS]; +static bool irq_validate_new_type(unsigned int curr, unsigned int new) +{ + return (curr == IRQ_TYPE_INVALID || curr == new ); +} + +static int irq_set_type(unsigned int irq, unsigned int type) +{ + unsigned long flags; + struct irq_desc *desc = irq_to_desc(irq); + int ret = -EBUSY; + + spin_lock_irqsave(&desc->lock, flags); + + if ( !irq_validate_new_type(desc->arch.type, type) ) + goto err; + + desc->arch.type = type; + + ret = 0; + +err: + spin_unlock_irqrestore(&desc->lock, flags); + + return ret; +} + +int platform_get_irq(const struct dt_device_node *device, int index) +{ + struct dt_irq dt_irq; + + if ( dt_device_get_irq(device, index, &dt_irq) ) + return -1; + + if ( irq_set_type(dt_irq.irq, dt_irq.type) ) + return -1; + + return dt_irq.irq; +} + int arch_init_one_irq_desc(struct irq_desc *desc) { desc->arch.type = IRQ_TYPE_INVALID; From patchwork Tue Apr 8 15:57:10 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Oleksii Kurochko X-Patchwork-Id: 14043257 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.xenproject.org (lists.xenproject.org [192.237.175.120]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 07800C369A5 for ; Tue, 8 Apr 2025 15:57:44 +0000 (UTC) Received: from list by lists.xenproject.org with outflank-mailman.942506.1341688 (Exim 4.92) (envelope-from ) id 1u2BKQ-0005wI-2v; Tue, 08 Apr 2025 15:57:34 +0000 X-Outflank-Mailman: Message body and most headers restored to incoming version Received: by outflank-mailman (output) from mailman id 942506.1341688; Tue, 08 Apr 2025 15:57:34 +0000 Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1u2BKP-0005vT-Qu; Tue, 08 Apr 2025 15:57:33 +0000 Received: by outflank-mailman (input) for mailman id 942506; Tue, 08 Apr 2025 15:57:32 +0000 Received: from se1-gles-flk1-in.inumbo.com ([94.247.172.50] helo=se1-gles-flk1.inumbo.com) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1u2BKO-0004Yq-Ih for xen-devel@lists.xenproject.org; Tue, 08 Apr 2025 15:57:32 +0000 Received: from mail-ej1-x62f.google.com (mail-ej1-x62f.google.com [2a00:1450:4864:20::62f]) by se1-gles-flk1.inumbo.com (Halon) with ESMTPS id 2d6a55dd-1492-11f0-9ffb-bf95429c2676; Tue, 08 Apr 2025 17:57:30 +0200 (CEST) Received: by mail-ej1-x62f.google.com with SMTP id a640c23a62f3a-abf3d64849dso966383466b.3 for ; Tue, 08 Apr 2025 08:57:30 -0700 (PDT) Received: from fedora.. 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As a helper function of_get_cpu_hwid() is introduced to deal specifically with reg propery of a CPU device node. Signed-off-by: Oleksii Kurochko --- xen/arch/riscv/include/asm/smp.h | 3 ++ xen/arch/riscv/smpboot.c | 68 ++++++++++++++++++++++++++++++++ 2 files changed, 71 insertions(+) diff --git a/xen/arch/riscv/include/asm/smp.h b/xen/arch/riscv/include/asm/smp.h index 188c033718..9b68f1e27a 100644 --- a/xen/arch/riscv/include/asm/smp.h +++ b/xen/arch/riscv/include/asm/smp.h @@ -26,6 +26,9 @@ static inline void set_cpuid_to_hartid(unsigned long cpuid, void setup_tp(unsigned int cpuid); +struct dt_device_node; +int riscv_of_processor_hartid(struct dt_device_node *node, unsigned long *hart); + void smp_clear_cpu_maps(void); #endif diff --git a/xen/arch/riscv/smpboot.c b/xen/arch/riscv/smpboot.c index 0f4dcc28e1..3193639f00 100644 --- a/xen/arch/riscv/smpboot.c +++ b/xen/arch/riscv/smpboot.c @@ -1,5 +1,8 @@ #include +#include +#include #include +#include cpumask_t cpu_online_map; cpumask_t cpu_present_map; @@ -13,3 +16,68 @@ void __init smp_clear_cpu_maps(void) cpumask_set_cpu(0, &cpu_online_map); cpumask_copy(&cpu_present_map, &cpu_possible_map); } + +/** + * of_get_cpu_hwid - Get the hardware ID from a CPU device node + * + * @cpun: CPU number(logical index) for which device node is required + * @thread: The local thread number to get the hardware ID for. + * + * Return: The hardware ID for the CPU node or ~0ULL if not found. + */ +static uint64_t of_get_cpu_hwid(struct dt_device_node *cpun, unsigned int thread) +{ + const __be32 *cell; + int ac; + uint32_t len; + + ac = dt_n_addr_cells(cpun); + cell = dt_get_property(cpun, "reg", &len); + if ( !cell || !ac || ((sizeof(*cell) * ac * (thread + 1)) > len) ) + return ~0ULL; + + cell += ac * thread; + return dt_read_number(cell, ac); +} + +/* + * Returns the hart ID of the given device tree node, or -ENODEV if the node + * isn't an enabled and valid RISC-V hart node. + */ +int riscv_of_processor_hartid(struct dt_device_node *node, unsigned long *hart) +{ + const char *isa; + + if ( !dt_device_is_compatible(node, "riscv") ) + { + printk("Found incompatible CPU\n"); + return -ENODEV; + } + + *hart = (unsigned long) of_get_cpu_hwid(node, 0); + if ( *hart == ~0UL ) + { + printk("Found CPU without hart ID\n"); + return -ENODEV; + } + + if ( !dt_device_is_available(node)) + { + printk("CPU with hartid=%lu is not available\n", *hart); + return -ENODEV; + } + + if ( dt_property_read_string(node, "riscv,isa", &isa) ) + { + printk("CPU with hartid=%lu has no \"riscv,isa\" property\n", *hart); + return -ENODEV; + } + + if ( isa[0] != 'r' || isa[1] != 'v' ) + { + printk("CPU with hartid=%lu has an invalid ISA of \"%s\"\n", *hart, isa); + return -ENODEV; + } + + return 0; +} From patchwork Tue Apr 8 15:57:11 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Oleksii Kurochko X-Patchwork-Id: 14043256 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.xenproject.org (lists.xenproject.org [192.237.175.120]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 1A433C369A4 for ; Tue, 8 Apr 2025 15:57:44 +0000 (UTC) Received: from list by lists.xenproject.org with outflank-mailman.942508.1341698 (Exim 4.92) (envelope-from ) id 1u2BKR-0006IR-AC; Tue, 08 Apr 2025 15:57:35 +0000 X-Outflank-Mailman: Message body and most headers restored to incoming version Received: by outflank-mailman (output) from mailman id 942508.1341698; Tue, 08 Apr 2025 15:57:35 +0000 Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1u2BKR-0006He-5j; Tue, 08 Apr 2025 15:57:35 +0000 Received: by outflank-mailman (input) for mailman id 942508; Tue, 08 Apr 2025 15:57:33 +0000 Received: from se1-gles-flk1-in.inumbo.com ([94.247.172.50] helo=se1-gles-flk1.inumbo.com) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1u2BKP-0004Yq-Ii for xen-devel@lists.xenproject.org; Tue, 08 Apr 2025 15:57:33 +0000 Received: from mail-ej1-x635.google.com (mail-ej1-x635.google.com [2a00:1450:4864:20::635]) by se1-gles-flk1.inumbo.com (Halon) with ESMTPS id 2dee1f74-1492-11f0-9ffb-bf95429c2676; Tue, 08 Apr 2025 17:57:31 +0200 (CEST) Received: by mail-ej1-x635.google.com with SMTP id a640c23a62f3a-ac2af2f15d1so776002666b.1 for ; Tue, 08 Apr 2025 08:57:31 -0700 (PDT) Received: from fedora.. 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This structure includes: - A pointer to interrupt controller information (`intc_info`) - Callbacks to initialize the controller and set IRQ type/priority - A reference to an interupt controller descriptor (`host_irq_type`) Also introduce generic helper functions: - `intc_init()`: Initializes the interrupt controller - `register_intc_ops()`: Registers the `intc_hw_operations` implementation - `intc_route_irq_to_xen()`: Configures IRQ routing to Xen, setting handler, type, and priority Most of these functions act as thin wrappers around the corresponding callbacks in `intc_hw_operations`. This abstraction lays the groundwork for supporting multiple interrupt controller types (e.g., PLIC, APLIC) in extensible way. This patch is based on the changes from [1]. [1] https://gitlab.com/xen-project/people/olkur/xen/-/commit/7cfb4bd4748ca268142497ac5c327d2766fb342d Co-developed-by: Romain Caritey Signed-off-by: Oleksii Kurochko --- xen/arch/riscv/include/asm/intc.h | 23 ++++++++++++++ xen/arch/riscv/intc.c | 51 +++++++++++++++++++++++++++++++ 2 files changed, 74 insertions(+) diff --git a/xen/arch/riscv/include/asm/intc.h b/xen/arch/riscv/include/asm/intc.h index 52ba196d87..0d498b10f4 100644 --- a/xen/arch/riscv/include/asm/intc.h +++ b/xen/arch/riscv/include/asm/intc.h @@ -17,6 +17,29 @@ struct intc_info { const struct dt_device_node *node; }; +struct intc_hw_operations { + /* Hold intc hw information */ + const struct intc_info *info; + /* Initialize the intc and the boot CPU */ + int (*init)(void); + + /* hw_irq_controller to enable/disable/eoi host irq */ + hw_irq_controller *host_irq_type; + + /* Set IRQ type */ + void (*set_irq_type)(struct irq_desc *desc, unsigned int type); + /* Set IRQ priority */ + void (*set_irq_priority)(struct irq_desc *desc, unsigned int priority); + +}; + void intc_preinit(void); +void intc_init(void); + +void register_intc_ops(const struct intc_hw_operations *ops); + +struct irq_desc; +void intc_route_irq_to_xen(struct irq_desc *desc, unsigned int priority); + #endif /* ASM__RISCV__INTERRUPT_CONTOLLER_H */ diff --git a/xen/arch/riscv/intc.c b/xen/arch/riscv/intc.c index 4061a3c457..8274897d8c 100644 --- a/xen/arch/riscv/intc.c +++ b/xen/arch/riscv/intc.c @@ -1,9 +1,21 @@ /* SPDX-License-Identifier: GPL-2.0-only */ #include +#include #include #include +#include #include +#include + +#include + +static const struct intc_hw_operations *intc_hw_ops; + +void register_intc_ops(const struct intc_hw_operations *ops) +{ + intc_hw_ops = ops; +} void __init intc_preinit(void) { @@ -12,3 +24,42 @@ void __init intc_preinit(void) else panic("ACPI interrupt controller preinit() isn't implemented\n"); } + +void __init intc_init(void) +{ + ASSERT(intc_hw_ops); + + if ( intc_hw_ops->init() ) + panic("Failed to initialize the interrupt controller drivers\n"); +} + +/* desc->irq needs to be disabled before calling this function */ +static void intc_set_irq_type(struct irq_desc *desc, unsigned int type) +{ + ASSERT(test_bit(_IRQ_DISABLED, &desc->status)); + ASSERT(spin_is_locked(&desc->lock)); + ASSERT(type != IRQ_TYPE_INVALID); + ASSERT(intc_hw_ops && intc_hw_ops->set_irq_type); + + intc_hw_ops->set_irq_type(desc, type); +} + +static void intc_set_irq_priority(struct irq_desc *desc, unsigned int priority) +{ + ASSERT(intc_hw_ops && intc_hw_ops->set_irq_priority); + + intc_hw_ops->set_irq_priority(desc, priority); +} + +void intc_route_irq_to_xen(struct irq_desc *desc, unsigned int priority) +{ + ASSERT(test_bit(_IRQ_DISABLED, &desc->status)); + ASSERT(spin_is_locked(&desc->lock)); + /* Can't route interrupts that don't exist */ + ASSERT(intc_hw_ops && desc->irq < intc_hw_ops->info->nr_irqs); + + desc->handler = intc_hw_ops->host_irq_type; + + intc_set_irq_type(desc, desc->arch.type); + intc_set_irq_priority(desc, priority); +} From patchwork Tue Apr 8 15:57:13 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Oleksii Kurochko X-Patchwork-Id: 14043260 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.xenproject.org (lists.xenproject.org [192.237.175.120]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 80A4DC369A9 for ; Tue, 8 Apr 2025 15:57:46 +0000 (UTC) Received: from list by lists.xenproject.org with outflank-mailman.942511.1341709 (Exim 4.92) (envelope-from ) id 1u2BKS-0006ag-RZ; Tue, 08 Apr 2025 15:57:36 +0000 X-Outflank-Mailman: Message body and most headers restored to incoming version Received: by outflank-mailman (output) from mailman id 942511.1341709; Tue, 08 Apr 2025 15:57:36 +0000 Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1u2BKS-0006XF-DK; Tue, 08 Apr 2025 15:57:36 +0000 Received: by outflank-mailman (input) for mailman id 942511; Tue, 08 Apr 2025 15:57:35 +0000 Received: from se1-gles-sth1-in.inumbo.com ([159.253.27.254] helo=se1-gles-sth1.inumbo.com) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1u2BKQ-0004Yr-Sf for xen-devel@lists.xenproject.org; Tue, 08 Apr 2025 15:57:35 +0000 Received: from mail-ej1-x62a.google.com (mail-ej1-x62a.google.com [2a00:1450:4864:20::62a]) by se1-gles-sth1.inumbo.com (Halon) with ESMTPS id 2f53f27d-1492-11f0-9eaa-5ba50f476ded; Tue, 08 Apr 2025 17:57:34 +0200 (CEST) Received: by mail-ej1-x62a.google.com with SMTP id a640c23a62f3a-ac28e66c0e1so874035966b.0 for ; Tue, 08 Apr 2025 08:57:34 -0700 (PDT) Received: from fedora.. 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[109.243.64.225]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-ac7c018556bsm929934566b.156.2025.04.08.08.57.32 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 08 Apr 2025 08:57:32 -0700 (PDT) X-BeenThere: xen-devel@lists.xenproject.org List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Errors-To: xen-devel-bounces@lists.xenproject.org Precedence: list Sender: "Xen-devel" X-Inumbo-ID: 2f53f27d-1492-11f0-9eaa-5ba50f476ded DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20230601; t=1744127853; x=1744732653; darn=lists.xenproject.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=d/3dao7nIwQTt2SEejDxKzt5Yw5IJNGsAcfMnIvzhVs=; b=kSWvFXs3y6DjB4CFA/rpOIdh9YOUQtRPc6SoXoJk6Ze81yT5TTKUh81DzhFHevI795 0btX8pLXam9GXuYvYn8l8wOywHlqTLjsSznCcWH9pv8HuIVmzNtQYSHsmvJoNprKn1mS 4i4MrI/9m7I6e+dkd6p3jD8uaJrN1nzkr+GFRTORwjX8QN1/2Kit6irt1rXwDd+AOVeL wRKYeE2ROql8CeGwBe867w3RPNwjBUotWkuVi97obdT0+G6agUFb7TsOlIt5+I4aA4fQ EO0Bud7GdWwADHpXSxrfz7bzz8mgrie6t7fc/lETcUiZHxptk8lzzBlNSehtAW5I47Co MzAQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1744127853; x=1744732653; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=d/3dao7nIwQTt2SEejDxKzt5Yw5IJNGsAcfMnIvzhVs=; b=DlzWVD2sBJnaAfWlaPxNuyS0ZOVnwmYA8+x/FBE1YjOOGROraYJRIaIBQXqSJRnkxc pk4YkssaHL0sI7X7TMAuZQXG3icX0hjtEQViWyhjoA9q34nbCvH2kcx9U25UZx0lrLjP Os/YyYDWLOGL95eph7j5YwCq1fq4kzTbKT2M4ichEAPqGSke464bSiqe17waRJGwxZQG Zg9S2v/VBboDeet+0zxaBx9vdNq+9li+wVdRBqQ3C44+x4zNBLJa4H5hHaWpzWYSfOR3 lewlVATJiXTDaldlTtUUYT+LZnVZFhR+VTf7AvmmxBCgRQ8N9TasE3H4lvUGLB2UnOfJ dt3A== X-Gm-Message-State: AOJu0YyUK2ow666GIsiXas9yySnjJocnXJNbvDuB4QtEo9/PBPM4DinL eLCYFfyUqYESJylD50P0WustRO95W1Vflonqh5FZG6sb44H0sVLglA5MHA== X-Gm-Gg: ASbGnctCGMuCzqMlGPx2Zr5t2BZ2/gfMiq+jO3fLQdvXJRePIt6RLgDvQlayhzLnhYC c2yTZyyUjzy1UVxs4/rml2xpVGSh17wTXQEF8B5yR/jwxtnhaXpTLXSgyScZ0NCwPJ8DKQ4LggK nF0jbKMjXvMoWonujzHRhiCYCkfiNp+ND97GbGnmjYQ+XJ5gEvB5SNPuJXw37WLGCyCtTJcee2z CJelfpuwAfhlYvIjeXHfvhCeYfFv2uwkxzmcMdi1WSBXhjT6gZDGslwOE3Ms4hH1YIdPSS8LCPZ jSgfZTdadbTqedXrao5UZgwMXd8dqewIl1MNH8tFJQ9NmRixZ5odbMbVdim+T9PwMSKiYiXOGbb KOUMq2oBqvLZTruURNBpMgshw X-Google-Smtp-Source: AGHT+IFwUUIkpfovoMDrPcqwhafTmBhx2g+D+hqeENK4vIZ7x9JFl5bRBtLOBsCJtqT3stqYNhsraA== X-Received: by 2002:a17:907:2d2b:b0:ac2:fd70:dda3 with SMTP id a640c23a62f3a-ac7d6d73905mr1303765366b.35.1744127853058; Tue, 08 Apr 2025 08:57:33 -0700 (PDT) From: Oleksii Kurochko To: xen-devel@lists.xenproject.org Cc: Oleksii Kurochko , Alistair Francis , Bob Eshleman , Connor Davis , Andrew Cooper , Anthony PERARD , Michal Orzel , Jan Beulich , Julien Grall , =?utf-8?q?Roger_Pau_Monn=C3=A9?= , Stefano Stabellini , Romain Caritey Subject: [PATCH v1 08/14] xen/riscv: imsic_init() implementation Date: Tue, 8 Apr 2025 17:57:13 +0200 Message-ID: <09e0fcd64f97062441a68102ead520b818150fe9.1744126720.git.oleksii.kurochko@gmail.com> X-Mailer: git-send-email 2.49.0 In-Reply-To: References: MIME-Version: 1.0 imsic_init() is introduced to parse device tree node, which has the following bindings [2], and based on the parsed information update IMSIC configuration which is stored in imsic_cfg. The following helpers are introduces for imsic_init() usage: - imsic_parse_node() parses IMSIC node from DTS - imsic_get_parent_hartid() returns the hart ( CPU ) ID of the given device tree node. This patch is based on the code from [1]. Since Microchip originally developed imsic.{c,h}, an internal discussion with them led to the decision to use the MIT license. [1] https://gitlab.com/xen-project/people/olkur/xen/-/commit/0b1a94f2bc3bb1a81cd26bb75f0bf578f84cb4d4 [2] https://elixir.bootlin.com/linux/v6.12/source/Documentation/devicetree/bindings/interrupt-controller/riscv,imsics.yaml Co-developed-by: Romain Caritey Signed-off-by: Oleksii Kurochko --- xen/arch/riscv/Makefile | 1 + xen/arch/riscv/imsic.c | 286 +++++++++++++++++++++++++++++ xen/arch/riscv/include/asm/imsic.h | 66 +++++++ 3 files changed, 353 insertions(+) create mode 100644 xen/arch/riscv/imsic.c create mode 100644 xen/arch/riscv/include/asm/imsic.h diff --git a/xen/arch/riscv/Makefile b/xen/arch/riscv/Makefile index 457e8e88a4..baa499a72d 100644 --- a/xen/arch/riscv/Makefile +++ b/xen/arch/riscv/Makefile @@ -2,6 +2,7 @@ obj-y += aplic.o obj-y += cpufeature.o obj-$(CONFIG_EARLY_PRINTK) += early_printk.o obj-y += entry.o +obj-y += imsic.o obj-y += intc.o obj-y += irq.o obj-y += mm.o diff --git a/xen/arch/riscv/imsic.c b/xen/arch/riscv/imsic.c new file mode 100644 index 0000000000..99def9af2d --- /dev/null +++ b/xen/arch/riscv/imsic.c @@ -0,0 +1,286 @@ +/* SPDX-License-Identifier: MIT */ + +/* + * xen/arch/riscv/imsic.c + * + * RISC-V Incoming MSI Controller support + * + * (c) 2023 Microchip Technology Inc. + * (c) 2024 Vates + */ + +#include +#include +#include +#include +#include +#include + +#include + +static struct imsic_config imsic_cfg; + +const struct imsic_config *imsic_get_config(void) +{ + return &imsic_cfg; +} + +static int __init imsic_get_parent_hartid(struct dt_device_node *node, + unsigned int index, + unsigned long *hartid) +{ + int res; + unsigned long hart; + struct dt_phandle_args args; + + /* Try the new-style interrupts-extended first */ + res = dt_parse_phandle_with_args(node, "interrupts-extended", + "#interrupt-cells", index, &args); + if ( !res ) + { + res = riscv_of_processor_hartid(args.np->parent, &hart); + if ( res < 0 ) + return -EINVAL; + + *hartid = hart; + } + return res; +} + + +static int imsic_parse_node(struct dt_device_node *node, + unsigned int *nr_parent_irqs) +{ + int rc; + unsigned int tmp; + paddr_t base_addr; + + /* Find number of parent interrupts */ + *nr_parent_irqs = dt_number_of_irq(node); + if ( !*nr_parent_irqs ) + { + printk(XENLOG_ERR "%s: no parent irqs available\n", node->name); + return -ENOENT; + } + + /* Find number of guest index bits in MSI address */ + rc = dt_property_read_u32(node, "riscv,guest-index-bits", + &imsic_cfg.guest_index_bits); + if ( !rc ) + imsic_cfg.guest_index_bits = 0; + tmp = BITS_PER_LONG - IMSIC_MMIO_PAGE_SHIFT; + if ( tmp < imsic_cfg.guest_index_bits ) + { + printk(XENLOG_ERR "%s: guest index bits too big\n", node->name); + return -ENOENT; + } + + /* Find number of HART index bits */ + rc = dt_property_read_u32(node, "riscv,hart-index-bits", + &imsic_cfg.hart_index_bits); + if ( !rc ) + { + /* Assume default value */ + imsic_cfg.hart_index_bits = fls(*nr_parent_irqs); + if ( BIT(imsic_cfg.hart_index_bits, UL) < *nr_parent_irqs ) + imsic_cfg.hart_index_bits++; + } + tmp = BITS_PER_LONG - IMSIC_MMIO_PAGE_SHIFT - + imsic_cfg.guest_index_bits; + if ( tmp < imsic_cfg.hart_index_bits ) + { + printk(XENLOG_ERR "%s: HART index bits too big\n", node->name); + return -ENOENT; + } + + /* Find number of group index bits */ + rc = dt_property_read_u32(node, "riscv,group-index-bits", + &imsic_cfg.group_index_bits); + if ( !rc ) + imsic_cfg.group_index_bits = 0; + tmp = BITS_PER_LONG - IMSIC_MMIO_PAGE_SHIFT - + imsic_cfg.guest_index_bits - imsic_cfg.hart_index_bits; + if ( tmp < imsic_cfg.group_index_bits ) + { + printk(XENLOG_ERR "%s: group index bits too big\n", node->name); + return -ENOENT; + } + + /* Find first bit position of group index */ + tmp = IMSIC_MMIO_PAGE_SHIFT * 2; + rc = dt_property_read_u32(node, "riscv,group-index-shift", + &imsic_cfg.group_index_shift); + if ( !rc ) + imsic_cfg.group_index_shift = tmp; + if ( imsic_cfg.group_index_shift < tmp ) + { + printk(XENLOG_ERR "%s: group index shift too small\n", node->name); + return -ENOENT; + } + tmp = imsic_cfg.group_index_bits + imsic_cfg.group_index_shift - 1; + if ( tmp >= BITS_PER_LONG ) + { + printk(XENLOG_ERR "%s: group index shift too big\n", node->name); + return -EINVAL; + } + + /* Find number of interrupt identities */ + rc = dt_property_read_u32(node, "riscv,num-ids", &imsic_cfg.nr_ids); + if ( !rc ) + { + printk(XENLOG_ERR "%s: number of interrupt identities not found\n", + node->name); + return -ENOENT; + } + + if ( (imsic_cfg.nr_ids < IMSIC_MIN_ID) || + (imsic_cfg.nr_ids >= IMSIC_MAX_ID) || + ((imsic_cfg.nr_ids & IMSIC_MIN_ID) != IMSIC_MIN_ID) ) + { + printk(XENLOG_ERR "%s: invalid number of interrupt identities\n", + node->name); + return -EINVAL; + } + + /* Compute base address */ + imsic_cfg.nr_mmios = 0; + rc = dt_device_get_address(node, imsic_cfg.nr_mmios, &base_addr, NULL); + if (rc) + { + printk(XENLOG_ERR "%s: first MMIO resource not found\n", node->name); + return -EINVAL; + } + + imsic_cfg.base_addr = base_addr; + imsic_cfg.base_addr &= ~(BIT(imsic_cfg.guest_index_bits + + imsic_cfg.hart_index_bits + + IMSIC_MMIO_PAGE_SHIFT, UL) - 1); + imsic_cfg.base_addr &= ~((BIT(imsic_cfg.group_index_bits, UL) - 1) << + imsic_cfg.group_index_shift); + + /* Find number of MMIO register sets */ + imsic_cfg.nr_mmios++; + while ( !dt_device_get_address(node, imsic_cfg.nr_mmios, &base_addr, NULL) ) + imsic_cfg.nr_mmios++; + + return 0; +} + +int __init imsic_init(struct dt_device_node *node) +{ + int rc; + unsigned long reloff, hartid; + uint32_t nr_parent_irqs, index, nr_handlers = 0; + paddr_t base_addr; + + /* Parse IMSIC node */ + rc = imsic_parse_node(node, &nr_parent_irqs); + if ( rc ) + return rc; + + /* Allocate MMIO resource array */ + imsic_cfg.mmios = xzalloc_array(struct imsic_mmios, imsic_cfg.nr_mmios); + if ( !imsic_cfg.mmios ) + return -ENOMEM; + + /* check MMIO register sets */ + for ( int i = 0; i < imsic_cfg.nr_mmios; i++ ) + { + rc = dt_device_get_address(node, i, &imsic_cfg.mmios[i].base_addr, + &imsic_cfg.mmios[i].size); + if ( rc ) + { + printk(XENLOG_ERR "%s: unable to parse MMIO regset %d\n", + node->name, i); + goto imsic_init_err; + } + + base_addr = imsic_cfg.mmios[i].base_addr; + base_addr &= ~(BIT(imsic_cfg.guest_index_bits + + imsic_cfg.hart_index_bits + + IMSIC_MMIO_PAGE_SHIFT, UL) - 1); + base_addr &= ~((BIT(imsic_cfg.group_index_bits, UL) - 1) << + imsic_cfg.group_index_shift); + if ( base_addr != imsic_cfg.base_addr ) + { + rc = -EINVAL; + printk(XENLOG_ERR "%s: address mismatch for regset %d\n", + node->name, i); + goto imsic_init_err; + } + } + + /* Configure handlers for target CPUs */ + for ( int i = 0; i < nr_parent_irqs; i++ ) + { + rc = imsic_get_parent_hartid(node, i, &hartid); + if ( rc ) + { + printk(XENLOG_WARNING "%s: hart ID for parent irq%d not found\n", + node->name, i); + continue; + } + + if ( hartid > NR_CPUS ) + { + printk(XENLOG_WARNING "%s: unsupported hart ID=%lu for parent irq%d\n", + node->name, hartid, i); + continue; + } + + /* Find MMIO location of MSI page */ + index = imsic_cfg.nr_mmios; + reloff = i * BIT(imsic_cfg.guest_index_bits, UL) * IMSIC_MMIO_PAGE_SZ; + for ( int j = 0; imsic_cfg.nr_mmios; j++ ) + { + if ( reloff < imsic_cfg.mmios[j].size ) + { + index = j; + break; + } + + /* + * MMIO region size may not be aligned to + * BIT(global->guest_index_bits) * IMSIC_MMIO_PAGE_SZ + * if holes are present. + */ + reloff -= ROUNDUP(imsic_cfg.mmios[j].size, + BIT(imsic_cfg.guest_index_bits, UL) * IMSIC_MMIO_PAGE_SZ); + } + + if ( index >= imsic_cfg.nr_mmios ) + { + printk(XENLOG_WARNING "%s: MMIO not found for parent irq%d\n", + node->name, i); + continue; + } + + if ( !IS_ALIGNED(imsic_cfg.msi[hartid].base_addr + reloff, PAGE_SIZE) ) + { + printk(XENLOG_WARNING "%s: MMIO address 0x%lx is not aligned on a page\n", + node->name, imsic_cfg.msi[hartid].base_addr + reloff); + imsic_cfg.msi[hartid].offset = 0; + imsic_cfg.msi[hartid].base_addr = 0; + continue; + } + + imsic_cfg.mmios[index].harts[hartid] = true; + imsic_cfg.msi[hartid].base_addr = imsic_cfg.mmios[index].base_addr; + imsic_cfg.msi[hartid].offset = reloff; + nr_handlers++; + } + + if ( !nr_handlers ) + { + printk(XENLOG_ERR "%s: No CPU handlers found\n", node->name); + rc = -ENODEV; + goto imsic_init_err; + } + + return 0; + +imsic_init_err: + xfree(imsic_cfg.mmios); + + return rc; +} diff --git a/xen/arch/riscv/include/asm/imsic.h b/xen/arch/riscv/include/asm/imsic.h new file mode 100644 index 0000000000..126e651863 --- /dev/null +++ b/xen/arch/riscv/include/asm/imsic.h @@ -0,0 +1,66 @@ +/* SPDX-License-Identifier: MIT */ + +/* + * xen/arch/riscv/imsic.h + * + * RISC-V Incoming MSI Controller support + * + * (c) 2023 Microchip Technology Inc. + */ + +#ifndef ASM__RISCV__IMSIC_H +#define ASM__RISCV__IMSIC_H + +#include + +#define IMSIC_MMIO_PAGE_SHIFT 12 +#define IMSIC_MMIO_PAGE_SZ (1UL << IMSIC_MMIO_PAGE_SHIFT) + +#define IMSIC_MIN_ID 63 +#define IMSIC_MAX_ID 2048 + +struct imsic_msi { + paddr_t base_addr; + unsigned long offset; +}; + +struct imsic_mmios { + paddr_t base_addr; + unsigned long size; + bool harts[NR_CPUS]; +}; + +struct imsic_config { + /* base address */ + paddr_t base_addr; + + /* Bits representing Guest index, HART index, and Group index */ + unsigned int guest_index_bits; + unsigned int hart_index_bits; + unsigned int group_index_bits; + unsigned int group_index_shift; + + /* imsic phandle */ + unsigned int phandle; + + /* number of parent irq */ + unsigned int nr_parent_irqs; + + /* number off interrupt identities */ + unsigned int nr_ids; + + /* mmios */ + unsigned int nr_mmios; + struct imsic_mmios *mmios; + + /* MSI */ + struct imsic_msi msi[NR_CPUS]; +}; + +struct dt_device_node; +int imsic_init(struct dt_device_node *n); + +struct imsic_config; +const struct imsic_config *imsic_get_config(void); + +#endif /* ASM__RISCV__IMSIC_H */ From patchwork Tue Apr 8 15:57:14 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Oleksii Kurochko X-Patchwork-Id: 14043259 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.xenproject.org (lists.xenproject.org [192.237.175.120]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 66191C369A2 for ; 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Since Microchip originally developed aplic.c, an internal discussion with them led to the decision to use the MIT license. [1] https://gitlab.com/xen-project/people/olkur/xen/-/commit/7cfb4bd4748ca268142497ac5c327d2766fb342d [2] https://gitlab.com/xen-project/people/olkur/xen/-/commit/392a531bfad39bf4656ce8128e004b241b8b3f3e Co-developed-by: Romain Caritey Signed-off-by: Oleksii Kurochko --- xen/arch/riscv/aplic.c | 97 ++++++++++++++++++++++++++++++ xen/arch/riscv/include/asm/aplic.h | 77 ++++++++++++++++++++++++ xen/arch/riscv/include/asm/intc.h | 3 + xen/arch/riscv/include/asm/irq.h | 1 - 4 files changed, 177 insertions(+), 1 deletion(-) create mode 100644 xen/arch/riscv/include/asm/aplic.h diff --git a/xen/arch/riscv/aplic.c b/xen/arch/riscv/aplic.c index 6dc040af6f..d1aa835c3e 100644 --- a/xen/arch/riscv/aplic.c +++ b/xen/arch/riscv/aplic.c @@ -9,19 +9,112 @@ * Copyright (c) 2024-2025 Vates */ +#include #include #include #include +#include #include #include +#include +#include #include +#include #include +#include + +#define APLIC_DEFAULT_PRIORITY 1 + +static struct aplic_priv aplic; static struct intc_info __ro_after_init aplic_info = { .hw_version = INTC_APLIC, }; +static void __init aplic_init_hw_interrupts(void) +{ + int i; + + /* Disable all interrupts */ + for ( i = 0; i <= aplic_info.nr_irqs; i += 32 ) + aplic.regs->clrie[i] = -1U; + + /* Set interrupt type and default priority for all interrupts */ + for ( i = 1; i <= aplic_info.nr_irqs; i++ ) + { + aplic.regs->sourcecfg[i - 1] = 0; + aplic.regs->target[i - 1] = APLIC_DEFAULT_PRIORITY; + } + + /* Clear APLIC domaincfg */ + aplic.regs->domaincfg = APLIC_DOMAINCFG_IE | APLIC_DOMAINCFG_DM; +} + +static int __init aplic_init(void) +{ + int rc; + dt_phandle imsic_phandle; + uint32_t irq_range[2]; + const __be32 *prop; + uint64_t size, paddr; + struct dt_device_node *imsic_node; + const struct dt_device_node *node = aplic_info.node; + + /* check for associated imsic node */ + rc = dt_property_read_u32(node, "msi-parent", &imsic_phandle); + if ( !rc ) + panic("%s: IDC mode not supported\n", node->full_name); + + imsic_node = dt_find_node_by_phandle(imsic_phandle); + if ( !imsic_node ) + panic("%s: unable to find IMSIC node\n", node->full_name); + + /* check imsic mode */ + rc = dt_property_read_u32_array(imsic_node, "interrupts-extended", + irq_range, ARRAY_SIZE(irq_range)); + if ( rc && (rc != -EOVERFLOW) ) + panic("%s: unable to find interrupt-extended in %s node\n", + node->full_name, imsic_node->full_name); + + if ( irq_range[1] == IRQ_M_EXT ) + /* machine mode imsic node, ignore this aplic node */ + return 0; + + rc = imsic_init(imsic_node); + if ( rc ) + panic("%s: Failded to initialize IMSIC\n", node->full_name); + + /* Find out number of interrupt sources */ + rc = dt_property_read_u32(node, "riscv,num-sources", &aplic_info.nr_irqs); + if ( !rc ) + panic("%s: failed to get number of interrupt sources\n", + node->full_name); + + prop = dt_get_property(node, "reg", NULL); + dt_get_range(&prop, node, &paddr, &size); + if ( !paddr ) + panic("%s: first MMIO resource not found\n", node->full_name); + + aplic.paddr_start = paddr; + aplic.paddr_end = paddr + size; + aplic.size = size; + + aplic.regs = ioremap(paddr, size); + if ( !aplic.regs ) + panic("%s: unable to map\n", node->full_name); + + /* Setup initial state APLIC interrupts */ + aplic_init_hw_interrupts(); + + return 0; +} + +static const struct intc_hw_operations __ro_after_init aplic_ops = { + .info = &aplic_info, + .init = aplic_init, +}; + static int aplic_irq_xlate(const uint32_t *intspec, unsigned int intsize, unsigned int *out_hwirq, unsigned int *out_type) @@ -52,8 +145,12 @@ static int __init aplic_preinit(struct dt_device_node *node, const void *dat) aplic_info.node = node; + aplic.imsic_cfg = imsic_get_config(); + dt_irq_xlate = aplic_irq_xlate; + register_intc_ops(&aplic_ops); + return 0; } diff --git a/xen/arch/riscv/include/asm/aplic.h b/xen/arch/riscv/include/asm/aplic.h new file mode 100644 index 0000000000..94b3d0b616 --- /dev/null +++ b/xen/arch/riscv/include/asm/aplic.h @@ -0,0 +1,77 @@ +/* SPDX-License-Identifier: MIT */ + +/* + * xen/arch/riscv/aplic.h + * + * RISC-V Advanced Platform-Level Interrupt Controller support + * + * Copyright (c) 2023 Microchip. + */ + +#ifndef ASM__RISCV__APLIC_H +#define ASM__RISCV__APLIC_H + +#include + +#include + +#define APLIC_DOMAINCFG_IE BIT(8, UL) +#define APLIC_DOMAINCFG_DM BIT(2, UL) + +struct aplic_regs { + uint32_t domaincfg; + uint32_t sourcecfg[1023]; + uint8_t _reserved1[0xBC0]; + + uint32_t mmsiaddrcfg; + uint32_t mmsiaddrcfgh; + uint32_t smsiaddrcfg; + uint32_t smsiaddrcfgh; + uint8_t _reserved2[0x30]; + + uint32_t setip[32]; + uint8_t _reserved3[92]; + + uint32_t setipnum; + uint8_t _reserved4[0x20]; + + uint32_t in_clrip[32]; + uint8_t _reserved5[92]; + + uint32_t clripnum; + uint8_t _reserved6[32]; + + uint32_t setie[32]; + uint8_t _reserved7[92]; + + uint32_t setienum; + uint8_t _reserved8[32]; + + uint32_t clrie[32]; + uint8_t _reserved9[92]; + + uint32_t clrienum; + uint8_t _reserved10[32]; + + uint32_t setipnum_le; + uint32_t setipnum_be; + uint8_t _reserved11[4088]; + + uint32_t genmsi; + uint32_t target[1023]; +}; + +struct aplic_priv { + /* base physical address and size */ + paddr_t paddr_start; + paddr_t paddr_end; + size_t size; + + /* registers */ + volatile struct aplic_regs *regs; + + /* imsic configuration */ + const struct imsic_config *imsic_cfg; +}; + +#endif /* ASM__RISCV__APLIC_H */ diff --git a/xen/arch/riscv/include/asm/intc.h b/xen/arch/riscv/include/asm/intc.h index 0d498b10f4..db53caa07b 100644 --- a/xen/arch/riscv/include/asm/intc.h +++ b/xen/arch/riscv/include/asm/intc.h @@ -15,6 +15,9 @@ enum intc_version { struct intc_info { enum intc_version hw_version; const struct dt_device_node *node; + + /* number of irqs */ + unsigned int nr_irqs; }; struct intc_hw_operations { diff --git a/xen/arch/riscv/include/asm/irq.h b/xen/arch/riscv/include/asm/irq.h index ff1c95e0be..163a478d78 100644 --- a/xen/arch/riscv/include/asm/irq.h +++ b/xen/arch/riscv/include/asm/irq.h @@ -27,7 +27,6 @@ #define IRQ_TYPE_INVALID DT_IRQ_TYPE_INVALID /* TODO */ -#define nr_irqs 0U #define nr_static_irqs 0 #define arch_hwdom_irqs(domid) 0U From patchwork Tue Apr 8 15:57:15 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Oleksii Kurochko X-Patchwork-Id: 14043310 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.xenproject.org (lists.xenproject.org [192.237.175.120]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id C4FFAC369A2 for ; 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[109.243.64.225]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-ac7c018556bsm929934566b.156.2025.04.08.08.57.34 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 08 Apr 2025 08:57:34 -0700 (PDT) X-BeenThere: xen-devel@lists.xenproject.org List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Errors-To: xen-devel-bounces@lists.xenproject.org Precedence: list Sender: "Xen-devel" X-Inumbo-ID: 30a2b2f0-1492-11f0-9ffb-bf95429c2676 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20230601; t=1744127855; x=1744732655; darn=lists.xenproject.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=obosTziijTFYXfPLbOAwqyMHx7uiRBVtztO5FdIKDt0=; b=WTecgZ75a8WNbXJ4hgvY9ID1Hs5jEjE/lJzgKv7ikrrSjl1SeDFDG14YKzlAISkhCX P26IEAlpsPnuow0Oui6GPe6qHtFpRx6B75FaKkmSyWMoF1LJka7lFUxASvPWmR3yD/Cx vFyI2BsXXJNXoQQJvrtxwrVubJITjmBd1lp4Xe61SQe4tKvPsg0604Vq5vpr35IV7QLD 5WBRDL5mQMoPMk1pDqpWiztjBRJShbHDfG1fZl7T8XqJ2yOZ2UbKrVR1FIwZiAVI9F/w f8LTr1QV0rB45O+O5qZUFgK7Qb2rnJiUIvGfaD8UyMnhgHUqSSfpWYUelCB1dLh+nS5w gRtw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1744127855; x=1744732655; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=obosTziijTFYXfPLbOAwqyMHx7uiRBVtztO5FdIKDt0=; b=KEiTAQpmWcSpcQoVoi3lJ0rgSpypYJc6/YBRqnDC47iCNjUBmiPfHXIsaSzNwn22uS fzHsSIsT4koco61/AhzlVo+0SOd9RQizmOfcCPr3Ie9Vt1VOcQ+SkMGninV0i+FuHZJR nrTUi2GkiOEvxuQ4v4BJSZ6234XYtZhAcjgS9p9XBvpW6Ib4FjaaeEhRnzTDwNVFs7+m pWcbV6SSppn0h3dshmlMR97CfYrpQiofMHO2pMTM4PpedznVtoQitAH/nXoLLP2lxrxL bv9QYuYXAjezfLtt8kiSwntvMs1EQvq7eL2uq77v7lftA4aT9PuGiylICeISdttkSbFb lWQw== X-Gm-Message-State: AOJu0Yx4Laz8P1v5nka0ZCPzvWePg1Z5HFtDJDiEvcJk7fx1WQUOX4Pc pSIcGHjc4/lt+mO6VchYDcUweyL0XBQ3Cv4h25NtYVLwij8RqnyEkJCTvA== X-Gm-Gg: ASbGnctUFOMTA+PikQd6582BsnDomEfClj3ljVDWbJSI8Xp/VZ0fIUlP9jiBuWsd+0v YekJu7Jrcsn/KHJrSidFD0IT1FTMH5UyNowZuYG1Y80sEyjQO4qD4SxvEyt62T/xqWpHjReofp0 uXqIw62kpLoeSmULzh6n3TxhWQjixXFuGHD62ldBlh2rd+K/z9+TCwDKyYrp+pWXwnp5XhYaudY y3wp9vv9kUgTrQ6V9UQfvJJdGjyaHnH+xHiKOo0VyjQn/HeNw76tgH559yHGuuyv54fJuefAMKP ZqMM/AzhN9GAc9JMBeiHQsP8bwuUMVj6eS5DvkyIj8NJFryzoNanCpekG6TEKCzubqwHNx1xmlU Ihe02CkwAEQkIYw== X-Google-Smtp-Source: AGHT+IEGspGPs+MME//LE3RWoyJqDPz+WYmt7DGj67vMc+ReaBhJ3Bcm6MIfxc1z+iw9GyXf45JObA== X-Received: by 2002:a17:907:724f:b0:ac2:cdcb:6a85 with SMTP id a640c23a62f3a-ac7d6d2b3f4mr1436812166b.22.1744127855300; Tue, 08 Apr 2025 08:57:35 -0700 (PDT) From: Oleksii Kurochko To: xen-devel@lists.xenproject.org Cc: Oleksii Kurochko , Alistair Francis , Bob Eshleman , Connor Davis , Andrew Cooper , Anthony PERARD , Michal Orzel , Jan Beulich , Julien Grall , =?utf-8?q?Roger_Pau_Monn=C3=A9?= , Stefano Stabellini , Romain Caritey Subject: [PATCH v1 10/14] xen/riscv: implementation of aplic and imsic operations Date: Tue, 8 Apr 2025 17:57:15 +0200 Message-ID: <74a07ed7c596bbcf581010685e01bfdfa19164f5.1744126720.git.oleksii.kurochko@gmail.com> X-Mailer: git-send-email 2.49.0 In-Reply-To: References: MIME-Version: 1.0 Introduce interrupt controller descriptor for host APLIC to describe the low-lovel hardare. It includes implementation of the following functions: - aplic_irq_startup() - aplic_irq_shutdown() - aplic_irq_enable() - aplic_irq_disable() - aplic_irq_ack() - aplic_host_irq_end() - aplic_set_irq_affinity() As APLIC is used in MSI mode it requires to enable/disable interrupts not only for APLIC but also for IMSIC. Thereby for the purpose of aplic_irq_{enable,disable}() it is introduced imsic_irq_{enable,disable)(). For the purpose of aplic_set_irq_affinity() aplic_get_cpu_from_mask() is introduced to get hart id. Also, introduce additional interrupt controller h/w operations and host_irq_type for APLIC: - aplic_host_irq_type - aplic_set_irq_priority() - aplic_set_irq_type() Patch is based on the code from [1]. [1] https://gitlab.com/xen-project/people/olkur/xen/-/commit/7390e2365828b83e27ead56b03114a56e3699dd5 Co-developed-by: Romain Caritey Signed-off-by: Oleksii Kurochko --- xen/arch/riscv/aplic.c | 169 ++++++++++++++++++++++++++++- xen/arch/riscv/imsic.c | 63 +++++++++++ xen/arch/riscv/include/asm/aplic.h | 12 ++ xen/arch/riscv/include/asm/imsic.h | 15 +++ 4 files changed, 258 insertions(+), 1 deletion(-) diff --git a/xen/arch/riscv/aplic.c b/xen/arch/riscv/aplic.c index d1aa835c3e..4b60cb9a77 100644 --- a/xen/arch/riscv/aplic.c +++ b/xen/arch/riscv/aplic.c @@ -15,6 +15,7 @@ #include #include #include +#include #include #include @@ -110,9 +111,173 @@ static int __init aplic_init(void) return 0; } -static const struct intc_hw_operations __ro_after_init aplic_ops = { +static void aplic_set_irq_type(struct irq_desc *desc, unsigned int type) +{ + unsigned int irq = desc->irq - 1; + + spin_lock(&aplic.lock); + switch(type) { + case IRQ_TYPE_EDGE_RISING: + aplic.regs->sourcecfg[irq] = APLIC_SOURCECFG_SM_EDGE_RISE; + break; + case IRQ_TYPE_EDGE_FALLING: + aplic.regs->sourcecfg[irq] = APLIC_SOURCECFG_SM_EDGE_FALL; + break; + case IRQ_TYPE_LEVEL_HIGH: + aplic.regs->sourcecfg[irq] = APLIC_SOURCECFG_SM_LEVEL_HIGH; + break; + case IRQ_TYPE_LEVEL_LOW: + aplic.regs->sourcecfg[irq] = APLIC_SOURCECFG_SM_LEVEL_LOW; + break; + default: + aplic.regs->sourcecfg[irq] = APLIC_SOURCECFG_SM_INACTIVE; + break; + } + spin_unlock(&aplic.lock); +} + +static void aplic_set_irq_priority(struct irq_desc *desc, + unsigned int priority) +{ + /* No priority, do nothing */ +} + +static void aplic_irq_enable(struct irq_desc *desc) +{ + unsigned long flags; + + /* + * TODO: Currently, APLIC is supported only with MSI interrupts. + * If APLIC without MSI interrupts is required in the future, + * this function will need to be updated accordingly. + */ + ASSERT(aplic.imsic_cfg->is_used); + + ASSERT(spin_is_locked(&desc->lock)); + + spin_lock_irqsave(&aplic.lock, flags); + + clear_bit(_IRQ_DISABLED, &desc->status); + + /* enable interrupt in IMSIC */ + imsic_irq_enable(desc->irq); + + /* enable interrupt in APLIC */ + aplic.regs->setienum = desc->irq; + + spin_unlock_irqrestore(&aplic.lock, flags); +} + +static void aplic_irq_disable(struct irq_desc *desc) +{ + unsigned long flags; + + /* + * TODO: Currently, APLIC is supported only with MSI interrupts. + * If APLIC without MSI interrupts is required in the future, + * this function will need to be updated accordingly. + */ + ASSERT(aplic.imsic_cfg->is_used); + + ASSERT(spin_is_locked(&desc->lock)); + + spin_lock_irqsave(&aplic.lock, flags); + + set_bit(_IRQ_DISABLED, &desc->status); + + /* disable interrupt in APLIC */ + aplic.regs->clrienum = desc->irq; + + /* disable interrupt in IMSIC */ + imsic_irq_disable(desc->irq); + + spin_unlock_irqrestore(&aplic.lock, flags); +} + +static unsigned int aplic_irq_startup(struct irq_desc *desc) +{ + aplic_irq_enable(desc); + + return 0; +} + +static void aplic_irq_shutdown(struct irq_desc *desc) +{ + aplic_irq_disable(desc); +} + +static void aplic_irq_ack(struct irq_desc *desc) +{ + /* nothing to do */ +} + +static void aplic_host_irq_end(struct irq_desc *desc) +{ + /* nothing to do */ +} + +static unsigned int aplic_get_cpu_from_mask(const cpumask_t *cpumask) +{ + unsigned int cpu; + cpumask_t possible_mask; + + cpumask_and(&possible_mask, cpumask, &cpu_possible_map); + cpu = cpumask_any(&possible_mask); + + return cpu; +} + +static void aplic_set_irq_affinity(struct irq_desc *desc, const cpumask_t *mask) +{ + unsigned int cpu; + uint64_t group_index, base_ppn; + uint32_t hhxw, lhxw ,hhxs, value; + const struct imsic_config *imsic = aplic.imsic_cfg; + + /* + * TODO: Currently, APLIC is supported only with MSI interrupts. + * If APLIC without MSI interrupts is required in the future, + * this function will need to be updated accordingly. + */ + ASSERT(aplic.imsic_cfg->is_used); + + ASSERT(!cpumask_empty(mask)); + + spin_lock(&aplic.lock); + + cpu = cpuid_to_hartid(aplic_get_cpu_from_mask(mask)); + hhxw = imsic->group_index_bits; + lhxw = imsic->hart_index_bits; + hhxs = imsic->group_index_shift - IMSIC_MMIO_PAGE_SHIFT * 2; + base_ppn = imsic->msi[cpu].base_addr >> IMSIC_MMIO_PAGE_SHIFT; + + /* update hart and EEID in the target register */ + group_index = (base_ppn >> (hhxs + 12)) & (BIT(hhxw, UL) - 1); + value = desc->irq; + value |= cpu << APLIC_TARGET_HART_IDX_SHIFT; + value |= group_index << (lhxw + APLIC_TARGET_HART_IDX_SHIFT) ; + aplic.regs->target[desc->irq - 1] = value; + + spin_unlock(&aplic.lock); +} + +static hw_irq_controller aplic_host_irq_type = { + .typename = "aplic", + .startup = aplic_irq_startup, + .shutdown = aplic_irq_shutdown, + .enable = aplic_irq_enable, + .disable = aplic_irq_disable, + .ack = aplic_irq_ack, + .end = aplic_host_irq_end, + .set_affinity = aplic_set_irq_affinity, +}; + +static const struct intc_hw_operations aplic_ops = { .info = &aplic_info, .init = aplic_init, + .host_irq_type = &aplic_host_irq_type, + .set_irq_priority = aplic_set_irq_priority, + .set_irq_type = aplic_set_irq_type, }; static int aplic_irq_xlate(const uint32_t *intspec, unsigned int intsize, @@ -149,6 +314,8 @@ static int __init aplic_preinit(struct dt_device_node *node, const void *dat) dt_irq_xlate = aplic_irq_xlate; + spin_lock_init(&aplic.lock); + register_intc_ops(&aplic_ops); return 0; diff --git a/xen/arch/riscv/imsic.c b/xen/arch/riscv/imsic.c index 99def9af2d..8198d008ef 100644 --- a/xen/arch/riscv/imsic.c +++ b/xen/arch/riscv/imsic.c @@ -14,12 +14,68 @@ #include #include #include +#include #include #include static struct imsic_config imsic_cfg; +#define imsic_csr_set(c, v) \ +do { \ + csr_write(CSR_SISELECT, c); \ + csr_set(CSR_SIREG, v); \ +} while (0) + +#define imsic_csr_clear(c, v) \ +do { \ + csr_write(CSR_SISELECT, c); \ + csr_clear(CSR_SIREG, v); \ +} while (0) + +static void imsic_local_eix_update(unsigned long base_id, unsigned long num_id, + bool pend, bool val) +{ + unsigned long i, isel, ireg; + unsigned long id = base_id, last_id = base_id + num_id; + + while ( id < last_id ) + { + isel = id / __riscv_xlen; + isel *= __riscv_xlen / IMSIC_EIPx_BITS; + isel += (pend) ? IMSIC_EIP0 : IMSIC_EIE0; + + ireg = 0; + for ( i = id & (__riscv_xlen - 1); + (id < last_id) && (i < __riscv_xlen); + i++, id++ ) + ireg |= (1 << i); + + if ( val ) + imsic_csr_set(isel, ireg); + else + imsic_csr_clear(isel, ireg); + } +} + +void imsic_irq_enable(unsigned int hwirq) +{ + unsigned long flags; + + spin_lock_irqsave(&imsic_cfg.lock, flags); + imsic_local_eix_update(hwirq, 1, false, true); + spin_unlock_irqrestore(&imsic_cfg.lock, flags); +} + +void imsic_irq_disable(unsigned int hwirq) +{ + unsigned long flags; + + spin_lock_irqsave(&imsic_cfg.lock, flags); + imsic_local_eix_update(hwirq, 1, false, false); + spin_unlock_irqrestore(&imsic_cfg.lock, flags); +} + const struct imsic_config *imsic_get_config(void) { return &imsic_cfg; @@ -277,6 +333,13 @@ int __init imsic_init(struct dt_device_node *node) goto imsic_init_err; } + spin_lock_init(&imsic_cfg.lock); + + /* Enable local interrupt delivery */ + imsic_ids_local_delivery(true); + + imsic_cfg.is_used = true; + return 0; imsic_init_err: diff --git a/xen/arch/riscv/include/asm/aplic.h b/xen/arch/riscv/include/asm/aplic.h index 94b3d0b616..ce858663a9 100644 --- a/xen/arch/riscv/include/asm/aplic.h +++ b/xen/arch/riscv/include/asm/aplic.h @@ -18,6 +18,15 @@ #define APLIC_DOMAINCFG_IE BIT(8, UL) #define APLIC_DOMAINCFG_DM BIT(2, UL) +#define APLIC_SOURCECFG_SM_INACTIVE 0x0 +#define APLIC_SOURCECFG_SM_DETACH 0x1 +#define APLIC_SOURCECFG_SM_EDGE_RISE 0x4 +#define APLIC_SOURCECFG_SM_EDGE_FALL 0x5 +#define APLIC_SOURCECFG_SM_LEVEL_HIGH 0x6 +#define APLIC_SOURCECFG_SM_LEVEL_LOW 0x7 + +#define APLIC_TARGET_HART_IDX_SHIFT 18 + struct aplic_regs { uint32_t domaincfg; uint32_t sourcecfg[1023]; @@ -70,6 +79,9 @@ struct aplic_priv { /* registers */ volatile struct aplic_regs *regs; + /* lock */ + spinlock_t lock; + /* imsic configuration */ const struct imsic_config *imsic_cfg; }; diff --git a/xen/arch/riscv/include/asm/imsic.h b/xen/arch/riscv/include/asm/imsic.h index 126e651863..d2c0178529 100644 --- a/xen/arch/riscv/include/asm/imsic.h +++ b/xen/arch/riscv/include/asm/imsic.h @@ -11,6 +11,7 @@ #ifndef ASM__RISCV__IMSIC_H #define ASM__RISCV__IMSIC_H +#include #include #define IMSIC_MMIO_PAGE_SHIFT 12 @@ -19,6 +20,11 @@ #define IMSIC_MIN_ID 63 #define IMSIC_MAX_ID 2048 +#define IMSIC_EIP0 0x80 +#define IMSIC_EIPx_BITS 32 + +#define IMSIC_EIE0 0xC0 + struct imsic_msi { paddr_t base_addr; unsigned long offset; @@ -55,6 +61,12 @@ struct imsic_config { /* MSI */ struct imsic_msi msi[NR_CPUS]; + + /* a check that IMSIC is used */ + bool is_used; + + /* lock */ + spinlock_t lock; }; struct dt_device_node; @@ -63,4 +75,7 @@ int imsic_init(struct dt_device_node *n); struct imsic_config; const struct imsic_config *imsic_get_config(void); +void imsic_irq_enable(unsigned int hwirq); +void imsic_irq_disable(unsigned int hwirq); + #endif /* ASM__RISCV__IMSIC_H */ From patchwork Tue Apr 8 15:57:16 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Oleksii Kurochko X-Patchwork-Id: 14043312 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.xenproject.org (lists.xenproject.org [192.237.175.120]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 1D9B0C369A2 for ; Tue, 8 Apr 2025 16:02:58 +0000 (UTC) Received: from list by lists.xenproject.org with outflank-mailman.942664.1341777 (Exim 4.92) (envelope-from ) id 1u2BPX-0006pK-0R; Tue, 08 Apr 2025 16:02:51 +0000 X-Outflank-Mailman: Message body and most headers restored to incoming version Received: by outflank-mailman (output) from mailman id 942664.1341777; Tue, 08 Apr 2025 16:02:50 +0000 Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1u2BPW-0006oo-S8; Tue, 08 Apr 2025 16:02:50 +0000 Received: by outflank-mailman (input) for mailman id 942664; Tue, 08 Apr 2025 16:02:49 +0000 Received: from se1-gles-flk1-in.inumbo.com ([94.247.172.50] helo=se1-gles-flk1.inumbo.com) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1u2BKc-0004Yq-KZ for xen-devel@lists.xenproject.org; Tue, 08 Apr 2025 15:57:46 +0000 Received: from mail-ed1-x536.google.com (mail-ed1-x536.google.com [2a00:1450:4864:20::536]) by se1-gles-flk1.inumbo.com (Halon) with ESMTPS id 3168b3ad-1492-11f0-9ffb-bf95429c2676; Tue, 08 Apr 2025 17:57:37 +0200 (CEST) Received: by mail-ed1-x536.google.com with SMTP id 4fb4d7f45d1cf-5e61da95244so9512658a12.2 for ; Tue, 08 Apr 2025 08:57:37 -0700 (PDT) Received: from fedora.. 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[109.243.64.225]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-ac7c018556bsm929934566b.156.2025.04.08.08.57.35 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 08 Apr 2025 08:57:36 -0700 (PDT) X-BeenThere: xen-devel@lists.xenproject.org List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Errors-To: xen-devel-bounces@lists.xenproject.org Precedence: list Sender: "Xen-devel" X-Inumbo-ID: 3168b3ad-1492-11f0-9ffb-bf95429c2676 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20230601; t=1744127857; x=1744732657; darn=lists.xenproject.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=sc7wfWEtEETos3Xy4ASDsRUDXv0bfhmJEvEO/7TawQo=; b=D61MvuwlhhT/iHjVl6KJsI8boKoCmvfGA8ZBmL52WQt30wmheVc8wPZtdIbPUW2Aa0 TAc4ZBm13fVg/R1b48S8DyT95OJTxlaSDzUeBJrM/IaJcjxYRiLziYkuPyieotta6Wd6 g5HdJS0LRcmGXvQFa0IR97w4yOn+dJ74FcKRH+g+9tapkCugDrXLwE0lfudbHMXCj4ec diTvT84ZzH4xlPVP1L7o2NCp+T5M2yvk/9aniLpVAjskrcfpoVMhUhXBlk1/r4+kV9NL 2Ust8vMSuCCHPziUnhoxHx8TlzreByuz6sqLwPvWXMne7VsThNRcpH3yLerLLnLMIrZ7 HOVA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1744127857; x=1744732657; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=sc7wfWEtEETos3Xy4ASDsRUDXv0bfhmJEvEO/7TawQo=; b=H6vr8TuqfbwdJkT4KP75hvJYQ7gc8XfgdeKXkRVRmqeAVm49iS//IUwIU+qsBQjjva IeO8qzFjJXolpDY5U29LwDXLhNXmGh6K9wgmJWsWvc3pE7Ok+3GyIu6OAosCWt5mCKAo hERpLXyvl5ECNdKBGhE/gXCHa7aJM60F8EEdO0kkX0WvmJvR//au1W4nasct5RLuXKj/ dDZsQQMTdE+4aq9WSggkfSGT2QFdROPCtxKnhSDugC+ldbMhEFOzRsExvxmZmIQN/InE vR4WvK/e8Q2K7xonMTSwIKTq4mpPRVEjA0yaXx5d/NO4EBaIWd43M3jP4TKJTuIPUqTO 4QmA== X-Gm-Message-State: AOJu0Yw2MOmEhOqhkBgPi/yHx6gKvAE6hF3Bm4YR27GAQmzZnQThQsTz 9ce8ICRQSrbZgJ28dcZSwwe53mtCd23tMceYe1Qq+Wnpjhqpf84IqfGopA== X-Gm-Gg: ASbGnctq48V1gmSzFSqFg7k5rnH8U18aA3NryJkijw98rObfjuekTWFlgL+9SeZRPuY j6dMV4UyqLTttwukM7Qf2GjQ1nGWQcRJyxA8JgjKXkyrb3f3WOimotccVQNvEDGTUryOBfwSB1V XR3O6F1USGLQ3rST8Tbsbx3zWEUdczI4PFEIjKdkraTCsF9YwjsL7PLqy0sj77WATLT3Y9bV1KZ iiA8JYZ/deQUekXEWp48jXaiWThkoN3jPlxBL7obBzDyCNsoF8Q/5+Z/5zG6lb7fcf/ZDyWe6/n rRrZx9uqXALgybDsa6brvGY728QuYBBGDU5G/l+0qOLyWmGutPR1xlCFNiLcmj/4YGUqkvgPJQ+ o/IfzPOnuGDNWkg== X-Google-Smtp-Source: AGHT+IFL3WNhj77fFPxV0cWMP8yo+oe1QoIkzk3e18tqqolBdgOLMj6ctPGIvdYduEJRVIBY++KgZA== X-Received: by 2002:a17:907:97d6:b0:ac7:391b:e68a with SMTP id a640c23a62f3a-ac7d1c14826mr1306772666b.60.1744127856612; Tue, 08 Apr 2025 08:57:36 -0700 (PDT) From: Oleksii Kurochko To: xen-devel@lists.xenproject.org Cc: Oleksii Kurochko , Alistair Francis , Bob Eshleman , Connor Davis , Andrew Cooper , Anthony PERARD , Michal Orzel , Jan Beulich , Julien Grall , =?utf-8?q?Roger_Pau_Monn=C3=A9?= , Stefano Stabellini , Romain Caritey Subject: [PATCH v1 11/14] xen/riscv: add external interrupt handling for hypervisor mode Date: Tue, 8 Apr 2025 17:57:16 +0200 Message-ID: <1685488b8c1b48149e94bd3625c7b46b78c72e8e.1744126720.git.oleksii.kurochko@gmail.com> X-Mailer: git-send-email 2.49.0 In-Reply-To: References: MIME-Version: 1.0 Implement functions necessarry to have working external interrupts in hypervisor mode. The following changes are done: - Add a common function intc_handle_external_irq() to call APLIC specific function to handle an interrupt. - Update do_trap() function to handle IRQ_S_EXT case; add the check to catch case when cause of trap is an interrupt. - Add handle_interrrupt() member to intc_hw_operations structure. - Enable local interrupt delivery for IMSIC by implementation and calling of imsic_ids_local_delivery() in imsic_init(); additionally introduce helper imsic_csr_write() to update IMSIC_EITHRESHOLD and IMSIC_EITHRESHOLD. - Enable hypervisor external interrupts. - Implement aplic_handler_interrupt() and use it to init ->handle_interrupt member of intc_hw_operations for APLIC. - Add implementation of do_IRQ() to dispatch the interrupt. The current patch is based on the code from [1]. [1] https://gitlab.com/xen-project/people/olkur/xen/-/commit/7390e2365828b83e27ead56b03114a56e3699dd5 Co-developed-by: Romain Caritey Signed-off-by: Oleksii Kurochko --- xen/arch/riscv/aplic.c | 19 +++++++++++++ xen/arch/riscv/imsic.c | 25 +++++++++++++++++ xen/arch/riscv/include/asm/imsic.h | 7 +++++ xen/arch/riscv/include/asm/intc.h | 5 ++++ xen/arch/riscv/include/asm/irq.h | 3 +++ xen/arch/riscv/intc.c | 7 +++++ xen/arch/riscv/irq.c | 43 ++++++++++++++++++++++++++++++ xen/arch/riscv/traps.c | 18 +++++++++++++ 8 files changed, 127 insertions(+) diff --git a/xen/arch/riscv/aplic.c b/xen/arch/riscv/aplic.c index 4b60cb9a77..38b57ed1ac 100644 --- a/xen/arch/riscv/aplic.c +++ b/xen/arch/riscv/aplic.c @@ -261,6 +261,21 @@ static void aplic_set_irq_affinity(struct irq_desc *desc, const cpumask_t *mask) spin_unlock(&aplic.lock); } +static void aplic_handle_interrupt(unsigned long cause, struct cpu_user_regs *regs) +{ + /* disable to avoid more external interrupts */ + csr_clear(CSR_SIE, 1UL << IRQ_S_EXT); + + /* clear the pending bit */ + csr_clear(CSR_SIP, 1UL << IRQ_S_EXT); + + /* dispatch the interrupt */ + do_IRQ(regs, csr_swap(CSR_STOPEI, 0) >> TOPI_IID_SHIFT); + + /* enable external interrupts */ + csr_set(CSR_SIE, 1UL << IRQ_S_EXT); +} + static hw_irq_controller aplic_host_irq_type = { .typename = "aplic", .startup = aplic_irq_startup, @@ -278,6 +293,7 @@ static const struct intc_hw_operations aplic_ops = { .host_irq_type = &aplic_host_irq_type, .set_irq_priority = aplic_set_irq_priority, .set_irq_type = aplic_set_irq_type, + .handle_interrupt = aplic_handle_interrupt, }; static int aplic_irq_xlate(const uint32_t *intspec, unsigned int intsize, @@ -318,6 +334,9 @@ static int __init aplic_preinit(struct dt_device_node *node, const void *dat) register_intc_ops(&aplic_ops); + /* Enable supervisor external interrupt */ + csr_set(CSR_SIE, 1UL << IRQ_S_EXT); + return 0; } diff --git a/xen/arch/riscv/imsic.c b/xen/arch/riscv/imsic.c index 8198d008ef..e00f2d69df 100644 --- a/xen/arch/riscv/imsic.c +++ b/xen/arch/riscv/imsic.c @@ -19,8 +19,19 @@ #include +#define IMSIC_DISABLE_EIDELIVERY 0 +#define IMSIC_ENABLE_EIDELIVERY 1 +#define IMSIC_DISABLE_EITHRESHOLD 1 +#define IMSIC_ENABLE_EITHRESHOLD 0 + static struct imsic_config imsic_cfg; +#define imsic_csr_write(c, v) \ +do { \ + csr_write(CSR_SISELECT, c); \ + csr_write(CSR_SIREG, v); \ +} while (0) + #define imsic_csr_set(c, v) \ do { \ csr_write(CSR_SISELECT, c); \ @@ -33,6 +44,20 @@ do { \ csr_clear(CSR_SIREG, v); \ } while (0) +void imsic_ids_local_delivery(bool enable) +{ + if ( enable ) + { + imsic_csr_write(IMSIC_EITHRESHOLD, IMSIC_ENABLE_EITHRESHOLD); + imsic_csr_write(IMSIC_EIDELIVERY, IMSIC_ENABLE_EIDELIVERY); + } + else + { + imsic_csr_write(IMSIC_EITHRESHOLD, IMSIC_DISABLE_EITHRESHOLD); + imsic_csr_write(IMSIC_EIDELIVERY, IMSIC_DISABLE_EIDELIVERY); + } +} + static void imsic_local_eix_update(unsigned long base_id, unsigned long num_id, bool pend, bool val) { diff --git a/xen/arch/riscv/include/asm/imsic.h b/xen/arch/riscv/include/asm/imsic.h index d2c0178529..b2c674f271 100644 --- a/xen/arch/riscv/include/asm/imsic.h +++ b/xen/arch/riscv/include/asm/imsic.h @@ -12,6 +12,7 @@ #define ASM__RISCV__IMSIC_H #include +#include #include #define IMSIC_MMIO_PAGE_SHIFT 12 @@ -20,6 +21,10 @@ #define IMSIC_MIN_ID 63 #define IMSIC_MAX_ID 2048 +#define IMSIC_EIDELIVERY 0x70 + +#define IMSIC_EITHRESHOLD 0x72 + #define IMSIC_EIP0 0x80 #define IMSIC_EIPx_BITS 32 @@ -78,4 +83,6 @@ const struct imsic_config *imsic_get_config(void); void imsic_irq_enable(unsigned int hwirq); void imsic_irq_disable(unsigned int hwirq); +void imsic_ids_local_delivery(bool enable); + #endif /* ASM__RISCV__IMSIC_H */ diff --git a/xen/arch/riscv/include/asm/intc.h b/xen/arch/riscv/include/asm/intc.h index db53caa07b..e4363af87d 100644 --- a/xen/arch/riscv/include/asm/intc.h +++ b/xen/arch/riscv/include/asm/intc.h @@ -34,6 +34,8 @@ struct intc_hw_operations { /* Set IRQ priority */ void (*set_irq_priority)(struct irq_desc *desc, unsigned int priority); + /* handle external interrupt */ + void (*handle_interrupt)(unsigned long cause, struct cpu_user_regs *regs); }; void intc_preinit(void); @@ -45,4 +47,7 @@ void register_intc_ops(const struct intc_hw_operations *ops); struct irq_desc; void intc_route_irq_to_xen(struct irq_desc *desc, unsigned int priority); +struct cpu_user_regs; +void intc_handle_external_irqs(unsigned long cause, struct cpu_user_regs *regs); + #endif /* ASM__RISCV__INTERRUPT_CONTOLLER_H */ diff --git a/xen/arch/riscv/include/asm/irq.h b/xen/arch/riscv/include/asm/irq.h index 163a478d78..9558d3fa61 100644 --- a/xen/arch/riscv/include/asm/irq.h +++ b/xen/arch/riscv/include/asm/irq.h @@ -51,6 +51,9 @@ int platform_get_irq(const struct dt_device_node *device, int index); void init_IRQ(void); +struct cpu_user_regs; +void do_IRQ(struct cpu_user_regs *regs, unsigned int irq); + #endif /* ASM__RISCV__IRQ_H */ /* diff --git a/xen/arch/riscv/intc.c b/xen/arch/riscv/intc.c index 8274897d8c..41a4310ead 100644 --- a/xen/arch/riscv/intc.c +++ b/xen/arch/riscv/intc.c @@ -51,6 +51,13 @@ static void intc_set_irq_priority(struct irq_desc *desc, unsigned int priority) intc_hw_ops->set_irq_priority(desc, priority); } +void intc_handle_external_irqs(unsigned long cause, struct cpu_user_regs *regs) +{ + ASSERT(intc_hw_ops && intc_hw_ops->handle_interrupt); + + intc_hw_ops->handle_interrupt(cause, regs); +} + void intc_route_irq_to_xen(struct irq_desc *desc, unsigned int priority) { ASSERT(test_bit(_IRQ_DISABLED, &desc->status)); diff --git a/xen/arch/riscv/irq.c b/xen/arch/riscv/irq.c index c332e000c4..3c0b95220a 100644 --- a/xen/arch/riscv/irq.c +++ b/xen/arch/riscv/irq.c @@ -11,6 +11,10 @@ #include #include #include +#include + +#include +#include static irq_desc_t irq_desc[NR_IRQS]; @@ -83,3 +87,42 @@ void __init init_IRQ(void) if ( init_irq_data() < 0 ) panic("initialization of IRQ data failed\n"); } + +/* Dispatch an interrupt */ +void do_IRQ(struct cpu_user_regs *regs, unsigned int irq) +{ + struct irq_desc *desc = irq_to_desc(irq); + struct irqaction *action; + + irq_enter(); + + spin_lock(&desc->lock); + desc->handler->ack(desc); + + if ( test_bit(_IRQ_DISABLED, &desc->status) ) + goto out; + + set_bit(_IRQ_INPROGRESS, &desc->status); + + action = desc->action; + + spin_unlock_irq(&desc->lock); + +#ifndef CONFIG_IRQ_HAS_MULTIPLE_ACTION + action->handler(irq, action->dev_id); +#else + do { + action->handler(irq, action->dev_id); + action = action->next; + } while ( action ); +#endif /* CONFIG_IRQ_HAS_MULTIPLE_ACTION */ + + spin_lock_irq(&desc->lock); + + clear_bit(_IRQ_INPROGRESS, &desc->status); + +out: + desc->handler->end(desc); + spin_unlock(&desc->lock); + irq_exit(); +} diff --git a/xen/arch/riscv/traps.c b/xen/arch/riscv/traps.c index ea3638a54f..da5813e34a 100644 --- a/xen/arch/riscv/traps.c +++ b/xen/arch/riscv/traps.c @@ -11,6 +11,7 @@ #include #include +#include #include #include #include @@ -128,6 +129,23 @@ void do_trap(struct cpu_user_regs *cpu_regs) } fallthrough; default: + if ( cause & CAUSE_IRQ_FLAG ) + { + /* Handle interrupt */ + unsigned long icause = cause & ~CAUSE_IRQ_FLAG; + + switch ( icause ) + { + case IRQ_S_EXT: + intc_handle_external_irqs(cause, cpu_regs); + break; + default: + break; + } + + break; + } + do_unexpected_trap(cpu_regs); break; } From patchwork Tue Apr 8 15:57:17 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Oleksii Kurochko X-Patchwork-Id: 14043313 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.xenproject.org (lists.xenproject.org [192.237.175.120]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 4871FC369A5 for ; Tue, 8 Apr 2025 16:03:00 +0000 (UTC) Received: from list by lists.xenproject.org with outflank-mailman.942660.1341771 (Exim 4.92) (envelope-from ) id 1u2BPW-0006mi-Or; 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Defined `IRQ_NO_PRIORITY` as default priority used when routing IRQs to Xen. [1] https://gitlab.com/xen-project/people/olkur/xen/-/commit/7390e2365828b83e27ead56b03114a56e3699dd5 Co-developed-by: Romain Caritey Signed-off-by: Oleksii Kurochko --- xen/arch/riscv/include/asm/irq.h | 6 ++ xen/arch/riscv/irq.c | 95 ++++++++++++++++++++++++++++++++ 2 files changed, 101 insertions(+) diff --git a/xen/arch/riscv/include/asm/irq.h b/xen/arch/riscv/include/asm/irq.h index 9558d3fa61..bba3a97e3e 100644 --- a/xen/arch/riscv/include/asm/irq.h +++ b/xen/arch/riscv/include/asm/irq.h @@ -26,6 +26,8 @@ #define IRQ_TYPE_SENSE_MASK DT_IRQ_TYPE_SENSE_MASK #define IRQ_TYPE_INVALID DT_IRQ_TYPE_INVALID +#define IRQ_NO_PRIORITY 0 + /* TODO */ #define nr_static_irqs 0 #define arch_hwdom_irqs(domid) 0U @@ -54,6 +56,10 @@ void init_IRQ(void); struct cpu_user_regs; void do_IRQ(struct cpu_user_regs *regs, unsigned int irq); +struct irq_desc; +struct cpumask_t; +void irq_set_affinity(struct irq_desc *desc, const cpumask_t *cpu_mask); + #endif /* ASM__RISCV__IRQ_H */ /* diff --git a/xen/arch/riscv/irq.c b/xen/arch/riscv/irq.c index 3c0b95220a..1e937d4306 100644 --- a/xen/arch/riscv/irq.c +++ b/xen/arch/riscv/irq.c @@ -6,7 +6,9 @@ * Copyright (c) 2024 Vates */ +#include #include +#include #include #include #include @@ -57,6 +59,99 @@ int platform_get_irq(const struct dt_device_node *device, int index) return dt_irq.irq; } +static int __setup_irq(struct irq_desc *desc, unsigned int irqflags, + struct irqaction *new) +{ + bool shared = irqflags & IRQF_SHARED; + + ASSERT(new != NULL); + + /* Sanity checks: + * - if the IRQ is marked as shared + * - dev_id is not NULL when IRQF_SHARED is set + */ + if ( desc->action != NULL && (!test_bit(_IRQF_SHARED, &desc->status) + || !shared) ) + return -EINVAL; + if ( shared && new->dev_id == NULL ) + return -EINVAL; + + if ( shared ) + set_bit(_IRQF_SHARED, &desc->status); + +#ifdef CONFIG_IRQ_HAS_MULTIPLE_ACTION + new->next = desc->action; + smp_mb(); +#endif + + desc->action = new; + smp_mb(); + + return 0; +} + +void irq_set_affinity(struct irq_desc *desc, const cpumask_t *cpu_mask) +{ + if ( desc != NULL ) + desc->handler->set_affinity(desc, cpu_mask); +} + +int setup_irq(unsigned int irq, unsigned int irqflags, struct irqaction *new) +{ + int rc; + unsigned long flags; + struct irq_desc *desc; + bool disabled; + + desc = irq_to_desc(irq); + + spin_lock_irqsave(&desc->lock, flags); + + disabled = (desc->action == NULL); + + if ( test_bit(_IRQ_GUEST, &desc->status) ) + { + spin_unlock_irqrestore(&desc->lock, flags); + /* + * TODO: would be nice to have functionality to print which domain owns + * an IRQ. + */ + printk(XENLOG_ERR "ERROR: IRQ %u is already in use by a domain\n", irq); + return -EBUSY; + } + + rc = __setup_irq(desc, irqflags, new); + if ( rc ) + goto err; + + /* First time the IRQ is setup */ + if ( disabled ) + { + /* disable irq by default */ + set_bit(_IRQ_DISABLED, &desc->status); + + /* route interrupt to xen */ + intc_route_irq_to_xen(desc, IRQ_NO_PRIORITY); + + /* + * we don't care for now which CPU will receive the + * interrupt + * + * TODO: Handle case where IRQ is setup on different CPU than + * the targeted CPU and the priority. + */ + irq_set_affinity(desc, cpumask_of(smp_processor_id())); + desc->handler->startup(desc); + /* enable irq */ + clear_bit(_IRQ_DISABLED, &desc->status); + } + +err: + spin_unlock_irqrestore(&desc->lock, flags); + + return rc; +} + int arch_init_one_irq_desc(struct irq_desc *desc) { desc->arch.type = IRQ_TYPE_INVALID; From patchwork Tue Apr 8 15:57:18 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Oleksii Kurochko X-Patchwork-Id: 14043261 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.xenproject.org (lists.xenproject.org [192.237.175.120]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id E894EC369A2 for ; Tue, 8 Apr 2025 15:57:56 +0000 (UTC) Received: from list by lists.xenproject.org with outflank-mailman.942518.1341742 (Exim 4.92) (envelope-from ) id 1u2BKX-0007mX-LM; Tue, 08 Apr 2025 15:57:41 +0000 X-Outflank-Mailman: Message body and most headers restored to incoming version Received: by outflank-mailman (output) from mailman id 942518.1341742; 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Signed-off-by: Oleksii Kurochko Acked-by: Jan Beulich --- xen/arch/riscv/setup.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/xen/arch/riscv/setup.c b/xen/arch/riscv/setup.c index a3189697da..9765bcbb08 100644 --- a/xen/arch/riscv/setup.c +++ b/xen/arch/riscv/setup.c @@ -136,6 +136,8 @@ void __init noreturn start_xen(unsigned long bootcpu_id, intc_preinit(); + intc_init(); + printk("All set up\n"); machine_halt(); From patchwork Tue Apr 8 15:57:19 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Oleksii Kurochko X-Patchwork-Id: 14043311 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.xenproject.org (lists.xenproject.org [192.237.175.120]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 275E5C369A4 for ; Tue, 8 Apr 2025 16:02:12 +0000 (UTC) Received: from list by lists.xenproject.org with outflank-mailman.942636.1341762 (Exim 4.92) (envelope-from ) id 1u2BOn-0005pi-GG; Tue, 08 Apr 2025 16:02:05 +0000 X-Outflank-Mailman: Message body and most headers restored to incoming version Received: by outflank-mailman (output) from mailman id 942636.1341762; Tue, 08 Apr 2025 16:02:05 +0000 Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1u2BOn-0005pb-D5; Tue, 08 Apr 2025 16:02:05 +0000 Received: by outflank-mailman (input) for mailman id 942636; Tue, 08 Apr 2025 16:02:04 +0000 Received: from se1-gles-flk1-in.inumbo.com ([94.247.172.50] helo=se1-gles-flk1.inumbo.com) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1u2BKi-0004Yq-Lx for xen-devel@lists.xenproject.org; Tue, 08 Apr 2025 15:57:52 +0000 Received: from mail-ed1-x530.google.com (mail-ed1-x530.google.com [2a00:1450:4864:20::530]) by se1-gles-flk1.inumbo.com (Halon) with ESMTPS id 33750f18-1492-11f0-9ffb-bf95429c2676; Tue, 08 Apr 2025 17:57:41 +0200 (CEST) Received: by mail-ed1-x530.google.com with SMTP id 4fb4d7f45d1cf-5e5cd420781so10291663a12.2 for ; Tue, 08 Apr 2025 08:57:41 -0700 (PDT) Received: from fedora.. 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[109.243.64.225]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-ac7c018556bsm929934566b.156.2025.04.08.08.57.39 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 08 Apr 2025 08:57:39 -0700 (PDT) X-BeenThere: xen-devel@lists.xenproject.org List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Errors-To: xen-devel-bounces@lists.xenproject.org Precedence: list Sender: "Xen-devel" X-Inumbo-ID: 33750f18-1492-11f0-9ffb-bf95429c2676 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20230601; t=1744127860; x=1744732660; darn=lists.xenproject.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=LZAsqksh1fodEX+Vcn8RPi+5F0QUQHpwEMKTK4l1sxc=; b=Tls7KmjwAQ7huME5XNnPO1lMLGvFr0ICWe2M7P8DDhFpeVdZLvyTV/9MFTnzAetvnq nrjdSPCm+MpoZOn6yROgfy7jptHcNWAIRqgYI/RfzmHz+fGVNqf3yQ4Ac5FeK3rQO0zX 6RDpwOAa4RLEY2cfG0/V6irUvmWKrbw6uDiWaTZe0jkQM3pA07ZKYgquMcsPX5aWpXvH 6SOaEdqpJU4KWbXCDbHhI+jZScPxrg6GQttcUFdJsKRa91O0k3jDqgq1qPMuEV75U9Jn kVb6PdPnwQ6lLEL9J5XIO2/6VxU/M0C40780yoIpuVS4RuSYRl2wghqSRZouNeWty5sZ nH7A== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1744127860; x=1744732660; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=LZAsqksh1fodEX+Vcn8RPi+5F0QUQHpwEMKTK4l1sxc=; b=ZRkcYHClcd2/nDkm8i5lkgIOfxU30iMcgBw4QuGju2I9Yz4Whi/gu+gfSzeAZLoVd5 NHVv4fxhku9cmV6ZBgy3sdvvrZXH77oKfiqa95bxDFES2GsLTchGTt8N8/r2q8QfaNdn +vJWNNJb32++zTOjUJsbo8RXIhgfrq3q1my1Rg0+daLoObzvcrP+Mx+CIoMiChNth2uh 9XPjg3yTu1+mHEntHw0lVtI499n1d3op9UAh+flvayO3fE0sb6qGfVnnyGl5d7EIS8rY si+kKaWjFeoYJ4SAdZg7eBKr8GwhsvT1/2JPe6WWV6eH4KXTBtkdonbRTwJIABb8/9mG UTLw== X-Gm-Message-State: AOJu0YwTc7d4sLyFogK9F9g4KzLLhs9QWpkE5YHHs/dOMmuY9z9PwMKw W+1Rs8DGX1YqN1FNVo4ZFz32rGIA5tuVkdnnHmrI3BlUCp7h1qx9jNQ7kw== X-Gm-Gg: ASbGncs5dgw8MdD0JiQaDbBRrR57f6SecRv85itatsV9Y8iZmg4a0tkEayoPAZQCAes 1WpV6VPJhMlpu6bvOH13AQUQ+5HYvrc1uZtL3s38gGD+k9iJW6NLkZAmCaTc6JEJp8N2SdAyFkJ MBNQKUXjCLCpCF3Qo0RQC6SQ4QTh/8g/K/8VficXCz/FrHZShaZI75QZmikWbxmU29XzLVY9C2d X4hzSV8QBPn5vUeOvr9rObAeJaH7gqmd4jkAGNQ7niCkByPPWJ0pym3auD3g74IvE8KS9ZMPM0s 7ksS25f1mtxZasUKKlSAmJw6MjEUzwDtLyIicMuJzAV3yCrFmmqO5eLEuQ30JMZc1W+fHBs7HVU IZE18SN6tFVOE4Q== X-Google-Smtp-Source: AGHT+IHb1nTpvqPPU3/cvk9fqYkrcWTiqLMA7eNx8KkR6zXwmdGxaSLHyc6G+tah5/nGnbkW6oRGfw== X-Received: by 2002:a17:907:3ea2:b0:ac6:e327:8de7 with SMTP id a640c23a62f3a-ac7e762349amr1044801466b.42.1744127860194; Tue, 08 Apr 2025 08:57:40 -0700 (PDT) From: Oleksii Kurochko To: xen-devel@lists.xenproject.org Cc: Oleksii Kurochko , Alistair Francis , Bob Eshleman , Connor Davis , Andrew Cooper , Anthony PERARD , Michal Orzel , Jan Beulich , Julien Grall , =?utf-8?q?Roger_Pau_Monn=C3=A9?= , Stefano Stabellini Subject: [PATCH v1 14/14] xen/riscv: add basic UART support Date: Tue, 8 Apr 2025 17:57:19 +0200 Message-ID: <3e96851da8751ac17cbf0cb5a649c0d86259460a.1744126720.git.oleksii.kurochko@gmail.com> X-Mailer: git-send-email 2.49.0 In-Reply-To: References: MIME-Version: 1.0 Update Kconfig to select GENERIC_UART_INIT for basic UART init ( find a dt node and call device specific device_init() ). Drop `default n if RISCV` statement for config HAS_NS16550 as now ns16550 is ready to be compiled and used by RISC-V. Initialize a minimal amount of stuff to have UART and Xen console: - Initialize uart by calling uart_init(). - Initialize Xen console by calling console_init_{pre,post}irq(). - Initialize timer and its internal lists which are used by init_timer() which is called by ns16550_init_postirq(); otherwise "Unhandled exception: Store/AMO Page Fault" occurs. - Enable local interrupt to recieve an input from UART Signed-off-by: Oleksii Kurochko --- xen/arch/riscv/Kconfig | 1 + xen/arch/riscv/setup.c | 16 ++++++++++++++++ xen/drivers/char/Kconfig | 1 - 3 files changed, 17 insertions(+), 1 deletion(-) diff --git a/xen/arch/riscv/Kconfig b/xen/arch/riscv/Kconfig index 27086cca9c..f5ba7a5a78 100644 --- a/xen/arch/riscv/Kconfig +++ b/xen/arch/riscv/Kconfig @@ -2,6 +2,7 @@ config RISCV def_bool y select FUNCTION_ALIGNMENT_16B select GENERIC_BUG_FRAME + select GENERIC_UART_INIT select HAS_DEVICE_TREE select HAS_PMAP select HAS_UBSAN diff --git a/xen/arch/riscv/setup.c b/xen/arch/riscv/setup.c index 9765bcbb08..b5fd660a4b 100644 --- a/xen/arch/riscv/setup.c +++ b/xen/arch/riscv/setup.c @@ -4,11 +4,16 @@ #include #include #include +#include #include #include #include +#include #include +#include +#include #include +#include #include #include @@ -73,6 +78,8 @@ void __init noreturn start_xen(unsigned long bootcpu_id, remove_identity_mapping(); + percpu_init_areas(); + smp_clear_cpu_maps(); set_processor_id(0); @@ -136,8 +143,17 @@ void __init noreturn start_xen(unsigned long bootcpu_id, intc_preinit(); + uart_init(); + console_init_preirq(); + intc_init(); + timer_init(); + + local_irq_enable(); + + console_init_postirq(); + printk("All set up\n"); machine_halt(); diff --git a/xen/drivers/char/Kconfig b/xen/drivers/char/Kconfig index e6e12bb413..01fa31fb2b 100644 --- a/xen/drivers/char/Kconfig +++ b/xen/drivers/char/Kconfig @@ -3,7 +3,6 @@ config GENERIC_UART_INIT config HAS_NS16550 bool "NS16550 UART driver" if ARM - default n if RISCV default y help This selects the 16550-series UART support. For most systems, say Y.