From patchwork Wed Apr 9 03:41:51 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Hans Zhang <18255117159@163.com> X-Patchwork-Id: 14044065 X-Patchwork-Delegate: kw@linux.com Received: from m16.mail.163.com (m16.mail.163.com [220.197.31.4]) by smtp.subspace.kernel.org (Postfix) with ESMTP id 19FA01D6195; Wed, 9 Apr 2025 03:42:36 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=220.197.31.4 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1744170159; cv=none; b=B81vVPOoQZjQ2uzMQsgCJeNQH+5wOpbac6SEnphhIaCAXaLRcVQhpYDpKAkRB13ACfuzL3gllkYzQQ09MkJF/hM7Lt6cjaIZEqboMOti1SMF/M7xIKp/zbxUXf9KlscgbCzlZlWpNrwcdVcA0aPaarHTm9mII8l+NZT9dc2o0EE= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1744170159; c=relaxed/simple; bh=0pFq+tUzBJXpqVJru5uQ+iT2LEHKruLJ6ze/L//1PA0=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=Btl2Rr5tQkN2uXmo2ZTuYuRn1WZf1saJ/ff+ncrp5ilJlGSlP5SOP2yY5rG7QEVtGeZe8Mvh4LEUdmWlPC0g0UtS0Sa6NcpdIfHq/hEa17sDUw6zS8v5kW1+zwxElB+RQEW0gmhz6T/YTwxWHcP06XcQAjLATwHfpHNijZuyKjs= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=163.com; spf=pass smtp.mailfrom=163.com; dkim=pass (1024-bit key) header.d=163.com header.i=@163.com header.b=ZgVdxCBR; arc=none smtp.client-ip=220.197.31.4 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=163.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=163.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=163.com header.i=@163.com header.b="ZgVdxCBR" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=163.com; s=s110527; h=From:Subject:Date:Message-Id:MIME-Version; bh=t9goI IdCZPlAHILa8GBZNLDBq8hqVNXvTZZGrRvFQPY=; b=ZgVdxCBRLPj5PutZRpBsL tJGU09bNEivS+ja0LsP+xP6ciRIFE7TfgjsAKLgKxaGiqtfh/Bo46YR29FvltkOz sriDzP+LD+XhNaSiTSq/VeJyhaXSFj6CwNd8O+VWAQT6V/Nu0BHTe5bkma9swt5N AWjzzxH091T+oDmG4rngf8= Received: from localhost.localdomain (unknown []) by gzga-smtp-mtada-g1-2 (Coremail) with SMTP id _____wDHD3GH7PVnbwQBFQ--.4446S3; Wed, 09 Apr 2025 11:42:03 +0800 (CST) From: Hans Zhang <18255117159@163.com> To: lpieralisi@kernel.org, bhelgaas@google.com Cc: kw@linux.com, manivannan.sadhasivam@linaro.org, ilpo.jarvinen@linux.intel.com, robh@kernel.org, jingoohan1@gmail.com, thomas.richard@bootlin.com, linux-pci@vger.kernel.org, linux-kernel@vger.kernel.org, Hans Zhang <18255117159@163.com> Subject: [PATCH v9 1/6] PCI: Introduce generic bus config read helper function Date: Wed, 9 Apr 2025 11:41:51 +0800 Message-Id: <20250409034156.92686-2-18255117159@163.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20250409034156.92686-1-18255117159@163.com> References: <20250409034156.92686-1-18255117159@163.com> Precedence: bulk X-Mailing-List: linux-pci@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-CM-TRANSID: _____wDHD3GH7PVnbwQBFQ--.4446S3 X-Coremail-Antispam: 1Uf129KBjvJXoW7uF18WF13CFW8ZFyfAF4rAFb_yoW8trW3pF W5AF1fAr48JFy5Aan5Zay8GFy5GF97tFWUGrWxC3sxZF1akayUAasaga43Xry2gr4DZr1x Z395KFyUG3WkAFJanT9S1TB71UUUUU7qnTZGkaVYY2UrUUUUjbIjqfuFe4nvWSU5nxnvy2 9KBjDUYxBIdaVFxhVjvjDU0xZFpf9x0zico7AUUUUU= X-CM-SenderInfo: rpryjkyvrrlimvzbiqqrwthudrp/xtbBDxcqo2f164krrgAAsk The primary PCI config space accessors are tied to the size of the read (byte/word/dword). Upcoming refactoring of PCI capability discovery logic requires passing a config accessor function that must be able to perform read with different sizes. Add any size config space read accessor pci_bus_read_config() to allow giving it as the config space accessor to the upcoming PCI capability discovery macro. Reconstructs the PCI function discovery logic to prepare for unified configuration of access modes. No function changes are intended. Signed-off-by: Hans Zhang <18255117159@163.com> --- Changes since v8: - The new split is patch 1/6. - The patch commit message were modified. --- drivers/pci/access.c | 17 +++++++++++++++++ drivers/pci/pci.h | 2 ++ 2 files changed, 19 insertions(+) diff --git a/drivers/pci/access.c b/drivers/pci/access.c index b123da16b63b..603332658ab3 100644 --- a/drivers/pci/access.c +++ b/drivers/pci/access.c @@ -85,6 +85,23 @@ EXPORT_SYMBOL(pci_bus_write_config_byte); EXPORT_SYMBOL(pci_bus_write_config_word); EXPORT_SYMBOL(pci_bus_write_config_dword); +int pci_bus_read_config(void *priv, unsigned int devfn, int where, u32 size, + u32 *val) +{ + struct pci_bus *bus = priv; + int ret; + + if (size == 1) + ret = pci_bus_read_config_byte(bus, devfn, where, (u8 *)val); + else if (size == 2) + ret = pci_bus_read_config_word(bus, devfn, where, (u16 *)val); + else + ret = pci_bus_read_config_dword(bus, devfn, where, val); + + return ret; +} +EXPORT_SYMBOL_GPL(pci_bus_read_config); + int pci_generic_config_read(struct pci_bus *bus, unsigned int devfn, int where, int size, u32 *val) { diff --git a/drivers/pci/pci.h b/drivers/pci/pci.h index b81e99cd4b62..5e1477d6e254 100644 --- a/drivers/pci/pci.h +++ b/drivers/pci/pci.h @@ -88,6 +88,8 @@ extern bool pci_early_dump; bool pcie_cap_has_lnkctl(const struct pci_dev *dev); bool pcie_cap_has_lnkctl2(const struct pci_dev *dev); bool pcie_cap_has_rtctl(const struct pci_dev *dev); +int pci_bus_read_config(void *priv, unsigned int devfn, int where, u32 size, + u32 *val); /* Functions internal to the PCI core code */ From patchwork Wed Apr 9 03:41:52 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Hans Zhang <18255117159@163.com> X-Patchwork-Id: 14044066 X-Patchwork-Delegate: kw@linux.com Received: from m16.mail.163.com (m16.mail.163.com [220.197.31.2]) by smtp.subspace.kernel.org (Postfix) with ESMTP id 30CAE1D798E; Wed, 9 Apr 2025 03:42:38 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=220.197.31.2 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1744170162; cv=none; b=dZZ/WuESrGY2EZns6nBzBTJBnxvbxI3pE3jaq/uiFTTXExp73LPIFSctfsZvp7Cs10TVUDSM87OiUu0lq3Cg6Hgf6P/RUH4DVJLhU23L3PF+QFDfeeeOGGunoZ3doGMiE0N58FWdMb8sqJtDmQYiivWACmGsOie0MVvH2qSYU6s= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1744170162; c=relaxed/simple; bh=8ex4AnGdOCDq4MQLZBhn23NJIS0pgkqRzZMgwrYoQq8=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=A+Ip6vfN8ScXtrMkT7nz2R+pH8RjUAj8DB6iOnm8hqEXnR9xpRHvMibj5Fk+H4lr0T/T+gYJFV/4WsSRPKJZ1nIZFGjn9xapJPAo6lpSub2/2PA8KiaSqf8R+bhugS+t9T9xmLsY7bTBMALzML3FM2wg835sTuXHRxdNvgpUin4= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=163.com; spf=pass smtp.mailfrom=163.com; dkim=pass (1024-bit key) header.d=163.com header.i=@163.com header.b=gcCa/vTv; arc=none smtp.client-ip=220.197.31.2 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=163.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=163.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=163.com header.i=@163.com header.b="gcCa/vTv" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=163.com; s=s110527; h=From:Subject:Date:Message-Id:MIME-Version; bh=CjjqZ qmAXqlpzEVuJvtvF/1/mb5ZZE8GD9uNewK1LIw=; b=gcCa/vTvHFz5kMmU7z4tI 9wZD2YMoKcKHl7FL6fIXJ3+bQWU5G/Fz3cozkwSgtBwM3En8D5RwyIJB25gmsdxx hFuaQWIYPNeaaPTirDkHuwNZ4nYxehkP4nB/M6/3djNawkVYPdEZXS7GSxSC4msz eXOh3Sz+KqUb5hpIkK13oI= Received: from localhost.localdomain (unknown []) by gzga-smtp-mtada-g1-2 (Coremail) with SMTP id _____wDHD3GH7PVnbwQBFQ--.4446S4; Wed, 09 Apr 2025 11:42:04 +0800 (CST) From: Hans Zhang <18255117159@163.com> To: lpieralisi@kernel.org, bhelgaas@google.com Cc: kw@linux.com, manivannan.sadhasivam@linaro.org, ilpo.jarvinen@linux.intel.com, robh@kernel.org, jingoohan1@gmail.com, thomas.richard@bootlin.com, linux-pci@vger.kernel.org, linux-kernel@vger.kernel.org, Hans Zhang <18255117159@163.com> Subject: [PATCH v9 2/6] PCI: Clean up __pci_find_next_cap_ttl() readability Date: Wed, 9 Apr 2025 11:41:52 +0800 Message-Id: <20250409034156.92686-3-18255117159@163.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20250409034156.92686-1-18255117159@163.com> References: <20250409034156.92686-1-18255117159@163.com> Precedence: bulk X-Mailing-List: linux-pci@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-CM-TRANSID: _____wDHD3GH7PVnbwQBFQ--.4446S4 X-Coremail-Antispam: 1Uf129KBjvJXoW7tFyUuF4Uur4kJr47AF13Jwb_yoW8tF13pF 98CFy7ArWrJF1UCws29w12yr13Xa4DCay8G3ySg3s8ZFy2yF1vqws29F1aqF17XrZ293W5 X3sIv395WFy5ZaUanT9S1TB71UUUUU7qnTZGkaVYY2UrUUUUjbIjqfuFe4nvWSU5nxnvy2 9KBjDUYxBIdaVFxhVjvjDU0xZFpf9x0pEq2NLUUUUU= X-CM-SenderInfo: rpryjkyvrrlimvzbiqqrwthudrp/1tbiWwsqo2f17CwQFQAAsO Refactor the __pci_find_next_cap_ttl() to improve code clarity: - Replace magic number 0x40 with PCI_STD_HEADER_SIZEOF. - Use ALIGN_DOWN() for position alignment instead of manual bitmask. - Extract PCI capability fields via FIELD_GET() with standardized masks. - Add necessary headers (linux/align.h, uapi/linux/pci_regs.h). The changes are purely non-functional cleanups, ensuring behavior remains identical to the original implementation. Signed-off-by: Hans Zhang <18255117159@163.com> --- Changes since v8: - Split into patch 1/6, patch 2/6. - The patch commit message were modified. --- drivers/pci/pci.c | 10 ++++++---- include/uapi/linux/pci_regs.h | 2 ++ 2 files changed, 8 insertions(+), 4 deletions(-) diff --git a/drivers/pci/pci.c b/drivers/pci/pci.c index 4d7c9f64ea24..1c29e8f20cb5 100644 --- a/drivers/pci/pci.c +++ b/drivers/pci/pci.c @@ -9,6 +9,7 @@ */ #include +#include #include #include #include @@ -30,6 +31,7 @@ #include #include #include +#include #include "pci.h" DEFINE_MUTEX(pci_slot_mutex); @@ -432,17 +434,17 @@ static u8 __pci_find_next_cap_ttl(struct pci_bus *bus, unsigned int devfn, pci_bus_read_config_byte(bus, devfn, pos, &pos); while ((*ttl)--) { - if (pos < 0x40) + if (pos < PCI_STD_HEADER_SIZEOF) break; - pos &= ~3; + pos = ALIGN_DOWN(pos, 4); pci_bus_read_config_word(bus, devfn, pos, &ent); - id = ent & 0xff; + id = FIELD_GET(PCI_CAP_ID_MASK, ent); if (id == 0xff) break; if (id == cap) return pos; - pos = (ent >> 8); + pos = FIELD_GET(PCI_CAP_LIST_NEXT_MASK, ent); } return 0; } diff --git a/include/uapi/linux/pci_regs.h b/include/uapi/linux/pci_regs.h index ba326710f9c8..b59179e1210a 100644 --- a/include/uapi/linux/pci_regs.h +++ b/include/uapi/linux/pci_regs.h @@ -206,6 +206,8 @@ /* 0x48-0x7f reserved */ /* Capability lists */ +#define PCI_CAP_ID_MASK 0x00ff +#define PCI_CAP_LIST_NEXT_MASK 0xff00 #define PCI_CAP_LIST_ID 0 /* Capability ID */ #define PCI_CAP_ID_PM 0x01 /* Power Management */ From patchwork Wed Apr 9 03:41:53 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Hans Zhang <18255117159@163.com> X-Patchwork-Id: 14044064 X-Patchwork-Delegate: kw@linux.com Received: from m16.mail.163.com (m16.mail.163.com [220.197.31.3]) by smtp.subspace.kernel.org (Postfix) with ESMTP id AB4E46F073; Wed, 9 Apr 2025 03:42:35 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=220.197.31.3 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1744170158; cv=none; b=X5edHA9rOkBXKBsJuj4Q14UHR2Af7ANhacznrBDveS8YXvvQnw3G25DSJD3Bq9FMEXoRztWb5pYWqs+2z5N0hVcx+JTLkNuNuaNZZ5AYNUeVktfU7Dtc0aRPKpX/JiCtykLRJkOLLgNONXW4TcmkRe2zeg61rWG1pswSA1bOj9E= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1744170158; c=relaxed/simple; bh=J+zKyTEgzphO9cWlCrz0p1AmMmqLKXgdUh17locy9vo=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=U5c/Vmi3v9tKE4Iit9q0QC/u2vsXmajc/L5cOyxuRCpD40JuZ52cxhjFSmL6EtQBMDyEe3cKWGBzvRRp49OWng3fP/xCBKAqmltdXsWs04RmjiCRMMrgmNE+RqjlGrQ5eTWZ/LZLTYonY2iAOvkNe4bzjiWVLYGybUW6M9xGqMA= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=163.com; spf=pass smtp.mailfrom=163.com; dkim=pass (1024-bit key) header.d=163.com header.i=@163.com header.b=p3bBd/Xz; arc=none smtp.client-ip=220.197.31.3 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=163.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=163.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=163.com header.i=@163.com header.b="p3bBd/Xz" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=163.com; s=s110527; h=From:Subject:Date:Message-Id:MIME-Version; bh=/g9u9 Optycs66mGNSFEzU9onJ0wOO/jzKXWaRawInJU=; b=p3bBd/Xz48JLYGQpgVa1s puMabqhiIO7zgs+NyUyUOdMhUDuNf3PNUCp9vaZw0xdPrQvLCevVqo7otEo5GoZ6 JfA5IEqvId43uk/y+RDY1m1gxLTe8pTWTrBJ0bBquF4svaBjIBwmhYIHbXNqkfkg d85xmJB9EroW77HRFC1MNQ= Received: from localhost.localdomain (unknown []) by gzga-smtp-mtada-g1-2 (Coremail) with SMTP id _____wDHD3GH7PVnbwQBFQ--.4446S5; Wed, 09 Apr 2025 11:42:05 +0800 (CST) From: Hans Zhang <18255117159@163.com> To: lpieralisi@kernel.org, bhelgaas@google.com Cc: kw@linux.com, manivannan.sadhasivam@linaro.org, ilpo.jarvinen@linux.intel.com, robh@kernel.org, jingoohan1@gmail.com, thomas.richard@bootlin.com, linux-pci@vger.kernel.org, linux-kernel@vger.kernel.org, Hans Zhang <18255117159@163.com> Subject: [PATCH v9 3/6] PCI: Refactor capability search into common macros Date: Wed, 9 Apr 2025 11:41:53 +0800 Message-Id: <20250409034156.92686-4-18255117159@163.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20250409034156.92686-1-18255117159@163.com> References: <20250409034156.92686-1-18255117159@163.com> Precedence: bulk X-Mailing-List: linux-pci@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-CM-TRANSID: _____wDHD3GH7PVnbwQBFQ--.4446S5 X-Coremail-Antispam: 1Uf129KBjvJXoW3XrW7ZF1fZF1ftFyxZFWkWFg_yoW3ur13pr y3A3WSyrW8J3W2qwsIva18tF1aga97Jay7urWxG3s8XFyqka4ktrySkF1aqFy7KrZ7uF13 Xws0qFWrC3ZIyF7anT9S1TB71UUUUU7qnTZGkaVYY2UrUUUUjbIjqfuFe4nvWSU5nxnvy2 9KBjDUYxBIdaVFxhVjvjDU0xZFpf9x0zRKL9UUUUUU= X-CM-SenderInfo: rpryjkyvrrlimvzbiqqrwthudrp/1tbiOhwqo2f16yc8IgAAsv The PCI Capability search functionality is duplicated across the PCI core and several controller drivers. The core's current implementation requires fully initialized PCI device and bus structures, which prevents controller drivers from using it during early initialization phases before these structures are available. Move the Capability search logic into a header-based macro that accepts a config space accessor function as an argument. This enables controller drivers to perform Capability discovery using their early access mechanisms prior to full device initialization while sharing the Capability search code. Convert the existing PCI core Capability search implementation to use this new macro. The macros now implement, parameterized by the config access method. The PCI core functions are converted to utilize these macros with the standard pci_bus_read_config accessors. Controller drivers can later use the same macros with their early access mechanisms while maintaining the existing protection against infinite loops through preserved TTL checks. The ttl parameter was originally an additional safeguard to prevent infinite loops in corrupted config space. However, the PCI_FIND_NEXT_CAP_TTL macro already enforces a TTL limit internally. Removing redundant ttl handling simplifies the interface while maintaining the safety guarantee. This aligns with the macro's design intent of encapsulating TTL management. Signed-off-by: Hans Zhang <18255117159@163.com> --- Changes since v8: - The patch commit message were modified. --- drivers/pci/pci.c | 70 +++++--------------------------------- drivers/pci/pci.h | 86 +++++++++++++++++++++++++++++++++++++++++++++++ 2 files changed, 95 insertions(+), 61 deletions(-) diff --git a/drivers/pci/pci.c b/drivers/pci/pci.c index 1c29e8f20cb5..8a1f47e8f5cc 100644 --- a/drivers/pci/pci.c +++ b/drivers/pci/pci.c @@ -9,7 +9,6 @@ */ #include -#include #include #include #include @@ -31,7 +30,6 @@ #include #include #include -#include #include "pci.h" DEFINE_MUTEX(pci_slot_mutex); @@ -426,35 +424,16 @@ static int pci_dev_str_match(struct pci_dev *dev, const char *p, } static u8 __pci_find_next_cap_ttl(struct pci_bus *bus, unsigned int devfn, - u8 pos, int cap, int *ttl) + u8 pos, int cap) { - u8 id; - u16 ent; - - pci_bus_read_config_byte(bus, devfn, pos, &pos); - - while ((*ttl)--) { - if (pos < PCI_STD_HEADER_SIZEOF) - break; - pos = ALIGN_DOWN(pos, 4); - pci_bus_read_config_word(bus, devfn, pos, &ent); - - id = FIELD_GET(PCI_CAP_ID_MASK, ent); - if (id == 0xff) - break; - if (id == cap) - return pos; - pos = FIELD_GET(PCI_CAP_LIST_NEXT_MASK, ent); - } - return 0; + return PCI_FIND_NEXT_CAP_TTL(pci_bus_read_config, pos, cap, bus, + devfn); } static u8 __pci_find_next_cap(struct pci_bus *bus, unsigned int devfn, u8 pos, int cap) { - int ttl = PCI_FIND_CAP_TTL; - - return __pci_find_next_cap_ttl(bus, devfn, pos, cap, &ttl); + return __pci_find_next_cap_ttl(bus, devfn, pos, cap); } u8 pci_find_next_capability(struct pci_dev *dev, u8 pos, int cap) @@ -555,42 +534,11 @@ EXPORT_SYMBOL(pci_bus_find_capability); */ u16 pci_find_next_ext_capability(struct pci_dev *dev, u16 start, int cap) { - u32 header; - int ttl; - u16 pos = PCI_CFG_SPACE_SIZE; - - /* minimum 8 bytes per capability */ - ttl = (PCI_CFG_SPACE_EXP_SIZE - PCI_CFG_SPACE_SIZE) / 8; - if (dev->cfg_size <= PCI_CFG_SPACE_SIZE) return 0; - if (start) - pos = start; - - if (pci_read_config_dword(dev, pos, &header) != PCIBIOS_SUCCESSFUL) - return 0; - - /* - * If we have no capabilities, this is indicated by cap ID, - * cap version and next pointer all being 0. - */ - if (header == 0) - return 0; - - while (ttl-- > 0) { - if (PCI_EXT_CAP_ID(header) == cap && pos != start) - return pos; - - pos = PCI_EXT_CAP_NEXT(header); - if (pos < PCI_CFG_SPACE_SIZE) - break; - - if (pci_read_config_dword(dev, pos, &header) != PCIBIOS_SUCCESSFUL) - break; - } - - return 0; + return PCI_FIND_NEXT_EXT_CAPABILITY(pci_bus_read_config, start, cap, + dev->bus, dev->devfn); } EXPORT_SYMBOL_GPL(pci_find_next_ext_capability); @@ -650,7 +598,7 @@ EXPORT_SYMBOL_GPL(pci_get_dsn); static u8 __pci_find_next_ht_cap(struct pci_dev *dev, u8 pos, int ht_cap) { - int rc, ttl = PCI_FIND_CAP_TTL; + int rc; u8 cap, mask; if (ht_cap == HT_CAPTYPE_SLAVE || ht_cap == HT_CAPTYPE_HOST) @@ -659,7 +607,7 @@ static u8 __pci_find_next_ht_cap(struct pci_dev *dev, u8 pos, int ht_cap) mask = HT_5BIT_CAP_MASK; pos = __pci_find_next_cap_ttl(dev->bus, dev->devfn, pos, - PCI_CAP_ID_HT, &ttl); + PCI_CAP_ID_HT); while (pos) { rc = pci_read_config_byte(dev, pos + 3, &cap); if (rc != PCIBIOS_SUCCESSFUL) @@ -670,7 +618,7 @@ static u8 __pci_find_next_ht_cap(struct pci_dev *dev, u8 pos, int ht_cap) pos = __pci_find_next_cap_ttl(dev->bus, dev->devfn, pos + PCI_CAP_LIST_NEXT, - PCI_CAP_ID_HT, &ttl); + PCI_CAP_ID_HT); } return 0; diff --git a/drivers/pci/pci.h b/drivers/pci/pci.h index 5e1477d6e254..79cd6402ba8d 100644 --- a/drivers/pci/pci.h +++ b/drivers/pci/pci.h @@ -2,7 +2,9 @@ #ifndef DRIVERS_PCI_H #define DRIVERS_PCI_H +#include #include +#include struct pcie_tlp_log; @@ -91,6 +93,90 @@ bool pcie_cap_has_rtctl(const struct pci_dev *dev); int pci_bus_read_config(void *priv, unsigned int devfn, int where, u32 size, u32 *val); +/* Standard Capability finder */ +/** + * PCI_FIND_NEXT_CAP_TTL - Find a PCI standard capability + * @read_cfg: Function pointer for reading PCI config space + * @start: Starting position to begin search + * @cap: Capability ID to find + * @args: Arguments to pass to read_cfg function + * + * Iterates through the capability list in PCI config space to find + * the specified capability. Implements TTL (time-to-live) protection + * against infinite loops. + * + * Returns: Position of the capability if found, 0 otherwise. + */ +#define PCI_FIND_NEXT_CAP_TTL(read_cfg, start, cap, args...) \ +({ \ + int __ttl = PCI_FIND_CAP_TTL; \ + u8 __id, __found_pos = 0; \ + u8 __pos = (start); \ + u16 __ent; \ + \ + read_cfg(args, __pos, 1, (u32 *)&__pos); \ + \ + while (__ttl--) { \ + if (__pos < PCI_STD_HEADER_SIZEOF) \ + break; \ + \ + __pos = ALIGN_DOWN(__pos, 4); \ + read_cfg(args, __pos, 2, (u32 *)&__ent); \ + \ + __id = FIELD_GET(PCI_CAP_ID_MASK, __ent); \ + if (__id == 0xff) \ + break; \ + \ + if (__id == (cap)) { \ + __found_pos = __pos; \ + break; \ + } \ + \ + __pos = FIELD_GET(PCI_CAP_LIST_NEXT_MASK, __ent); \ + } \ + __found_pos; \ +}) + +/* Extended Capability finder */ +/** + * PCI_FIND_NEXT_EXT_CAPABILITY - Find a PCI extended capability + * @read_cfg: Function pointer for reading PCI config space + * @start: Starting position to begin search (0 for initial search) + * @cap: Extended capability ID to find + * @args: Arguments to pass to read_cfg function + * + * Searches the extended capability space in PCI config registers + * for the specified capability. Implements TTL protection against + * infinite loops using a calculated maximum search count. + * + * Returns: Position of the capability if found, 0 otherwise. + */ +#define PCI_FIND_NEXT_EXT_CAPABILITY(read_cfg, start, cap, args...) \ +({ \ + u16 __pos = (start) ?: PCI_CFG_SPACE_SIZE; \ + u16 __found_pos = 0; \ + int __ttl, __ret; \ + u32 __header; \ + \ + __ttl = (PCI_CFG_SPACE_EXP_SIZE - PCI_CFG_SPACE_SIZE) / 8; \ + while (__ttl-- > 0 && __pos >= PCI_CFG_SPACE_SIZE) { \ + __ret = read_cfg(args, __pos, 4, &__header); \ + if (__ret != PCIBIOS_SUCCESSFUL) \ + break; \ + \ + if (__header == 0) \ + break; \ + \ + if (PCI_EXT_CAP_ID(__header) == (cap) && __pos != start) { \ + __found_pos = __pos; \ + break; \ + } \ + \ + __pos = PCI_EXT_CAP_NEXT(__header); \ + } \ + __found_pos; \ +}) + /* Functions internal to the PCI core code */ #ifdef CONFIG_DMI From patchwork Wed Apr 9 03:41:54 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Hans Zhang <18255117159@163.com> X-Patchwork-Id: 14044070 X-Patchwork-Delegate: kw@linux.com Received: from m16.mail.163.com (m16.mail.163.com [220.197.31.3]) by smtp.subspace.kernel.org (Postfix) with ESMTP id 5EA47258A; Wed, 9 Apr 2025 03:57:55 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=220.197.31.3 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1744171079; cv=none; b=PIyrbdRLv9DyGSJcvSLu/ZYdpoOze4Q/iSdRb22tfd1hxPXxODP+YqElklQeLOKe2lh19jRiH5GNC8BS5g6XxrwY2ekjSKotWl/Fq93k5x5ceD3Ok4aTz7rlJrxY92l5Ye2DZAsboXkPyTHWUvdw+CZdAz/I/SL5H+SxYjCnnpc= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1744171079; c=relaxed/simple; bh=C8VoMDP/9DwEUbnuWChyJAzFBxjjKZGOkfQ/fb1wU68=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=spb4V/XG3csNqsqUAmHThMwyOCu437iH2us+H2kNDnQuO3eZHIFyxBs9tl1XJf7AV1jkY8SB2BixADb1oxKs7u8CbPq6N/VEsHJs4qS1K5BGeYHp0dxhdWCiagCVGDiZv4/qxqgFlO/A8e9qZhE7xIo8OdQyrra121cjnQM7QG0= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=163.com; spf=pass smtp.mailfrom=163.com; dkim=pass (1024-bit key) header.d=163.com header.i=@163.com header.b=czI78n2P; arc=none smtp.client-ip=220.197.31.3 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=163.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=163.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=163.com header.i=@163.com header.b="czI78n2P" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=163.com; s=s110527; h=From:Subject:Date:Message-Id:MIME-Version; bh=KKEef WvqrG4PzRUfHiysIFUryV3aK/Eeg4jpW8eL55c=; b=czI78n2P/yvESCIDnKo8I FCgXJj2+3LlfT9p1VD/pT+z4i6MeXMTR8OyRV5ra286hV1YuOZtJmaTzKaQpRUJk somfp2KLxKAGMGX9LK+8NiexIfh80jVVoFpiNsOir2aHetfBRTXHEAfaXXnroPuG hXcYTSIihe+Rx39jgTKSFc= Received: from localhost.localdomain (unknown []) by gzga-smtp-mtada-g1-2 (Coremail) with SMTP id _____wDHD3GH7PVnbwQBFQ--.4446S6; Wed, 09 Apr 2025 11:42:06 +0800 (CST) From: Hans Zhang <18255117159@163.com> To: lpieralisi@kernel.org, bhelgaas@google.com Cc: kw@linux.com, manivannan.sadhasivam@linaro.org, ilpo.jarvinen@linux.intel.com, robh@kernel.org, jingoohan1@gmail.com, thomas.richard@bootlin.com, linux-pci@vger.kernel.org, linux-kernel@vger.kernel.org, Hans Zhang <18255117159@163.com> Subject: [PATCH v9 4/6] PCI: dwc: Use common PCI host bridge APIs for finding the capabilities Date: Wed, 9 Apr 2025 11:41:54 +0800 Message-Id: <20250409034156.92686-5-18255117159@163.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20250409034156.92686-1-18255117159@163.com> References: <20250409034156.92686-1-18255117159@163.com> Precedence: bulk X-Mailing-List: linux-pci@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-CM-TRANSID: _____wDHD3GH7PVnbwQBFQ--.4446S6 X-Coremail-Antispam: 1Uf129KBjvJXoWxury5Cw17JryfCFy7ZrW8JFb_yoW5ZFWDpa yrA3ZYkr4rtr4aqa1qvFnIyFy5AF9xAFWxZa97GwnavF12krWjg340kayaqF1IyrZFgF13 Kr48JF95Cw1ktFDanT9S1TB71UUUUU7qnTZGkaVYY2UrUUUUjbIjqfuFe4nvWSU5nxnvy2 9KBjDUYxBIdaVFxhVjvjDU0xZFpf9x0zEbAwPUUUUU= X-CM-SenderInfo: rpryjkyvrrlimvzbiqqrwthudrp/1tbiOhEqo2f16yc8WQAAsZ Use the PCI core is now exposing generic macros for the host bridges to search for the PCIe capabilities, make use of them in the DWC driver. Signed-off-by: Hans Zhang <18255117159@163.com> --- Changes since v8: - None Changes since v7: - Resolve compilation errors. Changes since v6: https://lore.kernel.org/linux-pci/20250323164852.430546-3-18255117159@163.com/ - The patch commit message were modified. Changes since v5: https://lore.kernel.org/linux-pci/20250321163803.391056-3-18255117159@163.com/ - Kconfig add "select PCI_HOST_HELPERS" --- drivers/pci/controller/dwc/pcie-designware.c | 72 ++------------------ 1 file changed, 7 insertions(+), 65 deletions(-) diff --git a/drivers/pci/controller/dwc/pcie-designware.c b/drivers/pci/controller/dwc/pcie-designware.c index 97d76d3dc066..274f1add95b0 100644 --- a/drivers/pci/controller/dwc/pcie-designware.c +++ b/drivers/pci/controller/dwc/pcie-designware.c @@ -205,83 +205,25 @@ void dw_pcie_version_detect(struct dw_pcie *pci) pci->type = ver; } -/* - * These interfaces resemble the pci_find_*capability() interfaces, but these - * are for configuring host controllers, which are bridges *to* PCI devices but - * are not PCI devices themselves. - */ -static u8 __dw_pcie_find_next_cap(struct dw_pcie *pci, u8 cap_ptr, - u8 cap) +static int dw_pcie_read_cfg(void *priv, int where, int size, u32 *val) { - u8 cap_id, next_cap_ptr; - u16 reg; - - if (!cap_ptr) - return 0; - - reg = dw_pcie_readw_dbi(pci, cap_ptr); - cap_id = (reg & 0x00ff); - - if (cap_id > PCI_CAP_ID_MAX) - return 0; + struct dw_pcie *pci = priv; - if (cap_id == cap) - return cap_ptr; + *val = dw_pcie_read_dbi(pci, where, size); - next_cap_ptr = (reg & 0xff00) >> 8; - return __dw_pcie_find_next_cap(pci, next_cap_ptr, cap); + return PCIBIOS_SUCCESSFUL; } u8 dw_pcie_find_capability(struct dw_pcie *pci, u8 cap) { - u8 next_cap_ptr; - u16 reg; - - reg = dw_pcie_readw_dbi(pci, PCI_CAPABILITY_LIST); - next_cap_ptr = (reg & 0x00ff); - - return __dw_pcie_find_next_cap(pci, next_cap_ptr, cap); + return PCI_FIND_NEXT_CAP_TTL(dw_pcie_read_cfg, PCI_CAPABILITY_LIST, cap, + pci); } EXPORT_SYMBOL_GPL(dw_pcie_find_capability); -static u16 dw_pcie_find_next_ext_capability(struct dw_pcie *pci, u16 start, - u8 cap) -{ - u32 header; - int ttl; - int pos = PCI_CFG_SPACE_SIZE; - - /* minimum 8 bytes per capability */ - ttl = (PCI_CFG_SPACE_EXP_SIZE - PCI_CFG_SPACE_SIZE) / 8; - - if (start) - pos = start; - - header = dw_pcie_readl_dbi(pci, pos); - /* - * If we have no capabilities, this is indicated by cap ID, - * cap version and next pointer all being 0. - */ - if (header == 0) - return 0; - - while (ttl-- > 0) { - if (PCI_EXT_CAP_ID(header) == cap && pos != start) - return pos; - - pos = PCI_EXT_CAP_NEXT(header); - if (pos < PCI_CFG_SPACE_SIZE) - break; - - header = dw_pcie_readl_dbi(pci, pos); - } - - return 0; -} - u16 dw_pcie_find_ext_capability(struct dw_pcie *pci, u8 cap) { - return dw_pcie_find_next_ext_capability(pci, 0, cap); + return PCI_FIND_NEXT_EXT_CAPABILITY(dw_pcie_read_cfg, 0, cap, pci); } EXPORT_SYMBOL_GPL(dw_pcie_find_ext_capability); From patchwork Wed Apr 9 03:41:55 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Hans Zhang <18255117159@163.com> X-Patchwork-Id: 14044063 X-Patchwork-Delegate: kw@linux.com Received: from m16.mail.163.com (m16.mail.163.com [220.197.31.4]) by smtp.subspace.kernel.org (Postfix) with ESMTP id DBB231D5AC6; Wed, 9 Apr 2025 03:42:33 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; 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dmarc=pass (p=none dis=none) header.from=163.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=163.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=163.com header.i=@163.com header.b="gcQoEcoc" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=163.com; s=s110527; h=From:Subject:Date:Message-Id:MIME-Version; bh=a1YB5 hqkhY77Dtj90kOr3AvWfHzC/YM1IVy4IYh4oCA=; b=gcQoEcocuMbyn/wfWmaZh Zm1AWS9GKJpOvbaAoJphjP1wHPsV26JeI//Cg9gt32vJquEo+CsR7JvB1UO4OV7y VEAPIg6nGzHgGbhMd6KKZcu94i7Ta4B5DOoGBMWMTsqL46ytg/JhA7j4G63pHnxW DK1rRHv7pqdbRqUy33VYJc= Received: from localhost.localdomain (unknown []) by gzga-smtp-mtada-g1-2 (Coremail) with SMTP id _____wDHD3GH7PVnbwQBFQ--.4446S7; Wed, 09 Apr 2025 11:42:08 +0800 (CST) From: Hans Zhang <18255117159@163.com> To: lpieralisi@kernel.org, bhelgaas@google.com Cc: kw@linux.com, manivannan.sadhasivam@linaro.org, ilpo.jarvinen@linux.intel.com, robh@kernel.org, jingoohan1@gmail.com, thomas.richard@bootlin.com, linux-pci@vger.kernel.org, linux-kernel@vger.kernel.org, Hans Zhang <18255117159@163.com> Subject: [PATCH v9 5/6] PCI: cadence: Use common PCI host bridge APIs for finding the capabilities Date: Wed, 9 Apr 2025 11:41:55 +0800 Message-Id: <20250409034156.92686-6-18255117159@163.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20250409034156.92686-1-18255117159@163.com> References: <20250409034156.92686-1-18255117159@163.com> Precedence: bulk X-Mailing-List: linux-pci@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-CM-TRANSID: _____wDHD3GH7PVnbwQBFQ--.4446S7 X-Coremail-Antispam: 1Uf129KBjvJXoWxuryrAr48Cw4rur1kCF4UJwb_yoW5ZF1DpF WDGFyfCa1rJFW3uFs3A3W5Xr15tFnak347ta92kw12vF17Cr1UGF12gFy3Kr9xKrs7Wr13 X3yDtFykKrn0yFUanT9S1TB71UUUUU7qnTZGkaVYY2UrUUUUjbIjqfuFe4nvWSU5nxnvy2 9KBjDUYxBIdaVFxhVjvjDU0xZFpf9x0zEjXdxUUUUU= X-CM-SenderInfo: rpryjkyvrrlimvzbiqqrwthudrp/1tbiOggqo2f16yc8lAAAsN Use the PCI core is now exposing generic macros for the host bridges to search for the PCIe capabilities, make use of them in the CDNS driver. Signed-off-by: Hans Zhang <18255117159@163.com> --- Changes since v8: - None Changes since v7: - Resolve compilation errors. Changes since v6: https://lore.kernel.org/linux-pci/20250323164852.430546-4-18255117159@163.com/ - The patch commit message were modified. Changes since v5: https://lore.kernel.org/linux-pci/20250321163803.391056-4-18255117159@163.com - Kconfig add "select PCI_HOST_HELPERS" --- drivers/pci/controller/cadence/pcie-cadence.c | 28 +++++++++++++++++++ drivers/pci/controller/cadence/pcie-cadence.h | 13 +++++++++ 2 files changed, 41 insertions(+) diff --git a/drivers/pci/controller/cadence/pcie-cadence.c b/drivers/pci/controller/cadence/pcie-cadence.c index 204e045aed8c..ca4a1a809fcb 100644 --- a/drivers/pci/controller/cadence/pcie-cadence.c +++ b/drivers/pci/controller/cadence/pcie-cadence.c @@ -7,6 +7,34 @@ #include #include "pcie-cadence.h" +#include "../../pci.h" + +static int cdns_pcie_read_cfg(void *priv, int where, int size, u32 *val) +{ + struct cdns_pcie *pcie = priv; + + if (size == 4) + *val = cdns_pcie_readl(pcie, where); + else if (size == 2) + *val = cdns_pcie_readw(pcie, where); + else if (size == 1) + *val = cdns_pcie_readb(pcie, where); + + return PCIBIOS_SUCCESSFUL; +} + +u8 cdns_pcie_find_capability(struct cdns_pcie *pcie, u8 cap) +{ + return PCI_FIND_NEXT_CAP_TTL(cdns_pcie_read_cfg, PCI_CAPABILITY_LIST, + cap, pcie); +} +EXPORT_SYMBOL_GPL(cdns_pcie_find_capability); + +u16 cdns_pcie_find_ext_capability(struct cdns_pcie *pcie, u8 cap) +{ + return PCI_FIND_NEXT_EXT_CAPABILITY(cdns_pcie_read_cfg, 0, cap, pcie); +} +EXPORT_SYMBOL_GPL(cdns_pcie_find_ext_capability); void cdns_pcie_detect_quiet_min_delay_set(struct cdns_pcie *pcie) { diff --git a/drivers/pci/controller/cadence/pcie-cadence.h b/drivers/pci/controller/cadence/pcie-cadence.h index 39ee9945c903..56d6a0e73eb7 100644 --- a/drivers/pci/controller/cadence/pcie-cadence.h +++ b/drivers/pci/controller/cadence/pcie-cadence.h @@ -398,6 +398,16 @@ static inline u32 cdns_pcie_readl(struct cdns_pcie *pcie, u32 reg) return readl(pcie->reg_base + reg); } +static inline u32 cdns_pcie_readw(struct cdns_pcie *pcie, u32 reg) +{ + return readw(pcie->reg_base + reg); +} + +static inline u32 cdns_pcie_readb(struct cdns_pcie *pcie, u32 reg) +{ + return readb(pcie->reg_base + reg); +} + static inline u32 cdns_pcie_read_sz(void __iomem *addr, int size) { void __iomem *aligned_addr = PTR_ALIGN_DOWN(addr, 0x4); @@ -557,6 +567,9 @@ static inline int cdns_pcie_ep_setup(struct cdns_pcie_ep *ep) } #endif +u8 cdns_pcie_find_capability(struct cdns_pcie *pcie, u8 cap); +u16 cdns_pcie_find_ext_capability(struct cdns_pcie *pcie, u8 cap); + void cdns_pcie_detect_quiet_min_delay_set(struct cdns_pcie *pcie); void cdns_pcie_set_outbound_region(struct cdns_pcie *pcie, u8 busnr, u8 fn, From patchwork Wed Apr 9 03:41:56 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Hans Zhang <18255117159@163.com> X-Patchwork-Id: 14044067 X-Patchwork-Delegate: kw@linux.com Received: from m16.mail.163.com (m16.mail.163.com [117.135.210.5]) by smtp.subspace.kernel.org (Postfix) with ESMTP id 4DC0D1D5AD4; Wed, 9 Apr 2025 03:42:56 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=117.135.210.5 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1744170179; cv=none; b=dep6qcVvwn95+jqubQdQRUvl5RMf8EnfXEfMPCh6TllezFlnGwWCDrZ/Gf8vOC8Fc1ziHqg+qkUDVbY0Qu3BV4Kw3HmdPUANiPU5hBqgiH3d5GX/yx1FTl7qWaHs8tKUhSp454P1JASm42HAtePfGka5IjuOX3eSKxANKmlA4yk= ARC-Message-Signature: i=1; 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d=163.com; s=s110527; h=From:Subject:Date:Message-Id:MIME-Version; bh=ewKvj vbEN5jLM7Npi/B6FjQv+k+CIxx9Il6D3QnwqY4=; b=agHcGOo0ZD69SX3nuCtXt PbEy47Ec36S75G8APKiQlHkzFVsQfNxboTlIt8zfykSyeDHXGWuRtPtCSvIgnwVH 4X4cdgW5eeI+0J/OPfe/1b98K93fsQ7jwV15dpInLhEieypwuHjSA6JdQNeArdys DQd0VWx4sa7cT5AsXhjQFo= Received: from localhost.localdomain (unknown []) by gzga-smtp-mtada-g1-2 (Coremail) with SMTP id _____wDHD3GH7PVnbwQBFQ--.4446S8; Wed, 09 Apr 2025 11:42:09 +0800 (CST) From: Hans Zhang <18255117159@163.com> To: lpieralisi@kernel.org, bhelgaas@google.com Cc: kw@linux.com, manivannan.sadhasivam@linaro.org, ilpo.jarvinen@linux.intel.com, robh@kernel.org, jingoohan1@gmail.com, thomas.richard@bootlin.com, linux-pci@vger.kernel.org, linux-kernel@vger.kernel.org, Hans Zhang <18255117159@163.com> Subject: [PATCH v9 6/6] PCI: cadence: Use cdns_pcie_find_*capability to avoid hardcode. Date: Wed, 9 Apr 2025 11:41:56 +0800 Message-Id: <20250409034156.92686-7-18255117159@163.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20250409034156.92686-1-18255117159@163.com> References: <20250409034156.92686-1-18255117159@163.com> Precedence: bulk X-Mailing-List: linux-pci@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-CM-TRANSID: _____wDHD3GH7PVnbwQBFQ--.4446S8 X-Coremail-Antispam: 1Uf129KBjvJXoW3JF1xAFy3Jw43GF17ur18AFb_yoWxCr4fpF Z8ua4SkF40qrW7uFsrAa15ZrnxtFnIv347Aa92kw15uF129FyUGFyIva43KF1akrs7uF17 XrWDtrsa93W3trUanT9S1TB71UUUUU7qnTZGkaVYY2UrUUUUjbIjqfuFe4nvWSU5nxnvy2 9KBjDUYxBIdaVFxhVjvjDU0xZFpf9x0zE18B8UUUUU= X-CM-SenderInfo: rpryjkyvrrlimvzbiqqrwthudrp/1tbiWxUqo2f17CwQ3QAAsY The PCIe capability/extended capability offsets are not guaranteed to be the same across all SoCs integrating the Cadence PCIe IP. Hence, use the cdns_pcie_find_{ext}_capability() APIs for finding them. This avoids hardcoding the offsets in the driver. Signed-off-by: Hans Zhang <18255117159@163.com> --- Changes since v5~v8: - None Changes since v4: https://lore.kernel.org/linux-pci/20250321101710.371480-5-18255117159@163.com/ - The patch subject and commit message were modified. --- .../pci/controller/cadence/pcie-cadence-ep.c | 40 +++++++++++-------- drivers/pci/controller/cadence/pcie-cadence.h | 5 --- 2 files changed, 23 insertions(+), 22 deletions(-) diff --git a/drivers/pci/controller/cadence/pcie-cadence-ep.c b/drivers/pci/controller/cadence/pcie-cadence-ep.c index 599ec4b1223e..5c4b2151d181 100644 --- a/drivers/pci/controller/cadence/pcie-cadence-ep.c +++ b/drivers/pci/controller/cadence/pcie-cadence-ep.c @@ -19,12 +19,13 @@ static u8 cdns_pcie_get_fn_from_vfn(struct cdns_pcie *pcie, u8 fn, u8 vfn) { - u32 cap = CDNS_PCIE_EP_FUNC_SRIOV_CAP_OFFSET; u32 first_vf_offset, stride; + u16 cap; if (vfn == 0) return fn; + cap = cdns_pcie_find_ext_capability(pcie, PCI_EXT_CAP_ID_SRIOV); first_vf_offset = cdns_pcie_ep_fn_readw(pcie, fn, cap + PCI_SRIOV_VF_OFFSET); stride = cdns_pcie_ep_fn_readw(pcie, fn, cap + PCI_SRIOV_VF_STRIDE); fn = fn + first_vf_offset + ((vfn - 1) * stride); @@ -36,10 +37,11 @@ static int cdns_pcie_ep_write_header(struct pci_epc *epc, u8 fn, u8 vfn, struct pci_epf_header *hdr) { struct cdns_pcie_ep *ep = epc_get_drvdata(epc); - u32 cap = CDNS_PCIE_EP_FUNC_SRIOV_CAP_OFFSET; struct cdns_pcie *pcie = &ep->pcie; u32 reg; + u16 cap; + cap = cdns_pcie_find_ext_capability(pcie, PCI_EXT_CAP_ID_SRIOV); if (vfn > 1) { dev_err(&epc->dev, "Only Virtual Function #1 has deviceID\n"); return -EINVAL; @@ -224,9 +226,10 @@ static int cdns_pcie_ep_set_msi(struct pci_epc *epc, u8 fn, u8 vfn, u8 mmc) { struct cdns_pcie_ep *ep = epc_get_drvdata(epc); struct cdns_pcie *pcie = &ep->pcie; - u32 cap = CDNS_PCIE_EP_FUNC_MSI_CAP_OFFSET; u16 flags; + u8 cap; + cap = cdns_pcie_find_capability(pcie, PCI_CAP_ID_MSI); fn = cdns_pcie_get_fn_from_vfn(pcie, fn, vfn); /* @@ -246,9 +249,10 @@ static int cdns_pcie_ep_get_msi(struct pci_epc *epc, u8 fn, u8 vfn) { struct cdns_pcie_ep *ep = epc_get_drvdata(epc); struct cdns_pcie *pcie = &ep->pcie; - u32 cap = CDNS_PCIE_EP_FUNC_MSI_CAP_OFFSET; u16 flags, mme; + u8 cap; + cap = cdns_pcie_find_capability(pcie, PCI_CAP_ID_MSI); fn = cdns_pcie_get_fn_from_vfn(pcie, fn, vfn); /* Validate that the MSI feature is actually enabled. */ @@ -269,9 +273,10 @@ static int cdns_pcie_ep_get_msix(struct pci_epc *epc, u8 func_no, u8 vfunc_no) { struct cdns_pcie_ep *ep = epc_get_drvdata(epc); struct cdns_pcie *pcie = &ep->pcie; - u32 cap = CDNS_PCIE_EP_FUNC_MSIX_CAP_OFFSET; u32 val, reg; + u8 cap; + cap = cdns_pcie_find_capability(pcie, PCI_CAP_ID_MSIX); func_no = cdns_pcie_get_fn_from_vfn(pcie, func_no, vfunc_no); reg = cap + PCI_MSIX_FLAGS; @@ -290,9 +295,10 @@ static int cdns_pcie_ep_set_msix(struct pci_epc *epc, u8 fn, u8 vfn, { struct cdns_pcie_ep *ep = epc_get_drvdata(epc); struct cdns_pcie *pcie = &ep->pcie; - u32 cap = CDNS_PCIE_EP_FUNC_MSIX_CAP_OFFSET; u32 val, reg; + u8 cap; + cap = cdns_pcie_find_capability(pcie, PCI_CAP_ID_MSIX); fn = cdns_pcie_get_fn_from_vfn(pcie, fn, vfn); reg = cap + PCI_MSIX_FLAGS; @@ -378,11 +384,11 @@ static int cdns_pcie_ep_send_msi_irq(struct cdns_pcie_ep *ep, u8 fn, u8 vfn, u8 interrupt_num) { struct cdns_pcie *pcie = &ep->pcie; - u32 cap = CDNS_PCIE_EP_FUNC_MSI_CAP_OFFSET; u16 flags, mme, data, data_mask; - u8 msi_count; u64 pci_addr, pci_addr_mask = 0xff; + u8 msi_count, cap; + cap = cdns_pcie_find_capability(pcie, PCI_CAP_ID_MSI); fn = cdns_pcie_get_fn_from_vfn(pcie, fn, vfn); /* Check whether the MSI feature has been enabled by the PCI host. */ @@ -430,14 +436,14 @@ static int cdns_pcie_ep_map_msi_irq(struct pci_epc *epc, u8 fn, u8 vfn, u32 *msi_addr_offset) { struct cdns_pcie_ep *ep = epc_get_drvdata(epc); - u32 cap = CDNS_PCIE_EP_FUNC_MSI_CAP_OFFSET; struct cdns_pcie *pcie = &ep->pcie; u64 pci_addr, pci_addr_mask = 0xff; u16 flags, mme, data, data_mask; - u8 msi_count; + u8 msi_count, cap; int ret; int i; + cap = cdns_pcie_find_capability(pcie, PCI_CAP_ID_MSI); fn = cdns_pcie_get_fn_from_vfn(pcie, fn, vfn); /* Check whether the MSI feature has been enabled by the PCI host. */ @@ -480,16 +486,16 @@ static int cdns_pcie_ep_map_msi_irq(struct pci_epc *epc, u8 fn, u8 vfn, static int cdns_pcie_ep_send_msix_irq(struct cdns_pcie_ep *ep, u8 fn, u8 vfn, u16 interrupt_num) { - u32 cap = CDNS_PCIE_EP_FUNC_MSIX_CAP_OFFSET; u32 tbl_offset, msg_data, reg; struct cdns_pcie *pcie = &ep->pcie; struct pci_epf_msix_tbl *msix_tbl; struct cdns_pcie_epf *epf; u64 pci_addr_mask = 0xff; u64 msg_addr; + u8 bir, cap; u16 flags; - u8 bir; + cap = cdns_pcie_find_capability(pcie, PCI_CAP_ID_MSIX); epf = &ep->epf[fn]; if (vfn > 0) epf = &epf->epf[vfn - 1]; @@ -563,7 +569,9 @@ static int cdns_pcie_ep_start(struct pci_epc *epc) int max_epfs = sizeof(epc->function_num_map) * 8; int ret, epf, last_fn; u32 reg, value; + u8 cap; + cap = cdns_pcie_find_capability(pcie, PCI_CAP_ID_EXP); /* * BIT(0) is hardwired to 1, hence function 0 is always enabled * and can't be disabled anyway. @@ -587,12 +595,10 @@ static int cdns_pcie_ep_start(struct pci_epc *epc) continue; value = cdns_pcie_ep_fn_readl(pcie, epf, - CDNS_PCIE_EP_FUNC_DEV_CAP_OFFSET + - PCI_EXP_DEVCAP); + cap + PCI_EXP_DEVCAP); value &= ~PCI_EXP_DEVCAP_FLR; - cdns_pcie_ep_fn_writel(pcie, epf, - CDNS_PCIE_EP_FUNC_DEV_CAP_OFFSET + - PCI_EXP_DEVCAP, value); + cdns_pcie_ep_fn_writel(pcie, epf, cap + PCI_EXP_DEVCAP, + value); } } diff --git a/drivers/pci/controller/cadence/pcie-cadence.h b/drivers/pci/controller/cadence/pcie-cadence.h index 56d6a0e73eb7..08491275349d 100644 --- a/drivers/pci/controller/cadence/pcie-cadence.h +++ b/drivers/pci/controller/cadence/pcie-cadence.h @@ -125,11 +125,6 @@ */ #define CDNS_PCIE_EP_FUNC_BASE(fn) (((fn) << 12) & GENMASK(19, 12)) -#define CDNS_PCIE_EP_FUNC_MSI_CAP_OFFSET 0x90 -#define CDNS_PCIE_EP_FUNC_MSIX_CAP_OFFSET 0xb0 -#define CDNS_PCIE_EP_FUNC_DEV_CAP_OFFSET 0xc0 -#define CDNS_PCIE_EP_FUNC_SRIOV_CAP_OFFSET 0x200 - /* * Endpoint PF Registers */