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h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=/h+KmEfjEwaWP7PdqWTKb6YIL4NuLpnIAIStX4bOq1M=; b=aQ4VFtn305A4gxRBRFKiM7RCl3P4EZdxWZmnwiZzVm2oPtVF6UpE6FZOXhzu0U7oq/F/ypfbzsoLXt5CdR74IOT6eIepx3XRBvhI7xU0e+W0rB8TMRCYIstWXsczDxvULTyJJ7Zc7IDeWab5jIjpU6wtRh5xwA8Dlew+wB5FgGw= X-MS-Exchange-Authentication-Results: spf=pass (sender IP is 165.204.84.17) smtp.mailfrom=amd.com; dkim=none (message not signed) header.d=none;dmarc=pass action=none header.from=amd.com; Received-SPF: Pass (protection.outlook.com: domain of amd.com designates 165.204.84.17 as permitted sender) receiver=protection.outlook.com; client-ip=165.204.84.17; helo=SATLEXMB04.amd.com; pr=C From: Jiqian Chen To: CC: Huang Rui , Jiqian Chen , "Andrew Cooper" , Anthony PERARD , Michal Orzel , Jan Beulich , Julien Grall , =?utf-8?q?Roger_Pau_Monn=C3=A9?= , "Stefano Stabellini" Subject: [PATCH v2 1/8] driver/pci: Get next capability without passing caps Date: Wed, 9 Apr 2025 14:45:21 +0800 Message-ID: <20250409064528.405573-2-Jiqian.Chen@amd.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20250409064528.405573-1-Jiqian.Chen@amd.com> References: <20250409064528.405573-1-Jiqian.Chen@amd.com> MIME-Version: 1.0 X-Originating-IP: [10.180.168.240] X-ClientProxiedBy: SATLEXMB03.amd.com (10.181.40.144) To SATLEXMB04.amd.com (10.181.40.145) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: BN2PEPF00004FBB:EE_|SJ0PR12MB6855:EE_ X-MS-Office365-Filtering-Correlation-Id: a92275bd-1b4f-4140-4aee-08dd773234ff X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|82310400026|376014|36860700013|1800799024; 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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 09 Apr 2025 06:46:07.7225 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: a92275bd-1b4f-4140-4aee-08dd773234ff X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: BN2PEPF00004FBB.namprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: SJ0PR12MB6855 Modify function pci_find_next_cap_ttl to support returning position of next capability when array "caps" is empty or size "n" is zero. That can help caller to get next capability offset if caller just has a information of current capability offset. That will be used in a follow-on change. Signed-off-by: Jiqian Chen --- cc: Andrew Cooper cc: Anthony PERARD cc: Michal Orzel cc: Jan Beulich cc: Julien Grall cc: "Roger Pau Monné" cc: Stefano Stabellini --- v1->v2 changes: new patch Best regards, Jiqian Chen. --- xen/drivers/pci/pci.c | 6 +++++- xen/include/xen/pci.h | 2 +- 2 files changed, 6 insertions(+), 2 deletions(-) diff --git a/xen/drivers/pci/pci.c b/xen/drivers/pci/pci.c index edf5b9f7ae9f..ec81d0db6133 100644 --- a/xen/drivers/pci/pci.c +++ b/xen/drivers/pci/pci.c @@ -40,7 +40,7 @@ unsigned int pci_find_cap_offset(pci_sbdf_t sbdf, unsigned int cap) } unsigned int pci_find_next_cap_ttl(pci_sbdf_t sbdf, unsigned int pos, - const unsigned int caps[], unsigned int n, + const unsigned int *caps, unsigned int n, unsigned int *ttl) { while ( (*ttl)-- ) @@ -55,6 +55,10 @@ unsigned int pci_find_next_cap_ttl(pci_sbdf_t sbdf, unsigned int pos, if ( id == 0xff ) break; + + if ( !caps || n == 0 ) + return pos; + for ( i = 0; i < n; i++ ) { if ( id == caps[i] ) diff --git a/xen/include/xen/pci.h b/xen/include/xen/pci.h index ef601966533e..cc84f2cbebfc 100644 --- a/xen/include/xen/pci.h +++ b/xen/include/xen/pci.h @@ -251,7 +251,7 @@ int pci_mmcfg_write(unsigned int seg, unsigned int bus, unsigned int devfn, int reg, int len, u32 value); unsigned int pci_find_cap_offset(pci_sbdf_t sbdf, unsigned int cap); unsigned int pci_find_next_cap_ttl(pci_sbdf_t sbdf, unsigned int pos, - const unsigned int caps[], unsigned int n, + const unsigned int *caps, unsigned int n, unsigned int *ttl); unsigned int pci_find_next_cap(pci_sbdf_t sbdf, unsigned int pos, unsigned int cap); From patchwork Wed Apr 9 06:45:22 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: "Chen, Jiqian" X-Patchwork-Id: 14044127 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.xenproject.org (lists.xenproject.org [192.237.175.120]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id D5915C369A9 for ; Wed, 9 Apr 2025 06:46:38 +0000 (UTC) Received: from list by lists.xenproject.org with outflank-mailman.943381.1342140 (Exim 4.92) (envelope-from ) id 1u2PCU-00046O-0U; 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pr=C From: Jiqian Chen To: CC: Huang Rui , Jiqian Chen , =?utf-8?q?Roger_Pau_Monn=C3=A9?= Subject: [PATCH v2 2/8] vpci/header: Emulate legacy capability list for host Date: Wed, 9 Apr 2025 14:45:22 +0800 Message-ID: <20250409064528.405573-3-Jiqian.Chen@amd.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20250409064528.405573-1-Jiqian.Chen@amd.com> References: <20250409064528.405573-1-Jiqian.Chen@amd.com> MIME-Version: 1.0 X-Originating-IP: [10.180.168.240] X-ClientProxiedBy: SATLEXMB03.amd.com (10.181.40.144) To SATLEXMB04.amd.com (10.181.40.145) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: BN2PEPF00004FBA:EE_|SJ0PR12MB5661:EE_ X-MS-Office365-Filtering-Correlation-Id: 9c4dea4d-7ef4-420c-07aa-08dd773235ee X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|1800799024|376014|36860700013|82310400026; X-Microsoft-Antispam-Message-Info: =?utf-8?q?E1tcq9v1yXUlZj53QdBleG8nWfKlWPx?= =?utf-8?q?iuuRRZsNf8cD4RcbdKvh1LkkgkzahIZX7Kpkum10AWtCGWTue7MKYMLcDVrgpSqEl?= =?utf-8?q?/O3QHZK8EUFRKs1LGujXUGss4hYPRtiPxVHnutskz22Ho9Am7SsvBjAaLXRFijjyA?= =?utf-8?q?+ePEtZF+A8OMWNNFLqGsk0xInR2YIqriEYRxKhrjDVKImdBqZXBCcQMYWjbBm0Ebj?= =?utf-8?q?6vethEzCtfv7MfXo+MUdJd2CVDPk+d2n+et1A53+brQQhKdA1Q+7k8triWY7a+ZZg?= =?utf-8?q?Oabf+77YjCnTbT05w+b7VtTiAuJExhnnHjrhMUgkwKX5n3vzcg0wfuxx+txtF+pZ4?= =?utf-8?q?wQ2sF/t45lZpLn9ueoMy/J5hbeTeSBOEYOFbZgxWEM7BY+Z6fQVTnTkTmL8jKqp9v?= =?utf-8?q?YNpQBjk9P4nxK/8ETYPG0ZlT/FV+7aa/S1QNK20ms//7d+gtzCLj/ikF6LkqD3wOu?= =?utf-8?q?1wMARwkjp/hMi9w1s9vgZJx60cu0enXrh0hm7pQ8m/0lZ5nX+3YFS0mkTPRih1GzP?= =?utf-8?q?KzamIfwrf1sbjPmCrIOFL6uau2JFS6ZpE5bKcAkvlfhX6cdV6Ek7lhOKE/lM2BUqu?= =?utf-8?q?ZVDNb+4wzJQTYAv19qjNLzllosxpkWM3M/eNhGfKpg8ZDbiOX4BoM3K8e3xrXjOk4?= =?utf-8?q?9VhPFJrpMQqPOYKolQRvBTN2bto/vL3A2rkadkhHQKpyG+8/ulsjzn3k5ZI/gMyBo?= =?utf-8?q?WlHNeCYMfFRvHUZUtVzjj+QDQZ7FsY14I0SG6r9RB5/SPZLiY/OFLQd3oVYnRZByI?= =?utf-8?q?BV8d+JPOniwwU46ftVYBHPAj99jac/uuxLdKEqK2cZahT0RZaDDhyvlM04aXteJXg?= =?utf-8?q?4jL4uqi4R5y7ouwSBEb5LyEikzottEG3E1ddbWd2yEITj6MF5Jiz2UNqRr2IOzUUO?= =?utf-8?q?hYzPRvNXD/FU0vH6SdPvBou4dXQZo9q6zlNlfXZOYQ8XypRjU/Vjq0ECjPymAF2cl?= =?utf-8?q?k/6NVoV5/VggFbHKAIHG7NTfmofxsNbZ+xv1CI9FJP3COPj2n+GYWqaMy0KfqH8x9?= =?utf-8?q?B0ShrMf88H20ORE4CdUARW4nrgCwV415HQtOHeJn3GENXjlvlOk/HVsevMnso1sWn?= =?utf-8?q?37Uqm3iyb4vY/g1BBn/mLHE2iDIyohVmGp1ckyz8GMxXDqBu947V4r6QlHpteQeFC?= =?utf-8?q?kVLUEYdXy2OhxFHxHqz32XF9mujqa8a1wTtCW4R0QKQGakU+AsQxbxuZekSFiI2Xq?= =?utf-8?q?J0P+b68jjuehS+ypOaMVtgMRltSwpHDjQT1xkSco5pEV0Tlc8DaI9PDqnLgnD00Ym?= =?utf-8?q?kG9HvrVmrf1Nq5nihn/T7cwOvCFzOp9u1WmY5M2T79x/zzpRaspCpSTuXlojVCKGW?= =?utf-8?q?TzUNvDZr8QGWpGvhyHnT3Xk75k0Fkq49vfaS695TwWFQe7P3sa0JekR3wNoi2B3QO?= =?utf-8?q?Kbc3PdzNWAO7TD6ww+FYZ5H6uvIOuZsgjrntGd7ouD2WeE/nO3lNcPxEUyZbxxJBR?= =?utf-8?q?BO0m0LSE8v?= X-Forefront-Antispam-Report: CIP:165.204.84.17;CTRY:US;LANG:en;SCL:1;SRV:;IPV:CAL;SFV:NSPM;H:SATLEXMB04.amd.com;PTR:InfoDomainNonexistent;CAT:NONE;SFS:(13230040)(1800799024)(376014)(36860700013)(82310400026);DIR:OUT;SFP:1101; X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 09 Apr 2025 06:46:09.2871 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 9c4dea4d-7ef4-420c-07aa-08dd773235ee X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: BN2PEPF00004FBA.namprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: SJ0PR12MB5661 Current logic of init_header() only emulates legacy capability list for guest, expand it to emulate for host too. So that it will be easy to hide a capability whose initialization fails and no need to distinguish host or guest. Signed-off-by: Jiqian Chen --- cc: "Roger Pau Monné" --- v1->v2 changes: new patch Best regards, Jiqian Chen. --- xen/drivers/vpci/header.c | 139 ++++++++++++++++++++------------------ 1 file changed, 74 insertions(+), 65 deletions(-) diff --git a/xen/drivers/vpci/header.c b/xen/drivers/vpci/header.c index ef6c965c081c..0910eb940e23 100644 --- a/xen/drivers/vpci/header.c +++ b/xen/drivers/vpci/header.c @@ -745,6 +745,76 @@ static int bar_add_rangeset(const struct pci_dev *pdev, struct vpci_bar *bar, return !bar->mem ? -ENOMEM : 0; } +/* These capabilities can be exposed to the guest, that vPCI can handle. */ +static const unsigned int guest_supported_caps[] = { + PCI_CAP_ID_MSI, + PCI_CAP_ID_MSIX, +}; + +static int vpci_init_capability_list(struct pci_dev *pdev) +{ + int rc; + bool mask_cap_list = false; + bool is_hwdom = is_hardware_domain(pdev->domain); + const unsigned int *caps = is_hwdom ? NULL : guest_supported_caps; + const unsigned int n = is_hwdom ? 0 : ARRAY_SIZE(guest_supported_caps); + + if ( pci_conf_read16(pdev->sbdf, PCI_STATUS) & PCI_STATUS_CAP_LIST ) + { + unsigned int next, ttl = 48; + + next = pci_find_next_cap_ttl(pdev->sbdf, PCI_CAPABILITY_LIST, + caps, n, &ttl); + + rc = vpci_add_register(pdev->vpci, vpci_read_val, NULL, + PCI_CAPABILITY_LIST, 1, + (void *)(uintptr_t)next); + if ( rc ) + return rc; + + next &= ~3; + + if ( !next && !is_hwdom ) + /* + * If we don't have any supported capabilities to expose to the + * guest, mask the PCI_STATUS_CAP_LIST bit in the status register. + */ + mask_cap_list = true; + + while ( next && ttl ) + { + unsigned int pos = next; + + next = pci_find_next_cap_ttl(pdev->sbdf, pos + PCI_CAP_LIST_NEXT, + caps, n, &ttl); + + rc = vpci_add_register(pdev->vpci, vpci_hw_read8, NULL, + pos + PCI_CAP_LIST_ID, 1, NULL); + if ( rc ) + return rc; + + rc = vpci_add_register(pdev->vpci, vpci_read_val, NULL, + pos + PCI_CAP_LIST_NEXT, 1, + (void *)(uintptr_t)next); + if ( rc ) + return rc; + + next &= ~3; + } + } + + /* Utilize rsvdp_mask to hide PCI_STATUS_CAP_LIST from the guest. */ + rc = vpci_add_register_mask(pdev->vpci, vpci_hw_read16, vpci_hw_write16, + PCI_STATUS, 2, NULL, + PCI_STATUS_RO_MASK & + ~(mask_cap_list ? PCI_STATUS_CAP_LIST : 0), + PCI_STATUS_RW1C_MASK, + mask_cap_list ? PCI_STATUS_CAP_LIST : 0, + PCI_STATUS_RSVDZ_MASK); + + return rc; +} + static int cf_check init_header(struct pci_dev *pdev) { uint16_t cmd; @@ -753,7 +823,6 @@ static int cf_check init_header(struct pci_dev *pdev) struct vpci_header *header = &pdev->vpci->header; struct vpci_bar *bars = header->bars; int rc; - bool mask_cap_list = false; bool is_hwdom = is_hardware_domain(pdev->domain); ASSERT(rw_is_write_locked(&pdev->domain->pci_lock)); @@ -794,61 +863,12 @@ static int cf_check init_header(struct pci_dev *pdev) if ( rc ) return rc; + rc = vpci_init_capability_list(pdev); + if ( rc ) + return rc; + if ( !is_hwdom ) { - if ( pci_conf_read16(pdev->sbdf, PCI_STATUS) & PCI_STATUS_CAP_LIST ) - { - /* Only expose capabilities to the guest that vPCI can handle. */ - unsigned int next, ttl = 48; - static const unsigned int supported_caps[] = { - PCI_CAP_ID_MSI, - PCI_CAP_ID_MSIX, - }; - - next = pci_find_next_cap_ttl(pdev->sbdf, PCI_CAPABILITY_LIST, - supported_caps, - ARRAY_SIZE(supported_caps), &ttl); - - rc = vpci_add_register(pdev->vpci, vpci_read_val, NULL, - PCI_CAPABILITY_LIST, 1, - (void *)(uintptr_t)next); - if ( rc ) - return rc; - - next &= ~3; - - if ( !next ) - /* - * If we don't have any supported capabilities to expose to the - * guest, mask the PCI_STATUS_CAP_LIST bit in the status - * register. - */ - mask_cap_list = true; - - while ( next && ttl ) - { - unsigned int pos = next; - - next = pci_find_next_cap_ttl(pdev->sbdf, - pos + PCI_CAP_LIST_NEXT, - supported_caps, - ARRAY_SIZE(supported_caps), &ttl); - - rc = vpci_add_register(pdev->vpci, vpci_hw_read8, NULL, - pos + PCI_CAP_LIST_ID, 1, NULL); - if ( rc ) - return rc; - - rc = vpci_add_register(pdev->vpci, vpci_read_val, NULL, - pos + PCI_CAP_LIST_NEXT, 1, - (void *)(uintptr_t)next); - if ( rc ) - return rc; - - next &= ~3; - } - } - /* Extended capabilities read as zero, write ignore */ rc = vpci_add_register(pdev->vpci, vpci_read_val, NULL, 0x100, 4, (void *)0); @@ -856,17 +876,6 @@ static int cf_check init_header(struct pci_dev *pdev) return rc; } - /* Utilize rsvdp_mask to hide PCI_STATUS_CAP_LIST from the guest. */ - rc = vpci_add_register_mask(pdev->vpci, vpci_hw_read16, vpci_hw_write16, - PCI_STATUS, 2, NULL, - PCI_STATUS_RO_MASK & - ~(mask_cap_list ? PCI_STATUS_CAP_LIST : 0), - PCI_STATUS_RW1C_MASK, - mask_cap_list ? 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pr=C From: Jiqian Chen To: CC: Huang Rui , Jiqian Chen , =?utf-8?q?Roger_Pau_Monn=C3=A9?= Subject: [PATCH v2 3/8] vpci/header: Emulate extended capability list for host Date: Wed, 9 Apr 2025 14:45:23 +0800 Message-ID: <20250409064528.405573-4-Jiqian.Chen@amd.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20250409064528.405573-1-Jiqian.Chen@amd.com> References: <20250409064528.405573-1-Jiqian.Chen@amd.com> MIME-Version: 1.0 X-Originating-IP: [10.180.168.240] X-ClientProxiedBy: SATLEXMB03.amd.com (10.181.40.144) To SATLEXMB04.amd.com (10.181.40.145) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: BN2PEPF00004FBA:EE_|SA1PR12MB8723:EE_ X-MS-Office365-Filtering-Correlation-Id: 7457f07f-e833-4c2d-82de-08dd7732372d X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|82310400026|36860700013|376014|1800799024; X-Microsoft-Antispam-Message-Info: =?utf-8?q?+b1mEnGW0nf6c7DpP7zXRd7pmCwuQ1X?= =?utf-8?q?kjXC61kuAiuXQPh9hXWCdKVwMrwN+oBUx9pAca791ffZukVUQ7QbDUEFMi2VWYCVr?= =?utf-8?q?lYURpOelloaY4HiG3vftDaNrYr+Em23r+zhByXnjTeglMHJfISL38yPDIVFQ+8/3n?= =?utf-8?q?k/tat4TsZuGpWfB2FpVxoDR+rH6U4uH/q+XY5H16V8/NVFZxK/mq4PZjo6MwekCbT?= =?utf-8?q?Tok2FrV3cuJOgQGeU8LX8c9jcRdNnoDFxkfTw4vSnAHpYcLs6jfjj5x0TkbcqgWr2?= =?utf-8?q?VfcB52r4ptK7hzevcJ+wNAfXTLvst1XU8Xq8sTU9swrwQ6P+mI8cJi4yu1CtLOuhn?= =?utf-8?q?yS9Y8LQr6IPegunMw22Akc3wO47zWcONvptI5AkNDBJ86e85eWwy1iYPS05z1e24W?= =?utf-8?q?lyskQSAzJJUCSSOItWN/bSanAET8UgW0cyEAissMRWT5xa9KUf+90QHz3bHPYWR4H?= =?utf-8?q?O4hvokSaES9qVJteevqCqTWjyGTVsmyOf+YVSyssKdW29CWJlxx5hFl5HWIdaaPB2?= =?utf-8?q?J13LEi1Qh2tNLweD+MD+Girqr/RaxsDbRXmByOkpEsgyXiBpNh97V7C+h/jyBjtF9?= =?utf-8?q?AVIZDXRYdaROxwuitOsENf8Fi954620HNKP0Jzyo2Yo7kqYwjdPkxpa/eBraNDOeB?= =?utf-8?q?kO0QrY1LItF3yogWchBtgyWRVKhGMYU7m3dI9ZLExxDpWSBwMqKuEHocNuyCnPOMm?= =?utf-8?q?FAKUfYO1hcTu8iXLIm5q82wYNB+ovRs40GjtRglG8Q73X+KSZxOlNENVTqPBx2Jvh?= =?utf-8?q?Y7iqDF1C04lSqxlzfEEIgE0mxyqP6JHDPMUHs/RHEgDaSSBQLfWsrzxD4rhxmpbki?= =?utf-8?q?H0BI0QAX2YKvxL7G7VPCjDMMc7JJS8en5gzs4nQj/fuPu3ZBHyxzu3eGSy6gI1K4w?= =?utf-8?q?X3yHjAEhhjydZlsR+6e1zZ2qfNrYiuGAEWv98LDlvFh+J0ZXAsAiHW13Qv7hvvZ9a?= =?utf-8?q?v84bVH5qSzZn8+m9ghzrqMlrEwuaU6kvpHfiV/pCKzLitC3cqVRvIj1BUSMJnBgZ1?= =?utf-8?q?pKR+0CulF0iWVTNyKiNw9m6tCJQen4spzgMmjCC87E3ae8s1+UBbpIbzSaF/Bh3LM?= =?utf-8?q?s5oicaj0LC5ODDBKvvfBuZ+q4UmuWDvN+kBUw3PtWFBulXaDPT6GIwmvpUXMAYEwV?= =?utf-8?q?zC93PZ2Mci1WoBKF7d40ZFX+FFAAdCXFl/ZQdC+CgTHeyBQQMQO+TaznelfUJZaK1?= =?utf-8?q?cQTSDpU4dke8c5228F9/wsXNnF6cnFIW6KmJJIsNAac8Bt8W3ItHuZ7x08Qg/G9on?= =?utf-8?q?R4ZH1PQMN1i62zFn+LXzsD7w0xe0jyqMHCMfO8QTIkbLfblp4rZfU5jQeGt2fZ6ow?= =?utf-8?q?8F53xO4jaQiQWbqRy4g2Hdv3PWBCHqkCqqvUQUAsnHCYTJpYZRyiYZ0ozsJ4VOFlc?= =?utf-8?q?4eQWVh42Yf3mfxzr0K+X0iTBcNN8ranjsUMGZVwhj8BU9a9/4GOTxql6EnFcBswm8?= =?utf-8?q?DkjB4kxZ2Z?= X-Forefront-Antispam-Report: CIP:165.204.84.17;CTRY:US;LANG:en;SCL:1;SRV:;IPV:CAL;SFV:NSPM;H:SATLEXMB04.amd.com;PTR:InfoDomainNonexistent;CAT:NONE;SFS:(13230040)(82310400026)(36860700013)(376014)(1800799024);DIR:OUT;SFP:1101; X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 09 Apr 2025 06:46:11.3965 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 7457f07f-e833-4c2d-82de-08dd7732372d X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: BN2PEPF00004FBA.namprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: SA1PR12MB8723 Add a new function to emulate extended capability list for host, and call it in init_header(). So that, it will be easy to hide a capability whose initialization fails. As for the extended capability list of guest, keep hiding it. Signed-off-by: Jiqian Chen --- cc: "Roger Pau Monné" --- v1->v2 changes: new patch Best regards, Jiqian Chen. --- xen/drivers/vpci/header.c | 44 ++++++++++++++++++++++++++++++++------- 1 file changed, 36 insertions(+), 8 deletions(-) diff --git a/xen/drivers/vpci/header.c b/xen/drivers/vpci/header.c index 0910eb940e23..6833d456566b 100644 --- a/xen/drivers/vpci/header.c +++ b/xen/drivers/vpci/header.c @@ -815,6 +815,39 @@ static int vpci_init_capability_list(struct pci_dev *pdev) return rc; } +static int vpci_init_ext_capability_list(struct pci_dev *pdev) +{ + int rc; + u32 header; + unsigned int pos = 0x100U, ttl = 480; + + if ( !is_hardware_domain(pdev->domain) ) + { + /* Extended capabilities read as zero, write ignore */ + rc = vpci_add_register(pdev->vpci, vpci_read_val, NULL, + pos, 4, (void *)0); + if ( rc ) + return rc; + } + + while ( pos && ttl-- ) + { + header = pci_conf_read32(pdev->sbdf, pos); + + rc = vpci_add_register(pdev->vpci, vpci_read_val, NULL, + pos, 4, (void *)(uintptr_t)header); + if ( rc ) + return rc; + + if ( (header == 0) || (header == -1) ) + return 0; + + pos = PCI_EXT_CAP_NEXT(header); + } + + return 0; +} + static int cf_check init_header(struct pci_dev *pdev) { uint16_t cmd; @@ -867,14 +900,9 @@ static int cf_check init_header(struct pci_dev *pdev) if ( rc ) return rc; - if ( !is_hwdom ) - { - /* Extended capabilities read as zero, write ignore */ - rc = vpci_add_register(pdev->vpci, vpci_read_val, NULL, 0x100, 4, - (void *)0); - if ( rc ) - return rc; - } + rc = vpci_init_ext_capability_list(pdev); + if ( rc ) + return rc; if ( pdev->ignore_bars ) return 0; From patchwork Wed Apr 9 06:45:24 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: "Chen, Jiqian" X-Patchwork-Id: 14044130 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.xenproject.org (lists.xenproject.org [192.237.175.120]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 7A927C36002 for ; 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dkim=none (message not signed) header.d=none;dmarc=pass action=none header.from=amd.com; Received-SPF: Pass (protection.outlook.com: domain of amd.com designates 165.204.84.17 as permitted sender) receiver=protection.outlook.com; client-ip=165.204.84.17; helo=SATLEXMB04.amd.com; pr=C From: Jiqian Chen To: CC: Huang Rui , Jiqian Chen , =?utf-8?q?Roger_Pau_Monn=C3=A9?= , Andrew Cooper , Anthony PERARD , Michal Orzel , Jan Beulich , "Julien Grall" , Stefano Stabellini Subject: [PATCH v2 4/8] vpci: Hide capability when it fails to initialize Date: Wed, 9 Apr 2025 14:45:24 +0800 Message-ID: <20250409064528.405573-5-Jiqian.Chen@amd.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20250409064528.405573-1-Jiqian.Chen@amd.com> References: <20250409064528.405573-1-Jiqian.Chen@amd.com> MIME-Version: 1.0 X-Originating-IP: [10.180.168.240] X-ClientProxiedBy: SATLEXMB03.amd.com (10.181.40.144) To SATLEXMB04.amd.com (10.181.40.145) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: BN2PEPF00004FBA:EE_|DM6PR12MB4434:EE_ X-MS-Office365-Filtering-Correlation-Id: 9e69c30c-7b73-42ca-8d8a-08dd773239a0 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|82310400026|376014|36860700013|1800799024; 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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 09 Apr 2025 06:46:15.4903 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 9e69c30c-7b73-42ca-8d8a-08dd773239a0 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: BN2PEPF00004FBA.namprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DM6PR12MB4434 When vpci fails to initialize a capability of a device, it just return error instead of catching and processing exception. That makes the entire device unusable. So, refactor REGISTER_VPCI_INIT to contain more capability specific information, and use new functions to hide capability when initialization fails in vpci_assign_device(). Those new functions remove the failed legacy/extended capability from the emulated legacy/extended capability list. What's more, change the definition of init_header() since it is not a capability and it is needed for all devices' PCI config space. Note: call vpci_make_msix_hole() in the end of init_msix() since the change of sequence of init_header() and init_msix(). Signed-off-by: Jiqian Chen --- cc: "Roger Pau Monné" cc: Andrew Cooper cc: Anthony PERARD cc: Michal Orzel cc: Jan Beulich cc: Julien Grall cc: Stefano Stabellini --- v1->v2 changes: * Removed the "priorities" of initializing capabilities since it isn't used anymore. * Added new function vpci_capability_mask() and vpci_ext_capability_mask() to remove failed capability from list. * Called vpci_make_msix_hole() in the end of init_msix(). Best regards, Jiqian Chen. --- xen/drivers/vpci/header.c | 3 +- xen/drivers/vpci/msi.c | 2 +- xen/drivers/vpci/msix.c | 8 +- xen/drivers/vpci/rebar.c | 2 +- xen/drivers/vpci/vpci.c | 175 +++++++++++++++++++++++++++++++------ xen/include/xen/pci_regs.h | 1 + xen/include/xen/vpci.h | 26 ++++-- xen/include/xen/xen.lds.h | 2 +- 8 files changed, 179 insertions(+), 40 deletions(-) diff --git a/xen/drivers/vpci/header.c b/xen/drivers/vpci/header.c index 6833d456566b..51a67d76ad8a 100644 --- a/xen/drivers/vpci/header.c +++ b/xen/drivers/vpci/header.c @@ -848,7 +848,7 @@ static int vpci_init_ext_capability_list(struct pci_dev *pdev) return 0; } -static int cf_check init_header(struct pci_dev *pdev) +int vpci_init_header(struct pci_dev *pdev) { uint16_t cmd; uint64_t addr, size; @@ -1044,7 +1044,6 @@ static int cf_check init_header(struct pci_dev *pdev) pci_conf_write16(pdev->sbdf, PCI_COMMAND, cmd); return rc; } -REGISTER_VPCI_INIT(init_header, VPCI_PRIORITY_MIDDLE); /* * Local variables: diff --git a/xen/drivers/vpci/msi.c b/xen/drivers/vpci/msi.c index 66e5a8a116be..ca89ae9b9c22 100644 --- a/xen/drivers/vpci/msi.c +++ b/xen/drivers/vpci/msi.c @@ -270,7 +270,7 @@ static int cf_check init_msi(struct pci_dev *pdev) return 0; } -REGISTER_VPCI_INIT(init_msi, VPCI_PRIORITY_LOW); +REGISTER_VPCI_LEGACY_CAP(PCI_CAP_ID_MSI, init_msi); void vpci_dump_msi(void) { diff --git a/xen/drivers/vpci/msix.c b/xen/drivers/vpci/msix.c index 6bd8c55bb48e..6537374c79a0 100644 --- a/xen/drivers/vpci/msix.c +++ b/xen/drivers/vpci/msix.c @@ -751,9 +751,13 @@ static int cf_check init_msix(struct pci_dev *pdev) pdev->vpci->msix = msix; list_add(&msix->next, &d->arch.hvm.msix_tables); - return 0; + spin_lock(&pdev->vpci->lock); + rc = vpci_make_msix_hole(pdev); + spin_unlock(&pdev->vpci->lock); + + return rc } -REGISTER_VPCI_INIT(init_msix, VPCI_PRIORITY_HIGH); +REGISTER_VPCI_LEGACY_CAP(PCI_CAP_ID_MSIX, init_msix); /* * Local variables: diff --git a/xen/drivers/vpci/rebar.c b/xen/drivers/vpci/rebar.c index 793937449af7..79858e5dc92f 100644 --- a/xen/drivers/vpci/rebar.c +++ b/xen/drivers/vpci/rebar.c @@ -118,7 +118,7 @@ static int cf_check init_rebar(struct pci_dev *pdev) return 0; } -REGISTER_VPCI_INIT(init_rebar, VPCI_PRIORITY_LOW); +REGISTER_VPCI_EXTEND_CAP(PCI_EXT_CAP_ID_REBAR, init_rebar); /* * Local variables: diff --git a/xen/drivers/vpci/vpci.c b/xen/drivers/vpci/vpci.c index 1e6aa5d799b9..f1f125bfdab1 100644 --- a/xen/drivers/vpci/vpci.c +++ b/xen/drivers/vpci/vpci.c @@ -35,9 +35,25 @@ struct vpci_register { uint32_t rsvdz_mask; }; +static int vpci_register_cmp(const struct vpci_register *r1, + const struct vpci_register *r2) +{ + /* Return 0 if registers overlap. */ + if ( r1->offset < r2->offset + r2->size && + r2->offset < r1->offset + r1->size ) + return 0; + if ( r1->offset < r2->offset ) + return -1; + if ( r1->offset > r2->offset ) + return 1; + + ASSERT_UNREACHABLE(); + return 0; +} + #ifdef __XEN__ -extern vpci_register_init_t *const __start_vpci_array[]; -extern vpci_register_init_t *const __end_vpci_array[]; +extern vpci_capability_t *const __start_vpci_array[]; +extern vpci_capability_t *const __end_vpci_array[]; #define NUM_VPCI_INIT (__end_vpci_array - __start_vpci_array) #ifdef CONFIG_HAS_VPCI_GUEST_SUPPORT @@ -83,6 +99,133 @@ static int assign_virtual_sbdf(struct pci_dev *pdev) #endif /* CONFIG_HAS_VPCI_GUEST_SUPPORT */ +static void vpci_capability_mask(struct pci_dev *pdev, + const unsigned int cap) +{ + const unsigned int size = 1; + const unsigned int offset = pci_find_cap_offset(pdev->sbdf, cap); + const struct vpci_register r = { .offset = offset, .size = size }; + struct vpci_register *rm; + struct vpci *vpci = pdev->vpci; + + spin_lock(&vpci->lock); + list_for_each_entry ( rm, &vpci->handlers, node ) + { + int cmp = vpci_register_cmp(&r, rm); + + if ( !cmp && rm->offset == offset && rm->size == size ) + { + struct vpci_register *pre = list_entry(rm->node.prev, + struct vpci_register, + node); + struct vpci_register *next = list_entry(rm->node.next, + struct vpci_register, + node); + + pre->private = next->private; + + /* PCI_CAP_LIST_ID register of current capability */ + list_del(&rm->node); + /* PCI_CAP_LIST_NEXT register of current capability */ + list_del(&next->node); + spin_unlock(&vpci->lock); + + xfree(rm); + xfree(next); + return; + } + if ( cmp <= 0 ) + break; + } + spin_unlock(&vpci->lock); +} + +static void vpci_ext_capability_mask(struct pci_dev *pdev, + const unsigned int cap) +{ + const unsigned int size = 4; + const unsigned int offset = pci_find_ext_capability(pdev->sbdf, cap); + const struct vpci_register r = { .offset = offset, .size = size }; + struct vpci_register *rm; + struct vpci *vpci = pdev->vpci; + + spin_lock(&vpci->lock); + list_for_each_entry ( rm, &vpci->handlers, node ) + { + int cmp = vpci_register_cmp(&r, rm); + + if ( !cmp && rm->offset == offset && rm->size == size ) + { + struct vpci_register *pre; + u32 pre_header, header = (u32)(uintptr_t)rm->private; + + if ( offset == 0x100U && PCI_EXT_CAP_NEXT(header) == 0 ) + { + rm->private = (void *)(uintptr_t)0; + spin_unlock(&vpci->lock); + return; + } + else if ( offset == 0x100U ) + { + pre = rm; + rm = list_entry(rm->node.next, struct vpci_register, node); + pre->private = rm->private; + } + else + { + pre = list_entry(rm->node.prev, struct vpci_register, node); + pre_header = (u32)(uintptr_t)pre->private; + pre->private = + (void *)(uintptr_t)((pre_header & !PCI_EXT_CAP_NEXT_MASK) | + (header & PCI_EXT_CAP_NEXT_MASK)); + } + list_del(&rm->node); + spin_unlock(&vpci->lock); + xfree(rm); + return; + } + if ( cmp <= 0 ) + break; + } + spin_unlock(&vpci->lock); +} + +static void vpci_init_capabilities(struct pci_dev *pdev) +{ + for ( unsigned int i = 0; i < NUM_VPCI_INIT; i++ ) + { + const vpci_capability_t *capability = __start_vpci_array[i]; + const unsigned int cap = capability->id; + const bool is_ext = capability->is_ext; + unsigned int pos; + int rc; + + if ( !is_hardware_domain(pdev->domain) && is_ext ) + continue; + + if ( is_ext ) + pos = pci_find_ext_capability(pdev->sbdf, cap); + else + pos = pci_find_cap_offset(pdev->sbdf, cap); + + if ( !pos ) + continue; + + rc = capability->init(pdev); + + if ( rc ) + { + printk(XENLOG_WARNING "%pd %pp: %s cap %u init fail rc=%d, mask it\n", + pdev->domain, &pdev->sbdf, + is_ext ? "extended" : "legacy", cap, rc); + if ( is_ext ) + vpci_ext_capability_mask(pdev, cap); + else + vpci_capability_mask(pdev, cap); + } + } +} + void vpci_deassign_device(struct pci_dev *pdev) { unsigned int i; @@ -128,7 +271,6 @@ void vpci_deassign_device(struct pci_dev *pdev) int vpci_assign_device(struct pci_dev *pdev) { - unsigned int i; const unsigned long *ro_map; int rc = 0; @@ -159,12 +301,11 @@ int vpci_assign_device(struct pci_dev *pdev) goto out; #endif - for ( i = 0; i < NUM_VPCI_INIT; i++ ) - { - rc = __start_vpci_array[i](pdev); - if ( rc ) - break; - } + rc = vpci_init_header(pdev); + if ( rc ) + goto out; + + vpci_init_capabilities(pdev); out: __maybe_unused; if ( rc ) @@ -174,22 +315,6 @@ int vpci_assign_device(struct pci_dev *pdev) } #endif /* __XEN__ */ -static int vpci_register_cmp(const struct vpci_register *r1, - const struct vpci_register *r2) -{ - /* Return 0 if registers overlap. */ - if ( r1->offset < r2->offset + r2->size && - r2->offset < r1->offset + r1->size ) - return 0; - if ( r1->offset < r2->offset ) - return -1; - if ( r1->offset > r2->offset ) - return 1; - - ASSERT_UNREACHABLE(); - return 0; -} - /* Dummy hooks, writes are ignored, reads return 1's */ static uint32_t cf_check vpci_ignored_read( const struct pci_dev *pdev, unsigned int reg, void *data) diff --git a/xen/include/xen/pci_regs.h b/xen/include/xen/pci_regs.h index 27b4f44eedf3..5fe6653fded4 100644 --- a/xen/include/xen/pci_regs.h +++ b/xen/include/xen/pci_regs.h @@ -449,6 +449,7 @@ #define PCI_EXT_CAP_ID(header) ((header) & 0x0000ffff) #define PCI_EXT_CAP_VER(header) (((header) >> 16) & 0xf) #define PCI_EXT_CAP_NEXT(header) (((header) >> 20) & 0xffc) +#define PCI_EXT_CAP_NEXT_MASK 0xFFC00000U #define PCI_EXT_CAP_ID_ERR 1 #define PCI_EXT_CAP_ID_VC 2 diff --git a/xen/include/xen/vpci.h b/xen/include/xen/vpci.h index 807401b2eaa2..5016ded64d89 100644 --- a/xen/include/xen/vpci.h +++ b/xen/include/xen/vpci.h @@ -13,11 +13,11 @@ typedef uint32_t vpci_read_t(const struct pci_dev *pdev, unsigned int reg, typedef void vpci_write_t(const struct pci_dev *pdev, unsigned int reg, uint32_t val, void *data); -typedef int vpci_register_init_t(struct pci_dev *dev); - -#define VPCI_PRIORITY_HIGH "1" -#define VPCI_PRIORITY_MIDDLE "5" -#define VPCI_PRIORITY_LOW "9" +typedef struct { + unsigned int id; + bool is_ext; + int (*init)(struct pci_dev *pdev); +} vpci_capability_t; #define VPCI_ECAM_BDF(addr) (((addr) & 0x0ffff000) >> 12) @@ -29,9 +29,19 @@ typedef int vpci_register_init_t(struct pci_dev *dev); */ #define VPCI_MAX_VIRT_DEV (PCI_SLOT(~0) + 1) -#define REGISTER_VPCI_INIT(x, p) \ - static vpci_register_init_t *const x##_entry \ - __used_section(".data.vpci." p) = (x) +#define REGISTER_VPCI_CAP(cap, x, ext) \ + static vpci_capability_t x##_t = { \ + .id = (cap), \ + .init = (x), \ + .is_ext = (ext), \ + }; \ + static vpci_capability_t *const x##_entry \ + __used_section(".data.vpci.") = &(x##_t) + +#define REGISTER_VPCI_LEGACY_CAP(cap, x) REGISTER_VPCI_CAP(cap, x, false) +#define REGISTER_VPCI_EXTEND_CAP(cap, x) REGISTER_VPCI_CAP(cap, x, true) + +int __must_check vpci_init_header(struct pci_dev *pdev); /* Assign vPCI to device by adding handlers. */ int __must_check vpci_assign_device(struct pci_dev *pdev); diff --git a/xen/include/xen/xen.lds.h b/xen/include/xen/xen.lds.h index 16a9b1ba03db..c73222112dd3 100644 --- a/xen/include/xen/xen.lds.h +++ b/xen/include/xen/xen.lds.h @@ -187,7 +187,7 @@ #define VPCI_ARRAY \ . = ALIGN(POINTER_ALIGN); \ __start_vpci_array = .; \ - *(SORT(.data.vpci.*)) \ + *(.data.vpci.*) \ __end_vpci_array = .; #else #define VPCI_ARRAY From patchwork Wed Apr 9 06:45:25 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: "Chen, Jiqian" X-Patchwork-Id: 14044126 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.xenproject.org (lists.xenproject.org [192.237.175.120]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 2DB15C369A6 for ; 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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 09 Apr 2025 06:46:17.9121 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 479017fd-2d5a-44a3-1a13-08dd77323b12 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: BN2PEPF00004FBA.namprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: PH0PR12MB8032 vpci_remove_register() only supports removing a register in a time, but the follow-on changes need to remove all registers within a range. And it is only used for test. So, refactor it to support removing all matched registers in a calling time. And it is no matter to remove a non exist register, so remove the __must_check prefix. Signed-off-by: Jiqian Chen --- cc: "Roger Pau Monné" cc: Anthony PERARD --- v1->v2 changes: new patch Best regards, Jiqian Chen. --- tools/tests/vpci/main.c | 4 ++-- xen/drivers/vpci/vpci.c | 23 ++++++++++++----------- xen/include/xen/vpci.h | 4 ++-- 3 files changed, 16 insertions(+), 15 deletions(-) diff --git a/tools/tests/vpci/main.c b/tools/tests/vpci/main.c index 33223db3eb77..ca72877d60cd 100644 --- a/tools/tests/vpci/main.c +++ b/tools/tests/vpci/main.c @@ -132,10 +132,10 @@ static void vpci_write32_mask(const struct pci_dev *pdev, unsigned int reg, rsvdz_mask)) #define VPCI_REMOVE_REG(off, size) \ - assert(!vpci_remove_register(test_pdev.vpci, off, size)) + assert(!vpci_remove_registers(test_pdev.vpci, off, size)) #define VPCI_REMOVE_INVALID_REG(off, size) \ - assert(vpci_remove_register(test_pdev.vpci, off, size)) + assert(vpci_remove_registers(test_pdev.vpci, off, size)) /* Read a 32b register using all possible sizes. */ void multiread4_check(unsigned int reg, uint32_t val) diff --git a/xen/drivers/vpci/vpci.c b/xen/drivers/vpci/vpci.c index f1f125bfdab1..115d3c5f0c84 100644 --- a/xen/drivers/vpci/vpci.c +++ b/xen/drivers/vpci/vpci.c @@ -418,34 +418,35 @@ int vpci_add_register_mask(struct vpci *vpci, vpci_read_t *read_handler, return 0; } -int vpci_remove_register(struct vpci *vpci, unsigned int offset, - unsigned int size) +int vpci_remove_registers(struct vpci *vpci, unsigned int offset, + unsigned int size) { const struct vpci_register r = { .offset = offset, .size = size }; struct vpci_register *rm; + int rc = -ENOENT; spin_lock(&vpci->lock); list_for_each_entry ( rm, &vpci->handlers, node ) { int cmp = vpci_register_cmp(&r, rm); - /* - * NB: do not use a switch so that we can use break to - * get out of the list loop earlier if required. - */ - if ( !cmp && rm->offset == offset && rm->size == size ) + if ( !cmp ) { + struct vpci_register *prev = + list_entry(rm->node.prev, struct vpci_register, node); + list_del(&rm->node); - spin_unlock(&vpci->lock); xfree(rm); - return 0; + rm = prev; + rc = 0; } - if ( cmp <= 0 ) + + if ( cmp < 0 ) break; } spin_unlock(&vpci->lock); - return -ENOENT; + return rc; } /* Wrappers for performing reads/writes to the underlying hardware. */ diff --git a/xen/include/xen/vpci.h b/xen/include/xen/vpci.h index 5016ded64d89..ee9163ca6a56 100644 --- a/xen/include/xen/vpci.h +++ b/xen/include/xen/vpci.h @@ -67,8 +67,8 @@ static inline int __must_check vpci_add_register(struct vpci *vpci, size, data, 0, 0, 0, 0); } -int __must_check vpci_remove_register(struct vpci *vpci, unsigned int offset, - unsigned int size); +int vpci_remove_registers(struct vpci *vpci, unsigned int offset, + unsigned int size); /* Generic read/write handlers for the PCI config space. */ uint32_t vpci_read(pci_sbdf_t sbdf, unsigned int reg, unsigned int size); From patchwork Wed Apr 9 06:45:26 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: "Chen, Jiqian" X-Patchwork-Id: 14044125 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.xenproject.org (lists.xenproject.org [192.237.175.120]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 1D2C4C369A2 for ; Wed, 9 Apr 2025 06:46:38 +0000 (UTC) Received: from list by lists.xenproject.org with outflank-mailman.943391.1342212 (Exim 4.92) (envelope-from ) id 1u2PCf-0005or-9k; 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pr=C From: Jiqian Chen To: CC: Huang Rui , Jiqian Chen , =?utf-8?q?Roger_Pau_Monn=C3=A9?= Subject: [PATCH v2 6/8] vpci/rebar: Remove registers when init_rebar() fails Date: Wed, 9 Apr 2025 14:45:26 +0800 Message-ID: <20250409064528.405573-7-Jiqian.Chen@amd.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20250409064528.405573-1-Jiqian.Chen@amd.com> References: <20250409064528.405573-1-Jiqian.Chen@amd.com> MIME-Version: 1.0 X-Originating-IP: [10.180.168.240] X-ClientProxiedBy: SATLEXMB03.amd.com (10.181.40.144) To SATLEXMB04.amd.com (10.181.40.145) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: BN2PEPF00004FBA:EE_|CY5PR12MB9053:EE_ X-MS-Office365-Filtering-Correlation-Id: e2b3e61b-7173-4252-f69a-08dd77323c72 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|1800799024|376014|82310400026|36860700013; X-Microsoft-Antispam-Message-Info: =?utf-8?q?7inZOZ6zjlMY2qapuvywNTj2hy2fM0l?= =?utf-8?q?ANxRQkFC27HLa0WtuTy4MnpaJusXGCmsJ517UOGsw/ClAA1uKf2VQq18lXnZ4r7E2?= =?utf-8?q?6x3nc5ovie7uF8KpT6yb9UswniaSCRThC+kclVmAWPXj0BJOTrv58mOStcQ2C9vQj?= =?utf-8?q?gd7yuq+3/oeFmaf7AzBK2JUda9mNIciTjv1PBJu74HjyQLXptELTDZ3CYVjhCJWfr?= =?utf-8?q?scp4daIr/tPh2JJEFU7f9ASuI0RNDYXYsPz/MpOWWKrYcif0nFCDpBarev3qDOA9S?= =?utf-8?q?qEQbVQSnUDihLgO5j8i9Ng01LspLpP8OzoqpeoLasB/ZoN1jWUGvV1zoBJsG0iz2X?= =?utf-8?q?BjQfke8Bxbji7zuSyb+qXdSnbopWq+RXbeccMjtwGybtgsPiIuf//YKvKY2R6KmpL?= =?utf-8?q?IyAy1yyfVdYIYkIClCz1Sm5W43UYeGM0yXJ5FEalkuW7b8MqaKVh089Xikdg3CM3p?= =?utf-8?q?NyHGlY6gtJvKEAyzSu3LfXHMSgMd/NdWhQCObbK6jG+RZ254h0RZARU5uHtRrLONF?= =?utf-8?q?3WE29NmRj8MrLSOKH4JLTnVHAYyeCTh8UmIBt47skY9ZRXy82u4QCGjKf8/9/vdlo?= =?utf-8?q?jE0JQxHKaH6gEZKmNMShRYJDqYRiI0dxvwZWc+zviCnDAX/UuR+g44CQDJHCPn1Xs?= =?utf-8?q?kRwsoMj/1XaZGPRY6p8NHWmUyzBJCYHU0F+L2wXNaQFVwU/ETAXaGm0qeMYhB67nu?= =?utf-8?q?bnnpjGxxqBsBxNxoeqnUbCbez90owP6v9luPljxmlcvBxziGH78lIuQvAmfX2V0T5?= =?utf-8?q?thgD0fZNWNqwyQ14Bif2veEwAZLzuivtKxqRHNJwMAxT3Sftjow9YbQ/NsMSmmFyC?= =?utf-8?q?zrmy1+/bm+zjNnNwibGll8+IOHyDp+QkerNY9whyZM249CLepJNh1d4bbJhfoEG7M?= =?utf-8?q?JtWRdHvqB9L9SJeCn6KiZuBpvY5ZGABQ13hsWMrrLAJ8ke5XNHfhd1nulmXNOqGyo?= =?utf-8?q?+uFVGvQGTaCzSpk7lELE5PFU7hQcF8GEzB/KHLPGEDniAbN6zTwxw8UmesM+iExMK?= =?utf-8?q?TXqnTZ9/esXBfyDLCzKSa+6flpEWbd1CkNQGQaMGBYQ1GP+b9M+gytTC+jFhacx4u?= =?utf-8?q?i9X7vq5I2Kzqm0w4+cyHCzuiroTMRa8ILI5ix1H4KW6ys1xbElYiaTk6i3Dv3fryY?= =?utf-8?q?3qRhZykCYAENCH5cTPt3D52l19wwW+QBic9QAE2jXmrq4Ooji2Tc4GRSQ7yX2Y4cO?= =?utf-8?q?oZMDSmMM3ZUshUsGLPQ5ejB03CH20V0WqANO3I2jRdO/e/Lp3q5aiHf4HPtbL74A7?= =?utf-8?q?8ubzOK56s/4I+mRMH9bC/qnyzISbkypCerztSvFOry+B6jmxp+Zeb5bc+J37pqAW4?= =?utf-8?q?VbTBm1L+0vJFMcuv9ciSgN7p6dxVqawXK3lKhoJ1yscTOgQlkfepuyiIJ36P5M2FB?= =?utf-8?q?YJeX40HIugtQFJ9D8bXVGlUiwj+7AZrJoJgYJuj8o6km+N5EkY+4i6QEvRAYXWt1l?= =?utf-8?q?lTAZ+vzciO?= X-Forefront-Antispam-Report: CIP:165.204.84.17;CTRY:US;LANG:en;SCL:1;SRV:;IPV:CAL;SFV:NSPM;H:SATLEXMB04.amd.com;PTR:InfoDomainNonexistent;CAT:NONE;SFS:(13230040)(1800799024)(376014)(82310400026)(36860700013);DIR:OUT;SFP:1101; X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 09 Apr 2025 06:46:20.2246 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: e2b3e61b-7173-4252-f69a-08dd77323c72 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: BN2PEPF00004FBA.namprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: CY5PR12MB9053 When init_rebar() fails, the previous new changes will hide Rebar capability, it can't rely on vpci_deassign_device() to remove all Rebar related registers anymore, those registers must be removed in failure path of init_rebar. To do that, call vpci_remove_registers() to remove all possible registered registers in the failure patch. Signed-off-by: Jiqian Chen --- cc: "Roger Pau Monné" --- v1->v2 changes: * Called vpci_remove_registers() to remove all possible registered registers instead of using a array to record all registered register. Best regards, Jiqian Chen. --- xen/drivers/vpci/rebar.c | 25 ++++++++++++++----------- 1 file changed, 14 insertions(+), 11 deletions(-) diff --git a/xen/drivers/vpci/rebar.c b/xen/drivers/vpci/rebar.c index 79858e5dc92f..e030937956e3 100644 --- a/xen/drivers/vpci/rebar.c +++ b/xen/drivers/vpci/rebar.c @@ -51,6 +51,7 @@ static void cf_check rebar_ctrl_write(const struct pci_dev *pdev, static int cf_check init_rebar(struct pci_dev *pdev) { + int rc = 0; uint32_t ctrl; unsigned int nbars; unsigned int rebar_offset = pci_find_ext_capability(pdev->sbdf, @@ -70,7 +71,6 @@ static int cf_check init_rebar(struct pci_dev *pdev) nbars = MASK_EXTR(ctrl, PCI_REBAR_CTRL_NBAR_MASK); for ( unsigned int i = 0; i < nbars; i++ ) { - int rc; struct vpci_bar *bar; unsigned int index; @@ -80,7 +80,7 @@ static int cf_check init_rebar(struct pci_dev *pdev) { printk(XENLOG_ERR "%pd %pp: too big BAR number %u in REBAR_CTRL\n", pdev->domain, &pdev->sbdf, index); - continue; + goto fail; } bar = &pdev->vpci->header.bars[index]; @@ -88,7 +88,7 @@ static int cf_check init_rebar(struct pci_dev *pdev) { printk(XENLOG_ERR "%pd %pp: BAR%u is not in memory space\n", pdev->domain, &pdev->sbdf, index); - continue; + goto fail; } rc = vpci_add_register(pdev->vpci, vpci_hw_read32, rebar_ctrl_write, @@ -97,14 +97,7 @@ static int cf_check init_rebar(struct pci_dev *pdev) { printk(XENLOG_ERR "%pd %pp: BAR%u fail to add reg of REBAR_CTRL rc=%d\n", pdev->domain, &pdev->sbdf, index, rc); - /* - * Ideally we would hide the ReBar capability on error, but code - * for doing so still needs to be written. Use continue instead - * to keep any already setup register hooks, as returning an - * error will cause the hardware domain to get unmediated access - * to all device registers. - */ - continue; + goto fail; } bar->resizable_sizes = @@ -117,6 +110,16 @@ static int cf_check init_rebar(struct pci_dev *pdev) } return 0; + + fail: + /* + * Remove all possible registered registers except header. + * Header register will be removed in mask function. + */ + vpci_remove_registers(pdev->vpci, rebar_offset + PCI_REBAR_CAP(0), + PCI_REBAR_CTRL(nbars - 1)); + + return rc; } REGISTER_VPCI_EXTEND_CAP(PCI_EXT_CAP_ID_REBAR, init_rebar); From patchwork Wed Apr 9 06:45:27 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: "Chen, Jiqian" X-Patchwork-Id: 14044128 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.xenproject.org (lists.xenproject.org [192.237.175.120]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 911E7C369A7 for ; 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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 09 Apr 2025 06:46:20.9590 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 96b59b37-7a9a-4c6f-04ee-08dd77323ce3 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: BN2PEPF00004FBA.namprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: MN2PR12MB4222 When init_msi() fails, the previous new changes will hide MSI capability, it can't rely on vpci_deassign_device() to remove all MSI related resources anymore, those resources must be cleaned up in failure path of init_msi. To do that, add a new function to free MSI resources. Signed-off-by: Jiqian Chen --- cc: "Roger Pau Monné" --- v1->v2 changes: * Added a new function fini_msi to free all MSI resources instead of using an array to record registered registers. --- xen/drivers/vpci/msi.c | 47 +++++++++++++++++++++++++++++++++--------- 1 file changed, 37 insertions(+), 10 deletions(-) diff --git a/xen/drivers/vpci/msi.c b/xen/drivers/vpci/msi.c index ca89ae9b9c22..48a466dba0ef 100644 --- a/xen/drivers/vpci/msi.c +++ b/xen/drivers/vpci/msi.c @@ -193,6 +193,33 @@ static void cf_check mask_write( msi->mask = val; } +/* 12 is size of MSI structure for 32-bit Message Address without PVM */ +#define MSI_STRUCTURE_SIZE_32 12 + +static void fini_msi(struct pci_dev *pdev) +{ + unsigned int size = MSI_STRUCTURE_SIZE_32; + + if ( !pdev->vpci->msi ) + return; + + if ( pdev->vpci->msi->address64 ) + size += 4; + if ( pdev->vpci->msi->masking ) + size += 4; + + /* + * Remove all possible registered registers except capability ID + * register and next capability pointer register, which will be + * removed in mask function. + */ + vpci_remove_registers(pdev->vpci, + msi_control_reg(pdev->msi_pos), + size - PCI_MSI_FLAGS); + xfree(pdev->vpci->msi); + pdev->vpci->msi = NULL; +} + static int cf_check init_msi(struct pci_dev *pdev) { unsigned int pos = pdev->msi_pos; @@ -209,12 +236,7 @@ static int cf_check init_msi(struct pci_dev *pdev) ret = vpci_add_register(pdev->vpci, control_read, control_write, msi_control_reg(pos), 2, pdev->vpci->msi); if ( ret ) - /* - * NB: there's no need to free the msi struct or remove the register - * handlers form the config space, the caller will take care of the - * cleanup. - */ - return ret; + goto fail; /* Get the maximum number of vectors the device supports. */ control = pci_conf_read16(pdev->sbdf, msi_control_reg(pos)); @@ -237,20 +259,20 @@ static int cf_check init_msi(struct pci_dev *pdev) ret = vpci_add_register(pdev->vpci, address_read, address_write, msi_lower_address_reg(pos), 4, pdev->vpci->msi); if ( ret ) - return ret; + goto fail; ret = vpci_add_register(pdev->vpci, data_read, data_write, msi_data_reg(pos, pdev->vpci->msi->address64), 2, pdev->vpci->msi); if ( ret ) - return ret; + goto fail; if ( pdev->vpci->msi->address64 ) { ret = vpci_add_register(pdev->vpci, address_hi_read, address_hi_write, msi_upper_address_reg(pos), 4, pdev->vpci->msi); if ( ret ) - return ret; + goto fail; } if ( pdev->vpci->msi->masking ) @@ -260,7 +282,7 @@ static int cf_check init_msi(struct pci_dev *pdev) pdev->vpci->msi->address64), 4, pdev->vpci->msi); if ( ret ) - return ret; + goto fail; /* * FIXME: do not add any handler for the pending bits for the hardware * domain, which means direct access. This will be revisited when @@ -269,6 +291,11 @@ static int cf_check init_msi(struct pci_dev *pdev) } return 0; + + fail: + fini_msi(pdev); + + return ret; } REGISTER_VPCI_LEGACY_CAP(PCI_CAP_ID_MSI, init_msi); From patchwork Wed Apr 9 06:45:28 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: "Chen, Jiqian" X-Patchwork-Id: 14044129 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.xenproject.org (lists.xenproject.org [192.237.175.120]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 86E7FC369A5 for ; Wed, 9 Apr 2025 06:46:40 +0000 (UTC) Received: from list by lists.xenproject.org with outflank-mailman.943387.1342190 (Exim 4.92) (envelope-from ) id 1u2PCd-0005PX-Gk; Wed, 09 Apr 2025 06:46:27 +0000 X-Outflank-Mailman: Message body and most headers restored to incoming version Received: by outflank-mailman (output) from mailman id 943387.1342190; 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pr=C From: Jiqian Chen To: CC: Huang Rui , Jiqian Chen , "Jan Beulich" , Andrew Cooper , =?utf-8?q?Roger_Pau_Monn=C3=A9?= Subject: [PATCH v2 8/8] vpci/msix: Add function to clean MSIX resources Date: Wed, 9 Apr 2025 14:45:28 +0800 Message-ID: <20250409064528.405573-9-Jiqian.Chen@amd.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20250409064528.405573-1-Jiqian.Chen@amd.com> References: <20250409064528.405573-1-Jiqian.Chen@amd.com> MIME-Version: 1.0 X-Originating-IP: [10.180.168.240] X-ClientProxiedBy: SATLEXMB03.amd.com (10.181.40.144) To SATLEXMB04.amd.com (10.181.40.145) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: BN2PEPF00004FBA:EE_|CY3PR12MB9554:EE_ X-MS-Office365-Filtering-Correlation-Id: 7ae12941-be2c-4c6e-b3f1-08dd77323d12 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|376014|36860700013|1800799024|82310400026; X-Microsoft-Antispam-Message-Info: =?utf-8?q?NUjfIJK5FNi+qsv3x2x8s8tPDIJG4A7?= =?utf-8?q?SaGNEfzvspoaBhQFPdSrlwqD/IMpe0b1jxZsNdyrhcgfpUN+EDvvVMdWnDdfGfDLq?= =?utf-8?q?HKsB+99nKrjPHz4Z2aEzTmrbPqpv0OBQIqU7RtEiSB3JhggkDGNcktYmCIEhY4+35?= =?utf-8?q?EAU0tZDT6iPjcXDWi4p+0Y3WuJHUqywjyc8gZuBra+h5X2Qaaq3G/E0pL4R3TyBjd?= =?utf-8?q?lmVfjmsJaCpUYcpaIrUkrkVoBSWr1Nl15KrTVlxc7azzRW+yGUSWeStnRRABqvWA5?= =?utf-8?q?ACeza5yXOCPUa5oHYHlqWksAyD1th96li1b01w62VagZE+rsF+xXNMNg1il7A0hy2?= =?utf-8?q?FMsyKEE8onkX5KS3FZeTGxPpcwA9iKmlfjPzyeMwLmCqHIvoUk/QVu6TsY9cT7qJo?= =?utf-8?q?qRTL+EvlOMYw757GJIoPj2c4ulz1UofJV17kh7KRbHuuPqxuCfIvbGu+4c4kiPoz/?= =?utf-8?q?7Twpyvb3m9yp9oBtasYv3IVHqkqpl4Ma6YOls8vyRBlCRONbZRQyOAqSdWGb5Y7qv?= =?utf-8?q?FdGkxUxgmgWmhBzmiZuDKYw7OCPz7ahBNcuwCShumIqOPUYVD/qHn3C+ZpielTmcS?= =?utf-8?q?Db4FLKHaBB4OufPtO7Gec3FBg5U4CwiArKtw05huWbdhwqLm6rJq4K21cfWHIBEWh?= =?utf-8?q?4R9O3P8rrAUKFCsXZswtDJ3yK1ZCjlwy4FlXL5RABlcqYpmjW7XhkCDCHCtbGcwQQ?= =?utf-8?q?GvNG1OOjopeC8kWKpvi4Erm6/Wu0Np8EQVG4ifPXhQLhVaF3oiO6eJbBQUmYdDjZL?= =?utf-8?q?tBMsM2eEYXN2+Yt5N2IG1r7pn3mGojx7thl4dcyuLk7GhnzB2ujaijcySjiME88/P?= =?utf-8?q?pktEXaQK/99bKjKRMs8BfcV1o7RYKt2tE/So2NZXiQwbdd2p9xxaRhOEQzpxob2gI?= =?utf-8?q?vqEThVDnl6JWsVV362aVdpXwCiF/b+0FegztYhwSeBYBIUymgP2n7LqUnN3F/4cjg?= =?utf-8?q?PN8OwKr+RVDTb6qHMVs5EBNc4hk/70LqOULy4+favPfX6ji5faXUZmUMFhAzqarnU?= =?utf-8?q?cw4reOF1FfDsjEGSN8tNSuX7TQluNdRQhBLxcYXD0N9BfH3tAx8+rA6VAXTUHI12R?= =?utf-8?q?6MO3K+iJlaSmQEw4qTvStzazDF22q7YqzoicvDG2LAjAIr/7mL97lIz/+s4hajOv6?= =?utf-8?q?6Jq6AAC5JfenU+YmRMIrt6Y5HQBRzOQQwp1NPxQO7r5pJdW5uViLazLwqYPNH//KE?= =?utf-8?q?j2KaaULJ5MojJdNkLQnNkBUY09zvQ1GSN0plWaJnDAE01g6DfEqecDQ5YoFikvwv8?= =?utf-8?q?V9nKaFvOAVsCt/CaN76KFqxN4B/gURMrqXW0Pei17TbkYI6I0xDs0EKmahUn/2P6i?= =?utf-8?q?0oFcKhgC6qSCiKRm+PSF/67pSEktFlzPriYhW0wd7/SO+OrwzuClt/05XlYEJnaXm?= =?utf-8?q?aQwqSZxu1U9zLqto60RW27Xe1KHR9aglyJKcWy+dZLok0IzNSIup3A=3D?= X-Forefront-Antispam-Report: CIP:165.204.84.17;CTRY:US;LANG:en;SCL:1;SRV:;IPV:CAL;SFV:NSPM;H:SATLEXMB04.amd.com;PTR:InfoDomainNonexistent;CAT:NONE;SFS:(13230040)(376014)(36860700013)(1800799024)(82310400026);DIR:OUT;SFP:1101; X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 09 Apr 2025 06:46:21.2715 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 7ae12941-be2c-4c6e-b3f1-08dd77323d12 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: BN2PEPF00004FBA.namprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: CY3PR12MB9554 When init_msix() fails, it needs to clean all MSIX resources. So, add a new function fini_msix() to do that. And to unregister the mmio handler of vpci_msix_table_ops, add a new function. Signed-off-by: Jiqian Chen --- cc: Jan Beulich cc: Andrew Cooper cc: "Roger Pau Monné" --- v1->v2 changes: new patch. Best regards, Jiqian Chen. --- xen/arch/x86/hvm/intercept.c | 44 ++++++++++++++++++++++ xen/arch/x86/include/asm/hvm/io.h | 3 ++ xen/drivers/vpci/msix.c | 61 ++++++++++++++++++++++++++++--- 3 files changed, 103 insertions(+), 5 deletions(-) diff --git a/xen/arch/x86/hvm/intercept.c b/xen/arch/x86/hvm/intercept.c index da22c386763e..5eacf51d4d2c 100644 --- a/xen/arch/x86/hvm/intercept.c +++ b/xen/arch/x86/hvm/intercept.c @@ -276,6 +276,50 @@ void register_mmio_handler(struct domain *d, handler->mmio.ops = ops; } +void unregister_mmio_handler(struct domain *d, + const struct hvm_mmio_ops *ops) +{ + unsigned int i, count = d->arch.hvm.io_handler_count; + + ASSERT(d->arch.hvm.io_handler); + + if ( !count ) + return; + + for ( i = 0; i < count; i++ ) + if ( d->arch.hvm.io_handler[i].type == IOREQ_TYPE_COPY && + d->arch.hvm.io_handler[i].mmio.ops == ops ) + break; + + if ( i == count ) + return; + + for ( ; i < count - 1; i++ ) + { + struct hvm_io_handler *curr = &d->arch.hvm.io_handler[i]; + struct hvm_io_handler *next = &d->arch.hvm.io_handler[i + 1]; + + curr->type = next->type; + curr->ops = next->ops; + if ( next->type == IOREQ_TYPE_COPY ) + { + curr->portio.port = 0; + curr->portio.size = 0; + curr->portio.action = 0; + curr->mmio.ops = next->mmio.ops; + } + else + { + curr->mmio.ops = 0; + curr->portio.port = next->portio.port; + curr->portio.size = next->portio.size; + curr->portio.action = next->portio.action; + } + } + + d->arch.hvm.io_handler_count--; +} + void register_portio_handler(struct domain *d, unsigned int port, unsigned int size, portio_action_t action) { diff --git a/xen/arch/x86/include/asm/hvm/io.h b/xen/arch/x86/include/asm/hvm/io.h index 565bad300d20..018d2745fd99 100644 --- a/xen/arch/x86/include/asm/hvm/io.h +++ b/xen/arch/x86/include/asm/hvm/io.h @@ -75,6 +75,9 @@ bool hvm_mmio_internal(paddr_t gpa); void register_mmio_handler(struct domain *d, const struct hvm_mmio_ops *ops); +void unregister_mmio_handler(struct domain *d, + const struct hvm_mmio_ops *ops); + void register_portio_handler( struct domain *d, unsigned int port, unsigned int size, portio_action_t action); diff --git a/xen/drivers/vpci/msix.c b/xen/drivers/vpci/msix.c index 6537374c79a0..60654d4f6d0b 100644 --- a/xen/drivers/vpci/msix.c +++ b/xen/drivers/vpci/msix.c @@ -703,6 +703,54 @@ int vpci_make_msix_hole(const struct pci_dev *pdev) return 0; } +static void fini_msix(struct pci_dev *pdev) +{ + struct vpci *vpci = pdev->vpci; + + if ( !vpci->msix ) + return; + + list_del(&vpci->msix->next); + if ( list_empty(&pdev->domain->arch.hvm.msix_tables) ) + unregister_mmio_handler(pdev->domain, &vpci_msix_table_ops); + + /* Remove any MSIX regions if present. */ + for ( unsigned int i = 0; + vpci->msix && i < ARRAY_SIZE(vpci->msix->tables); + i++ ) + { + unsigned long start = PFN_DOWN(vmsix_table_addr(pdev->vpci, i)); + unsigned long end = PFN_DOWN(vmsix_table_addr(pdev->vpci, i) + + vmsix_table_size(pdev->vpci, i) - 1); + + for ( unsigned int j = 0; j < ARRAY_SIZE(vpci->header.bars); j++ ) + { + int rc; + const struct vpci_bar *bar = &vpci->header.bars[j]; + + if ( rangeset_is_empty(bar->mem) ) + continue; + + rc = rangeset_remove_range(bar->mem, start, end); + if ( rc ) + { + gprintk(XENLOG_WARNING, + "%pp: failed to remove MSIX table [%lx, %lx]: %d\n", + &pdev->sbdf, start, end, rc); + return; + } + } + } + + for ( unsigned int i = 0; i < ARRAY_SIZE(vpci->msix->table); i++ ) + if ( vpci->msix->table[i] ) + iounmap(vpci->msix->table[i]); + + vpci_remove_registers(vpci, msix_control_reg(pdev->msix_pos), 2); + xfree(vpci->msix); + vpci->msix = NULL; +} + static int cf_check init_msix(struct pci_dev *pdev) { struct domain *d = pdev->domain; @@ -726,10 +774,7 @@ static int cf_check init_msix(struct pci_dev *pdev) rc = vpci_add_register(pdev->vpci, control_read, control_write, msix_control_reg(msix_offset), 2, msix); if ( rc ) - { - xfree(msix); - return rc; - } + goto fail; msix->max_entries = max_entries; msix->pdev = pdev; @@ -755,7 +800,13 @@ static int cf_check init_msix(struct pci_dev *pdev) rc = vpci_make_msix_hole(pdev); spin_unlock(&pdev->vpci->lock); - return rc + if ( !rc ) + return 0; + + fail: + fini_msix(pdev); + + return rc; } REGISTER_VPCI_LEGACY_CAP(PCI_CAP_ID_MSIX, init_msix);