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Wed, 9 Apr 2025 09:30:31 +0000 (GMT) Received: from eusmgms1.samsung.com (unknown [182.198.249.179]) by eusmtrp1.samsung.com (KnoxPortal) with ESMTP id 20250409093031eusmtrp1c091b027f744040d7f056718b50f2a0b~0nIBxXYi_1346513465eusmtrp10; Wed, 9 Apr 2025 09:30:31 +0000 (GMT) X-AuditID: cbfec7f5-e59c770000004fad-ef-67f63e3727a4 Received: from eusmtip2.samsung.com ( [203.254.199.222]) by eusmgms1.samsung.com (EUCPMTA) with SMTP id C4.35.19920.73E36F76; Wed, 9 Apr 2025 10:30:31 +0100 (BST) Received: from AMDC4942.home (unknown [106.210.136.40]) by eusmtip2.samsung.com (KnoxPortal) with ESMTPA id 20250409093030eusmtip2d8cd87a82f5916eb2fc3e94379087b87~0nIBHVz3h2948829488eusmtip2F; Wed, 9 Apr 2025 09:30:30 +0000 (GMT) From: Michal Wilczynski To: robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, drew@pdp7.com, guoren@kernel.org, wefu@redhat.com, ulf.hansson@linaro.org, p.zabel@pengutronix.de, m.szyprowski@samsung.com Cc: linux-kernel@vger.kernel.org, linux-riscv@lists.infradead.org, linux-pm@vger.kernel.org, Michal Wilczynski Subject: [PATCH v1 1/2] dt-bindings: firmware: thead,th1520: Add clocks and resets Date: Wed, 9 Apr 2025 11:30:24 +0200 Message-Id: <20250409093025.2917087-2-m.wilczynski@samsung.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20250409093025.2917087-1-m.wilczynski@samsung.com> MIME-Version: 1.0 X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFtrFKsWRmVeSWpSXmKPExsWy7djPc7rmdt/SDaZ3mlus2XuOyeLepS1M Fi/2NrJYvJx1j83i8q45bBafe48wWmz73MJmsfbIXXaL9V/nM1ncvXeCxeL/nh3sFsfXhlu0 7J/C4sDrsWlVJ5vHnWt72Dw2L6n3aFl7jMmj/6+Bx/t9V9k8+rasYvT4vEkugCOKyyYlNSez LLVI3y6BK+PU2W72ggUiFbM+XWVvYDzE38XIwSEhYCJx9YFHFyMXh5DACkaJ3vn7WbsYOYGc L4wSbRv4IRKfGSV2zGtmA0mANHz73M4OkVjOKLHk9TQo5w2jxOPFi9lBqtgEjCQeLJ/PCpIQ EdjLKNF56gMziMMs0M0osXbbDVaQ5cICIRJPPvKCNLAIqEqcWXMWbAWvgL3EpVkTWCDWyUvs P3iWGcTmFHCQONRzgh2iRlDi5MwnYDXMQDXNW2eDzZcQ+MIhMWHZNyaIZheJeZPuskLYwhKv jm9hh7BlJE5P7oFakC/xYOsnZgi7RmJnz3Eo21rizrlfbCB3MgtoSqzfpQ8RdpTofL2JFRJ2 fBI33gpCnMAnMWnbdGaIMK9ER5sQRLWaxNSeXril51ZsgzrMQ2LDt5esExgVZyF5ZhaSZ2Yh 7F3AyLyKUTy1tDg3PbXYOC+1XK84Mbe4NC9dLzk/dxMjMHmd/nf86w7GFa8+6h1iZOJgPMQo wcGsJML7duKXdCHelMTKqtSi/Pii0pzU4kOM0hwsSuK8i/a3pgsJpCeWpGanphakFsFkmTg4 pRqYJL5PlVP4cv2imNf5YObiyza+sTxsxi3CZ/wk1fcJrUlZXXdvrlqrfaRdLGdLQMuz2JS+ l83e8edf1V7vtrLptDnMxtfGfj/DaPqzjTPiGmr9C1XudRjVFqxnPhI3obHs1v0febrzpgmf kbi4pDpeO8vBMtjsJWf9O745/Iu9PNpkmP8rZ/zKTGd0MLp9uzH6hKVBruPdpdskpssKRK54 p9y6dseNypmGhx9/m9ZcN8er8Pcv26f6RyzF1nJtf1Q7dc8m5xTnwrlCezU3f1edq9Pf+Nt1 4s2lqrM25jMLqv4JnybW8OprgqRn9OpjXud0f3/59OYyZ9H9n+2hvx5Pie68dJiRr2XLYoZY 08dKLMUZiYZazEXFiQBQW9lezQMAAA== X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFlrNIsWRmVeSWpSXmKPExsVy+t/xe7rmdt/SDRZcYbNYs/cck8W9S1uY LF7sbWSxeDnrHpvF5V1z2Cw+9x5htNj2uYXNYu2Ru+wW67/OZ7K4e+8Ei8X/PTvYLY6vDbdo 2T+FxYHXY9OqTjaPO9f2sHlsXlLv0bL2GJNH/18Dj/f7rrJ59G1ZxejxeZNcAEeUnk1RfmlJ qkJGfnGJrVK0oYWRnqGlhZ6RiaWeobF5rJWRqZK+nU1Kak5mWWqRvl2CXsaps93sBQtEKmZ9 usrewHiIv4uRk0NCwETi2+d29i5GLg4hgaWMEief/2WGSMhIXOt+yQJhC0v8udbFBlH0ilHi yLOljCAJNgEjiQfL57OC2CICJxkl7r6qAyliFuhnlJj68QpYQlggSOLChSNgU1kEVCXOrDnL BmLzCthLXJo1AWqDvMT+g2fBajgFHCQO9ZxgB7GFQGrerGGCqBeUODnzCVg9M1B989bZzBMY BWYhSc1CklrAyLSKUSS1tDg3PbfYUK84Mbe4NC9dLzk/dxMjMNa2Hfu5eQfjvFcf9Q4xMnEw HmKU4GBWEuF9O/FLuhBvSmJlVWpRfnxRaU5q8SFGU6C7JzJLiSbnA6M9ryTe0MzA1NDEzNLA 1NLMWEmc1+3y+TQhgfTEktTs1NSC1CKYPiYOTqkGJi+V5I18Wgbr9x7VnnjP76C24QaFa99T Rebdz+fKa3XQW7jd76vGM8XeLSX66zcfil7smzzzw7+lX3fMll1RPftlj+xXmZiwDccaVmWw TJ27SFd1143Ppx7fqintKHjLK+M8IfQZw63+DS/Levjn8sdfv3eedy+rZolP658bhXnbIjU+ 5tvclHcrFdWWMvsgd8s/+qUXb2HJyhnsm1ZFiFzdYnHa9503n9yGUsPbK3ovimyWOGRvlNQd afVBevnGyTc+L5seor2je7FAcPqxmbOvHcxjXXX6xaKsHJtlRhc0slWqLaWv12jI7+zwqXwQ O02Iz3CHro5frun+TJE76QlHrNcvKP7//bDb2YqG70osxRmJhlrMRcWJAPkESq8+AwAA X-CMS-MailID: 20250409093031eucas1p2222e9dc4d354e9b66b7183922c0fb3cf X-Msg-Generator: CA X-RootMTR: 20250409093031eucas1p2222e9dc4d354e9b66b7183922c0fb3cf X-EPHeader: CA CMS-TYPE: 201P X-CMS-RootMailID: 20250409093031eucas1p2222e9dc4d354e9b66b7183922c0fb3cf References: <20250409093025.2917087-1-m.wilczynski@samsung.com> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20250409_023037_246199_1F95C01F X-CRM114-Status: GOOD ( 12.54 ) X-BeenThere: linux-riscv@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-riscv" Errors-To: linux-riscv-bounces+linux-riscv=archiver.kernel.org@lists.infradead.org Prepare for handling GPU clock and reset sequencing through a generic power domain by adding clock and reset properties to the TH1520 AON firmware bindings. The T-HEAD TH1520 GPU requires coordinated management of two clocks (core and sys) and two resets (GPU and GPU CLKGEN). Due to SoC-specific requirements, the CLKGEN reset must be carefully managed alongside clock enables to ensure proper GPU operation, as discussed on the mailing list [1]. Since the coordination is now handled through a power domain, only the programmable clocks (core and sys) are exposed. The GPU MEM clock is ignored, as it is not controllable on the TH1520 SoC. This approach follows upstream maintainers' recommendations [1] to avoid SoC-specific details leaking into the GPU driver or clock/reset frameworks directly. [1] - https://lore.kernel.org/all/38d9650fc11a674c8b689d6bab937acf@kernel.org/ Signed-off-by: Michal Wilczynski --- .../bindings/firmware/thead,th1520-aon.yaml | 28 +++++++++++++++++++ 1 file changed, 28 insertions(+) diff --git a/Documentation/devicetree/bindings/firmware/thead,th1520-aon.yaml b/Documentation/devicetree/bindings/firmware/thead,th1520-aon.yaml index bbc183200400..8075874bcd6b 100644 --- a/Documentation/devicetree/bindings/firmware/thead,th1520-aon.yaml +++ b/Documentation/devicetree/bindings/firmware/thead,th1520-aon.yaml @@ -25,6 +25,16 @@ properties: compatible: const: thead,th1520-aon + clocks: + items: + - description: GPU core clock + - description: GPU sys clock + + clock-names: + items: + - const: gpu-core + - const: gpu-sys + mboxes: maxItems: 1 @@ -32,13 +42,27 @@ properties: items: - const: aon + resets: + items: + - description: GPU reset + - description: GPU CLKGEN reset + + reset-names: + items: + - const: gpu + - const: gpu-clkgen + "#power-domain-cells": const: 1 required: - compatible + - clocks + - clock-names - mboxes - mbox-names + - resets + - reset-names - "#power-domain-cells" additionalProperties: false @@ -47,7 +71,11 @@ examples: - | aon: aon { compatible = "thead,th1520-aon"; + clocks = <&clk_vo 0>, <&clk_vo 1>; + clock-names = "gpu-core", "gpu-sys"; mboxes = <&mbox_910t 1>; mbox-names = "aon"; + resets = <&rst 0>, <&rst 1>; + reset-names = "gpu", "gpu-clkgen"; #power-domain-cells = <1>; }; From patchwork Wed Apr 9 09:30:25 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Michal Wilczynski X-Patchwork-Id: 14044373 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id E323EC36002 for ; Wed, 9 Apr 2025 09:31:05 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:References:MIME-Version:In-Reply-To: Message-Id:Date:Subject:Cc:To:From:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; 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Wed, 9 Apr 2025 09:30:31 +0000 (GMT) Received: from eusmgms2.samsung.com (unknown [182.198.249.180]) by eusmtrp2.samsung.com (KnoxPortal) with ESMTP id 20250409093031eusmtrp2451d5156809499af4eb9147d35d3dec8~0nICcicCv2888728887eusmtrp2W; Wed, 9 Apr 2025 09:30:31 +0000 (GMT) X-AuditID: cbfec7f4-c0df970000004fb9-4b-67f63e38fa6b Received: from eusmtip2.samsung.com ( [203.254.199.222]) by eusmgms2.samsung.com (EUCPMTA) with SMTP id D3.2D.19654.73E36F76; Wed, 9 Apr 2025 10:30:31 +0100 (BST) Received: from AMDC4942.home (unknown [106.210.136.40]) by eusmtip2.samsung.com (KnoxPortal) with ESMTPA id 20250409093031eusmtip2971b7ac4857a25cc513aa322db744f80~0nIBvcpd12903329033eusmtip2G; Wed, 9 Apr 2025 09:30:31 +0000 (GMT) From: Michal Wilczynski To: robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, drew@pdp7.com, guoren@kernel.org, wefu@redhat.com, ulf.hansson@linaro.org, p.zabel@pengutronix.de, m.szyprowski@samsung.com Cc: linux-kernel@vger.kernel.org, linux-riscv@lists.infradead.org, linux-pm@vger.kernel.org, Michal Wilczynski Subject: [PATCH v1 2/2] pmdomain: thead: Add GPU-specific clock and reset handling for TH1520 Date: Wed, 9 Apr 2025 11:30:25 +0200 Message-Id: <20250409093025.2917087-3-m.wilczynski@samsung.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20250409093025.2917087-1-m.wilczynski@samsung.com> MIME-Version: 1.0 X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFtrDKsWRmVeSWpSXmKPExsWy7djPc7oWdt/SDXYuFrJYs/cck8W9S1uY LF7sbWSxeDnrHpvF5V1z2Cw+9x5htNj2uYXNYu2Ru+wW67/OZ7K4e+8Ei8X/PTvYLY6vDbdo 2T+FxYHXY9OqTjaPO9f2sHlsXlLv0bL2GJNH/18Dj/f7rrJ59G1ZxejxeZNcAEcUl01Kak5m WWqRvl0CV8b0e2vZCzbpVjxfVdbA+Ey1i5GTQ0LARGJxw2TmLkYuDiGBFYwS99b/Y4dwvjBK dHTtYYJwPjNKHJl8lBWmZdbSWVAtyxklHiyZxAjhvGGUuP5xNztIFZuAkcSD5fNZQRIiAnsZ JTpPfQBrYRboZpRYu+0G2CxhgXiJO/Mns4DYLAKqEt/2bWUGsXkF7CVO9LQzQuyTl9h/8CxY nFPAQeJQzwl2iBpBiZMzn4D1MgPVNG+dDbZAQuAHh8Th5zfYIJpdJG5M62SGsIUlXh3fwg5h y0j83zmfCcLOl3iw9RNUTY3Ezp7jULa1xJ1zv4DmcAAt0JRYv0sfIuwoMf/xDBaQsIQAn8SN t4IQJ/BJTNo2nRkizCvR0SYEUa0mMbWnF27puRXboJZ6SBx+ep5tAqPiLCTPzELyzCyEvQsY mVcxiqeWFuempxYb5aWW6xUn5haX5qXrJefnbmIEJrDT/45/2cG4/NVHvUOMTByMhxglOJiV RHjfTvySLsSbklhZlVqUH19UmpNafIhRmoNFSZx30f7WdCGB9MSS1OzU1ILUIpgsEwenVAMT Y/+XDfs8zocwTVWzFMsrPjU97dfDkvNf879aMX48dyo6u/FZQaXcybrcSAfP1SwTxdatNrqn axCxVHdBptetNUwmu5kyRYISnqvc+81arvtztfDiMM/dr3c8VVVOY5/a8fndv+QJqcohSdmq MlIXvvGqpp+Nueh98smDO3oCCVpLsm9ynNoarpahcXaK1OkdUQGzGhgyIjfxb9Zy32GcHfml pmx3RUbtNHaxb04su35LdRYp1nO8cjr279mNc7Xh4cnsP+1c1ddlmhV8LLpYzM60UPgQp61F 2aOkuxw1i7M6QrZf+3RZ47T0Mtm7uyes4OcLrz0bojbFdKrc+ThfmwKrovWLFxd1aM88t1yJ pTgj0VCLuag4EQCfGyIgzwMAAA== X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFlrFIsWRmVeSWpSXmKPExsVy+t/xe7rmdt/SDbp/GVms2XuOyeLepS1M Fi/2NrJYvJx1j83i8q45bBafe48wWmz73MJmsfbIXXaL9V/nM1ncvXeCxeL/nh3sFsfXhlu0 7J/C4sDrsWlVJ5vHnWt72Dw2L6n3aFl7jMmj/6+Bx/t9V9k8+rasYvT4vEkugCNKz6Yov7Qk VSEjv7jEVina0MJIz9DSQs/IxFLP0Ng81srIVEnfziYlNSezLLVI3y5BL2P6vbXsBZt0K56v KmtgfKbaxcjJISFgIjFr6SzmLkYuDiGBpYwSV5Y/ZIJIyEhc637JAmELS/y51sUGUfSKUWLO 8d/sIAk2ASOJB8vns4LYIgInGSXuvqoDKWIW6GeUmPrxClhCWCBW4mrzb0YQm0VAVeLbvq3M IDavgL3EiZ52RogN8hL7D54Fi3MKOEgc6jkBtkAIqObSmzVMEPWCEidnPgG7iBmovnnrbOYJ jAKzkKRmIUktYGRaxSiSWlqcm55bbKRXnJhbXJqXrpecn7uJERhp24793LKDceWrj3qHGJk4 GA8xSnAwK4nwvp34JV2INyWxsiq1KD++qDQntfgQoynQ3ROZpUST84GxnlcSb2hmYGpoYmZp YGppZqwkzst25XyakEB6YklqdmpqQWoRTB8TB6dUA1PH1NN7O7NauScZ7J++2OL+Fx0f9TuX puSsmWpzNnX6zAmB3890aPG58r3vYm6o1T1r1unik3h9yyodS8aPmTned0zUlV8/YjqdtuyU Gesil2vuNnlO20NnisWJJrDMcdO/e1dqDfdRgadN23jUbFtzjoRdm97BftpQd+/5tSfc33zP zhc8Z2u0Rt636U3837RXPy53GJtWL+/LcCl0+W1nc3fDNqUVNZ6NH87xPYn6K1f/NiS4UtnA xbN5guCcs4WFAR84Fr7fZ7Lh0D2ZN/c3W7nXZ7/fczV/wye5efPMGfOe6pkIXUrlq3s3a/Pn 6d8ZbrbxrBXs87pQuiVIdUW7H+/tp7GOZ5q7Ljy89UiJpTgj0VCLuag4EQB6y0gPPQMAAA== X-CMS-MailID: 20250409093031eucas1p1ee277da31b7de9a16f6b7345df6a89ab X-Msg-Generator: CA X-RootMTR: 20250409093031eucas1p1ee277da31b7de9a16f6b7345df6a89ab X-EPHeader: CA CMS-TYPE: 201P X-CMS-RootMailID: 20250409093031eucas1p1ee277da31b7de9a16f6b7345df6a89ab References: <20250409093025.2917087-1-m.wilczynski@samsung.com> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20250409_023037_246310_0856F373 X-CRM114-Status: GOOD ( 22.21 ) X-BeenThere: linux-riscv@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-riscv" Errors-To: linux-riscv-bounces+linux-riscv=archiver.kernel.org@lists.infradead.org Extend the TH1520 power domain driver to manage GPU related clocks and resets via generic PM domain start/stop callbacks. The TH1520 GPU requires a special sequence to correctly initialize: - Enable the GPU clocks - Deassert the GPU clkgen reset - Delay for a few cycles to satisfy hardware requirements - Deassert the GPU core reset This sequence is SoC-specific and needs to be abstracted away from the Imagination GPU driver, which expects a standard single reset line. Following discussions with kernel maintainers, this logic is placed inside a PM domain instead of polluting the clock or reset frameworks, or the GPU driver itself [1]. Managing this inside a generic power domain allows better coordination of clocks, resets, and power state, and aligns with the direction of treating PM domains as SoC-specific "power management drivers". [1] - https://lore.kernel.org/all/CAPDyKFqsJaTrF0tBSY-TjpqdVt5=6aPQHYfnDebtphfRZSU=-Q@mail.gmail.com/ Signed-off-by: Michal Wilczynski --- drivers/pmdomain/thead/th1520-pm-domains.c | 119 +++++++++++++++++++++ 1 file changed, 119 insertions(+) diff --git a/drivers/pmdomain/thead/th1520-pm-domains.c b/drivers/pmdomain/thead/th1520-pm-domains.c index f702e20306f4..aa85c3954c39 100644 --- a/drivers/pmdomain/thead/th1520-pm-domains.c +++ b/drivers/pmdomain/thead/th1520-pm-domains.c @@ -5,17 +5,29 @@ * Author: Michal Wilczynski */ +#include +#include #include #include #include #include +#include #include +#define TH1520_GPU_RESET_IDX 0 +#define TH1520_GPU_CLKGEN_RESET_IDX 1 + struct th1520_power_domain { struct th1520_aon_chan *aon_chan; struct generic_pm_domain genpd; u32 rsrc; + + struct clk_bulk_data *clks; + int num_clks; + struct reset_control_bulk_data *resets; + int num_resets; + }; struct th1520_power_info { @@ -61,6 +73,99 @@ static int th1520_pd_power_off(struct generic_pm_domain *domain) return th1520_aon_power_update(pd->aon_chan, pd->rsrc, false); } +static int th1520_gpu_init_clocks(struct device *dev, + struct th1520_power_domain *pd) +{ + static const char *const clk_names[] = { "gpu-core", "gpu-sys" }; + int i, ret; + + pd->num_clks = ARRAY_SIZE(clk_names); + pd->clks = devm_kcalloc(dev, pd->num_clks, sizeof(*pd->clks), GFP_KERNEL); + if (!pd->clks) + return -ENOMEM; + + for (i = 0; i < pd->num_clks; i++) + pd->clks[i].id = clk_names[i]; + + ret = devm_clk_bulk_get(dev, pd->num_clks, pd->clks); + if (ret) + return dev_err_probe(dev, ret, "Failed to get GPU clocks\n"); + + return 0; +} + +static int th1520_gpu_init_resets(struct device *dev, + struct th1520_power_domain *pd) +{ + static const char *const reset_names[] = { "gpu", "gpu-clkgen" }; + int i, ret; + + pd->num_resets = ARRAY_SIZE(reset_names); + pd->resets = devm_kcalloc(dev, pd->num_resets, sizeof(*pd->resets), + GFP_KERNEL); + if (!pd->resets) + return -ENOMEM; + + for (i = 0; i < pd->num_resets; i++) + pd->resets[i].id = reset_names[i]; + + ret = devm_reset_control_bulk_get_exclusive(dev, pd->num_resets, + pd->resets); + if (ret) + return dev_err_probe(dev, ret, "Failed to get GPU resets\n"); + + return 0; +} + +static int th1520_gpu_domain_start(struct device *dev) +{ + struct generic_pm_domain *genpd = pd_to_genpd(dev->pm_domain); + struct th1520_power_domain *pd = to_th1520_power_domain(genpd); + int ret; + + ret = clk_bulk_prepare_enable(pd->num_clks, pd->clks); + if (ret) + return ret; + + ret = reset_control_deassert(pd->resets[TH1520_GPU_CLKGEN_RESET_IDX].rstc); + if (ret) + goto err_disable_clks; + + /* + * According to the hardware manual, a delay of at least 32 clock + * cycles is required between de-asserting the clkgen reset and + * de-asserting the GPU reset. Assuming a worst-case scenario with + * a very high GPU clock frequency, a delay of 1 microsecond is + * sufficient to ensure this requirement is met across all + * feasible GPU clock speeds. + */ + udelay(1); + + ret = reset_control_deassert(pd->resets[TH1520_GPU_RESET_IDX].rstc); + if (ret) + goto err_assert_clkgen; + + return 0; + +err_assert_clkgen: + reset_control_assert(pd->resets[TH1520_GPU_CLKGEN_RESET_IDX].rstc); +err_disable_clks: + clk_bulk_disable_unprepare(pd->num_clks, pd->clks); + return ret; +} + +static int th1520_gpu_domain_stop(struct device *dev) +{ + struct generic_pm_domain *genpd = pd_to_genpd(dev->pm_domain); + struct th1520_power_domain *pd = to_th1520_power_domain(genpd); + + reset_control_assert(pd->resets[TH1520_GPU_RESET_IDX].rstc); + reset_control_assert(pd->resets[TH1520_GPU_CLKGEN_RESET_IDX].rstc); + clk_bulk_disable_unprepare(pd->num_clks, pd->clks); + + return 0; +} + static struct generic_pm_domain *th1520_pd_xlate(const struct of_phandle_args *spec, void *data) { @@ -99,6 +204,20 @@ th1520_add_pm_domain(struct device *dev, const struct th1520_power_info *pi) pd->genpd.power_off = th1520_pd_power_off; pd->genpd.name = pi->name; + /* there are special callbacks for the GPU */ + if (pi == &th1520_pd_ranges[TH1520_GPU_PD]) { + ret = th1520_gpu_init_clocks(dev, pd); + if (ret) + return ERR_PTR(ret); + + ret = th1520_gpu_init_resets(dev, pd); + if (ret) + return ERR_PTR(ret); + + pd->genpd.dev_ops.start = th1520_gpu_domain_start; + pd->genpd.dev_ops.stop = th1520_gpu_domain_stop; + } + ret = pm_genpd_init(&pd->genpd, NULL, true); if (ret) return ERR_PTR(ret);