From patchwork Fri Mar 22 00:58:45 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Annaliese McDermond X-Patchwork-Id: 10864767 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 1450E922 for ; Fri, 22 Mar 2019 01:01:02 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id D2A022A4F4 for ; Fri, 22 Mar 2019 01:01:01 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id B5E062A504; Fri, 22 Mar 2019 01:01:01 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-2.9 required=2.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,MAILING_LIST_MULTI,RCVD_IN_DNSWL_NONE autolearn=ham version=3.3.1 Received: from alsa0.perex.cz (alsa0.perex.cz [77.48.224.243]) (using TLSv1.2 with cipher DHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.wl.linuxfoundation.org (Postfix) with ESMTPS id C20B92A503 for ; Fri, 22 Mar 2019 01:00:59 +0000 (UTC) Received: from alsa1.perex.cz (alsa1.perex.cz [207.180.221.201]) (using TLSv1.2 with cipher AECDH-AES256-SHA (256/256 bits)) (No client certificate requested) by alsa0.perex.cz (Postfix) with ESMTPS id EE6B0953; Fri, 22 Mar 2019 02:00:07 +0100 (CET) DKIM-Filter: OpenDKIM Filter v2.11.0 alsa0.perex.cz EE6B0953 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=alsa-project.org; s=default; t=1553216458; bh=jAv5P3hvWGGX9aY7gKDaG6N3mzhC7RdUiMRhLPOw/cc=; h=From:To:Date:In-Reply-To:References:Cc:Subject:List-Id: List-Unsubscribe:List-Archive:List-Post:List-Help:List-Subscribe: From; b=szTFqEFEhXgPMqjQRjHAhOrsZut9aaCKZxk7G2xEbOKJ6YIYvgC9VK03pPm3ZsYNe bm6PG7GQ6NPFEhzRiOOtJ7M9sTpfC6VcbrkdFvHQl25w7dAXhSnYJ1UqrIEgAnEVJc ALXEBx70xX24X78NwoSDiue3yFnPXQqWKFsDR1NE= Received: from alsa1.perex.cz (localhost.localdomain [127.0.0.1]) by alsa1.perex.cz (Postfix) with ESMTP id 1C8C1F8076F; Fri, 22 Mar 2019 01:59:10 +0100 (CET) X-Original-To: alsa-devel@alsa-project.org Delivered-To: alsa-devel@alsa-project.org Received: by alsa1.perex.cz (Postfix, from userid 50401) id B0E60F896B7; Fri, 22 Mar 2019 01:59:07 +0100 (CET) Received: from smtp73.ord1d.emailsrvr.com (smtp73.ord1d.emailsrvr.com [184.106.54.73]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by alsa1.perex.cz (Postfix) with ESMTPS id 7DA4BF8968A for ; Fri, 22 Mar 2019 01:59:02 +0100 (CET) DKIM-Filter: OpenDKIM Filter v2.11.0 alsa1.perex.cz 7DA4BF8968A Received: from smtp18.relay.ord1d.emailsrvr.com (localhost [127.0.0.1]) by smtp18.relay.ord1d.emailsrvr.com (SMTP Server) with ESMTP id D6E38A0239; Thu, 21 Mar 2019 20:59:01 -0400 (EDT) X-SMTPDoctor-Processed: csmtpprox beta Received: from smtp18.relay.ord1d.emailsrvr.com (localhost [127.0.0.1]) by smtp18.relay.ord1d.emailsrvr.com (SMTP Server) with ESMTP id D2953A029F; Thu, 21 Mar 2019 20:59:01 -0400 (EDT) X-Auth-ID: mcdermj@xenotropic.com Received: by smtp18.relay.ord1d.emailsrvr.com (Authenticated sender: mcdermj-AT-xenotropic.com) with ESMTPSA id 182B6A0239; Thu, 21 Mar 2019 20:59:01 -0400 (EDT) X-Sender-Id: mcdermj@xenotropic.com Received: from commune.xenotropic.com (c-73-96-52-102.hsd1.or.comcast.net [73.96.52.102]) (using TLSv1.2 with cipher DHE-RSA-AES128-GCM-SHA256) by 0.0.0.0:25 (trex/5.7.12); Thu, 21 Mar 2019 20:59:01 -0400 From: Annaliese McDermond To: broonie@kernel.org, alsa-devel@alsa-project.org Date: Thu, 21 Mar 2019 17:58:45 -0700 Message-Id: <20190322005854.23360-2-nh6z@nh6z.net> X-Mailer: git-send-email 2.19.1 In-Reply-To: <20190322005854.23360-1-nh6z@nh6z.net> References: <20190322005854.23360-1-nh6z@nh6z.net> MIME-Version: 1.0 Cc: team@nwdigitalradio.com, Annaliese McDermond Subject: [alsa-devel] [PATCH v4 01/10] ASoC: tlv320aic32x4: Model PLL in CCF X-BeenThere: alsa-devel@alsa-project.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: "Alsa-devel mailing list for ALSA developers - http://www.alsa-project.org" List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: alsa-devel-bounces@alsa-project.org Sender: "Alsa-devel" X-Virus-Scanned: ClamAV using ClamSMTP Model and manage the on-board PLL as a component in the Core Clock Framework. This should allow us to do some more complex clock management and power control. Also, some of the on-board chip clocks can be exposed to the outside, and this change will make those clocks easier to consume by other parts of the kernel. Signed-off-by: Annaliese McDermond --- sound/soc/codecs/Kconfig | 1 + sound/soc/codecs/Makefile | 2 +- sound/soc/codecs/tlv320aic32x4-clk.c | 323 +++++++++++++++++++++++++++ sound/soc/codecs/tlv320aic32x4.c | 195 ++++++++-------- sound/soc/codecs/tlv320aic32x4.h | 5 + 5 files changed, 431 insertions(+), 95 deletions(-) diff --git a/sound/soc/codecs/Kconfig b/sound/soc/codecs/Kconfig index 05f16632296b..6e99320c79b8 100644 --- a/sound/soc/codecs/Kconfig +++ b/sound/soc/codecs/Kconfig @@ -1105,6 +1105,7 @@ config SND_SOC_TLV320AIC31XX config SND_SOC_TLV320AIC32X4 tristate + depends on COMMON_CLK config SND_SOC_TLV320AIC32X4_I2C tristate "Texas Instruments TLV320AIC32x4 audio CODECs - I2C" diff --git a/sound/soc/codecs/Makefile b/sound/soc/codecs/Makefile index a597de946027..aa7720a7a0aa 100644 --- a/sound/soc/codecs/Makefile +++ b/sound/soc/codecs/Makefile @@ -193,7 +193,7 @@ snd-soc-tlv320aic23-i2c-objs := tlv320aic23-i2c.o snd-soc-tlv320aic23-spi-objs := tlv320aic23-spi.o snd-soc-tlv320aic26-objs := tlv320aic26.o snd-soc-tlv320aic31xx-objs := tlv320aic31xx.o -snd-soc-tlv320aic32x4-objs := tlv320aic32x4.o +snd-soc-tlv320aic32x4-objs := tlv320aic32x4.o tlv320aic32x4-clk.o snd-soc-tlv320aic32x4-i2c-objs := tlv320aic32x4-i2c.o snd-soc-tlv320aic32x4-spi-objs := tlv320aic32x4-spi.o snd-soc-tlv320aic3x-objs := tlv320aic3x.o diff --git a/sound/soc/codecs/tlv320aic32x4-clk.c b/sound/soc/codecs/tlv320aic32x4-clk.c new file mode 100644 index 000000000000..5e495fc8d931 --- /dev/null +++ b/sound/soc/codecs/tlv320aic32x4-clk.c @@ -0,0 +1,323 @@ +/* SPDX-License-Identifier: GPL-2.0 + * + * Clock Tree for the Texas Instruments TLV320AIC32x4 + * + * Copyright 2019 Annaliese McDermond + * + * Author: Annaliese McDermond + */ + +#include +#include +#include +#include + +#include "tlv320aic32x4.h" + +#define to_clk_aic32x4(_hw) container_of(_hw, struct clk_aic32x4, hw) +struct clk_aic32x4 { + struct clk_hw hw; + struct device *dev; + struct regmap *regmap; + unsigned int reg; +}; + +/* + * struct clk_aic32x4_pll_muldiv - Multiplier/divider settings + * @p: Divider + * @r: first multiplier + * @j: integer part of second multiplier + * @d: decimal part of second multiplier + */ +struct clk_aic32x4_pll_muldiv { + u8 p; + u16 r; + u8 j; + u16 d; +}; + +struct aic32x4_clkdesc { + const char *name; + const char * const *parent_names; + unsigned int num_parents; + const struct clk_ops *ops; + unsigned int reg; +}; + +static int clk_aic32x4_pll_prepare(struct clk_hw *hw) +{ + struct clk_aic32x4 *pll = to_clk_aic32x4(hw); + + return regmap_update_bits(pll->regmap, AIC32X4_PLLPR, + AIC32X4_PLLEN, AIC32X4_PLLEN); +} + +static void clk_aic32x4_pll_unprepare(struct clk_hw *hw) +{ + struct clk_aic32x4 *pll = to_clk_aic32x4(hw); + + regmap_update_bits(pll->regmap, AIC32X4_PLLPR, + AIC32X4_PLLEN, 0); +} + +static int clk_aic32x4_pll_is_prepared(struct clk_hw *hw) +{ + struct clk_aic32x4 *pll = to_clk_aic32x4(hw); + + unsigned int val; + int ret; + + ret = regmap_read(pll->regmap, AIC32X4_PLLPR, &val); + if (ret < 0) + return ret; + + return !!(val & AIC32X4_PLLEN); +} + +static int clk_aic32x4_pll_get_muldiv(struct clk_aic32x4 *pll, + struct clk_aic32x4_pll_muldiv *settings) +{ + /* Change to use regmap_bulk_read? */ + unsigned int val; + int ret; + + ret = regmap_read(pll->regmap, AIC32X4_PLLPR, &val); + if (ret) + return ret; + settings->r = val & AIC32X4_PLL_R_MASK; + settings->p = (val & AIC32X4_PLL_P_MASK) >> AIC32X4_PLL_P_SHIFT; + + ret = regmap_read(pll->regmap, AIC32X4_PLLJ, &val); + if (ret < 0) + return ret; + settings->j = val; + + ret = regmap_read(pll->regmap, AIC32X4_PLLDMSB, &val); + if (ret < 0) + return ret; + settings->d = val << 8; + + ret = regmap_read(pll->regmap, AIC32X4_PLLDLSB, &val); + if (ret < 0) + return ret; + settings->d |= val; + + return 0; +} + +static int clk_aic32x4_pll_set_muldiv(struct clk_aic32x4 *pll, + struct clk_aic32x4_pll_muldiv *settings) +{ + int ret; + /* Change to use regmap_bulk_write for some if not all? */ + + ret = regmap_update_bits(pll->regmap, AIC32X4_PLLPR, + AIC32X4_PLL_R_MASK, settings->r); + if (ret < 0) + return ret; + + ret = regmap_update_bits(pll->regmap, AIC32X4_PLLPR, + AIC32X4_PLL_P_MASK, + settings->p << AIC32X4_PLL_P_SHIFT); + if (ret < 0) + return ret; + + ret = regmap_write(pll->regmap, AIC32X4_PLLJ, settings->j); + if (ret < 0) + return ret; + + ret = regmap_write(pll->regmap, AIC32X4_PLLDMSB, (settings->d >> 8)); + if (ret < 0) + return ret; + ret = regmap_write(pll->regmap, AIC32X4_PLLDLSB, (settings->d & 0xff)); + if (ret < 0) + return ret; + + return 0; +} + +static unsigned long clk_aic32x4_pll_calc_rate( + struct clk_aic32x4_pll_muldiv *settings, + unsigned long parent_rate) +{ + u64 rate; + /* + * We scale j by 10000 to account for the decimal part of P and divide + * it back out later. + */ + rate = (u64) parent_rate * settings->r * + ((settings->j * 10000) + settings->d); + + return (unsigned long) DIV_ROUND_UP_ULL(rate, settings->p * 10000); +} + +static int clk_aic32x4_pll_calc_muldiv(struct clk_aic32x4_pll_muldiv *settings, + unsigned long rate, unsigned long parent_rate) +{ + u64 multiplier; + + settings->p = parent_rate / AIC32X4_MAX_PLL_CLKIN + 1; + if (settings->p > 8) + return -1; + + /* + * We scale this figure by 10000 so that we can get the decimal part + * of the multiplier. This is because we can't do floating point + * math in the kernel. + */ + multiplier = (u64) rate * settings->p * 10000; + do_div(multiplier, parent_rate); + + /* + * J can't be over 64, so R can scale this. + * R can't be greater than 4. + */ + settings->r = ((u32) multiplier / 640000) + 1; + if (settings->r > 4) + return -1; + do_div(multiplier, settings->r); + + /* + * J can't be < 1. + */ + if (multiplier < 10000) + return -1; + + /* Figure out the integer part, J, and the fractional part, D. */ + settings->j = (u32) multiplier / 10000; + settings->d = (u32) multiplier % 10000; + + return 0; +} + +static unsigned long clk_aic32x4_pll_recalc_rate(struct clk_hw *hw, + unsigned long parent_rate) +{ + struct clk_aic32x4 *pll = to_clk_aic32x4(hw); + struct clk_aic32x4_pll_muldiv settings; + int ret; + + ret = clk_aic32x4_pll_get_muldiv(pll, &settings); + if (ret < 0) + return 0; + + return clk_aic32x4_pll_calc_rate(&settings, parent_rate); +} + +static long clk_aic32x4_pll_round_rate(struct clk_hw *hw, + unsigned long rate, + unsigned long *parent_rate) +{ + struct clk_aic32x4_pll_muldiv settings; + int ret; + + ret = clk_aic32x4_pll_calc_muldiv(&settings, rate, *parent_rate); + if (ret < 0) + return 0; + + return clk_aic32x4_pll_calc_rate(&settings, *parent_rate); +} + +static int clk_aic32x4_pll_set_rate(struct clk_hw *hw, + unsigned long rate, + unsigned long parent_rate) +{ + struct clk_aic32x4 *pll = to_clk_aic32x4(hw); + struct clk_aic32x4_pll_muldiv settings; + int ret; + + ret = clk_aic32x4_pll_calc_muldiv(&settings, rate, parent_rate); + if (ret < 0) + return -EINVAL; + + return clk_aic32x4_pll_set_muldiv(pll, &settings); +} + +static int clk_aic32x4_pll_set_parent(struct clk_hw *hw, u8 index) +{ + struct clk_aic32x4 *pll = to_clk_aic32x4(hw); + + return regmap_update_bits(pll->regmap, + AIC32X4_CLKMUX, + AIC32X4_PLL_CLKIN_MASK, + index << AIC32X4_PLL_CLKIN_SHIFT); +} + +static u8 clk_aic32x4_pll_get_parent(struct clk_hw *hw) +{ + struct clk_aic32x4 *pll = to_clk_aic32x4(hw); + unsigned int val; + + regmap_read(pll->regmap, AIC32X4_PLLPR, &val); + + return (val & AIC32X4_PLL_CLKIN_MASK) >> AIC32X4_PLL_CLKIN_SHIFT; +} + + +static const struct clk_ops aic32x4_pll_ops = { + .prepare = clk_aic32x4_pll_prepare, + .unprepare = clk_aic32x4_pll_unprepare, + .is_prepared = clk_aic32x4_pll_is_prepared, + .recalc_rate = clk_aic32x4_pll_recalc_rate, + .round_rate = clk_aic32x4_pll_round_rate, + .set_rate = clk_aic32x4_pll_set_rate, + .set_parent = clk_aic32x4_pll_set_parent, + .get_parent = clk_aic32x4_pll_get_parent, +}; + +static struct aic32x4_clkdesc aic32x4_clkdesc_array[] = { + { + .name = "pll", + .parent_names = + (const char* []) { "mclk", "bclk", "gpio", "din" }, + .num_parents = 4, + .ops = &aic32x4_pll_ops, + .reg = 0, + }, +}; + +static struct clk *aic32x4_register_clk(struct device *dev, + struct aic32x4_clkdesc *desc) +{ + struct clk_init_data init; + struct clk_aic32x4 *priv; + const char *devname = dev_name(dev); + + init.ops = desc->ops; + init.name = desc->name; + init.parent_names = desc->parent_names; + init.num_parents = desc->num_parents; + init.flags = 0; + + priv = devm_kzalloc(dev, sizeof(struct clk_aic32x4), GFP_KERNEL); + if (priv == NULL) + return (struct clk *) -ENOMEM; + + priv->dev = dev; + priv->hw.init = &init; + priv->regmap = dev_get_regmap(dev, NULL); + priv->reg = desc->reg; + + clk_hw_register_clkdev(&priv->hw, desc->name, devname); + return devm_clk_register(dev, &priv->hw); +} + +int aic32x4_register_clocks(struct device *dev, const char *mclk_name) +{ + int i; + + /* + * These lines are here to preserve the current functionality of + * the driver with regard to the DT. These should eventually be set + * by DT nodes so that the connections can be set up in configuration + * rather than code. + */ + aic32x4_clkdesc_array[0].parent_names = + (const char* []) { mclk_name, "bclk", "gpio", "din" }; + + for (i = 0; i < ARRAY_SIZE(aic32x4_clkdesc_array); ++i) + aic32x4_register_clk(dev, &aic32x4_clkdesc_array[i]); + + return 0; +} +EXPORT_SYMBOL_GPL(aic32x4_register_clocks); diff --git a/sound/soc/codecs/tlv320aic32x4.c b/sound/soc/codecs/tlv320aic32x4.c index 71a93fbc5971..7cf8c7cedfe1 100644 --- a/sound/soc/codecs/tlv320aic32x4.c +++ b/sound/soc/codecs/tlv320aic32x4.c @@ -14,7 +14,7 @@ * * This program is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. * * You should have received a copy of the GNU General Public License @@ -33,6 +33,7 @@ #include #include #include +#include #include #include @@ -49,9 +50,7 @@ struct aic32x4_rate_divs { u32 mclk; u32 rate; - u8 p_val; - u8 pll_j; - u16 pll_d; + unsigned long pll_rate; u16 dosr; u8 ndac; u8 mdac; @@ -71,6 +70,7 @@ struct aic32x4_priv { bool swapdacs; int rstn_gpio; struct clk *mclk; + const char *mclk_name; struct regulator *supply_ldo; struct regulator *supply_iov; @@ -309,34 +309,34 @@ static const struct snd_kcontrol_new aic32x4_snd_controls[] = { static const struct aic32x4_rate_divs aic32x4_divs[] = { /* 8k rate */ - {12000000, 8000, 1, 7, 6800, 768, 5, 3, 128, 5, 18, 24, 1, 1}, - {24000000, 8000, 2, 7, 6800, 768, 15, 1, 64, 45, 4, 24, 1, 1}, - {25000000, 8000, 2, 7, 3728, 768, 15, 1, 64, 45, 4, 24, 1, 1}, + { 12000000, 8000, 57120000, 768, 5, 3, 128, 5, 18, 24, 1, 1 }, + { 24000000, 8000, 57120000, 768, 15, 1, 64, 45, 4, 24, 1, 1 }, + { 25000000, 8000, 32620000, 768, 15, 1, 64, 45, 4, 24, 1, 1 }, /* 11.025k rate */ - {12000000, 11025, 1, 7, 5264, 512, 8, 2, 128, 8, 8, 16, 1, 1}, - {24000000, 11025, 2, 7, 5264, 512, 16, 1, 64, 32, 4, 16, 1, 1}, + { 12000000, 11025, 44217600, 512, 8, 2, 128, 8, 8, 16, 1, 1 }, + { 24000000, 11025, 44217600, 512, 16, 1, 64, 32, 4, 16, 1, 1 }, /* 16k rate */ - {12000000, 16000, 1, 7, 6800, 384, 5, 3, 128, 5, 9, 12, 1, 1}, - {24000000, 16000, 2, 7, 6800, 384, 15, 1, 64, 18, 5, 12, 1, 1}, - {25000000, 16000, 2, 7, 3728, 384, 15, 1, 64, 18, 5, 12, 1, 1}, + { 12000000, 16000, 57120000, 384, 5, 3, 128, 5, 9, 12, 1, 1 }, + { 24000000, 16000, 57120000, 384, 15, 1, 64, 18, 5, 12, 1, 1 }, + { 25000000, 16000, 32620000, 384, 15, 1, 64, 18, 5, 12, 1, 1 }, /* 22.05k rate */ - {12000000, 22050, 1, 7, 5264, 256, 4, 4, 128, 4, 8, 8, 1, 1}, - {24000000, 22050, 2, 7, 5264, 256, 16, 1, 64, 16, 4, 8, 1, 1}, - {25000000, 22050, 2, 7, 2253, 256, 16, 1, 64, 16, 4, 8, 1, 1}, + { 12000000, 22050, 44217600, 256, 4, 4, 128, 4, 8, 8, 1, 1 }, + { 24000000, 22050, 44217600, 256, 16, 1, 64, 16, 4, 8, 1, 1 }, + { 25000000, 22050, 19713750, 256, 16, 1, 64, 16, 4, 8, 1, 1 }, /* 32k rate */ - {12000000, 32000, 1, 7, 1680, 192, 2, 7, 64, 2, 21, 6, 1, 1}, - {24000000, 32000, 2, 7, 1680, 192, 7, 2, 64, 7, 6, 6, 1, 1}, + { 12000000, 32000, 14112000, 192, 2, 7, 64, 2, 21, 6, 1, 1 }, + { 24000000, 32000, 14112000, 192, 7, 2, 64, 7, 6, 6, 1, 1 }, /* 44.1k rate */ - {12000000, 44100, 1, 7, 5264, 128, 2, 8, 128, 2, 8, 4, 1, 1}, - {24000000, 44100, 2, 7, 5264, 128, 8, 2, 64, 8, 4, 4, 1, 1}, - {25000000, 44100, 2, 7, 2253, 128, 8, 2, 64, 8, 4, 4, 1, 1}, + { 12000000, 44100, 44217600, 128, 2, 8, 128, 2, 8, 4, 1, 1 }, + { 24000000, 44100, 44217600, 128, 8, 2, 64, 8, 4, 4, 1, 1 }, + { 25000000, 44100, 19713750, 128, 8, 2, 64, 8, 4, 4, 1, 1 }, /* 48k rate */ - {12000000, 48000, 1, 8, 1920, 128, 2, 8, 128, 2, 8, 4, 1, 1}, - {24000000, 48000, 2, 8, 1920, 128, 8, 2, 64, 8, 4, 4, 1, 1}, - {25000000, 48000, 2, 7, 8643, 128, 8, 2, 64, 8, 4, 4, 1, 1}, + { 12000000, 48000, 18432000, 128, 2, 8, 128, 2, 8, 4, 1, 1 }, + { 24000000, 48000, 18432000, 128, 8, 2, 64, 8, 4, 4, 1, 1 }, + { 25000000, 48000, 75626250, 128, 8, 2, 64, 8, 4, 4, 1, 1 }, /* 96k rate */ - {25000000, 96000, 2, 7, 8643, 64, 4, 4, 64, 4, 4, 1, 1, 9}, + { 25000000, 96000, 75626250, 64, 4, 4, 64, 4, 4, 1, 1, 9 }, }; static const struct snd_kcontrol_new hpl_output_mixer_controls[] = { @@ -393,7 +393,7 @@ static const struct snd_kcontrol_new in3r_to_lmixer_controls[] = { SOC_DAPM_ENUM("IN3_R L- Switch", in3r_lpga_n_enum), }; -/* Right mixer pins */ +/* Right mixer pins */ static SOC_ENUM_SINGLE_DECL(in1r_rpga_p_enum, AIC32X4_RMICPGAPIN, 6, resistor_text); static SOC_ENUM_SINGLE_DECL(in2r_rpga_p_enum, AIC32X4_RMICPGAPIN, 4, resistor_text); static SOC_ENUM_SINGLE_DECL(in3r_rpga_p_enum, AIC32X4_RMICPGAPIN, 2, resistor_text); @@ -595,7 +595,7 @@ static const struct snd_soc_dapm_route aic32x4_dapm_routes[] = { static const struct regmap_range_cfg aic32x4_regmap_pages[] = { { .selector_reg = 0, - .selector_mask = 0xff, + .selector_mask = 0xff, .window_start = 0, .window_len = 128, .range_min = 0, @@ -616,7 +616,7 @@ static inline int aic32x4_get_divs(int mclk, int rate) for (i = 0; i < ARRAY_SIZE(aic32x4_divs); i++) { if ((aic32x4_divs[i].rate == rate) - && (aic32x4_divs[i].mclk == mclk)) { + && (aic32x4_divs[i].mclk == mclk)) { return i; } } @@ -688,12 +688,12 @@ static int aic32x4_set_dai_fmt(struct snd_soc_dai *codec_dai, unsigned int fmt) } snd_soc_component_update_bits(component, AIC32X4_IFACE1, - AIC32X4_IFACE1_DATATYPE_MASK | - AIC32X4_IFACE1_MASTER_MASK, iface_reg_1); + AIC32X4_IFACE1_DATATYPE_MASK | + AIC32X4_IFACE1_MASTER_MASK, iface_reg_1); snd_soc_component_update_bits(component, AIC32X4_IFACE2, - AIC32X4_DATA_OFFSET_MASK, iface_reg_2); + AIC32X4_DATA_OFFSET_MASK, iface_reg_2); snd_soc_component_update_bits(component, AIC32X4_IFACE3, - AIC32X4_BCLKINV_MASK, iface_reg_3); + AIC32X4_BCLKINV_MASK, iface_reg_3); return 0; } @@ -715,6 +715,11 @@ static int aic32x4_setup_clocks(struct snd_soc_component *component, unsigned int parent_rate) { int i; + int ret; + + struct clk_bulk_data clocks[] = { + { .id = "pll" }, + }; i = aic32x4_get_divs(parent_rate, sample_rate); if (i < 0) { @@ -722,39 +727,29 @@ static int aic32x4_setup_clocks(struct snd_soc_component *component, return i; } + ret = devm_clk_bulk_get(component->dev, ARRAY_SIZE(clocks), clocks); + if (ret) + return ret; + + clk_set_rate(clocks[0].clk, sample_rate); + aic32x4_set_processing_blocks(component, aic32x4_divs[i].r_block, aic32x4_divs[i].p_block); - /* MCLK as PLL_CLKIN */ - snd_soc_component_update_bits(component, AIC32X4_CLKMUX, AIC32X4_PLL_CLKIN_MASK, - AIC32X4_PLL_CLKIN_MCLK << AIC32X4_PLL_CLKIN_SHIFT); /* PLL as CODEC_CLKIN */ - snd_soc_component_update_bits(component, AIC32X4_CLKMUX, AIC32X4_CODEC_CLKIN_MASK, - AIC32X4_CODEC_CLKIN_PLL << AIC32X4_CODEC_CLKIN_SHIFT); + snd_soc_component_update_bits(component, AIC32X4_CLKMUX, + AIC32X4_CODEC_CLKIN_MASK, + AIC32X4_CODEC_CLKIN_PLL << AIC32X4_CODEC_CLKIN_SHIFT); /* DAC_MOD_CLK as BDIV_CLKIN */ snd_soc_component_update_bits(component, AIC32X4_IFACE3, AIC32X4_BDIVCLK_MASK, - AIC32X4_DACMOD2BCLK << AIC32X4_BDIVCLK_SHIFT); - - /* We will fix R value to 1 and will make P & J=K.D as variable */ - snd_soc_component_update_bits(component, AIC32X4_PLLPR, AIC32X4_PLL_R_MASK, 0x01); - - /* PLL P value */ - snd_soc_component_update_bits(component, AIC32X4_PLLPR, AIC32X4_PLL_P_MASK, - aic32x4_divs[i].p_val << AIC32X4_PLL_P_SHIFT); - - /* PLL J value */ - snd_soc_component_write(component, AIC32X4_PLLJ, aic32x4_divs[i].pll_j); - - /* PLL D value */ - snd_soc_component_write(component, AIC32X4_PLLDMSB, (aic32x4_divs[i].pll_d >> 8)); - snd_soc_component_write(component, AIC32X4_PLLDLSB, (aic32x4_divs[i].pll_d & 0xff)); + AIC32X4_DACMOD2BCLK << AIC32X4_BDIVCLK_SHIFT); /* NDAC divider value */ snd_soc_component_update_bits(component, AIC32X4_NDAC, - AIC32X4_NDAC_MASK, aic32x4_divs[i].ndac); + AIC32X4_NDAC_MASK, aic32x4_divs[i].ndac); /* MDAC divider value */ snd_soc_component_update_bits(component, AIC32X4_MDAC, - AIC32X4_MDAC_MASK, aic32x4_divs[i].mdac); + AIC32X4_MDAC_MASK, aic32x4_divs[i].mdac); /* DOSR MSB & LSB values */ snd_soc_component_write(component, AIC32X4_DOSRMSB, aic32x4_divs[i].dosr >> 8); @@ -762,18 +757,18 @@ static int aic32x4_setup_clocks(struct snd_soc_component *component, /* NADC divider value */ snd_soc_component_update_bits(component, AIC32X4_NADC, - AIC32X4_NADC_MASK, aic32x4_divs[i].nadc); + AIC32X4_NADC_MASK, aic32x4_divs[i].nadc); /* MADC divider value */ snd_soc_component_update_bits(component, AIC32X4_MADC, - AIC32X4_MADC_MASK, aic32x4_divs[i].madc); + AIC32X4_MADC_MASK, aic32x4_divs[i].madc); /* AOSR value */ snd_soc_component_write(component, AIC32X4_AOSR, aic32x4_divs[i].aosr); /* BCLK N divider */ snd_soc_component_update_bits(component, AIC32X4_BCLKN, - AIC32X4_BCLK_MASK, aic32x4_divs[i].blck_N); + AIC32X4_BCLK_MASK, aic32x4_divs[i].blck_N); return 0; } @@ -792,23 +787,23 @@ static int aic32x4_hw_params(struct snd_pcm_substream *substream, switch (params_width(params)) { case 16: iface1_reg |= (AIC32X4_WORD_LEN_16BITS << - AIC32X4_IFACE1_DATALEN_SHIFT); + AIC32X4_IFACE1_DATALEN_SHIFT); break; case 20: iface1_reg |= (AIC32X4_WORD_LEN_20BITS << - AIC32X4_IFACE1_DATALEN_SHIFT); + AIC32X4_IFACE1_DATALEN_SHIFT); break; case 24: iface1_reg |= (AIC32X4_WORD_LEN_24BITS << - AIC32X4_IFACE1_DATALEN_SHIFT); + AIC32X4_IFACE1_DATALEN_SHIFT); break; case 32: iface1_reg |= (AIC32X4_WORD_LEN_32BITS << - AIC32X4_IFACE1_DATALEN_SHIFT); + AIC32X4_IFACE1_DATALEN_SHIFT); break; } snd_soc_component_update_bits(component, AIC32X4_IFACE1, - AIC32X4_IFACE1_DATALEN_MASK, iface1_reg); + AIC32X4_IFACE1_DATALEN_MASK, iface1_reg); if (params_channels(params) == 1) { dacsetup_reg = AIC32X4_RDAC2LCHN | AIC32X4_LDAC2LCHN; @@ -819,7 +814,7 @@ static int aic32x4_hw_params(struct snd_pcm_substream *substream, dacsetup_reg = AIC32X4_LDAC2LCHN | AIC32X4_RDAC2RCHN; } snd_soc_component_update_bits(component, AIC32X4_DACSETUP, - AIC32X4_DAC_CHAN_MASK, dacsetup_reg); + AIC32X4_DAC_CHAN_MASK, dacsetup_reg); return 0; } @@ -829,7 +824,7 @@ static int aic32x4_mute(struct snd_soc_dai *dai, int mute) struct snd_soc_component *component = dai->component; snd_soc_component_update_bits(component, AIC32X4_DACMUTE, - AIC32X4_MUTEON, mute ? AIC32X4_MUTEON : 0); + AIC32X4_MUTEON, mute ? AIC32X4_MUTEON : 0); return 0; } @@ -851,27 +846,27 @@ static int aic32x4_set_bias_level(struct snd_soc_component *component, /* Switch on PLL */ snd_soc_component_update_bits(component, AIC32X4_PLLPR, - AIC32X4_PLLEN, AIC32X4_PLLEN); + AIC32X4_PLLEN, AIC32X4_PLLEN); /* Switch on NDAC Divider */ snd_soc_component_update_bits(component, AIC32X4_NDAC, - AIC32X4_NDACEN, AIC32X4_NDACEN); + AIC32X4_NDACEN, AIC32X4_NDACEN); /* Switch on MDAC Divider */ snd_soc_component_update_bits(component, AIC32X4_MDAC, - AIC32X4_MDACEN, AIC32X4_MDACEN); + AIC32X4_MDACEN, AIC32X4_MDACEN); /* Switch on NADC Divider */ snd_soc_component_update_bits(component, AIC32X4_NADC, - AIC32X4_NADCEN, AIC32X4_NADCEN); + AIC32X4_NADCEN, AIC32X4_NADCEN); /* Switch on MADC Divider */ snd_soc_component_update_bits(component, AIC32X4_MADC, - AIC32X4_MADCEN, AIC32X4_MADCEN); + AIC32X4_MADCEN, AIC32X4_MADCEN); /* Switch on BCLK_N Divider */ snd_soc_component_update_bits(component, AIC32X4_BCLKN, - AIC32X4_BCLKEN, AIC32X4_BCLKEN); + AIC32X4_BCLKEN, AIC32X4_BCLKEN); break; case SND_SOC_BIAS_PREPARE: break; @@ -882,27 +877,27 @@ static int aic32x4_set_bias_level(struct snd_soc_component *component, /* Switch off BCLK_N Divider */ snd_soc_component_update_bits(component, AIC32X4_BCLKN, - AIC32X4_BCLKEN, 0); + AIC32X4_BCLKEN, 0); /* Switch off MADC Divider */ snd_soc_component_update_bits(component, AIC32X4_MADC, - AIC32X4_MADCEN, 0); + AIC32X4_MADCEN, 0); /* Switch off NADC Divider */ snd_soc_component_update_bits(component, AIC32X4_NADC, - AIC32X4_NADCEN, 0); + AIC32X4_NADCEN, 0); /* Switch off MDAC Divider */ snd_soc_component_update_bits(component, AIC32X4_MDAC, - AIC32X4_MDACEN, 0); + AIC32X4_MDACEN, 0); /* Switch off NDAC Divider */ snd_soc_component_update_bits(component, AIC32X4_NDAC, - AIC32X4_NDACEN, 0); + AIC32X4_NDACEN, 0); /* Switch off PLL */ snd_soc_component_update_bits(component, AIC32X4_PLLPR, - AIC32X4_PLLEN, 0); + AIC32X4_PLLEN, 0); /* Switch off master clock */ clk_disable_unprepare(aic32x4->mclk); @@ -914,7 +909,7 @@ static int aic32x4_set_bias_level(struct snd_soc_component *component, } #define AIC32X4_RATES SNDRV_PCM_RATE_8000_96000 -#define AIC32X4_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S20_3LE \ +#define AIC32X4_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S20_3LE \ | SNDRV_PCM_FMTBIT_S24_3LE | SNDRV_PCM_FMTBIT_S32_LE) static const struct snd_soc_dai_ops aic32x4_ops = { @@ -927,17 +922,17 @@ static const struct snd_soc_dai_ops aic32x4_ops = { static struct snd_soc_dai_driver aic32x4_dai = { .name = "tlv320aic32x4-hifi", .playback = { - .stream_name = "Playback", - .channels_min = 1, - .channels_max = 2, - .rates = AIC32X4_RATES, - .formats = AIC32X4_FORMATS,}, + .stream_name = "Playback", + .channels_min = 1, + .channels_max = 2, + .rates = AIC32X4_RATES, + .formats = AIC32X4_FORMATS,}, .capture = { - .stream_name = "Capture", - .channels_min = 1, - .channels_max = 2, - .rates = AIC32X4_RATES, - .formats = AIC32X4_FORMATS,}, + .stream_name = "Capture", + .channels_min = 1, + .channels_max = 2, + .rates = AIC32X4_RATES, + .formats = AIC32X4_FORMATS,}, .ops = &aic32x4_ops, .symmetric_rates = 1, }; @@ -950,7 +945,7 @@ static void aic32x4_setup_gpios(struct snd_soc_component *component) /* MFP1 */ if (aic32x4->setup->gpio_func[0] != AIC32X4_MFPX_DEFAULT_VALUE) { snd_soc_component_write(component, AIC32X4_DINCTL, - aic32x4->setup->gpio_func[0]); + aic32x4->setup->gpio_func[0]); snd_soc_add_component_controls(component, aic32x4_mfp1, ARRAY_SIZE(aic32x4_mfp1)); } @@ -958,7 +953,7 @@ static void aic32x4_setup_gpios(struct snd_soc_component *component) /* MFP2 */ if (aic32x4->setup->gpio_func[1] != AIC32X4_MFPX_DEFAULT_VALUE) { snd_soc_component_write(component, AIC32X4_DOUTCTL, - aic32x4->setup->gpio_func[1]); + aic32x4->setup->gpio_func[1]); snd_soc_add_component_controls(component, aic32x4_mfp2, ARRAY_SIZE(aic32x4_mfp2)); } @@ -966,7 +961,7 @@ static void aic32x4_setup_gpios(struct snd_soc_component *component) /* MFP3 */ if (aic32x4->setup->gpio_func[2] != AIC32X4_MFPX_DEFAULT_VALUE) { snd_soc_component_write(component, AIC32X4_SCLKCTL, - aic32x4->setup->gpio_func[2]); + aic32x4->setup->gpio_func[2]); snd_soc_add_component_controls(component, aic32x4_mfp3, ARRAY_SIZE(aic32x4_mfp3)); } @@ -974,7 +969,7 @@ static void aic32x4_setup_gpios(struct snd_soc_component *component) /* MFP4 */ if (aic32x4->setup->gpio_func[3] != AIC32X4_MFPX_DEFAULT_VALUE) { snd_soc_component_write(component, AIC32X4_MISOCTL, - aic32x4->setup->gpio_func[3]); + aic32x4->setup->gpio_func[3]); snd_soc_add_component_controls(component, aic32x4_mfp4, ARRAY_SIZE(aic32x4_mfp4)); } @@ -982,7 +977,7 @@ static void aic32x4_setup_gpios(struct snd_soc_component *component) /* MFP5 */ if (aic32x4->setup->gpio_func[4] != AIC32X4_MFPX_DEFAULT_VALUE) { snd_soc_component_write(component, AIC32X4_GPIOCTL, - aic32x4->setup->gpio_func[4]); + aic32x4->setup->gpio_func[4]); snd_soc_add_component_controls(component, aic32x4_mfp5, ARRAY_SIZE(aic32x4_mfp5)); } @@ -1006,8 +1001,8 @@ static int aic32x4_component_probe(struct snd_soc_component *component) /* Power platform configuration */ if (aic32x4->power_cfg & AIC32X4_PWR_MICBIAS_2075_LDOIN) { - snd_soc_component_write(component, AIC32X4_MICBIAS, AIC32X4_MICBIAS_LDOIN | - AIC32X4_MICBIAS_2075V); + snd_soc_component_write(component, AIC32X4_MICBIAS, + AIC32X4_MICBIAS_LDOIN | AIC32X4_MICBIAS_2075V); } if (aic32x4->power_cfg & AIC32X4_PWR_AVDD_DVDD_WEAK_DISABLE) snd_soc_component_write(component, AIC32X4_PWRCFG, AIC32X4_AVDDWEAKDISABLE); @@ -1070,12 +1065,18 @@ static int aic32x4_parse_dt(struct aic32x4_priv *aic32x4, struct device_node *np) { struct aic32x4_setup_data *aic32x4_setup; + int ret; aic32x4_setup = devm_kzalloc(aic32x4->dev, sizeof(*aic32x4_setup), GFP_KERNEL); if (!aic32x4_setup) return -ENOMEM; + ret = of_property_match_string(np, "clock-names", "mclk"); + if (ret < 0) + return -EINVAL; + aic32x4->mclk_name = of_clk_get_parent_name(np, ret); + aic32x4->swapdacs = false; aic32x4->micpga_routing = 0; aic32x4->rstn_gpio = of_get_named_gpio(np, "reset-gpios", 0); @@ -1197,7 +1198,7 @@ int aic32x4_probe(struct device *dev, struct regmap *regmap) return PTR_ERR(regmap); aic32x4 = devm_kzalloc(dev, sizeof(struct aic32x4_priv), - GFP_KERNEL); + GFP_KERNEL); if (aic32x4 == NULL) return -ENOMEM; @@ -1209,6 +1210,7 @@ int aic32x4_probe(struct device *dev, struct regmap *regmap) aic32x4->swapdacs = pdata->swapdacs; aic32x4->micpga_routing = pdata->micpga_routing; aic32x4->rstn_gpio = pdata->rstn_gpio; + aic32x4->mclk_name = "mclk"; } else if (np) { ret = aic32x4_parse_dt(aic32x4, np); if (ret) { @@ -1220,6 +1222,7 @@ int aic32x4_probe(struct device *dev, struct regmap *regmap) aic32x4->swapdacs = false; aic32x4->micpga_routing = 0; aic32x4->rstn_gpio = -1; + aic32x4->mclk_name = "mclk"; } aic32x4->mclk = devm_clk_get(dev, "mclk"); @@ -1228,6 +1231,10 @@ int aic32x4_probe(struct device *dev, struct regmap *regmap) return PTR_ERR(aic32x4->mclk); } + ret = aic32x4_register_clocks(dev, aic32x4->mclk_name); + if (ret) + return ret; + if (gpio_is_valid(aic32x4->rstn_gpio)) { ret = devm_gpio_request_one(dev, aic32x4->rstn_gpio, GPIOF_OUT_INIT_LOW, "tlv320aic32x4 rstn"); diff --git a/sound/soc/codecs/tlv320aic32x4.h b/sound/soc/codecs/tlv320aic32x4.h index c2d74025bf4b..e2b65bbba7c2 100644 --- a/sound/soc/codecs/tlv320aic32x4.h +++ b/sound/soc/codecs/tlv320aic32x4.h @@ -16,6 +16,7 @@ struct regmap_config; extern const struct regmap_config aic32x4_regmap_config; int aic32x4_probe(struct device *dev, struct regmap *regmap); int aic32x4_remove(struct device *dev); +int aic32x4_register_clocks(struct device *dev, const char *mclk_name); /* tlv320aic32x4 register space (in decimal to match datasheet) */ @@ -205,4 +206,8 @@ int aic32x4_remove(struct device *dev); #define AIC32X4_RMICPGANIN_IN1L_10K 0x10 #define AIC32X4_RMICPGANIN_CM1R_10K 0x40 +/* Clock Limits */ +#define AIC32X4_MAX_PLL_CLKIN 20000000 + + #endif /* _TLV320AIC32X4_H */ From patchwork Fri Mar 22 00:58:46 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Annaliese McDermond X-Patchwork-Id: 10864769 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id A1F4D139A for ; Fri, 22 Mar 2019 01:01:51 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 6F11A2A504 for ; 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Fri, 22 Mar 2019 01:59:05 +0100 (CET) DKIM-Filter: OpenDKIM Filter v2.11.0 alsa1.perex.cz C5724F8076F Received: from smtp18.relay.ord1d.emailsrvr.com (localhost [127.0.0.1]) by smtp18.relay.ord1d.emailsrvr.com (SMTP Server) with ESMTP id 94015A029F; Thu, 21 Mar 2019 20:59:02 -0400 (EDT) X-SMTPDoctor-Processed: csmtpprox beta Received: from smtp18.relay.ord1d.emailsrvr.com (localhost [127.0.0.1]) by smtp18.relay.ord1d.emailsrvr.com (SMTP Server) with ESMTP id 8FCEEA02DD; Thu, 21 Mar 2019 20:59:02 -0400 (EDT) X-Auth-ID: mcdermj@xenotropic.com Received: by smtp18.relay.ord1d.emailsrvr.com (Authenticated sender: mcdermj-AT-xenotropic.com) with ESMTPSA id 088BEA029F; Thu, 21 Mar 2019 20:59:01 -0400 (EDT) X-Sender-Id: mcdermj@xenotropic.com Received: from commune.xenotropic.com (c-73-96-52-102.hsd1.or.comcast.net [73.96.52.102]) (using TLSv1.2 with cipher DHE-RSA-AES128-GCM-SHA256) by 0.0.0.0:25 (trex/5.7.12); Thu, 21 Mar 2019 20:59:02 -0400 From: Annaliese McDermond To: broonie@kernel.org, alsa-devel@alsa-project.org Date: Thu, 21 Mar 2019 17:58:46 -0700 Message-Id: <20190322005854.23360-3-nh6z@nh6z.net> X-Mailer: git-send-email 2.19.1 In-Reply-To: <20190322005854.23360-1-nh6z@nh6z.net> References: <20190322005854.23360-1-nh6z@nh6z.net> MIME-Version: 1.0 Cc: team@nwdigitalradio.com, Annaliese McDermond Subject: [alsa-devel] [PATCH v4 02/10] ASoC: tlv320aic32x4: Model CODEC_CLKIN in CCF X-BeenThere: alsa-devel@alsa-project.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: "Alsa-devel mailing list for ALSA developers - http://www.alsa-project.org" List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: alsa-devel-bounces@alsa-project.org Sender: "Alsa-devel" X-Virus-Scanned: ClamAV using ClamSMTP Model and manage codec clock input as a component in the Core Clock Framework. This should allow us to do some more complex clock management and power control. Also, some of the on-board chip clocks can be exposed to the outside, and this change will make those clocks easier to consume by other parts of the kernel. Signed-off-by: Annaliese McDermond --- sound/soc/codecs/tlv320aic32x4-clk.c | 34 ++++++++++++++++++++++++++++ sound/soc/codecs/tlv320aic32x4.c | 18 +++++++++++---- 2 files changed, 47 insertions(+), 5 deletions(-) diff --git a/sound/soc/codecs/tlv320aic32x4-clk.c b/sound/soc/codecs/tlv320aic32x4-clk.c index 5e495fc8d931..cded85009c8c 100644 --- a/sound/soc/codecs/tlv320aic32x4-clk.c +++ b/sound/soc/codecs/tlv320aic32x4-clk.c @@ -265,6 +265,30 @@ static const struct clk_ops aic32x4_pll_ops = { .get_parent = clk_aic32x4_pll_get_parent, }; +static int clk_aic32x4_codec_clkin_set_parent(struct clk_hw *hw, u8 index) +{ + struct clk_aic32x4 *mux = to_clk_aic32x4(hw); + + return regmap_update_bits(mux->regmap, + AIC32X4_CLKMUX, + AIC32X4_CODEC_CLKIN_MASK, index << AIC32X4_CODEC_CLKIN_SHIFT); +} + +static u8 clk_aic32x4_codec_clkin_get_parent(struct clk_hw *hw) +{ + struct clk_aic32x4 *mux = to_clk_aic32x4(hw); + unsigned int val; + + regmap_read(mux->regmap, AIC32X4_CLKMUX, &val); + + return (val & AIC32X4_CODEC_CLKIN_MASK) >> AIC32X4_CODEC_CLKIN_SHIFT; +} + +static const struct clk_ops aic32x4_codec_clkin_ops = { + .set_parent = clk_aic32x4_codec_clkin_set_parent, + .get_parent = clk_aic32x4_codec_clkin_get_parent, +}; + static struct aic32x4_clkdesc aic32x4_clkdesc_array[] = { { .name = "pll", @@ -274,6 +298,14 @@ static struct aic32x4_clkdesc aic32x4_clkdesc_array[] = { .ops = &aic32x4_pll_ops, .reg = 0, }, + { + .name = "codec_clkin", + .parent_names = + (const char *[]) { "mclk", "bclk", "gpio", "pll" }, + .num_parents = 4, + .ops = &aic32x4_codec_clkin_ops, + .reg = 0, + }, }; static struct clk *aic32x4_register_clk(struct device *dev, @@ -314,6 +346,8 @@ int aic32x4_register_clocks(struct device *dev, const char *mclk_name) */ aic32x4_clkdesc_array[0].parent_names = (const char* []) { mclk_name, "bclk", "gpio", "din" }; + aic32x4_clkdesc_array[1].parent_names = + (const char *[]) { mclk_name, "bclk", "gpio", "pll" }; for (i = 0; i < ARRAY_SIZE(aic32x4_clkdesc_array); ++i) aic32x4_register_clk(dev, &aic32x4_clkdesc_array[i]); diff --git a/sound/soc/codecs/tlv320aic32x4.c b/sound/soc/codecs/tlv320aic32x4.c index 7cf8c7cedfe1..5496e4e080f4 100644 --- a/sound/soc/codecs/tlv320aic32x4.c +++ b/sound/soc/codecs/tlv320aic32x4.c @@ -735,12 +735,9 @@ static int aic32x4_setup_clocks(struct snd_soc_component *component, aic32x4_set_processing_blocks(component, aic32x4_divs[i].r_block, aic32x4_divs[i].p_block); - /* PLL as CODEC_CLKIN */ - snd_soc_component_update_bits(component, AIC32X4_CLKMUX, - AIC32X4_CODEC_CLKIN_MASK, - AIC32X4_CODEC_CLKIN_PLL << AIC32X4_CODEC_CLKIN_SHIFT); /* DAC_MOD_CLK as BDIV_CLKIN */ - snd_soc_component_update_bits(component, AIC32X4_IFACE3, AIC32X4_BDIVCLK_MASK, + snd_soc_component_update_bits(component, AIC32X4_IFACE3, + AIC32X4_BDIVCLK_MASK, AIC32X4_DACMOD2BCLK << AIC32X4_BDIVCLK_SHIFT); /* NDAC divider value */ @@ -987,6 +984,15 @@ static int aic32x4_component_probe(struct snd_soc_component *component) { struct aic32x4_priv *aic32x4 = snd_soc_component_get_drvdata(component); u32 tmp_reg; + int ret; + + struct clk_bulk_data clocks[] = { + { .id = "codec_clkin" }, + }; + + ret = devm_clk_bulk_get(component->dev, ARRAY_SIZE(clocks), clocks); + if (ret) + return ret; if (gpio_is_valid(aic32x4->rstn_gpio)) { ndelay(10); @@ -999,6 +1005,8 @@ static int aic32x4_component_probe(struct snd_soc_component *component) if (aic32x4->setup) aic32x4_setup_gpios(component); + clk_set_parent(clocks[0].clk, clocks[1].clk); + /* Power platform configuration */ if (aic32x4->power_cfg & AIC32X4_PWR_MICBIAS_2075_LDOIN) { snd_soc_component_write(component, AIC32X4_MICBIAS, From patchwork Fri Mar 22 00:58:47 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Annaliese McDermond X-Patchwork-Id: 10864771 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 1D57A139A for ; Fri, 22 Mar 2019 01:02:38 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id DEAD82A4F3 for ; Fri, 22 Mar 2019 01:02:37 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id D30112A503; Fri, 22 Mar 2019 01:02:37 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-2.9 required=2.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,MAILING_LIST_MULTI,RCVD_IN_DNSWL_NONE autolearn=ham version=3.3.1 Received: from alsa0.perex.cz (alsa0.perex.cz [77.48.224.243]) (using TLSv1.2 with cipher DHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.wl.linuxfoundation.org (Postfix) with ESMTPS id AA2762A4F3 for ; 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Thu, 21 Mar 2019 20:59:03 -0400 From: Annaliese McDermond To: broonie@kernel.org, alsa-devel@alsa-project.org Date: Thu, 21 Mar 2019 17:58:47 -0700 Message-Id: <20190322005854.23360-4-nh6z@nh6z.net> X-Mailer: git-send-email 2.19.1 In-Reply-To: <20190322005854.23360-1-nh6z@nh6z.net> References: <20190322005854.23360-1-nh6z@nh6z.net> MIME-Version: 1.0 Cc: team@nwdigitalradio.com, Annaliese McDermond Subject: [alsa-devel] [PATCH v4 03/10] ASoC: tlv320aic32x4: Model DAC/ADC dividers in CCF X-BeenThere: alsa-devel@alsa-project.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: "Alsa-devel mailing list for ALSA developers - http://www.alsa-project.org" List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: alsa-devel-bounces@alsa-project.org Sender: "Alsa-devel" X-Virus-Scanned: ClamAV using ClamSMTP Model and manage DAC/ADC dividers as components in the Core Clock Framework. This should allow us to do some more complex clock management and power control. Also, some of the on-board chip clocks can be exposed to the outside, and this change will make those clocks easier to consume by other parts of the kernel. Signed-off-by: Annaliese McDermond --- sound/soc/codecs/tlv320aic32x4-clk.c | 90 ++++++++++++++++++++++++ sound/soc/codecs/tlv320aic32x4.c | 101 +++++++++++++++------------ sound/soc/codecs/tlv320aic32x4.h | 4 ++ 3 files changed, 151 insertions(+), 44 deletions(-) diff --git a/sound/soc/codecs/tlv320aic32x4-clk.c b/sound/soc/codecs/tlv320aic32x4-clk.c index cded85009c8c..daf14924e324 100644 --- a/sound/soc/codecs/tlv320aic32x4-clk.c +++ b/sound/soc/codecs/tlv320aic32x4-clk.c @@ -289,6 +289,68 @@ static const struct clk_ops aic32x4_codec_clkin_ops = { .get_parent = clk_aic32x4_codec_clkin_get_parent, }; +static int clk_aic32x4_div_prepare(struct clk_hw *hw) +{ + struct clk_aic32x4 *div = to_clk_aic32x4(hw); + + return regmap_update_bits(div->regmap, div->reg, + AIC32X4_DIVEN, AIC32X4_DIVEN); +} + +static void clk_aic32x4_div_unprepare(struct clk_hw *hw) +{ + struct clk_aic32x4 *div = to_clk_aic32x4(hw); + + regmap_update_bits(div->regmap, div->reg, + AIC32X4_DIVEN, 0); +} + +static int clk_aic32x4_div_set_rate(struct clk_hw *hw, unsigned long rate, + unsigned long parent_rate) +{ + struct clk_aic32x4 *div = to_clk_aic32x4(hw); + u8 divisor; + + divisor = DIV_ROUND_UP(parent_rate, rate); + if (divisor > 128) + return -EINVAL; + + return regmap_update_bits(div->regmap, div->reg, + AIC32X4_DIV_MASK, divisor); +} + +static long clk_aic32x4_div_round_rate(struct clk_hw *hw, unsigned long rate, + unsigned long *parent_rate) +{ + unsigned long divisor; + + divisor = DIV_ROUND_UP(*parent_rate, rate); + if (divisor > 128) + return -EINVAL; + + return DIV_ROUND_UP(*parent_rate, divisor); +} + +static unsigned long clk_aic32x4_div_recalc_rate(struct clk_hw *hw, + unsigned long parent_rate) +{ + struct clk_aic32x4 *div = to_clk_aic32x4(hw); + + unsigned int val; + + regmap_read(div->regmap, div->reg, &val); + + return DIV_ROUND_UP(parent_rate, val & AIC32X4_DIV_MASK); +} + +static const struct clk_ops aic32x4_div_ops = { + .prepare = clk_aic32x4_div_prepare, + .unprepare = clk_aic32x4_div_unprepare, + .set_rate = clk_aic32x4_div_set_rate, + .round_rate = clk_aic32x4_div_round_rate, + .recalc_rate = clk_aic32x4_div_recalc_rate, +}; + static struct aic32x4_clkdesc aic32x4_clkdesc_array[] = { { .name = "pll", @@ -306,6 +368,34 @@ static struct aic32x4_clkdesc aic32x4_clkdesc_array[] = { .ops = &aic32x4_codec_clkin_ops, .reg = 0, }, + { + .name = "ndac", + .parent_names = (const char * []) { "codec_clkin" }, + .num_parents = 1, + .ops = &aic32x4_div_ops, + .reg = AIC32X4_NDAC, + }, + { + .name = "mdac", + .parent_names = (const char * []) { "ndac" }, + .num_parents = 1, + .ops = &aic32x4_div_ops, + .reg = AIC32X4_MDAC, + }, + { + .name = "nadc", + .parent_names = (const char * []) { "codec_clkin" }, + .num_parents = 1, + .ops = &aic32x4_div_ops, + .reg = AIC32X4_NADC, + }, + { + .name = "madc", + .parent_names = (const char * []) { "nadc" }, + .num_parents = 1, + .ops = &aic32x4_div_ops, + .reg = AIC32X4_MADC, + }, }; static struct clk *aic32x4_register_clk(struct device *dev, diff --git a/sound/soc/codecs/tlv320aic32x4.c b/sound/soc/codecs/tlv320aic32x4.c index 5496e4e080f4..0cf942938372 100644 --- a/sound/soc/codecs/tlv320aic32x4.c +++ b/sound/soc/codecs/tlv320aic32x4.c @@ -52,11 +52,11 @@ struct aic32x4_rate_divs { u32 rate; unsigned long pll_rate; u16 dosr; - u8 ndac; - u8 mdac; + unsigned long ndac_rate; + unsigned long mdac_rate; u8 aosr; - u8 nadc; - u8 madc; + unsigned long nadc_rate; + unsigned long madc_rate; u8 blck_N; u8 r_block; u8 p_block; @@ -309,34 +309,54 @@ static const struct snd_kcontrol_new aic32x4_snd_controls[] = { static const struct aic32x4_rate_divs aic32x4_divs[] = { /* 8k rate */ - { 12000000, 8000, 57120000, 768, 5, 3, 128, 5, 18, 24, 1, 1 }, - { 24000000, 8000, 57120000, 768, 15, 1, 64, 45, 4, 24, 1, 1 }, - { 25000000, 8000, 32620000, 768, 15, 1, 64, 45, 4, 24, 1, 1 }, + { 12000000, 8000, 57120000, 768, 18432000, 6144000, 128, 18432000, + 1024000, 24, 1, 1 }, + { 24000000, 8000, 57120000, 768, 6144000, 6144000, 64, 2048000, + 512000, 24, 1, 1 }, + { 25000000, 8000, 32620000, 768, 6144000, 6144000, 64, 2048000, + 512000, 24, 1, 1 }, /* 11.025k rate */ - { 12000000, 11025, 44217600, 512, 8, 2, 128, 8, 8, 16, 1, 1 }, - { 24000000, 11025, 44217600, 512, 16, 1, 64, 32, 4, 16, 1, 1 }, + { 12000000, 11025, 44217600, 512, 11289600, 5644800, 128, 11289600, + 1411200, 16, 1, 1 }, + { 24000000, 11025, 44217600, 512, 5644800, 5644800, 64, 2822400, + 705600, 16, 1, 1 }, /* 16k rate */ - { 12000000, 16000, 57120000, 384, 5, 3, 128, 5, 9, 12, 1, 1 }, - { 24000000, 16000, 57120000, 384, 15, 1, 64, 18, 5, 12, 1, 1 }, - { 25000000, 16000, 32620000, 384, 15, 1, 64, 18, 5, 12, 1, 1 }, + { 12000000, 16000, 57120000, 384, 18432000, 6144000, 128, 18432000, + 2048000, 12, 1, 1 }, + { 24000000, 16000, 57120000, 384, 6144000, 6144000, 64, 5120000, + 1024000, 12, 1, 1 }, + { 25000000, 16000, 32620000, 384, 6144000, 6144000, 64, 5120000, + 1024000, 12, 1, 1 }, /* 22.05k rate */ - { 12000000, 22050, 44217600, 256, 4, 4, 128, 4, 8, 8, 1, 1 }, - { 24000000, 22050, 44217600, 256, 16, 1, 64, 16, 4, 8, 1, 1 }, - { 25000000, 22050, 19713750, 256, 16, 1, 64, 16, 4, 8, 1, 1 }, + { 12000000, 22050, 44217600, 256, 22579200, 5644800, 128, 22579200, + 2822400, 8, 1, 1 }, + { 24000000, 22050, 44217600, 256, 5644800, 5644800, 64, 5644800, + 1411200, 8, 1, 1 }, + { 25000000, 22050, 19713750, 256, 5644800, 5644800, 64, 5644800, + 1411200, 8, 1, 1 }, /* 32k rate */ - { 12000000, 32000, 14112000, 192, 2, 7, 64, 2, 21, 6, 1, 1 }, - { 24000000, 32000, 14112000, 192, 7, 2, 64, 7, 6, 6, 1, 1 }, + { 12000000, 32000, 14112000, 192, 43008000, 6144000, 64, 43008000, + 2048000, 6, 1, 1 }, + { 24000000, 32000, 14112000, 192, 12288000, 6144000, 64, 12288000, + 2048000, 6, 1, 1 }, /* 44.1k rate */ - { 12000000, 44100, 44217600, 128, 2, 8, 128, 2, 8, 4, 1, 1 }, - { 24000000, 44100, 44217600, 128, 8, 2, 64, 8, 4, 4, 1, 1 }, - { 25000000, 44100, 19713750, 128, 8, 2, 64, 8, 4, 4, 1, 1 }, + { 12000000, 44100, 44217600, 128, 45158400, 5644800, 128, 45158400, + 5644800, 4, 1, 1 }, + { 24000000, 44100, 44217600, 128, 11289600, 5644800, 64, 11289600, + 2822400, 4, 1, 1 }, + { 25000000, 44100, 19713750, 128, 11289600, 5644800, 64, 11289600, + 2822400, 4, 1, 1 }, /* 48k rate */ - { 12000000, 48000, 18432000, 128, 2, 8, 128, 2, 8, 4, 1, 1 }, - { 24000000, 48000, 18432000, 128, 8, 2, 64, 8, 4, 4, 1, 1 }, - { 25000000, 48000, 75626250, 128, 8, 2, 64, 8, 4, 4, 1, 1 }, + { 12000000, 48000, 18432000, 128, 49152000, 6144000, 128, 49152000, + 6144000, 4, 1, 1 }, + { 24000000, 48000, 18432000, 128, 12288000, 6144000, 64, 12288000, + 3072000, 4, 1, 1 }, + { 25000000, 48000, 75626250, 128, 12288000, 6144000, 64, 12288000, + 3072000, 4, 1, 1 }, /* 96k rate */ - { 25000000, 96000, 75626250, 64, 4, 4, 64, 4, 4, 1, 1, 9 }, + { 25000000, 96000, 75626250, 64, 24576000, 6144000, 64, 24576000, + 6144000, 1, 1, 9 }, }; static const struct snd_kcontrol_new hpl_output_mixer_controls[] = { @@ -719,6 +739,10 @@ static int aic32x4_setup_clocks(struct snd_soc_component *component, struct clk_bulk_data clocks[] = { { .id = "pll" }, + { .id = "nadc" }, + { .id = "madc" }, + { .id = "ndac" }, + { .id = "mdac" }, }; i = aic32x4_get_divs(parent_rate, sample_rate); @@ -731,7 +755,11 @@ static int aic32x4_setup_clocks(struct snd_soc_component *component, if (ret) return ret; - clk_set_rate(clocks[0].clk, sample_rate); + clk_set_rate(clocks[0].clk, aic32x4_divs[i].pll_rate); + clk_set_rate(clocks[1].clk, aic32x4_divs[i].nadc_rate); + clk_set_rate(clocks[2].clk, aic32x4_divs[i].madc_rate); + clk_set_rate(clocks[3].clk, aic32x4_divs[i].ndac_rate); + clk_set_rate(clocks[4].clk, aic32x4_divs[i].mdac_rate); aic32x4_set_processing_blocks(component, aic32x4_divs[i].r_block, aic32x4_divs[i].p_block); @@ -740,26 +768,10 @@ static int aic32x4_setup_clocks(struct snd_soc_component *component, AIC32X4_BDIVCLK_MASK, AIC32X4_DACMOD2BCLK << AIC32X4_BDIVCLK_SHIFT); - /* NDAC divider value */ - snd_soc_component_update_bits(component, AIC32X4_NDAC, - AIC32X4_NDAC_MASK, aic32x4_divs[i].ndac); - - /* MDAC divider value */ - snd_soc_component_update_bits(component, AIC32X4_MDAC, - AIC32X4_MDAC_MASK, aic32x4_divs[i].mdac); - /* DOSR MSB & LSB values */ snd_soc_component_write(component, AIC32X4_DOSRMSB, aic32x4_divs[i].dosr >> 8); snd_soc_component_write(component, AIC32X4_DOSRLSB, (aic32x4_divs[i].dosr & 0xff)); - /* NADC divider value */ - snd_soc_component_update_bits(component, AIC32X4_NADC, - AIC32X4_NADC_MASK, aic32x4_divs[i].nadc); - - /* MADC divider value */ - snd_soc_component_update_bits(component, AIC32X4_MADC, - AIC32X4_MADC_MASK, aic32x4_divs[i].madc); - /* AOSR value */ snd_soc_component_write(component, AIC32X4_AOSR, aic32x4_divs[i].aosr); @@ -771,8 +783,8 @@ static int aic32x4_setup_clocks(struct snd_soc_component *component, } static int aic32x4_hw_params(struct snd_pcm_substream *substream, - struct snd_pcm_hw_params *params, - struct snd_soc_dai *dai) + struct snd_pcm_hw_params *params, + struct snd_soc_dai *dai) { struct snd_soc_component *component = dai->component; struct aic32x4_priv *aic32x4 = snd_soc_component_get_drvdata(component); @@ -987,7 +999,8 @@ static int aic32x4_component_probe(struct snd_soc_component *component) int ret; struct clk_bulk_data clocks[] = { - { .id = "codec_clkin" }, + { .id = "codec_clkin" }, + { .id = "pll" }, }; ret = devm_clk_bulk_get(component->dev, ARRAY_SIZE(clocks), clocks); diff --git a/sound/soc/codecs/tlv320aic32x4.h b/sound/soc/codecs/tlv320aic32x4.h index e2b65bbba7c2..6ede877b00a0 100644 --- a/sound/soc/codecs/tlv320aic32x4.h +++ b/sound/soc/codecs/tlv320aic32x4.h @@ -206,6 +206,10 @@ int aic32x4_register_clocks(struct device *dev, const char *mclk_name); #define AIC32X4_RMICPGANIN_IN1L_10K 0x10 #define AIC32X4_RMICPGANIN_CM1R_10K 0x40 +/* Common mask and enable for all of the dividers */ +#define AIC32X4_DIVEN BIT(7) +#define AIC32X4_DIV_MASK GENMASK(6, 0) + /* Clock Limits */ #define AIC32X4_MAX_PLL_CLKIN 20000000 From patchwork Fri Mar 22 00:58:48 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Annaliese McDermond X-Patchwork-Id: 10864775 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 0F3D0922 for ; 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Fri, 22 Mar 2019 01:59:08 +0100 (CET) DKIM-Filter: OpenDKIM Filter v2.11.0 alsa1.perex.cz 4E2C8F896B7 Received: from smtp18.relay.ord1d.emailsrvr.com (localhost [127.0.0.1]) by smtp18.relay.ord1d.emailsrvr.com (SMTP Server) with ESMTP id 09EC0A02E0; Thu, 21 Mar 2019 20:59:04 -0400 (EDT) X-SMTPDoctor-Processed: csmtpprox beta Received: from smtp18.relay.ord1d.emailsrvr.com (localhost [127.0.0.1]) by smtp18.relay.ord1d.emailsrvr.com (SMTP Server) with ESMTP id 05C5EA02E1; Thu, 21 Mar 2019 20:59:04 -0400 (EDT) X-Auth-ID: mcdermj@xenotropic.com Received: by smtp18.relay.ord1d.emailsrvr.com (Authenticated sender: mcdermj-AT-xenotropic.com) with ESMTPSA id 73874A02E3; Thu, 21 Mar 2019 20:59:03 -0400 (EDT) X-Sender-Id: mcdermj@xenotropic.com Received: from commune.xenotropic.com (c-73-96-52-102.hsd1.or.comcast.net [73.96.52.102]) (using TLSv1.2 with cipher DHE-RSA-AES128-GCM-SHA256) by 0.0.0.0:25 (trex/5.7.12); Thu, 21 Mar 2019 20:59:03 -0400 From: Annaliese McDermond To: broonie@kernel.org, alsa-devel@alsa-project.org Date: Thu, 21 Mar 2019 17:58:48 -0700 Message-Id: <20190322005854.23360-5-nh6z@nh6z.net> X-Mailer: git-send-email 2.19.1 In-Reply-To: <20190322005854.23360-1-nh6z@nh6z.net> References: <20190322005854.23360-1-nh6z@nh6z.net> MIME-Version: 1.0 Cc: team@nwdigitalradio.com, Annaliese McDermond Subject: [alsa-devel] [PATCH v4 04/10] ASoC: tlv320aic32x4: Model BDIV divider in CCF X-BeenThere: alsa-devel@alsa-project.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: "Alsa-devel mailing list for ALSA developers - http://www.alsa-project.org" List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: alsa-devel-bounces@alsa-project.org Sender: "Alsa-devel" X-Virus-Scanned: ClamAV using ClamSMTP Model and manage BDIV divider as components in the Core Clock Framework. This should allow us to do some more complex clock management and power control. Also, some of the on-board chip clocks can be exposed to the outside, and this change will make those clocks easier to consume by other parts of the kernel. Signed-off-by: Annaliese McDermond --- sound/soc/codecs/tlv320aic32x4-clk.c | 36 ++++++++++++++++++ sound/soc/codecs/tlv320aic32x4.c | 56 +++++++++++++--------------- 2 files changed, 62 insertions(+), 30 deletions(-) diff --git a/sound/soc/codecs/tlv320aic32x4-clk.c b/sound/soc/codecs/tlv320aic32x4-clk.c index daf14924e324..667ec2c03508 100644 --- a/sound/soc/codecs/tlv320aic32x4-clk.c +++ b/sound/soc/codecs/tlv320aic32x4-clk.c @@ -351,6 +351,34 @@ static const struct clk_ops aic32x4_div_ops = { .recalc_rate = clk_aic32x4_div_recalc_rate, }; +static int clk_aic32x4_bdiv_set_parent(struct clk_hw *hw, u8 index) +{ + struct clk_aic32x4 *mux = to_clk_aic32x4(hw); + + return regmap_update_bits(mux->regmap, AIC32X4_IFACE3, + AIC32X4_BDIVCLK_MASK, index); +} + +static u8 clk_aic32x4_bdiv_get_parent(struct clk_hw *hw) +{ + struct clk_aic32x4 *mux = to_clk_aic32x4(hw); + unsigned int val; + + regmap_read(mux->regmap, AIC32X4_IFACE3, &val); + + return val & AIC32X4_BDIVCLK_MASK; +} + +static const struct clk_ops aic32x4_bdiv_ops = { + .prepare = clk_aic32x4_div_prepare, + .unprepare = clk_aic32x4_div_unprepare, + .set_parent = clk_aic32x4_bdiv_set_parent, + .get_parent = clk_aic32x4_bdiv_get_parent, + .set_rate = clk_aic32x4_div_set_rate, + .round_rate = clk_aic32x4_div_round_rate, + .recalc_rate = clk_aic32x4_div_recalc_rate, +}; + static struct aic32x4_clkdesc aic32x4_clkdesc_array[] = { { .name = "pll", @@ -396,6 +424,14 @@ static struct aic32x4_clkdesc aic32x4_clkdesc_array[] = { .ops = &aic32x4_div_ops, .reg = AIC32X4_MADC, }, + { + .name = "bdiv", + .parent_names = + (const char *[]) { "ndac", "mdac", "nadc", "madc" }, + .num_parents = 4, + .ops = &aic32x4_bdiv_ops, + .reg = AIC32X4_BCLKN, + }, }; static struct clk *aic32x4_register_clk(struct device *dev, diff --git a/sound/soc/codecs/tlv320aic32x4.c b/sound/soc/codecs/tlv320aic32x4.c index 0cf942938372..bf9ccda6616d 100644 --- a/sound/soc/codecs/tlv320aic32x4.c +++ b/sound/soc/codecs/tlv320aic32x4.c @@ -57,7 +57,7 @@ struct aic32x4_rate_divs { u8 aosr; unsigned long nadc_rate; unsigned long madc_rate; - u8 blck_N; + unsigned long bdiv_rate; u8 r_block; u8 p_block; }; @@ -310,53 +310,53 @@ static const struct snd_kcontrol_new aic32x4_snd_controls[] = { static const struct aic32x4_rate_divs aic32x4_divs[] = { /* 8k rate */ { 12000000, 8000, 57120000, 768, 18432000, 6144000, 128, 18432000, - 1024000, 24, 1, 1 }, + 1024000, 256000, 1, 1 }, { 24000000, 8000, 57120000, 768, 6144000, 6144000, 64, 2048000, - 512000, 24, 1, 1 }, + 512000, 256000, 1, 1 }, { 25000000, 8000, 32620000, 768, 6144000, 6144000, 64, 2048000, - 512000, 24, 1, 1 }, + 512000, 256000, 1, 1 }, /* 11.025k rate */ { 12000000, 11025, 44217600, 512, 11289600, 5644800, 128, 11289600, - 1411200, 16, 1, 1 }, + 1411200, 352800, 1, 1 }, { 24000000, 11025, 44217600, 512, 5644800, 5644800, 64, 2822400, - 705600, 16, 1, 1 }, + 705600, 352800, 1, 1 }, /* 16k rate */ { 12000000, 16000, 57120000, 384, 18432000, 6144000, 128, 18432000, - 2048000, 12, 1, 1 }, + 2048000, 512000, 1, 1 }, { 24000000, 16000, 57120000, 384, 6144000, 6144000, 64, 5120000, - 1024000, 12, 1, 1 }, + 1024000, 512000, 1, 1 }, { 25000000, 16000, 32620000, 384, 6144000, 6144000, 64, 5120000, - 1024000, 12, 1, 1 }, + 1024000, 512000, 1, 1 }, /* 22.05k rate */ { 12000000, 22050, 44217600, 256, 22579200, 5644800, 128, 22579200, - 2822400, 8, 1, 1 }, + 2822400, 705600, 1, 1 }, { 24000000, 22050, 44217600, 256, 5644800, 5644800, 64, 5644800, - 1411200, 8, 1, 1 }, + 1411200, 705600, 1, 1 }, { 25000000, 22050, 19713750, 256, 5644800, 5644800, 64, 5644800, - 1411200, 8, 1, 1 }, + 1411200, 705600, 1, 1 }, /* 32k rate */ { 12000000, 32000, 14112000, 192, 43008000, 6144000, 64, 43008000, - 2048000, 6, 1, 1 }, + 2048000, 1024000, 1, 1 }, { 24000000, 32000, 14112000, 192, 12288000, 6144000, 64, 12288000, - 2048000, 6, 1, 1 }, + 2048000, 1024000, 1, 1 }, /* 44.1k rate */ { 12000000, 44100, 44217600, 128, 45158400, 5644800, 128, 45158400, - 5644800, 4, 1, 1 }, + 5644800, 1411200, 1, 1 }, { 24000000, 44100, 44217600, 128, 11289600, 5644800, 64, 11289600, - 2822400, 4, 1, 1 }, + 2822400, 1411200, 1, 1 }, { 25000000, 44100, 19713750, 128, 11289600, 5644800, 64, 11289600, - 2822400, 4, 1, 1 }, + 2822400, 1411200, 1, 1 }, /* 48k rate */ { 12000000, 48000, 18432000, 128, 49152000, 6144000, 128, 49152000, - 6144000, 4, 1, 1 }, + 6144000, 1536000, 1, 1 }, { 24000000, 48000, 18432000, 128, 12288000, 6144000, 64, 12288000, - 3072000, 4, 1, 1 }, + 3072000, 1536000, 1, 1 }, { 25000000, 48000, 75626250, 128, 12288000, 6144000, 64, 12288000, - 3072000, 4, 1, 1 }, + 3072000, 1536000, 1, 1 }, /* 96k rate */ { 25000000, 96000, 75626250, 64, 24576000, 6144000, 64, 24576000, - 6144000, 1, 1, 9 }, + 6144000, 3072000, 1, 9 }, }; static const struct snd_kcontrol_new hpl_output_mixer_controls[] = { @@ -743,6 +743,7 @@ static int aic32x4_setup_clocks(struct snd_soc_component *component, { .id = "madc" }, { .id = "ndac" }, { .id = "mdac" }, + { .id = "bdiv" }, }; i = aic32x4_get_divs(parent_rate, sample_rate); @@ -760,14 +761,10 @@ static int aic32x4_setup_clocks(struct snd_soc_component *component, clk_set_rate(clocks[2].clk, aic32x4_divs[i].madc_rate); clk_set_rate(clocks[3].clk, aic32x4_divs[i].ndac_rate); clk_set_rate(clocks[4].clk, aic32x4_divs[i].mdac_rate); + clk_set_rate(clocks[5].clk, aic32x4_divs[i].bdiv_rate); aic32x4_set_processing_blocks(component, aic32x4_divs[i].r_block, aic32x4_divs[i].p_block); - /* DAC_MOD_CLK as BDIV_CLKIN */ - snd_soc_component_update_bits(component, AIC32X4_IFACE3, - AIC32X4_BDIVCLK_MASK, - AIC32X4_DACMOD2BCLK << AIC32X4_BDIVCLK_SHIFT); - /* DOSR MSB & LSB values */ snd_soc_component_write(component, AIC32X4_DOSRMSB, aic32x4_divs[i].dosr >> 8); snd_soc_component_write(component, AIC32X4_DOSRLSB, (aic32x4_divs[i].dosr & 0xff)); @@ -775,10 +772,6 @@ static int aic32x4_setup_clocks(struct snd_soc_component *component, /* AOSR value */ snd_soc_component_write(component, AIC32X4_AOSR, aic32x4_divs[i].aosr); - /* BCLK N divider */ - snd_soc_component_update_bits(component, AIC32X4_BCLKN, - AIC32X4_BCLK_MASK, aic32x4_divs[i].blck_N); - return 0; } @@ -1001,6 +994,8 @@ static int aic32x4_component_probe(struct snd_soc_component *component) struct clk_bulk_data clocks[] = { { .id = "codec_clkin" }, { .id = "pll" }, + { .id = "bdiv" }, + { .id = "mdac" }, }; ret = devm_clk_bulk_get(component->dev, ARRAY_SIZE(clocks), clocks); @@ -1019,6 +1014,7 @@ static int aic32x4_component_probe(struct snd_soc_component *component) aic32x4_setup_gpios(component); clk_set_parent(clocks[0].clk, clocks[1].clk); + clk_set_parent(clocks[2].clk, clocks[3].clk); /* Power platform configuration */ if (aic32x4->power_cfg & AIC32X4_PWR_MICBIAS_2075_LDOIN) { From patchwork Fri Mar 22 00:58:49 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Annaliese McDermond X-Patchwork-Id: 10864773 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 1D5FD922 for ; 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This allows us to prepare_enalbe only 3 clocks and the relationships assigned to them will cause upstream clockss to enable automatically. Additionally we can do this in a single call to the CCF. Signed-off-by: Annaliese McDermond --- sound/soc/codecs/tlv320aic32x4.c | 67 +++++++------------------------- 1 file changed, 13 insertions(+), 54 deletions(-) diff --git a/sound/soc/codecs/tlv320aic32x4.c b/sound/soc/codecs/tlv320aic32x4.c index bf9ccda6616d..c3e9f65b26a7 100644 --- a/sound/soc/codecs/tlv320aic32x4.c +++ b/sound/soc/codecs/tlv320aic32x4.c @@ -834,41 +834,25 @@ static int aic32x4_mute(struct snd_soc_dai *dai, int mute) static int aic32x4_set_bias_level(struct snd_soc_component *component, enum snd_soc_bias_level level) { - struct aic32x4_priv *aic32x4 = snd_soc_component_get_drvdata(component); int ret; + struct clk_bulk_data clocks[] = { + { .id = "madc" }, + { .id = "mdac" }, + { .id = "bdiv" }, + }; + + ret = devm_clk_bulk_get(component->dev, ARRAY_SIZE(clocks), clocks); + if (ret) + return ret; + switch (level) { case SND_SOC_BIAS_ON: - /* Switch on master clock */ - ret = clk_prepare_enable(aic32x4->mclk); + ret = clk_bulk_prepare_enable(ARRAY_SIZE(clocks), clocks); if (ret) { - dev_err(component->dev, "Failed to enable master clock\n"); + dev_err(component->dev, "Failed to enable clocks\n"); return ret; } - - /* Switch on PLL */ - snd_soc_component_update_bits(component, AIC32X4_PLLPR, - AIC32X4_PLLEN, AIC32X4_PLLEN); - - /* Switch on NDAC Divider */ - snd_soc_component_update_bits(component, AIC32X4_NDAC, - AIC32X4_NDACEN, AIC32X4_NDACEN); - - /* Switch on MDAC Divider */ - snd_soc_component_update_bits(component, AIC32X4_MDAC, - AIC32X4_MDACEN, AIC32X4_MDACEN); - - /* Switch on NADC Divider */ - snd_soc_component_update_bits(component, AIC32X4_NADC, - AIC32X4_NADCEN, AIC32X4_NADCEN); - - /* Switch on MADC Divider */ - snd_soc_component_update_bits(component, AIC32X4_MADC, - AIC32X4_MADCEN, AIC32X4_MADCEN); - - /* Switch on BCLK_N Divider */ - snd_soc_component_update_bits(component, AIC32X4_BCLKN, - AIC32X4_BCLKEN, AIC32X4_BCLKEN); break; case SND_SOC_BIAS_PREPARE: break; @@ -877,32 +861,7 @@ static int aic32x4_set_bias_level(struct snd_soc_component *component, if (snd_soc_component_get_bias_level(component) == SND_SOC_BIAS_OFF) break; - /* Switch off BCLK_N Divider */ - snd_soc_component_update_bits(component, AIC32X4_BCLKN, - AIC32X4_BCLKEN, 0); - - /* Switch off MADC Divider */ - snd_soc_component_update_bits(component, AIC32X4_MADC, - AIC32X4_MADCEN, 0); - - /* Switch off NADC Divider */ - snd_soc_component_update_bits(component, AIC32X4_NADC, - AIC32X4_NADCEN, 0); - - /* Switch off MDAC Divider */ - snd_soc_component_update_bits(component, AIC32X4_MDAC, - AIC32X4_MDACEN, 0); - - /* Switch off NDAC Divider */ - snd_soc_component_update_bits(component, AIC32X4_NDAC, - AIC32X4_NDACEN, 0); - - /* Switch off PLL */ - snd_soc_component_update_bits(component, AIC32X4_PLLPR, - AIC32X4_PLLEN, 0); - - /* Switch off master clock */ - clk_disable_unprepare(aic32x4->mclk); + clk_bulk_disable_unprepare(ARRAY_SIZE(clocks), clocks); break; case SND_SOC_BIAS_OFF: break; From patchwork Fri Mar 22 00:58:50 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Annaliese McDermond X-Patchwork-Id: 10864777 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 574646C2 for ; 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Fri, 22 Mar 2019 01:59:10 +0100 (CET) DKIM-Filter: OpenDKIM Filter v2.11.0 alsa1.perex.cz A83EAF89714 Received: from smtp18.relay.ord1d.emailsrvr.com (localhost [127.0.0.1]) by smtp18.relay.ord1d.emailsrvr.com (SMTP Server) with ESMTP id 6843DA02F5; Thu, 21 Mar 2019 20:59:05 -0400 (EDT) X-SMTPDoctor-Processed: csmtpprox beta Received: from smtp18.relay.ord1d.emailsrvr.com (localhost [127.0.0.1]) by smtp18.relay.ord1d.emailsrvr.com (SMTP Server) with ESMTP id 635B7A01CC; Thu, 21 Mar 2019 20:59:05 -0400 (EDT) X-Auth-ID: mcdermj@xenotropic.com Received: by smtp18.relay.ord1d.emailsrvr.com (Authenticated sender: mcdermj-AT-xenotropic.com) with ESMTPSA id D67E5A02F5; Thu, 21 Mar 2019 20:59:04 -0400 (EDT) X-Sender-Id: mcdermj@xenotropic.com Received: from commune.xenotropic.com (c-73-96-52-102.hsd1.or.comcast.net [73.96.52.102]) (using TLSv1.2 with cipher DHE-RSA-AES128-GCM-SHA256) by 0.0.0.0:25 (trex/5.7.12); Thu, 21 Mar 2019 20:59:05 -0400 From: Annaliese McDermond To: broonie@kernel.org, alsa-devel@alsa-project.org Date: Thu, 21 Mar 2019 17:58:50 -0700 Message-Id: <20190322005854.23360-7-nh6z@nh6z.net> X-Mailer: git-send-email 2.19.1 In-Reply-To: <20190322005854.23360-1-nh6z@nh6z.net> References: <20190322005854.23360-1-nh6z@nh6z.net> MIME-Version: 1.0 Cc: team@nwdigitalradio.com, Annaliese McDermond Subject: [alsa-devel] [PATCH v4 06/10] ASoC: tlv320aic32x4: Move aosr and dosr setting to separate functions X-BeenThere: alsa-devel@alsa-project.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: "Alsa-devel mailing list for ALSA developers - http://www.alsa-project.org" List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: alsa-devel-bounces@alsa-project.org Sender: "Alsa-devel" X-Virus-Scanned: ClamAV using ClamSMTP Move these to separate helper functions. This looks cleaner and fits better with the new clock setting in CCF. Signed-off-by: Annaliese McDermond --- sound/soc/codecs/tlv320aic32x4.c | 24 +++++++++++++++++------- 1 file changed, 17 insertions(+), 7 deletions(-) diff --git a/sound/soc/codecs/tlv320aic32x4.c b/sound/soc/codecs/tlv320aic32x4.c index c3e9f65b26a7..bf3a80237b03 100644 --- a/sound/soc/codecs/tlv320aic32x4.c +++ b/sound/soc/codecs/tlv320aic32x4.c @@ -718,6 +718,20 @@ static int aic32x4_set_dai_fmt(struct snd_soc_dai *codec_dai, unsigned int fmt) return 0; } +static int aic32x4_set_aosr(struct snd_soc_component *component, u8 aosr) +{ + return snd_soc_component_write(component, AIC32X4_AOSR, aosr); +} + +static int aic32x4_set_dosr(struct snd_soc_component *component, u16 dosr) +{ + snd_soc_component_write(component, AIC32X4_DOSRMSB, dosr >> 8); + snd_soc_component_write(component, AIC32X4_DOSRLSB, + (dosr & 0xff)); + + return 0; +} + static int aic32x4_set_processing_blocks(struct snd_soc_component *component, u8 r_block, u8 p_block) { @@ -763,14 +777,10 @@ static int aic32x4_setup_clocks(struct snd_soc_component *component, clk_set_rate(clocks[4].clk, aic32x4_divs[i].mdac_rate); clk_set_rate(clocks[5].clk, aic32x4_divs[i].bdiv_rate); - aic32x4_set_processing_blocks(component, aic32x4_divs[i].r_block, aic32x4_divs[i].p_block); + aic32x4_set_aosr(component, aic32x4_divs[i].aosr); + aic32x4_set_dosr(component, aic32x4_divs[i].dosr); - /* DOSR MSB & LSB values */ - snd_soc_component_write(component, AIC32X4_DOSRMSB, aic32x4_divs[i].dosr >> 8); - snd_soc_component_write(component, AIC32X4_DOSRLSB, (aic32x4_divs[i].dosr & 0xff)); - - /* AOSR value */ - snd_soc_component_write(component, AIC32X4_AOSR, aic32x4_divs[i].aosr); + aic32x4_set_processing_blocks(component, aic32x4_divs[i].r_block, aic32x4_divs[i].p_block); return 0; } From patchwork Fri Mar 22 00:58:51 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Annaliese McDermond X-Patchwork-Id: 10864779 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id D9F9F1708 for ; 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Fri, 22 Mar 2019 01:59:10 +0100 (CET) DKIM-Filter: OpenDKIM Filter v2.11.0 alsa1.perex.cz EEB04F89713 Received: from smtp18.relay.ord1d.emailsrvr.com (localhost [127.0.0.1]) by smtp18.relay.ord1d.emailsrvr.com (SMTP Server) with ESMTP id 25673A01CC; Thu, 21 Mar 2019 20:59:06 -0400 (EDT) X-SMTPDoctor-Processed: csmtpprox beta Received: from smtp18.relay.ord1d.emailsrvr.com (localhost [127.0.0.1]) by smtp18.relay.ord1d.emailsrvr.com (SMTP Server) with ESMTP id 1FFE2A0239; Thu, 21 Mar 2019 20:59:06 -0400 (EDT) X-Auth-ID: mcdermj@xenotropic.com Received: by smtp18.relay.ord1d.emailsrvr.com (Authenticated sender: mcdermj-AT-xenotropic.com) with ESMTPSA id 89564A01CC; Thu, 21 Mar 2019 20:59:05 -0400 (EDT) X-Sender-Id: mcdermj@xenotropic.com Received: from commune.xenotropic.com (c-73-96-52-102.hsd1.or.comcast.net [73.96.52.102]) (using TLSv1.2 with cipher DHE-RSA-AES128-GCM-SHA256) by 0.0.0.0:25 (trex/5.7.12); Thu, 21 Mar 2019 20:59:06 -0400 From: Annaliese McDermond To: broonie@kernel.org, alsa-devel@alsa-project.org Date: Thu, 21 Mar 2019 17:58:51 -0700 Message-Id: <20190322005854.23360-8-nh6z@nh6z.net> X-Mailer: git-send-email 2.19.1 In-Reply-To: <20190322005854.23360-1-nh6z@nh6z.net> References: <20190322005854.23360-1-nh6z@nh6z.net> MIME-Version: 1.0 Cc: team@nwdigitalradio.com, Annaliese McDermond Subject: [alsa-devel] [PATCH v4 07/10] ASoC: tlv320aic32x4: Dynamically Determine Clocking X-BeenThere: alsa-devel@alsa-project.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: "Alsa-devel mailing list for ALSA developers - http://www.alsa-project.org" List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: alsa-devel-bounces@alsa-project.org Sender: "Alsa-devel" X-Virus-Scanned: ClamAV using ClamSMTP The existing code uses a static lookup table to determine the settings of the various clock devices on board the chip. This is limiting in a couple of ways. First, this doesn't allow for any master clock rates other than the three that have been precalculated. Additionally, new sample rates are difficult to add to the table. Witness that the chip is capable of 192000 Hz sampling, but it is not provided by this driver. Last, if the driver is clocked by something that isn't a crystal, the upstream clock may not be able to achieve exactly the rate requested in the driver. This will mean that clocking will be slightly off for the sampling clock or that it won't work at all. This patch determines the settings for all of the clocks at runtime considering the real conditions of the clocks in the system. The rules for the clocks are in TI's SLAA557 application guide on pages 37, 51 and 77. Signed-off-by: Annaliese McDermond --- sound/soc/codecs/tlv320aic32x4.c | 190 ++++++++++++++----------------- sound/soc/codecs/tlv320aic32x4.h | 4 +- 2 files changed, 90 insertions(+), 104 deletions(-) diff --git a/sound/soc/codecs/tlv320aic32x4.c b/sound/soc/codecs/tlv320aic32x4.c index bf3a80237b03..625528500f8d 100644 --- a/sound/soc/codecs/tlv320aic32x4.c +++ b/sound/soc/codecs/tlv320aic32x4.c @@ -47,21 +47,6 @@ #include "tlv320aic32x4.h" -struct aic32x4_rate_divs { - u32 mclk; - u32 rate; - unsigned long pll_rate; - u16 dosr; - unsigned long ndac_rate; - unsigned long mdac_rate; - u8 aosr; - unsigned long nadc_rate; - unsigned long madc_rate; - unsigned long bdiv_rate; - u8 r_block; - u8 p_block; -}; - struct aic32x4_priv { struct regmap *regmap; u32 sysclk; @@ -307,58 +292,6 @@ static const struct snd_kcontrol_new aic32x4_snd_controls[] = { 0, 0x0F, 0), }; -static const struct aic32x4_rate_divs aic32x4_divs[] = { - /* 8k rate */ - { 12000000, 8000, 57120000, 768, 18432000, 6144000, 128, 18432000, - 1024000, 256000, 1, 1 }, - { 24000000, 8000, 57120000, 768, 6144000, 6144000, 64, 2048000, - 512000, 256000, 1, 1 }, - { 25000000, 8000, 32620000, 768, 6144000, 6144000, 64, 2048000, - 512000, 256000, 1, 1 }, - /* 11.025k rate */ - { 12000000, 11025, 44217600, 512, 11289600, 5644800, 128, 11289600, - 1411200, 352800, 1, 1 }, - { 24000000, 11025, 44217600, 512, 5644800, 5644800, 64, 2822400, - 705600, 352800, 1, 1 }, - /* 16k rate */ - { 12000000, 16000, 57120000, 384, 18432000, 6144000, 128, 18432000, - 2048000, 512000, 1, 1 }, - { 24000000, 16000, 57120000, 384, 6144000, 6144000, 64, 5120000, - 1024000, 512000, 1, 1 }, - { 25000000, 16000, 32620000, 384, 6144000, 6144000, 64, 5120000, - 1024000, 512000, 1, 1 }, - /* 22.05k rate */ - { 12000000, 22050, 44217600, 256, 22579200, 5644800, 128, 22579200, - 2822400, 705600, 1, 1 }, - { 24000000, 22050, 44217600, 256, 5644800, 5644800, 64, 5644800, - 1411200, 705600, 1, 1 }, - { 25000000, 22050, 19713750, 256, 5644800, 5644800, 64, 5644800, - 1411200, 705600, 1, 1 }, - /* 32k rate */ - { 12000000, 32000, 14112000, 192, 43008000, 6144000, 64, 43008000, - 2048000, 1024000, 1, 1 }, - { 24000000, 32000, 14112000, 192, 12288000, 6144000, 64, 12288000, - 2048000, 1024000, 1, 1 }, - /* 44.1k rate */ - { 12000000, 44100, 44217600, 128, 45158400, 5644800, 128, 45158400, - 5644800, 1411200, 1, 1 }, - { 24000000, 44100, 44217600, 128, 11289600, 5644800, 64, 11289600, - 2822400, 1411200, 1, 1 }, - { 25000000, 44100, 19713750, 128, 11289600, 5644800, 64, 11289600, - 2822400, 1411200, 1, 1 }, - /* 48k rate */ - { 12000000, 48000, 18432000, 128, 49152000, 6144000, 128, 49152000, - 6144000, 1536000, 1, 1 }, - { 24000000, 48000, 18432000, 128, 12288000, 6144000, 64, 12288000, - 3072000, 1536000, 1, 1 }, - { 25000000, 48000, 75626250, 128, 12288000, 6144000, 64, 12288000, - 3072000, 1536000, 1, 1 }, - - /* 96k rate */ - { 25000000, 96000, 75626250, 64, 24576000, 6144000, 64, 24576000, - 6144000, 3072000, 1, 9 }, -}; - static const struct snd_kcontrol_new hpl_output_mixer_controls[] = { SOC_DAPM_SINGLE("L_DAC Switch", AIC32X4_HPLROUTE, 3, 1, 0), SOC_DAPM_SINGLE("IN1_L Switch", AIC32X4_HPLROUTE, 2, 1, 0), @@ -630,20 +563,6 @@ const struct regmap_config aic32x4_regmap_config = { }; EXPORT_SYMBOL(aic32x4_regmap_config); -static inline int aic32x4_get_divs(int mclk, int rate) -{ - int i; - - for (i = 0; i < ARRAY_SIZE(aic32x4_divs); i++) { - if ((aic32x4_divs[i].rate == rate) - && (aic32x4_divs[i].mclk == mclk)) { - return i; - } - } - printk(KERN_ERR "aic32x4: master clock and sample rate is not supported\n"); - return -EINVAL; -} - static int aic32x4_set_dai_sysclk(struct snd_soc_dai *codec_dai, int clk_id, unsigned int freq, int dir) { @@ -745,11 +664,17 @@ static int aic32x4_set_processing_blocks(struct snd_soc_component *component, } static int aic32x4_setup_clocks(struct snd_soc_component *component, - unsigned int sample_rate, - unsigned int parent_rate) + unsigned int sample_rate) { - int i; + u8 aosr; + u16 dosr; + u8 adc_resource_class, dac_resource_class; + u8 madc, nadc, mdac, ndac, max_nadc, min_mdac, max_ndac; + u8 dosr_increment; + u16 max_dosr, min_dosr; + unsigned long mclk_rate, adc_clock_rate, dac_clock_rate; int ret; + struct clk *mclk; struct clk_bulk_data clocks[] = { { .id = "pll" }, @@ -759,30 +684,89 @@ static int aic32x4_setup_clocks(struct snd_soc_component *component, { .id = "mdac" }, { .id = "bdiv" }, }; - - i = aic32x4_get_divs(parent_rate, sample_rate); - if (i < 0) { - printk(KERN_ERR "aic32x4: sampling rate not supported\n"); - return i; - } - ret = devm_clk_bulk_get(component->dev, ARRAY_SIZE(clocks), clocks); if (ret) return ret; - clk_set_rate(clocks[0].clk, aic32x4_divs[i].pll_rate); - clk_set_rate(clocks[1].clk, aic32x4_divs[i].nadc_rate); - clk_set_rate(clocks[2].clk, aic32x4_divs[i].madc_rate); - clk_set_rate(clocks[3].clk, aic32x4_divs[i].ndac_rate); - clk_set_rate(clocks[4].clk, aic32x4_divs[i].mdac_rate); - clk_set_rate(clocks[5].clk, aic32x4_divs[i].bdiv_rate); - - aic32x4_set_aosr(component, aic32x4_divs[i].aosr); - aic32x4_set_dosr(component, aic32x4_divs[i].dosr); + mclk = clk_get_parent(clocks[1].clk); + mclk_rate = clk_get_rate(mclk); + + if (sample_rate <= 48000) { + aosr = 128; + adc_resource_class = 6; + dac_resource_class = 8; + dosr_increment = 8; + aic32x4_set_processing_blocks(component, 1, 1); + } else if (sample_rate <= 96000) { + aosr = 64; + adc_resource_class = 6; + dac_resource_class = 8; + dosr_increment = 4; + aic32x4_set_processing_blocks(component, 1, 9); + } else if (sample_rate == 192000) { + aosr = 32; + adc_resource_class = 3; + dac_resource_class = 4; + dosr_increment = 2; + aic32x4_set_processing_blocks(component, 13, 19); + } else { + dev_err(component->dev, "Sampling rate not supported\n"); + return -EINVAL; + } - aic32x4_set_processing_blocks(component, aic32x4_divs[i].r_block, aic32x4_divs[i].p_block); + madc = DIV_ROUND_UP((32 * adc_resource_class), aosr); + max_dosr = (AIC32X4_MAX_DOSR_FREQ / sample_rate / dosr_increment) * + dosr_increment; + min_dosr = (AIC32X4_MIN_DOSR_FREQ / sample_rate / dosr_increment) * + dosr_increment; + max_nadc = AIC32X4_MAX_CODEC_CLKIN_FREQ / (madc * aosr * sample_rate); + + for (nadc = max_nadc; nadc > 0; --nadc) { + adc_clock_rate = nadc * madc * aosr * sample_rate; + for (dosr = max_dosr; dosr >= min_dosr; + dosr -= dosr_increment) { + min_mdac = DIV_ROUND_UP((32 * dac_resource_class), dosr); + max_ndac = AIC32X4_MAX_CODEC_CLKIN_FREQ / + (min_mdac * dosr * sample_rate); + for (mdac = min_mdac; mdac <= 128; ++mdac) { + for (ndac = max_ndac; ndac > 0; --ndac) { + dac_clock_rate = ndac * mdac * dosr * + sample_rate; + if (dac_clock_rate == adc_clock_rate) { + if (clk_round_rate(clocks[0].clk, dac_clock_rate) == 0) + continue; + + clk_set_rate(clocks[0].clk, + dac_clock_rate); + + clk_set_rate(clocks[1].clk, + sample_rate * aosr * + madc); + clk_set_rate(clocks[2].clk, + sample_rate * aosr); + aic32x4_set_aosr(component, + aosr); + + clk_set_rate(clocks[3].clk, + sample_rate * dosr * + mdac); + clk_set_rate(clocks[4].clk, + sample_rate * dosr); + aic32x4_set_dosr(component, + dosr); + + clk_set_rate(clocks[5].clk, + sample_rate * 32); + return 0; + } + } + } + } + } - return 0; + dev_err(component->dev, + "Could not set clocks to support sample rate.\n"); + return -EINVAL; } static int aic32x4_hw_params(struct snd_pcm_substream *substream, @@ -794,7 +778,7 @@ static int aic32x4_hw_params(struct snd_pcm_substream *substream, u8 iface1_reg = 0; u8 dacsetup_reg = 0; - aic32x4_setup_clocks(component, params_rate(params), aic32x4->sysclk); + aic32x4_setup_clocks(component, params_rate(params)); switch (params_width(params)) { case 16: diff --git a/sound/soc/codecs/tlv320aic32x4.h b/sound/soc/codecs/tlv320aic32x4.h index 6ede877b00a0..88205bc97198 100644 --- a/sound/soc/codecs/tlv320aic32x4.h +++ b/sound/soc/codecs/tlv320aic32x4.h @@ -211,7 +211,9 @@ int aic32x4_register_clocks(struct device *dev, const char *mclk_name); #define AIC32X4_DIV_MASK GENMASK(6, 0) /* Clock Limits */ +#define AIC32X4_MAX_DOSR_FREQ 6200000 +#define AIC32X4_MIN_DOSR_FREQ 2800000 +#define AIC32X4_MAX_CODEC_CLKIN_FREQ 110000000 #define AIC32X4_MAX_PLL_CLKIN 20000000 - #endif /* _TLV320AIC32X4_H */ From patchwork Fri Mar 22 00:58:52 2019 Content-Type: text/plain; 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Thu, 21 Mar 2019 20:59:06 -0400 From: Annaliese McDermond To: broonie@kernel.org, alsa-devel@alsa-project.org Date: Thu, 21 Mar 2019 17:58:52 -0700 Message-Id: <20190322005854.23360-9-nh6z@nh6z.net> X-Mailer: git-send-email 2.19.1 In-Reply-To: <20190322005854.23360-1-nh6z@nh6z.net> References: <20190322005854.23360-1-nh6z@nh6z.net> MIME-Version: 1.0 Cc: team@nwdigitalradio.com, Annaliese McDermond Subject: [alsa-devel] [PATCH v4 08/10] ASoC: tlv320aic32x4: Restructure set_dai_sysclk X-BeenThere: alsa-devel@alsa-project.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: "Alsa-devel mailing list for ALSA developers - http://www.alsa-project.org" List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: alsa-devel-bounces@alsa-project.org Sender: "Alsa-devel" X-Virus-Scanned: ClamAV using ClamSMTP The sysclk is now managed by the CCF. Change this function to merely find the system clock and set it using clk_set_rate. Signed-off-by: Annaliese McDermond --- sound/soc/codecs/tlv320aic32x4.c | 17 ++++++----------- 1 file changed, 6 insertions(+), 11 deletions(-) diff --git a/sound/soc/codecs/tlv320aic32x4.c b/sound/soc/codecs/tlv320aic32x4.c index 625528500f8d..289bf411e60e 100644 --- a/sound/soc/codecs/tlv320aic32x4.c +++ b/sound/soc/codecs/tlv320aic32x4.c @@ -49,7 +49,6 @@ struct aic32x4_priv { struct regmap *regmap; - u32 sysclk; u32 power_cfg; u32 micpga_routing; bool swapdacs; @@ -567,17 +566,13 @@ static int aic32x4_set_dai_sysclk(struct snd_soc_dai *codec_dai, int clk_id, unsigned int freq, int dir) { struct snd_soc_component *component = codec_dai->component; - struct aic32x4_priv *aic32x4 = snd_soc_component_get_drvdata(component); + struct clk *mclk; + struct clk *pll; - switch (freq) { - case 12000000: - case 24000000: - case 25000000: - aic32x4->sysclk = freq; - return 0; - } - printk(KERN_ERR "aic32x4: invalid frequency to set DAI system clock\n"); - return -EINVAL; + pll = devm_clk_get(component->dev, "pll"); + mclk = clk_get_parent(pll); + + return clk_set_rate(mclk, freq); } static int aic32x4_set_dai_fmt(struct snd_soc_dai *codec_dai, unsigned int fmt) From patchwork Fri Mar 22 00:58:53 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Annaliese McDermond X-Patchwork-Id: 10864783 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 781716C2 for ; Fri, 22 Mar 2019 01:06:34 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 46F1D2A5AF for ; Fri, 22 Mar 2019 01:06:34 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 3B3212A5B5; Fri, 22 Mar 2019 01:06:34 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-2.9 required=2.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,MAILING_LIST_MULTI,RCVD_IN_DNSWL_NONE autolearn=ham version=3.3.1 Received: from alsa0.perex.cz (alsa0.perex.cz [77.48.224.243]) (using TLSv1.2 with cipher DHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.wl.linuxfoundation.org (Postfix) with ESMTPS id 8D9E82A5AF for ; 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Thu, 21 Mar 2019 20:59:07 -0400 From: Annaliese McDermond To: broonie@kernel.org, alsa-devel@alsa-project.org Date: Thu, 21 Mar 2019 17:58:53 -0700 Message-Id: <20190322005854.23360-10-nh6z@nh6z.net> X-Mailer: git-send-email 2.19.1 In-Reply-To: <20190322005854.23360-1-nh6z@nh6z.net> References: <20190322005854.23360-1-nh6z@nh6z.net> MIME-Version: 1.0 Cc: team@nwdigitalradio.com, Annaliese McDermond Subject: [alsa-devel] [PATCH v4 09/10] ASoC: tlv320aic32x4: Remove mclk references X-BeenThere: alsa-devel@alsa-project.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: "Alsa-devel mailing list for ALSA developers - http://www.alsa-project.org" List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: alsa-devel-bounces@alsa-project.org Sender: "Alsa-devel" X-Virus-Scanned: ClamAV using ClamSMTP mclk is not used by anything anymore. Remove support for it. All that information now comes from the clock tree. Signed-off-by: Annaliese McDermond --- sound/soc/codecs/tlv320aic32x4.c | 7 ------- 1 file changed, 7 deletions(-) diff --git a/sound/soc/codecs/tlv320aic32x4.c b/sound/soc/codecs/tlv320aic32x4.c index 289bf411e60e..a5457d3de1b1 100644 --- a/sound/soc/codecs/tlv320aic32x4.c +++ b/sound/soc/codecs/tlv320aic32x4.c @@ -53,7 +53,6 @@ struct aic32x4_priv { u32 micpga_routing; bool swapdacs; int rstn_gpio; - struct clk *mclk; const char *mclk_name; struct regulator *supply_ldo; @@ -1190,12 +1189,6 @@ int aic32x4_probe(struct device *dev, struct regmap *regmap) aic32x4->mclk_name = "mclk"; } - aic32x4->mclk = devm_clk_get(dev, "mclk"); - if (IS_ERR(aic32x4->mclk)) { - dev_err(dev, "Failed getting the mclk. The current implementation does not support the usage of this codec without mclk\n"); - return PTR_ERR(aic32x4->mclk); - } - ret = aic32x4_register_clocks(dev, aic32x4->mclk_name); if (ret) return ret; From patchwork Fri Mar 22 00:58:54 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Annaliese McDermond X-Patchwork-Id: 10864785 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 0B0021708 for ; Fri, 22 Mar 2019 01:07:13 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id CD4922A5B6 for ; Fri, 22 Mar 2019 01:07:12 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id C12BF2A5B9; Fri, 22 Mar 2019 01:07:12 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-2.9 required=2.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,MAILING_LIST_MULTI,RCVD_IN_DNSWL_NONE autolearn=ham version=3.3.1 Received: from alsa0.perex.cz (alsa0.perex.cz [77.48.224.243]) (using TLSv1.2 with cipher DHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.wl.linuxfoundation.org (Postfix) with ESMTPS id 28E212A5B7 for ; Fri, 22 Mar 2019 01:07:12 +0000 (UTC) Received: from alsa1.perex.cz (alsa1.perex.cz [207.180.221.201]) (using TLSv1.2 with cipher AECDH-AES256-SHA (256/256 bits)) (No client certificate requested) by alsa0.perex.cz (Postfix) with ESMTPS id 5A43C15E4; Fri, 22 Mar 2019 02:06:20 +0100 (CET) DKIM-Filter: OpenDKIM Filter v2.11.0 alsa0.perex.cz 5A43C15E4 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=alsa-project.org; s=default; t=1553216830; bh=YiGAa865oUtM6MOq0WZ+LxmgADtcyWKgZ9fQo6wYnbw=; h=From:To:Date:In-Reply-To:References:Cc:Subject:List-Id: List-Unsubscribe:List-Archive:List-Post:List-Help:List-Subscribe: From; b=ltkxl+A2GfaaOA65PgG8vVp+fGuul59pbNIcoPuD9rCsEYR9z3BQAHMJuA3GdMgar 4SpVroepfE97zMnb0rUDuX2LDMQ8ZwSl1zFDB57ggiPwtfCfrRpoUhB9Zx2mbUVzNo SXDVtPdUx8Ahy1a3LQwz7QjRMHgmO1Ur3D4iVypU= Received: from alsa1.perex.cz (localhost.localdomain [127.0.0.1]) by alsa1.perex.cz (Postfix) with ESMTP id EB67AF8973F; Fri, 22 Mar 2019 01:59:25 +0100 (CET) X-Original-To: alsa-devel@alsa-project.org Delivered-To: alsa-devel@alsa-project.org Received: by alsa1.perex.cz (Postfix, from userid 50401) id 8DDBAF89721; Fri, 22 Mar 2019 01:59:18 +0100 (CET) Received: from smtp73.ord1d.emailsrvr.com (smtp73.ord1d.emailsrvr.com [184.106.54.73]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by alsa1.perex.cz (Postfix) with ESMTPS id 32877F8971E for ; Fri, 22 Mar 2019 01:59:15 +0100 (CET) DKIM-Filter: OpenDKIM Filter v2.11.0 alsa1.perex.cz 32877F8971E Received: from smtp18.relay.ord1d.emailsrvr.com (localhost [127.0.0.1]) by smtp18.relay.ord1d.emailsrvr.com (SMTP Server) with ESMTP id 26CDEA029F; Thu, 21 Mar 2019 20:59:08 -0400 (EDT) X-SMTPDoctor-Processed: csmtpprox beta Received: from smtp18.relay.ord1d.emailsrvr.com (localhost [127.0.0.1]) by smtp18.relay.ord1d.emailsrvr.com (SMTP Server) with ESMTP id 22EB8A02DD; Thu, 21 Mar 2019 20:59:08 -0400 (EDT) X-Auth-ID: mcdermj@xenotropic.com Received: by smtp18.relay.ord1d.emailsrvr.com (Authenticated sender: mcdermj-AT-xenotropic.com) with ESMTPSA id 99DC5A029F; Thu, 21 Mar 2019 20:59:07 -0400 (EDT) X-Sender-Id: mcdermj@xenotropic.com Received: from commune.xenotropic.com (c-73-96-52-102.hsd1.or.comcast.net [73.96.52.102]) (using TLSv1.2 with cipher DHE-RSA-AES128-GCM-SHA256) by 0.0.0.0:25 (trex/5.7.12); Thu, 21 Mar 2019 20:59:08 -0400 From: Annaliese McDermond To: broonie@kernel.org, alsa-devel@alsa-project.org Date: Thu, 21 Mar 2019 17:58:54 -0700 Message-Id: <20190322005854.23360-11-nh6z@nh6z.net> X-Mailer: git-send-email 2.19.1 In-Reply-To: <20190322005854.23360-1-nh6z@nh6z.net> References: <20190322005854.23360-1-nh6z@nh6z.net> MIME-Version: 1.0 Cc: team@nwdigitalradio.com, Annaliese McDermond Subject: [alsa-devel] [PATCH v4 10/10] ASoC: tlv320aic32x4: Allow 192000 Sample Rate X-BeenThere: alsa-devel@alsa-project.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: "Alsa-devel mailing list for ALSA developers - http://www.alsa-project.org" List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: alsa-devel-bounces@alsa-project.org Sender: "Alsa-devel" X-Virus-Scanned: ClamAV using ClamSMTP The clocking and processing blocks are now properly set up to support 192000 sample rates. Allow drivers to ask for that. Signed-off-by: Annaliese McDermond --- sound/soc/codecs/tlv320aic32x4.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/sound/soc/codecs/tlv320aic32x4.c b/sound/soc/codecs/tlv320aic32x4.c index a5457d3de1b1..75443efeda69 100644 --- a/sound/soc/codecs/tlv320aic32x4.c +++ b/sound/soc/codecs/tlv320aic32x4.c @@ -857,7 +857,7 @@ static int aic32x4_set_bias_level(struct snd_soc_component *component, return 0; } -#define AIC32X4_RATES SNDRV_PCM_RATE_8000_96000 +#define AIC32X4_RATES SNDRV_PCM_RATE_8000_192000 #define AIC32X4_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S20_3LE \ | SNDRV_PCM_FMTBIT_S24_3LE | SNDRV_PCM_FMTBIT_S32_LE)