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Fri, 22 Mar 2019 01:48:06 +0000 From: Anson Huang To: "thierry.reding@gmail.com" , "robh+dt@kernel.org" , "mark.rutland@arm.com" , "shawnguo@kernel.org" , "s.hauer@pengutronix.de" , "kernel@pengutronix.de" , "festevam@gmail.com" , "linux@armlinux.org.uk" , "stefan@agner.ch" , "otavio@ossystems.com.br" , Leonard Crestez , Robin Gong , "jan.tuerk@emtrion.com" , "linux-pwm@vger.kernel.org" , "devicetree@vger.kernel.org" , "linux-arm-kernel@lists.infradead.org" , "linux-kernel@vger.kernel.org" , "u.kleine-koenig@pengutronix.de" Subject: [PATCH V9 1/5] dt-bindings: pwm: Add i.MX TPM PWM binding Thread-Topic: [PATCH V9 1/5] dt-bindings: pwm: Add i.MX TPM PWM binding Thread-Index: AQHU4FFLawhysUr2ckuOKuIEIybWsQ== Date: Fri, 22 Mar 2019 01:48:05 +0000 Message-ID: <1553218974-20464-2-git-send-email-Anson.Huang@nxp.com> References: <1553218974-20464-1-git-send-email-Anson.Huang@nxp.com> In-Reply-To: <1553218974-20464-1-git-send-email-Anson.Huang@nxp.com> Accept-Language: en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: x-mailer: git-send-email 2.7.4 x-clientproxiedby: HK2PR02CA0172.apcprd02.prod.outlook.com (2603:1096:201:1f::32) To DB3PR0402MB3916.eurprd04.prod.outlook.com (2603:10a6:8:10::18) x-ms-exchange-messagesentrepresentingtype: 1 x-originating-ip: [119.31.174.67] x-ms-publictraffictype: Email x-ms-office365-filtering-correlation-id: cdd297c1-dc8d-4e44-1b4f-08d6ae686d75 x-ms-office365-filtering-ht: Tenant x-microsoft-antispam: BCL:0; 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Signed-off-by: Anson Huang --- No changes. --- .../devicetree/bindings/pwm/imx-tpm-pwm.txt | 22 ++++++++++++++++++++++ 1 file changed, 22 insertions(+) create mode 100644 Documentation/devicetree/bindings/pwm/imx-tpm-pwm.txt diff --git a/Documentation/devicetree/bindings/pwm/imx-tpm-pwm.txt b/Documentation/devicetree/bindings/pwm/imx-tpm-pwm.txt new file mode 100644 index 0000000..94f1ad5 --- /dev/null +++ b/Documentation/devicetree/bindings/pwm/imx-tpm-pwm.txt @@ -0,0 +1,22 @@ +Freescale i.MX TPM PWM controller + +Required properties: +- compatible : Should be "fsl,imx-tpm". +- reg: Physical base address and length of the controller's registers. +- #pwm-cells: Should be 3. See pwm.txt in this directory for a description of the cells format. +- clocks : The clock provided by the SoC to drive the PWM. +- interrupts: The interrupt for the PWM controller. + +Note: The TPM counter and period counter are shared between multiple channels, so all channels +should use same period setting. + +Example: + +pwm0: tpm@40250000 { + compatible = "fsl,imx-tpm"; + reg = <0x40250000 0x1000>; + assigned-clocks = <&clks IMX7ULP_CLK_LPTPM4>; + assigned-clock-parents = <&clks IMX7ULP_CLK_SOSC_BUS_CLK>; + clocks = <&clks IMX7ULP_CLK_LPTPM4>; + #pwm-cells = <3>; +}; From patchwork Fri Mar 22 01:48:11 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Anson Huang X-Patchwork-Id: 10864799 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 075A8922 for ; Fri, 22 Mar 2019 01:48:36 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id D79722A584 for ; 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bh=Uc+bKzvtUg4pPh8cJTXcqhYJsjREhd55oBNcYQik6nk=; b=BPsKdPzsV4TDXH5bqxAm+aJJk6ShIwHIiYjIQ+DN/ddpH1h9Dqi52HskhFjBg1NGxVEY7C6M6COH4VGLHwxL9GWWBQZMzZDoZ6un1tNnBO9N3VW8ihAw5Ue787euC+QRePyV1a0TZXYY4sNECBDe7N2IAnNY1Rd0wfr76yYsT0c= Received: from DB3PR0402MB3916.eurprd04.prod.outlook.com (52.134.72.18) by DB3PR0402MB3754.eurprd04.prod.outlook.com (52.134.67.26) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.1730.15; Fri, 22 Mar 2019 01:48:12 +0000 Received: from DB3PR0402MB3916.eurprd04.prod.outlook.com ([fe80::f1b4:a1fb:cfd1:3f08]) by DB3PR0402MB3916.eurprd04.prod.outlook.com ([fe80::f1b4:a1fb:cfd1:3f08%7]) with mapi id 15.20.1730.013; Fri, 22 Mar 2019 01:48:12 +0000 From: Anson Huang To: "thierry.reding@gmail.com" , "robh+dt@kernel.org" , "mark.rutland@arm.com" , "shawnguo@kernel.org" , "s.hauer@pengutronix.de" , "kernel@pengutronix.de" , "festevam@gmail.com" , "linux@armlinux.org.uk" , "stefan@agner.ch" , "otavio@ossystems.com.br" , Leonard Crestez , Robin Gong , "jan.tuerk@emtrion.com" , "linux-pwm@vger.kernel.org" , "devicetree@vger.kernel.org" , "linux-arm-kernel@lists.infradead.org" , "linux-kernel@vger.kernel.org" , "u.kleine-koenig@pengutronix.de" Subject: [PATCH V9 2/5] pwm: Add i.MX TPM PWM driver support Thread-Topic: [PATCH V9 2/5] pwm: Add i.MX TPM PWM driver support Thread-Index: AQHU4FFOpecAv9hHzEalsnukYYli6Q== Date: Fri, 22 Mar 2019 01:48:11 +0000 Message-ID: <1553218974-20464-3-git-send-email-Anson.Huang@nxp.com> References: <1553218974-20464-1-git-send-email-Anson.Huang@nxp.com> In-Reply-To: <1553218974-20464-1-git-send-email-Anson.Huang@nxp.com> Accept-Language: en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: x-mailer: git-send-email 2.7.4 x-clientproxiedby: HK2PR02CA0172.apcprd02.prod.outlook.com (2603:1096:201:1f::32) To DB3PR0402MB3916.eurprd04.prod.outlook.com (2603:10a6:8:10::18) x-ms-exchange-messagesentrepresentingtype: 1 x-originating-ip: [119.31.174.67] x-ms-publictraffictype: Email x-ms-office365-filtering-correlation-id: cf029ce1-f613-4e23-4f87-08d6ae687110 x-ms-office365-filtering-ht: Tenant x-microsoft-antispam: BCL:0; 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FPR:; SPF:None; LANG:en; PTR:InfoNoRecords; MX:1; A:1; received-spf: None (protection.outlook.com: nxp.com does not designate permitted sender hosts) authentication-results: spf=none (sender IP is ) smtp.mailfrom=anson.huang@nxp.com; x-ms-exchange-senderadcheck: 1 x-microsoft-antispam-message-info: 5/WTywNUNu9F+JcryyypHFoMeVlH6PYmOIpW6GmJfcsBRka5x7gv6CeM+W7vuXwwdk1D9mawe9y7gLLhHLATGyoH+AtbpEtpmMoKTxv0sGpdN/WbGGzHHfhJirdNVKycD4VRKWpvUZ+NVV3o/ZMWLJ0EDKwE2+E59/wqYrmsZD6eby+FMPIjWXFmmwbJtXFNu8irfcT1v/p8/MGbmEbubEytTD3Ly/NUC77rUulZAqcUjEVqtly6iWiosAYyRu9XMLLuhRa91rrczIlvsPR/XdO9YlGcs8h1o0fx1RqKU896z2ddZEk+xQOh2rlGL3xHdPo2u4+BUyyoGvLYKzyjIg1h7N5doV6BpsVDfT3TefhqNszlfIeD7OAu/SQYRjsr7AMF7PaVp5XNRXheu9oxozV8PIZBgrMka/yHw/TyZAw= Content-ID: MIME-Version: 1.0 X-OriginatorOrg: nxp.com X-MS-Exchange-CrossTenant-Network-Message-Id: cf029ce1-f613-4e23-4f87-08d6ae687110 X-MS-Exchange-CrossTenant-originalarrivaltime: 22 Mar 2019 01:48:11.9612 (UTC) X-MS-Exchange-CrossTenant-fromentityheader: Hosted X-MS-Exchange-CrossTenant-id: 686ea1d3-bc2b-4c6f-a92c-d99c5c301635 X-MS-Exchange-CrossTenant-mailboxtype: HOSTED X-MS-Exchange-Transport-CrossTenantHeadersStamped: DB3PR0402MB3754 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20190321_184815_536162_7B554147 X-CRM114-Status: GOOD ( 24.18 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: dl-linux-imx Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org X-Virus-Scanned: ClamAV using ClamSMTP i.MX7ULP has TPM(Low Power Timer/Pulse Width Modulation Module) inside, it can support multiple PWM channels, all the channels share same counter and period setting, but each channel can configure its duty and polarity independently. There are several TPM modules in i.MX7ULP, the number of channels in TPM modules are different, it can be read from each TPM module's PARAM register. Signed-off-by: Anson Huang --- Changes since V8: - add more limitation notes for period/duty update un-atomic limitations; - add waiting for period/duty update actually applied to HW; - move the duty update into period update function to make them to be updated as together as possiable; - don't allow PS change if counter is running; - save channel polarity settings and return it directly when .get_state is called, as the HW polarity setting could be impacted by enable status. --- drivers/pwm/Kconfig | 11 + drivers/pwm/Makefile | 1 + drivers/pwm/pwm-imx-tpm.c | 518 ++++++++++++++++++++++++++++++++++++++++++++++ 3 files changed, 530 insertions(+) create mode 100644 drivers/pwm/pwm-imx-tpm.c diff --git a/drivers/pwm/Kconfig b/drivers/pwm/Kconfig index 54f8238..3ea0391 100644 --- a/drivers/pwm/Kconfig +++ b/drivers/pwm/Kconfig @@ -210,6 +210,17 @@ config PWM_IMX27 To compile this driver as a module, choose M here: the module will be called pwm-imx27. +config PWM_IMX_TPM + tristate "i.MX TPM PWM support" + depends on ARCH_MXC || COMPILE_TEST + depends on HAVE_CLK && HAS_IOMEM + help + Generic PWM framework driver for i.MX7ULP TPM module, TPM's full + name is Low Power Timer/Pulse Width Modulation Module. + + To compile this driver as a module, choose M here: the module + will be called pwm-imx-tpm. + config PWM_JZ4740 tristate "Ingenic JZ47xx PWM support" depends on MACH_INGENIC diff --git a/drivers/pwm/Makefile b/drivers/pwm/Makefile index 448825e..c368599 100644 --- a/drivers/pwm/Makefile +++ b/drivers/pwm/Makefile @@ -19,6 +19,7 @@ obj-$(CONFIG_PWM_HIBVT) += pwm-hibvt.o obj-$(CONFIG_PWM_IMG) += pwm-img.o obj-$(CONFIG_PWM_IMX1) += pwm-imx1.o obj-$(CONFIG_PWM_IMX27) += pwm-imx27.o +obj-$(CONFIG_PWM_IMX_TPM) += pwm-imx-tpm.o obj-$(CONFIG_PWM_JZ4740) += pwm-jz4740.o obj-$(CONFIG_PWM_LP3943) += pwm-lp3943.o obj-$(CONFIG_PWM_LPC18XX_SCT) += pwm-lpc18xx-sct.o diff --git a/drivers/pwm/pwm-imx-tpm.c b/drivers/pwm/pwm-imx-tpm.c new file mode 100644 index 0000000..58af0915 --- /dev/null +++ b/drivers/pwm/pwm-imx-tpm.c @@ -0,0 +1,518 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright 2018-2019 NXP. + * + * Limitations: + * - The TPM counter and period counter are shared between + * multiple channels, so all channels should use same period + * settings. + * - Changes to polarity cannot be latched at the time of the + * next period start. + * - The period and duty changes are NOT atomic, if new period and + * new duty are requested simultaneously when counter is running, + * there could be a small window of running old duty with new + * period, as the period is updated before duty in this driver, the + * probability is very low, ONLY happen when the TPM counter changes + * from MOD to zero between the consecutive update of period and + * duty. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#define PWM_IMX_TPM_PARAM 0x4 +#define PWM_IMX_TPM_GLOBAL 0x8 +#define PWM_IMX_TPM_SC 0x10 +#define PWM_IMX_TPM_CNT 0x14 +#define PWM_IMX_TPM_MOD 0x18 +#define PWM_IMX_TPM_CnSC(n) (0x20 + (n) * 0x8) +#define PWM_IMX_TPM_CnV(n) (0x24 + (n) * 0x8) + +#define PWM_IMX_TPM_PARAM_CHAN GENMASK(7, 0) + +#define PWM_IMX_TPM_SC_PS GENMASK(2, 0) +#define PWM_IMX_TPM_SC_CMOD GENMASK(4, 3) +#define PWM_IMX_TPM_SC_CMOD_INC_EVERY_CLK FIELD_PREP(PWM_IMX_TPM_SC_CMOD, 1) +#define PWM_IMX_TPM_SC_CPWMS BIT(5) + +#define PWM_IMX_TPM_CnSC_CHF BIT(7) +#define PWM_IMX_TPM_CnSC_MSB BIT(5) +#define PWM_IMX_TPM_CnSC_MSA BIT(4) + +/* + * The reference manual describes this field as two separate bits. The + * samantic of the two bits isn't orthogonal though, so they are treated + * together as a 2-bit field here. + */ +#define PWM_IMX_TPM_CnSC_ELS GENMASK(3, 2) +#define PWM_IMX_TPM_CnSC_ELS_POLARITY_INVERSED 0x1 +#define PWM_IMX_TPM_CnSC_ELS_INVERSED FIELD_PREP(PWM_IMX_TPM_CnSC_ELS, 1) +#define PWM_IMX_TPM_CnSC_ELS_NORMAL FIELD_PREP(PWM_IMX_TPM_CnSC_ELS, 2) + + +#define PWM_IMX_TPM_MOD_WIDTH 16 +#define PWM_IMX_TPM_MOD_MOD GENMASK(PWM_IMX_TPM_MOD_WIDTH - 1, 0) + +struct imx_tpm_pwm_chip { + struct pwm_chip chip; + struct clk *clk; + void __iomem *base; + struct mutex lock; + u32 user_count; + u32 enable_count; + u32 real_period; +}; + +struct imx_tpm_pwm_param { + u8 prescale; + u32 mod; + u32 val; +}; + +struct imx_tpm_pwm_channel { + enum pwm_polarity polarity; +}; + +static inline struct imx_tpm_pwm_chip *to_imx_tpm_pwm_chip(struct pwm_chip *chip) +{ + return container_of(chip, struct imx_tpm_pwm_chip, chip); +} + +static int pwm_imx_tpm_round_state(struct pwm_chip *chip, + struct imx_tpm_pwm_param *p, + struct pwm_state *state, + struct pwm_state *real_state) +{ + struct imx_tpm_pwm_chip *tpm = to_imx_tpm_pwm_chip(chip); + u32 rate, prescale, period_count, clock_unit; + u64 tmp; + + rate = clk_get_rate(tpm->clk); + tmp = (u64)state->period * rate; + clock_unit = DIV_ROUND_CLOSEST_ULL(tmp, NSEC_PER_SEC); + if (clock_unit <= PWM_IMX_TPM_MOD_MOD) + prescale = 0; + else + prescale = ilog2(clock_unit) + 1 - PWM_IMX_TPM_MOD_WIDTH; + + if ((!FIELD_FIT(PWM_IMX_TPM_SC_PS, prescale))) + return -ERANGE; + p->prescale = prescale; + + period_count = (clock_unit + ((1 << prescale) >> 1)) >> prescale; + p->mod = period_count; + + /* calculate real period HW can support */ + tmp = (u64)period_count << prescale; + tmp *= NSEC_PER_SEC; + real_state->period = DIV_ROUND_CLOSEST_ULL(tmp, rate); + + /* + * if eventually the PWM output is inactive, either + * duty cycle is 0 or status is disabled, need to + * make sure the output pin is inactive. + */ + if (!state->enabled) + real_state->duty_cycle = 0; + else + real_state->duty_cycle = state->duty_cycle; + + tmp = (u64)p->mod * real_state->duty_cycle; + p->val = DIV_ROUND_CLOSEST_ULL(tmp, real_state->period); + + real_state->polarity = state->polarity; + real_state->enabled = state->enabled; + + return 0; +} + +/* this function is supposed to be called with mutex hold */ +static int pwm_imx_tpm_setup_period_duty(struct pwm_chip *chip, + struct pwm_device *pwm, + struct imx_tpm_pwm_param *p) +{ + struct imx_tpm_pwm_chip *tpm = to_imx_tpm_pwm_chip(chip); + unsigned long timeout; + u32 val, cmod, cur_prescale; + + val = readl(tpm->base + PWM_IMX_TPM_SC); + cmod = FIELD_GET(PWM_IMX_TPM_SC_CMOD, val); + cur_prescale = FIELD_GET(PWM_IMX_TPM_SC_PS, val); + if (cmod && cur_prescale != p->prescale) + return -EBUSY; + + /* set TPM counter prescale */ + val &= ~PWM_IMX_TPM_SC_PS; + val |= FIELD_PREP(PWM_IMX_TPM_SC_PS, p->prescale); + writel(val, tpm->base + PWM_IMX_TPM_SC); + + /* + * set period count: + * if (CMOD[1:0] = 0:0) then MOD register is updated when MOD + * register is written. + * + * if (CMOD[1:0] ≠ 0:0), then MOD register is updated according + * to the CPWMS bit, that is: + * + * if the selected mode is not CPWM then MOD register is updated + * after MOD register was written and the TPM counter changes from + * MOD to zero. + * + * if the selected mode is CPWM then MOD register is updated after + * MOD register was written and the TPM counter changes from MOD + * to (MOD – 1). + */ + writel(p->mod, tpm->base + PWM_IMX_TPM_MOD); + + /* + * set channel value: + * if (CMOD[1:0] = 0:0) then CnV register is updated when CnV + * register is written. + * + * if (CMOD[1:0] ≠ 0:0), then CnV register is updated according + * to the selected mode, that is: + * + * if the selected mode is output compare then CnV register is + * updated on the next TPM counter increment (end of the prescaler + * counting) after CnV register was written. + * + * if the selected mode is EPWM then CnV register is updated after + * CnV register was written and the TPM counter changes from MOD + * to zero. + * + * if the selected mode is CPWM then CnV register is updated after + * CnV register was written and the TPM counter changes from MOD + * to (MOD – 1). + */ + writel(p->val, tpm->base + PWM_IMX_TPM_CnV(pwm->hwpwm)); + + /* make sure MOD & CnV registers are updated */ + timeout = jiffies + msecs_to_jiffies(tpm->real_period / + NSEC_PER_MSEC + 1); + while (readl(tpm->base + PWM_IMX_TPM_MOD) != p->mod + || readl(tpm->base + PWM_IMX_TPM_CnV(pwm->hwpwm)) + != p->val) { + if (time_after(jiffies, timeout)) + return -ETIME; + cpu_relax(); + } + + return 0; +} + +static void pwm_imx_tpm_get_state(struct pwm_chip *chip, + struct pwm_device *pwm, + struct pwm_state *state) +{ + struct imx_tpm_pwm_chip *tpm = to_imx_tpm_pwm_chip(chip); + struct imx_tpm_pwm_channel *chan = pwm_get_chip_data(pwm); + u32 rate, val, prescale; + u64 tmp; + + /* get period */ + state->period = tpm->real_period; + + /* get duty cycle */ + rate = clk_get_rate(tpm->clk); + val = readl(tpm->base + PWM_IMX_TPM_SC); + prescale = FIELD_GET(PWM_IMX_TPM_SC_PS, val); + tmp = readl(tpm->base + PWM_IMX_TPM_CnV(pwm->hwpwm)); + tmp = (tmp << prescale) * NSEC_PER_SEC; + state->duty_cycle = DIV_ROUND_CLOSEST_ULL(tmp, rate); + + /* get polarity */ + if (chan) { + state->polarity = chan->polarity; + } else { + /* in case no channel requested yet, return HW status */ + val = readl(tpm->base + PWM_IMX_TPM_CnSC(pwm->hwpwm)); + if (FIELD_GET(PWM_IMX_TPM_CnSC_ELS, val) == + PWM_IMX_TPM_CnSC_ELS_POLARITY_INVERSED) + state->polarity = PWM_POLARITY_INVERSED; + else + /* + * Assume reserved values (2b00 and 2b11) to yield + * normal polarity. + */ + state->polarity = PWM_POLARITY_NORMAL; + } + + /* get channel status */ + state->enabled = FIELD_GET(PWM_IMX_TPM_CnSC_ELS, val) ? true : false; +} + +/* this function is supposed to be called with mutex hold */ +static int pwm_imx_tpm_apply_hw(struct pwm_chip *chip, + struct pwm_device *pwm, + struct pwm_state *state) +{ + struct imx_tpm_pwm_chip *tpm = to_imx_tpm_pwm_chip(chip); + struct imx_tpm_pwm_channel *chan = pwm_get_chip_data(pwm); + unsigned long timeout; + struct pwm_state c; + u32 val; + u64 tmp; + + pwm_imx_tpm_get_state(chip, pwm, &c); + + if (state->duty_cycle != c.duty_cycle) { + /* set duty counter */ + tmp = readl(tpm->base + PWM_IMX_TPM_MOD) & PWM_IMX_TPM_MOD_MOD; + tmp *= state->duty_cycle; + val = DIV_ROUND_CLOSEST_ULL(tmp, state->period); + writel(val, tpm->base + PWM_IMX_TPM_CnV(pwm->hwpwm)); + + /* make sure CnV register is updated */ + timeout = jiffies + msecs_to_jiffies(tpm->real_period / + NSEC_PER_MSEC + 1); + while (readl(tpm->base + PWM_IMX_TPM_CnV(pwm->hwpwm)) != val) { + if (time_after(jiffies, timeout)) + return -ETIME; + cpu_relax(); + } + } + + val = readl(tpm->base + PWM_IMX_TPM_CnSC(pwm->hwpwm)); + val &= ~(PWM_IMX_TPM_CnSC_ELS | PWM_IMX_TPM_CnSC_MSA | + PWM_IMX_TPM_CnSC_MSB); + if (state->enabled) { + /* + * set polarity (for edge-aligned PWM modes) + * + * ELS[1:0] = 2b10 yields normal polarity behaviour, + * ELS[1:0] = 2b01 yields inversed polarity. + * The other values are reserved. + * + * polarity settings will enabled/disable output status + * immediately, so if the channel is disabled, need to + * make sure MSA/MSB/ELS are set to 0 which means channel + * disabled. + */ + val |= PWM_IMX_TPM_CnSC_MSB; + val |= (state->polarity == PWM_POLARITY_NORMAL) ? + PWM_IMX_TPM_CnSC_ELS_NORMAL : + PWM_IMX_TPM_CnSC_ELS_INVERSED; + } + writel(val, tpm->base + PWM_IMX_TPM_CnSC(pwm->hwpwm)); + + /* control the counter status */ + if (state->enabled != c.enabled) { + val = readl(tpm->base + PWM_IMX_TPM_SC); + if (state->enabled) { + if (++tpm->enable_count == 1) + val |= PWM_IMX_TPM_SC_CMOD_INC_EVERY_CLK; + } else { + if (--tpm->enable_count == 0) + val &= ~PWM_IMX_TPM_SC_CMOD; + } + writel(val, tpm->base + PWM_IMX_TPM_SC); + } + + /* save last polarity setting */ + chan->polarity = state->polarity; + + return 0; +} + +static int pwm_imx_tpm_apply(struct pwm_chip *chip, + struct pwm_device *pwm, + struct pwm_state *state) +{ + struct imx_tpm_pwm_chip *tpm = to_imx_tpm_pwm_chip(chip); + struct imx_tpm_pwm_param param; + struct pwm_state real_state; + int ret; + + ret = pwm_imx_tpm_round_state(chip, ¶m, state, &real_state); + if (ret) + return -EINVAL; + + mutex_lock(&tpm->lock); + + /* + * TPM counter is shared by multiple channels, so + * prescale and period can NOT be modified when + * there are multiple channels in use with different + * period settings. + */ + if (real_state.period != tpm->real_period) { + if (tpm->user_count > 1) { + ret = -EBUSY; + goto exit; + } + + ret = pwm_imx_tpm_setup_period_duty(chip, pwm, ¶m); + if (ret) + goto exit; + + tpm->real_period = real_state.period; + } + + ret = pwm_imx_tpm_apply_hw(chip, pwm, &real_state); + +exit: + mutex_unlock(&tpm->lock); + + return ret; +} + +static int pwm_imx_tpm_request(struct pwm_chip *chip, struct pwm_device *pwm) +{ + struct imx_tpm_pwm_chip *tpm = to_imx_tpm_pwm_chip(chip); + struct imx_tpm_pwm_channel *chan; + + chan = devm_kzalloc(chip->dev, sizeof(*chan), GFP_KERNEL); + if (!chan) + return -ENOMEM; + + pwm_set_chip_data(pwm, chan); + + mutex_lock(&tpm->lock); + tpm->user_count++; + mutex_unlock(&tpm->lock); + + return 0; +} + +static void pwm_imx_tpm_free(struct pwm_chip *chip, struct pwm_device *pwm) +{ + struct imx_tpm_pwm_chip *tpm = to_imx_tpm_pwm_chip(chip); + + mutex_lock(&tpm->lock); + tpm->user_count--; + mutex_unlock(&tpm->lock); + + devm_kfree(chip->dev, pwm_get_chip_data(pwm)); + pwm_set_chip_data(pwm, NULL); +} + +static const struct pwm_ops imx_tpm_pwm_ops = { + .request = pwm_imx_tpm_request, + .free = pwm_imx_tpm_free, + .get_state = pwm_imx_tpm_get_state, + .apply = pwm_imx_tpm_apply, + .owner = THIS_MODULE, +}; + +static int pwm_imx_tpm_probe(struct platform_device *pdev) +{ + struct imx_tpm_pwm_chip *tpm; + int ret; + u32 val; + + tpm = devm_kzalloc(&pdev->dev, sizeof(*tpm), GFP_KERNEL); + if (!tpm) + return -ENOMEM; + + platform_set_drvdata(pdev, tpm); + + tpm->base = devm_platform_ioremap_resource(pdev, 0); + if (IS_ERR(tpm->base)) + return PTR_ERR(tpm->base); + + tpm->clk = devm_clk_get(&pdev->dev, NULL); + if (IS_ERR(tpm->clk)) { + ret = PTR_ERR(tpm->clk); + if (ret != -EPROBE_DEFER) + dev_err(&pdev->dev, + "failed to get PWM clock: %d\n", ret); + return ret; + } + + ret = clk_prepare_enable(tpm->clk); + if (ret) { + dev_err(&pdev->dev, + "failed to prepare or enable clock: %d\n", ret); + return ret; + } + + tpm->chip.dev = &pdev->dev; + tpm->chip.ops = &imx_tpm_pwm_ops; + tpm->chip.base = -1; + tpm->chip.of_xlate = of_pwm_xlate_with_flags; + tpm->chip.of_pwm_n_cells = 3; + + /* get number of channels */ + val = readl(tpm->base + PWM_IMX_TPM_PARAM); + tpm->chip.npwm = FIELD_GET(PWM_IMX_TPM_PARAM_CHAN, val); + + mutex_init(&tpm->lock); + + ret = pwmchip_add(&tpm->chip); + if (ret) { + dev_err(&pdev->dev, "failed to add PWM chip: %d\n", ret); + clk_disable_unprepare(tpm->clk); + } + + return ret; +} + +static int pwm_imx_tpm_remove(struct platform_device *pdev) +{ + struct imx_tpm_pwm_chip *tpm = platform_get_drvdata(pdev); + int ret = pwmchip_remove(&tpm->chip); + + clk_disable_unprepare(tpm->clk); + + return ret; +} + +static int __maybe_unused pwm_imx_tpm_suspend(struct device *dev) +{ + struct imx_tpm_pwm_chip *tpm = dev_get_drvdata(dev); + + if (tpm->enable_count > 0) + return -EBUSY; + + clk_disable_unprepare(tpm->clk); + + return 0; +} + +static int __maybe_unused pwm_imx_tpm_resume(struct device *dev) +{ + struct imx_tpm_pwm_chip *tpm = dev_get_drvdata(dev); + int ret = 0; + + ret = clk_prepare_enable(tpm->clk); + if (ret) + dev_err(dev, + "failed to prepare or enable clock: %d\n", + ret); + + return ret; +} + +static SIMPLE_DEV_PM_OPS(imx_tpm_pwm_pm, + pwm_imx_tpm_suspend, pwm_imx_tpm_resume); + +static const struct of_device_id imx_tpm_pwm_dt_ids[] = { + { .compatible = "fsl,imx-tpm", }, + { /* sentinel */ } +}; +MODULE_DEVICE_TABLE(of, imx_tpm_pwm_dt_ids); + +static struct platform_driver imx_tpm_pwm_driver = { + .driver = { + .name = "imx-tpm-pwm", + .of_match_table = imx_tpm_pwm_dt_ids, + .pm = &imx_tpm_pwm_pm, + }, + .probe = pwm_imx_tpm_probe, + .remove = pwm_imx_tpm_remove, +}; +module_platform_driver(imx_tpm_pwm_driver); + +MODULE_AUTHOR("Anson Huang "); +MODULE_DESCRIPTION("i.MX TPM PWM Driver"); +MODULE_LICENSE("GPL v2"); From patchwork Fri Mar 22 01:48:18 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Anson Huang X-Patchwork-Id: 10864801 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id A378A14DE for ; Fri, 22 Mar 2019 01:48:53 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 777D32A584 for ; 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bh=1QsgBow0rRm9AatOX7NIo7cays5MrnLK1+PmTnmOXl0=; b=tYwPLSuCx4Id9cXyoonHNxFazSltJUbvfzuhqbTlAiPeTb/p2YSTwwhskPW+ZHalyvUhgXux7qYfTIh7PCQKuUSpVadXRsrM0kgLUd70c4v9XAiFvuZ9nbghOd12ad22xDOW/bPwgi96BZbfZXGf8UyxPbxUyqvovF8zAwGrdPw= Received: from DB3PR0402MB3916.eurprd04.prod.outlook.com (52.134.72.18) by DB3PR0402MB3754.eurprd04.prod.outlook.com (52.134.67.26) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.1730.15; Fri, 22 Mar 2019 01:48:18 +0000 Received: from DB3PR0402MB3916.eurprd04.prod.outlook.com ([fe80::f1b4:a1fb:cfd1:3f08]) by DB3PR0402MB3916.eurprd04.prod.outlook.com ([fe80::f1b4:a1fb:cfd1:3f08%7]) with mapi id 15.20.1730.013; Fri, 22 Mar 2019 01:48:18 +0000 From: Anson Huang To: "thierry.reding@gmail.com" , "robh+dt@kernel.org" , "mark.rutland@arm.com" , "shawnguo@kernel.org" , "s.hauer@pengutronix.de" , "kernel@pengutronix.de" , "festevam@gmail.com" , "linux@armlinux.org.uk" , "stefan@agner.ch" , "otavio@ossystems.com.br" , Leonard Crestez , Robin Gong , "jan.tuerk@emtrion.com" , "linux-pwm@vger.kernel.org" , "devicetree@vger.kernel.org" , "linux-arm-kernel@lists.infradead.org" , "linux-kernel@vger.kernel.org" , "u.kleine-koenig@pengutronix.de" Subject: [PATCH V9 3/5] ARM: imx_v6_v7_defconfig: Add TPM PWM support by default Thread-Topic: [PATCH V9 3/5] ARM: imx_v6_v7_defconfig: Add TPM PWM support by default Thread-Index: AQHU4FFS3v7ojFB32kucwKUOCj4FIg== Date: Fri, 22 Mar 2019 01:48:18 +0000 Message-ID: <1553218974-20464-4-git-send-email-Anson.Huang@nxp.com> References: <1553218974-20464-1-git-send-email-Anson.Huang@nxp.com> In-Reply-To: <1553218974-20464-1-git-send-email-Anson.Huang@nxp.com> Accept-Language: en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: x-mailer: git-send-email 2.7.4 x-clientproxiedby: HK2PR02CA0172.apcprd02.prod.outlook.com (2603:1096:201:1f::32) To DB3PR0402MB3916.eurprd04.prod.outlook.com (2603:10a6:8:10::18) x-ms-exchange-messagesentrepresentingtype: 1 x-originating-ip: [119.31.174.67] x-ms-publictraffictype: Email x-ms-office365-filtering-correlation-id: f7dd6617-179f-47a1-f0c9-08d6ae68749b x-ms-office365-filtering-ht: Tenant x-microsoft-antispam: BCL:0; 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Signed-off-by: Anson Huang --- No changes. --- arch/arm/configs/imx_v6_v7_defconfig | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm/configs/imx_v6_v7_defconfig b/arch/arm/configs/imx_v6_v7_defconfig index 1872dac..2a35806 100644 --- a/arch/arm/configs/imx_v6_v7_defconfig +++ b/arch/arm/configs/imx_v6_v7_defconfig @@ -400,6 +400,7 @@ CONFIG_MPL3115=y CONFIG_PWM=y CONFIG_PWM_FSL_FTM=y CONFIG_PWM_IMX=y +CONFIG_PWM_IMX_TPM=y CONFIG_NVMEM_IMX_OCOTP=y CONFIG_NVMEM_VF610_OCOTP=y CONFIG_TEE=y From patchwork Fri Mar 22 01:48:24 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Anson Huang X-Patchwork-Id: 10864803 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 5D39414DE for ; Fri, 22 Mar 2019 01:49:08 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 286862894E for ; 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bh=sVXPzP7KQmQ947uy603ag1TWGDdrV4hItN4yxLswomk=; b=CidsUyLO96ym+e63uUDBTIbBCivGCJ+RaeYig8htw09caIAAnwGagOCbJ0PxnFnF8rNK/h3m40gbzytSY5aLCzxaziPxZf5/ncXawcknlRuXWaCEgA6TRb6ofmBgoW9FdVU6p/uPg82hGEfpoxCTRQVBPamskvVmYf+VFR0xp5w= Received: from DB3PR0402MB3916.eurprd04.prod.outlook.com (52.134.72.18) by DB3PR0402MB3754.eurprd04.prod.outlook.com (52.134.67.26) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.1730.15; Fri, 22 Mar 2019 01:48:24 +0000 Received: from DB3PR0402MB3916.eurprd04.prod.outlook.com ([fe80::f1b4:a1fb:cfd1:3f08]) by DB3PR0402MB3916.eurprd04.prod.outlook.com ([fe80::f1b4:a1fb:cfd1:3f08%7]) with mapi id 15.20.1730.013; Fri, 22 Mar 2019 01:48:24 +0000 From: Anson Huang To: "thierry.reding@gmail.com" , "robh+dt@kernel.org" , "mark.rutland@arm.com" , "shawnguo@kernel.org" , "s.hauer@pengutronix.de" , "kernel@pengutronix.de" , "festevam@gmail.com" , "linux@armlinux.org.uk" , "stefan@agner.ch" , "otavio@ossystems.com.br" , Leonard Crestez , Robin Gong , "jan.tuerk@emtrion.com" , "linux-pwm@vger.kernel.org" , "devicetree@vger.kernel.org" , "linux-arm-kernel@lists.infradead.org" , "linux-kernel@vger.kernel.org" , "u.kleine-koenig@pengutronix.de" Subject: [PATCH V9 4/5] ARM: dts: imx7ulp: Add pwm0 support Thread-Topic: [PATCH V9 4/5] ARM: dts: imx7ulp: Add pwm0 support Thread-Index: AQHU4FFWnnezNzzxM0OvJm5Y1KVEKA== Date: Fri, 22 Mar 2019 01:48:24 +0000 Message-ID: <1553218974-20464-5-git-send-email-Anson.Huang@nxp.com> References: <1553218974-20464-1-git-send-email-Anson.Huang@nxp.com> In-Reply-To: <1553218974-20464-1-git-send-email-Anson.Huang@nxp.com> Accept-Language: en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: x-mailer: git-send-email 2.7.4 x-clientproxiedby: HK2PR02CA0172.apcprd02.prod.outlook.com (2603:1096:201:1f::32) To DB3PR0402MB3916.eurprd04.prod.outlook.com (2603:10a6:8:10::18) x-ms-exchange-messagesentrepresentingtype: 1 x-originating-ip: [119.31.174.67] x-ms-publictraffictype: Email x-ms-office365-filtering-correlation-id: 69a2742e-5f2b-4469-7a39-08d6ae687852 x-ms-office365-filtering-ht: Tenant x-microsoft-antispam: BCL:0; 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Signed-off-by: Anson Huang --- No changes; --- arch/arm/boot/dts/imx7ulp.dtsi | 10 ++++++++++ 1 file changed, 10 insertions(+) diff --git a/arch/arm/boot/dts/imx7ulp.dtsi b/arch/arm/boot/dts/imx7ulp.dtsi index eb349fd..15d04fb 100644 --- a/arch/arm/boot/dts/imx7ulp.dtsi +++ b/arch/arm/boot/dts/imx7ulp.dtsi @@ -124,6 +124,16 @@ status = "disabled"; }; + pwm0: pwm@40250000 { + compatible = "fsl,imx-tpm"; + reg = <0x40250000 0x1000>; + assigned-clocks = <&pcc2 IMX7ULP_CLK_LPTPM4>; + assigned-clock-parents = <&scg1 IMX7ULP_CLK_SOSC_BUS_CLK>; + clocks = <&pcc2 IMX7ULP_CLK_LPTPM4>; + #pwm-cells = <3>; + status = "disabled"; + }; + tpm5: tpm@40260000 { compatible = "fsl,imx7ulp-tpm"; reg = <0x40260000 0x1000>; From patchwork Fri Mar 22 01:48:30 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Anson Huang X-Patchwork-Id: 10864805 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 3FCF514DE for ; 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bh=3RzwAE7/kX/wTe3EaKtsByn0tAbNPwKGvMQxU9VxZ/I=; b=hML0GvRe9Y+XWlA2wihCXoMUUeR8BXMXvFaDANG7uasMs2QO0kTS7x+t26vz3E159vd8bnMw5KqokIcSfl/Z66iJsZtiKpHCxasvpNn8a2hiu1dysRHiNa6NpBE55rnz48CDG1H9NDtBFIxJlhDUND6XUo/jO6+7crgobEr57ZY= Received: from DB3PR0402MB3916.eurprd04.prod.outlook.com (52.134.72.18) by DB3PR0402MB3754.eurprd04.prod.outlook.com (52.134.67.26) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.1730.15; Fri, 22 Mar 2019 01:48:30 +0000 Received: from DB3PR0402MB3916.eurprd04.prod.outlook.com ([fe80::f1b4:a1fb:cfd1:3f08]) by DB3PR0402MB3916.eurprd04.prod.outlook.com ([fe80::f1b4:a1fb:cfd1:3f08%7]) with mapi id 15.20.1730.013; Fri, 22 Mar 2019 01:48:30 +0000 From: Anson Huang To: "thierry.reding@gmail.com" , "robh+dt@kernel.org" , "mark.rutland@arm.com" , "shawnguo@kernel.org" , "s.hauer@pengutronix.de" , "kernel@pengutronix.de" , "festevam@gmail.com" , "linux@armlinux.org.uk" , "stefan@agner.ch" , "otavio@ossystems.com.br" , Leonard Crestez , Robin Gong , "jan.tuerk@emtrion.com" , "linux-pwm@vger.kernel.org" , "devicetree@vger.kernel.org" , "linux-arm-kernel@lists.infradead.org" , "linux-kernel@vger.kernel.org" , "u.kleine-koenig@pengutronix.de" Subject: [PATCH V9 5/5] ARM: dts: imx7ulp-evk: Add backlight support Thread-Topic: [PATCH V9 5/5] ARM: dts: imx7ulp-evk: Add backlight support Thread-Index: AQHU4FFZk4s+VmXk00W+xx0KUY0FJQ== Date: Fri, 22 Mar 2019 01:48:30 +0000 Message-ID: <1553218974-20464-6-git-send-email-Anson.Huang@nxp.com> References: <1553218974-20464-1-git-send-email-Anson.Huang@nxp.com> In-Reply-To: <1553218974-20464-1-git-send-email-Anson.Huang@nxp.com> Accept-Language: en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: x-mailer: git-send-email 2.7.4 x-clientproxiedby: HK2PR02CA0172.apcprd02.prod.outlook.com (2603:1096:201:1f::32) To DB3PR0402MB3916.eurprd04.prod.outlook.com (2603:10a6:8:10::18) x-ms-exchange-messagesentrepresentingtype: 1 x-originating-ip: [119.31.174.67] x-ms-publictraffictype: Email x-ms-office365-filtering-correlation-id: 6e96d582-bf10-42fd-4334-08d6ae687bf2 x-ms-office365-filtering-ht: Tenant x-microsoft-antispam: BCL:0; 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SPF:None; LANG:en; PTR:InfoNoRecords; MX:1; A:1; received-spf: None (protection.outlook.com: nxp.com does not designate permitted sender hosts) authentication-results: spf=none (sender IP is ) smtp.mailfrom=anson.huang@nxp.com; x-ms-exchange-senderadcheck: 1 x-microsoft-antispam-message-info: kDxbTnR5QltgwupizE8Q3LykgNV7ElWKu2BA9Elk/yeLDhZKMoT9VpdWawi+dfiBrSVEDXKaa39QCwRXkKEOESWXFkhSwsfAaCM8xFKO9CrDcib04KVmjysPAw4hAO8Aqi1nO+ezqFuogpDfxrcx641C/QQj1Fe4FHFQ+ItfpbgQycC8cy60ntKBmFcf2A9IF8bWfOR2Yb4Yu+u8VXJCLAIwkIg3yFhg6cyK7wnC8xF2nh/Zf8cOO2jvdUOCMuwDtzSGJD/GUcSA1vlTl65ckh3+/wXsIEVG6wS/BpRTq82ZDeNDhQzV55W1HvGveuk7215m3SFKprM3Paumj5nn2Ee7UUW+rV+C0SgO1j/JKdMsmEBj1UPdlqbRvsYDgF9vJcOw6dkxEOIm98rwEGg1oiHVQumsRSbd2m/BKGem8z8= MIME-Version: 1.0 X-OriginatorOrg: nxp.com X-MS-Exchange-CrossTenant-Network-Message-Id: 6e96d582-bf10-42fd-4334-08d6ae687bf2 X-MS-Exchange-CrossTenant-originalarrivaltime: 22 Mar 2019 01:48:30.3403 (UTC) X-MS-Exchange-CrossTenant-fromentityheader: Hosted X-MS-Exchange-CrossTenant-id: 686ea1d3-bc2b-4c6f-a92c-d99c5c301635 X-MS-Exchange-CrossTenant-mailboxtype: HOSTED X-MS-Exchange-Transport-CrossTenantHeadersStamped: DB3PR0402MB3754 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20190321_184843_947650_CEDEF1A6 X-CRM114-Status: GOOD ( 12.86 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: dl-linux-imx Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org X-Virus-Scanned: ClamAV using ClamSMTP This patch adds i.MX7ULP EVK board MIPI-DSI backlight support. Signed-off-by: Anson Huang --- No changes. --- arch/arm/boot/dts/imx7ulp-evk.dts | 21 +++++++++++++++++++++ 1 file changed, 21 insertions(+) diff --git a/arch/arm/boot/dts/imx7ulp-evk.dts b/arch/arm/boot/dts/imx7ulp-evk.dts index a09026a..7c44ffa 100644 --- a/arch/arm/boot/dts/imx7ulp-evk.dts +++ b/arch/arm/boot/dts/imx7ulp-evk.dts @@ -8,6 +8,7 @@ /dts-v1/; #include "imx7ulp.dtsi" +#include / { model = "NXP i.MX7ULP EVK"; @@ -22,6 +23,14 @@ reg = <0x60000000 0x40000000>; }; + backlight { + compatible = "pwm-backlight"; + pwms = <&pwm0 1 50000 0>; + brightness-levels = <0 20 25 30 35 40 100>; + default-brightness-level = <6>; + status = "okay"; + }; + reg_vsd_3v3: regulator-vsd-3v3 { compatible = "regulator-fixed"; regulator-name = "VSD_3V3"; @@ -40,6 +49,12 @@ status = "okay"; }; +&pwm0 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pwm0>; + status = "okay"; +}; + &usdhc0 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_usdhc0>; @@ -57,6 +72,12 @@ bias-pull-up; }; + pinctrl_pwm0: pwm0grp { + fsl,pins = < + IMX7ULP_PAD_PTF2__TPM4_CH1 0x2 + >; + }; + pinctrl_usdhc0: usdhc0grp { fsl,pins = < IMX7ULP_PAD_PTD1__SDHC0_CMD 0x43