From patchwork Thu Apr 10 22:50:28 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Shyam Saini X-Patchwork-Id: 14047335 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id BE879C3601E for ; Thu, 10 Apr 2025 22:56:20 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender:List-Subscribe:List-Help :List-Post:List-Archive:List-Unsubscribe:List-Id:Content-Transfer-Encoding: MIME-Version:References:In-Reply-To:Message-Id:Date:Subject:Cc:To:From: Reply-To:Content-Type:Content-ID:Content-Description:Resent-Date:Resent-From: Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:List-Owner; bh=1L/lBwFs+AoYXX7M34lWjEC0yx+AYdjFCcZZm+bO1mg=; b=3b0EIK4Fr/GWN0wkB2JYxNnLcD GUoG1fgKGSDOV0yS0HSdeZF1icjkfQQV/KtBUECXnDqGRGYmtsj38enTLsf3jMqDldlOVDCbxU56r 2yP7149DLeCERRaaThuGusBz1vcTJddYsfd2bgVk72pPxP+t3Me9RmkhTj0vuG23XThvBqlQyeh2r 6ZAs3rYQ/HNXbd+VyqUmIANORv1fjz/2wl4rjJlYuDJOJfSB0rtyIMlAZ9W/VnzFAhApz/a4NNlyM ytHuajmMuLLk+qWvoL30Fuyynxw3XrSB+FhHzMfgq2tIaqNJEBcI4XXPGqmAIiZZGdf29dnIey+TE pqCxNhwQ==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.98.2 #2 (Red Hat Linux)) id 1u30oc-0000000C0IU-44Ib; Thu, 10 Apr 2025 22:56:10 +0000 Received: from linux.microsoft.com ([13.77.154.182]) by bombadil.infradead.org with esmtp (Exim 4.98.2 #2 (Red Hat Linux)) id 1u30jE-0000000BzJq-3Z3q for linux-arm-kernel@lists.infradead.org; Thu, 10 Apr 2025 22:50:39 +0000 Received: from thinkpad-p16sg1.corp.microsoft.com (unknown [20.236.10.206]) by linux.microsoft.com (Postfix) with ESMTPSA id 470912114DAC; Thu, 10 Apr 2025 15:50:35 -0700 (PDT) DKIM-Filter: OpenDKIM Filter v2.11.0 linux.microsoft.com 470912114DAC DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linux.microsoft.com; s=default; t=1744325435; bh=1L/lBwFs+AoYXX7M34lWjEC0yx+AYdjFCcZZm+bO1mg=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=ouD2J1M6Syc04G0BdVTKC6Tw5VlDo00LLQq/BPfc84OcOz77peQdCCw8Zqxt+neSn ABkg8kpYvzqIIkB0YtJe/KN823X2z7FYOJRUkv6fcU6UMSZ509smgkZkpOCGIt66tU ZD4JhUiztiVVO9ZcLBHA74sry1k76aapLHDrwEzQ= From: Shyam Saini To: iommu@lists.linux.dev, linux-arm-kernel@lists.infradead.org, devicetree@vger.kernel.org, virtualization@lists.linux.dev Cc: jgg@ziepe.ca, will@kernel.org, jacob.pan@linux.microsoft.com, eric.auger@redhat.com, code@tyhicks.com, eahariha@linux.microsoft.com, vijayb@linux.microsoft.com Subject: [PATCH v2 1/3] arm-smmu: move MSI_IOVA macro definitions Date: Thu, 10 Apr 2025 15:50:28 -0700 Message-Id: <20250410225030.2528385-2-shyamsaini@linux.microsoft.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20250410225030.2528385-1-shyamsaini@linux.microsoft.com> References: <20250410225030.2528385-1-shyamsaini@linux.microsoft.com> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20250410_155036_914397_B4CF9A24 X-CRM114-Status: GOOD ( 10.81 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org MSI_IOVA* are common among different iommu/smu drivers, so move them to common iommu.h header file. Suggested-by: Jacob Pan Signed-off-by: Shyam Saini --- drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h | 3 --- drivers/iommu/arm/arm-smmu/arm-smmu.c | 3 --- drivers/iommu/virtio-iommu.c | 2 -- include/linux/iommu.h | 3 +++ 4 files changed, 3 insertions(+), 8 deletions(-) diff --git a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h index bd9d7c85576a..d1713f6bbe6d 100644 --- a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h +++ b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h @@ -502,9 +502,6 @@ static inline unsigned int arm_smmu_cdtab_l2_idx(unsigned int ssid) #define ARM_SMMU_POLL_TIMEOUT_US 1000000 /* 1s! */ #define ARM_SMMU_POLL_SPIN_COUNT 10 -#define MSI_IOVA_BASE 0x8000000 -#define MSI_IOVA_LENGTH 0x100000 - enum pri_resp { PRI_RESP_DENY = 0, PRI_RESP_FAIL = 1, diff --git a/drivers/iommu/arm/arm-smmu/arm-smmu.c b/drivers/iommu/arm/arm-smmu/arm-smmu.c index 8f439c265a23..a54dc4608c62 100644 --- a/drivers/iommu/arm/arm-smmu/arm-smmu.c +++ b/drivers/iommu/arm/arm-smmu/arm-smmu.c @@ -50,9 +50,6 @@ */ #define QCOM_DUMMY_VAL -1 -#define MSI_IOVA_BASE 0x8000000 -#define MSI_IOVA_LENGTH 0x100000 - static int force_stage; module_param(force_stage, int, S_IRUGO); MODULE_PARM_DESC(force_stage, diff --git a/drivers/iommu/virtio-iommu.c b/drivers/iommu/virtio-iommu.c index b85ce6310ddb..8c8783c8b31b 100644 --- a/drivers/iommu/virtio-iommu.c +++ b/drivers/iommu/virtio-iommu.c @@ -24,8 +24,6 @@ #include "dma-iommu.h" -#define MSI_IOVA_BASE 0x8000000 -#define MSI_IOVA_LENGTH 0x100000 #define VIOMMU_REQUEST_VQ 0 #define VIOMMU_EVENT_VQ 1 diff --git a/include/linux/iommu.h b/include/linux/iommu.h index cf8c16ba04a0..8d38d85f23f1 100644 --- a/include/linux/iommu.h +++ b/include/linux/iommu.h @@ -1530,6 +1530,9 @@ static inline void iommu_debugfs_setup(void) {} #endif #ifdef CONFIG_IOMMU_DMA +#define MSI_IOVA_BASE 0x8000000 +#define MSI_IOVA_LENGTH 0x100000 + int iommu_get_msi_cookie(struct iommu_domain *domain, dma_addr_t base); #else /* CONFIG_IOMMU_DMA */ static inline int iommu_get_msi_cookie(struct iommu_domain *domain, dma_addr_t base) From patchwork Thu Apr 10 22:50:29 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Shyam Saini X-Patchwork-Id: 14047328 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id B0D9EC3601E for ; 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Thu, 10 Apr 2025 22:54:20 +0000 Received: from linux.microsoft.com ([13.77.154.182]) by bombadil.infradead.org with esmtp (Exim 4.98.2 #2 (Red Hat Linux)) id 1u30jE-0000000BzJs-3H5c for linux-arm-kernel@lists.infradead.org; Thu, 10 Apr 2025 22:50:38 +0000 Received: from thinkpad-p16sg1.corp.microsoft.com (unknown [20.236.10.206]) by linux.microsoft.com (Postfix) with ESMTPSA id 9CA892114DAD; Thu, 10 Apr 2025 15:50:35 -0700 (PDT) DKIM-Filter: OpenDKIM Filter v2.11.0 linux.microsoft.com 9CA892114DAD DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linux.microsoft.com; s=default; t=1744325435; bh=f4tDEWmcrI3cttYgef9jFAuJ7VDRpJ9tPVO1HUepdXY=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=kwuSM8mR5JE4ONOWRVD4F+0ZI8CKWi0X9AIXlxQavBUj+CMQu61nL5G4hCRbJTQLU lLOQDPgLc2pgplhXcklE+vRd9iKNQ1lXAAl/Qj0zzBNLnUczOOf5mbvV0fhNqXpgRK C396TsxzLDab0H9tEE7N8LxPqbrtxoqBf6EGQvPM= From: Shyam Saini To: iommu@lists.linux.dev, linux-arm-kernel@lists.infradead.org, devicetree@vger.kernel.org, virtualization@lists.linux.dev Cc: jgg@ziepe.ca, will@kernel.org, jacob.pan@linux.microsoft.com, eric.auger@redhat.com, code@tyhicks.com, eahariha@linux.microsoft.com, vijayb@linux.microsoft.com Subject: [PATCH v2 2/3] dt-bindings: iommu: add "arm,smmu-faulty-msi-iova" property Date: Thu, 10 Apr 2025 15:50:29 -0700 Message-Id: <20250410225030.2528385-3-shyamsaini@linux.microsoft.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20250410225030.2528385-1-shyamsaini@linux.microsoft.com> References: <20250410225030.2528385-1-shyamsaini@linux.microsoft.com> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20250410_155036_867440_AF554450 X-CRM114-Status: GOOD ( 12.99 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org By default ARM SMMU drivers use MSI_IOVA_BASE macro to reserve PCI MSI IOVA memory range, this assumes that all the platforms have MSI_IOVA_BASE address available for MSI reservation. However, this is not always the case, as some platforms may have the default address reserved for some other purposes and as a consequence ARM SMMU drivers can't reserve MSI memory for those platforms. To address this issue, add a new dts property "arm,smmu-faulty-msi-iova" which can be used to hold faulty MSI IOVA address. This property can be passed to ARM SMMU drivers via device tree so that the drivers can select appropriate MSI IOVA base address which doesn't intersect with the faulty MSI IOVA address. Signed-off-by: Shyam Saini --- Documentation/devicetree/bindings/iommu/arm,smmu-v3.yaml | 8 ++++++++ Documentation/devicetree/bindings/iommu/arm,smmu.yaml | 8 ++++++++ 2 files changed, 16 insertions(+) diff --git a/Documentation/devicetree/bindings/iommu/arm,smmu-v3.yaml b/Documentation/devicetree/bindings/iommu/arm,smmu-v3.yaml index 75fcf4cb52d9..13b615ca38e1 100644 --- a/Documentation/devicetree/bindings/iommu/arm,smmu-v3.yaml +++ b/Documentation/devicetree/bindings/iommu/arm,smmu-v3.yaml @@ -56,6 +56,13 @@ properties: NOTE: this only applies to the SMMU itself, not masters connected upstream of the SMMU. + arm,smmu-faulty-msi-iova: + $ref: /schemas/types.yaml#/definitions/uint32 + description: | + Specifies a faulty PCI MSI base I/O Virtual Address. If this is passed + via dts then arm SMMU driver appropriately select suitable MSI_IOVA base + which does not intersect with faulty MSI IOVA passed in this dts property. + msi-parent: true hisilicon,broken-prefetch-cmd: @@ -92,4 +99,5 @@ examples: dma-coherent; #iommu-cells = <1>; msi-parent = <&its 0xff0000>; + arm,smmu-faulty-msi-iova = <0x8000000>; }; diff --git a/Documentation/devicetree/bindings/iommu/arm,smmu.yaml b/Documentation/devicetree/bindings/iommu/arm,smmu.yaml index 7b9d5507d6cc..1aba9d59d495 100644 --- a/Documentation/devicetree/bindings/iommu/arm,smmu.yaml +++ b/Documentation/devicetree/bindings/iommu/arm,smmu.yaml @@ -208,6 +208,13 @@ properties: NOTE: this only applies to the SMMU itself, not masters connected upstream of the SMMU. + arm,smmu-faulty-msi-iova: + $ref: /schemas/types.yaml#/definitions/uint32 + description: | + Specifies a faulty PCI MSI base I/O Virtual Address. If this is passed + via dts then ARM SMMU driver appropriately select suitable MSI_IOVA base + which does not intersect with faulty MSI IOVA passed in this dts property. + calxeda,smmu-secure-config-access: type: boolean description: @@ -680,6 +687,7 @@ examples: #iommu-cells = <1>; /* always ignore appended 5-bit TBU number */ stream-match-mask = <0x7c00>; + arm,smmu-faulty-msi-iova = <0x8000000>; }; bus { From patchwork Thu Apr 10 22:50:30 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Shyam Saini X-Patchwork-Id: 14047327 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id EAFF8C3601E for ; Thu, 10 Apr 2025 22:52:41 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender:List-Subscribe:List-Help :List-Post:List-Archive:List-Unsubscribe:List-Id:Content-Transfer-Encoding: MIME-Version:References:In-Reply-To:Message-Id:Date:Subject:Cc:To:From: Reply-To:Content-Type:Content-ID:Content-Description:Resent-Date:Resent-From: Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:List-Owner; bh=7gtu6nH7srNfvTtxxwiTNF8qbQE3fc+/uSVqmjie7Kk=; b=EpjZTZgjdi0oFTl7rVt9XiVo3J GkwWhFOmj2EYOyHdN40ATl5m1UJ96DMQY3Kf+jK/HYXjZd6/YdPKx/3fL+eC19hWX84XFeEd18tvi AhH3bVjEXH74Zcxfa1/jht9bRwrzGokAQvW5wubDJq/sdUV0lf7QeaKTAJ64fA7BvYCFRn5bL22GA ukUWfMCCo6V/39oGy/WaOvCK8Fu1Z5MBPMx7O9YBy2+1IbzBH3DaA649oEKOCG4ttMIwMPH6/Q0z1 Tnk8zbV1IgaXmS6TP+IXJcxz3hU8MBkfgU67u9dMkgWsiifMEJSYQOkdqG52VmO8R4pz86JvZA0H3 PXGOCzHg==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.98.2 #2 (Red Hat Linux)) id 1u30l3-0000000Bzig-2PLZ; Thu, 10 Apr 2025 22:52:29 +0000 Received: from linux.microsoft.com ([13.77.154.182]) by bombadil.infradead.org with esmtp (Exim 4.98.2 #2 (Red Hat Linux)) id 1u30jE-0000000BzJt-3RLO for linux-arm-kernel@lists.infradead.org; Thu, 10 Apr 2025 22:50:38 +0000 Received: from thinkpad-p16sg1.corp.microsoft.com (unknown [20.236.10.206]) by linux.microsoft.com (Postfix) with ESMTPSA id 05FEA2114DAE; Thu, 10 Apr 2025 15:50:35 -0700 (PDT) DKIM-Filter: OpenDKIM Filter v2.11.0 linux.microsoft.com 05FEA2114DAE DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linux.microsoft.com; s=default; t=1744325436; bh=7gtu6nH7srNfvTtxxwiTNF8qbQE3fc+/uSVqmjie7Kk=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=ar5iCyWv/QVBsLCCJFSqIY3ZHBZI2x61i2WxVHZ+lvnVMCy4vq9FKsvvgBAk1HT+w +1lEETI/HuA8bD6AKBf336epHfsi/fLw4wlM4JmFUPXenfHseNInTSdc2qXD8jtqWu oQvtuf6RkBkC45BRU/ZEVTKkKllPMqYn0zbkRTSA= From: Shyam Saini To: iommu@lists.linux.dev, linux-arm-kernel@lists.infradead.org, devicetree@vger.kernel.org, virtualization@lists.linux.dev Cc: jgg@ziepe.ca, will@kernel.org, jacob.pan@linux.microsoft.com, eric.auger@redhat.com, code@tyhicks.com, eahariha@linux.microsoft.com, vijayb@linux.microsoft.com Subject: [PATCH v2 3/3] arm-smmu: select suitable MSI IOVA Date: Thu, 10 Apr 2025 15:50:30 -0700 Message-Id: <20250410225030.2528385-4-shyamsaini@linux.microsoft.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20250410225030.2528385-1-shyamsaini@linux.microsoft.com> References: <20250410225030.2528385-1-shyamsaini@linux.microsoft.com> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20250410_155036_910194_D95A5DC9 X-CRM114-Status: GOOD ( 16.77 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org Currently ARM SMMU drivers hardcode PCI MSI IOVA address. Not all the platform have same memory mappings and some platform could have this address already being mapped for something else. This can lead to collision and as a consequence the MSI IOVA addr range is never reserved. Fix this by adding one more MSI_IOVA base address, so that if the platforms can select suitable PCI MSI IOVA address if SMMU dts node has "arm,smmu-faulty-msi-iova". If this property is not found in the dtb for the given platform then the driver falls back on the default MSI IOVA address. Signed-off-by: Shyam Saini --- drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c | 9 +++- drivers/iommu/arm/arm-smmu/arm-smmu.c | 9 +++- include/linux/iommu.h | 49 +++++++++++++++++++++ 3 files changed, 63 insertions(+), 4 deletions(-) diff --git a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c index 358072b4e293..d6ea82ed4530 100644 --- a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c +++ b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c @@ -33,6 +33,8 @@ #include "arm-smmu-v3.h" #include "../../dma-iommu.h" +u32 msi_iova_base; + static bool disable_msipolling; module_param(disable_msipolling, bool, 0444); MODULE_PARM_DESC(disable_msipolling, @@ -3541,8 +3543,8 @@ static void arm_smmu_get_resv_regions(struct device *dev, struct iommu_resv_region *region; int prot = IOMMU_WRITE | IOMMU_NOEXEC | IOMMU_MMIO; - region = iommu_alloc_resv_region(MSI_IOVA_BASE, MSI_IOVA_LENGTH, - prot, IOMMU_RESV_SW_MSI, GFP_KERNEL); + region = iommu_alloc_resv_region(msi_iova_base, MSI_IOVA_LENGTH, prot, + IOMMU_RESV_SW_MSI, GFP_KERNEL); if (!region) return; @@ -4570,6 +4572,9 @@ static int arm_smmu_device_dt_probe(struct platform_device *pdev, struct device *dev = &pdev->dev; u32 cells; int ret = -EINVAL; + u32 msi_iova_ptr; + + iommu_configure_msi_iova(dev, "arm,smmu-faulty-msi-iova", msi_iova_ptr); if (of_property_read_u32(dev->of_node, "#iommu-cells", &cells)) dev_err(dev, "missing #iommu-cells property\n"); diff --git a/drivers/iommu/arm/arm-smmu/arm-smmu.c b/drivers/iommu/arm/arm-smmu/arm-smmu.c index a54dc4608c62..cd8bf2278057 100644 --- a/drivers/iommu/arm/arm-smmu/arm-smmu.c +++ b/drivers/iommu/arm/arm-smmu/arm-smmu.c @@ -50,6 +50,8 @@ */ #define QCOM_DUMMY_VAL -1 +u32 msi_iova_base; + static int force_stage; module_param(force_stage, int, S_IRUGO); MODULE_PARM_DESC(force_stage, @@ -1594,8 +1596,8 @@ static void arm_smmu_get_resv_regions(struct device *dev, struct iommu_resv_region *region; int prot = IOMMU_WRITE | IOMMU_NOEXEC | IOMMU_MMIO; - region = iommu_alloc_resv_region(MSI_IOVA_BASE, MSI_IOVA_LENGTH, - prot, IOMMU_RESV_SW_MSI, GFP_KERNEL); + region = iommu_alloc_resv_region(msi_iova_base, MSI_IOVA_LENGTH, prot, + IOMMU_RESV_SW_MSI, GFP_KERNEL); if (!region) return; @@ -2030,6 +2032,9 @@ static int arm_smmu_device_dt_probe(struct arm_smmu_device *smmu, const struct arm_smmu_match_data *data; struct device *dev = smmu->dev; bool legacy_binding; + u32 *msi_iova_ptr = &msi_iova_base; + + iommu_configure_msi_iova(dev, "arm,smmu-faulty-msi-iova", msi_iova_ptr); if (of_property_read_u32(dev->of_node, "#global-interrupts", global_irqs)) return dev_err_probe(dev, -ENODEV, diff --git a/include/linux/iommu.h b/include/linux/iommu.h index 8d38d85f23f1..cfd047fdf225 100644 --- a/include/linux/iommu.h +++ b/include/linux/iommu.h @@ -1531,10 +1531,59 @@ static inline void iommu_debugfs_setup(void) {} #ifdef CONFIG_IOMMU_DMA #define MSI_IOVA_BASE 0x8000000 +#define MSI_IOVA_BASE2 0xa0000000 #define MSI_IOVA_LENGTH 0x100000 +static inline u32 select_msi_iova_base(u32 erratic_iova_addr) +{ + phys_addr_t start, end, msi_iova_end; + + if (!erratic_iova_addr) + return MSI_IOVA_BASE; + + start = erratic_iova_addr; + end = start + MSI_IOVA_LENGTH - 1; + msi_iova_end = MSI_IOVA_BASE + MSI_IOVA_LENGTH - 1; + + /* return non-overlapping address */ + return (start > MSI_IOVA_BASE || + end < msi_iova_end) ? MSI_IOVA_BASE : MSI_IOVA_BASE2; +} + +static inline void iommu_configure_msi_iova(struct device *iommu_dev, + const char *faulty_msi_iova_prop, + u32 *msi_iova) +{ + static bool is_msi_iova_selected; + u32 faulty_msi_iova_from_dt; + int rc; + + rc = of_property_read_u32(iommu_dev->of_node, faulty_msi_iova_prop, + &faulty_msi_iova_from_dt); + if (!is_msi_iova_selected) { + *msi_iova = select_msi_iova_base(rc ? 0 : faulty_msi_iova_from_dt); + dev_dbg(iommu_dev, "setting custom MSI IOVA base to 0x%x\n", *msi_iova); + is_msi_iova_selected = true; + return; + } + + dev_dbg(iommu_dev, "custom MSI IOVA base already set to 0x%x\n", *msi_iova); +} + int iommu_get_msi_cookie(struct iommu_domain *domain, dma_addr_t base); #else /* CONFIG_IOMMU_DMA */ + +static inline u32 select_msi_iova_base(u32 erratic_iova_addr) +{ +} + +static inline void iommu_configure_msi_iova(struct device *iommu_dev, + const char *faulty_msi_iova_prop, + u32 *msi_iova) +{ +} + + static inline int iommu_get_msi_cookie(struct iommu_domain *domain, dma_addr_t base) { return -ENODEV;