From patchwork Fri Apr 11 09:54:11 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Jani Nikula X-Patchwork-Id: 14048000 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 29337C369A8 for ; Fri, 11 Apr 2025 09:54:28 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id BD38410EB4D; Fri, 11 Apr 2025 09:54:27 +0000 (UTC) Authentication-Results: gabe.freedesktop.org; dkim=pass (2048-bit key; unprotected) header.d=intel.com header.i=@intel.com header.b="lfDnIJBB"; dkim-atps=neutral Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.11]) by gabe.freedesktop.org (Postfix) with ESMTPS id 2DEBD10EB4D; Fri, 11 Apr 2025 09:54:27 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1744365267; x=1775901267; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=qHXAEPfFr+7DNA8vH6hB4jsLGvuSpyi9C0VCX7SSJes=; b=lfDnIJBBIVMX3T20mIH451TdONmZ1fO7BhSrzxB7Su+4DbrtgahhskZQ upCQPxCDgH6AMtH4CuVH/Cpx0hPVJf8LuQlI60nozAo+TkZc12NRb3Ztn DbX79wh7eVrFlx7NFuiwK7Ey9L+PjAi4qAQeKPAI3P+qA0lK/cV9ikrEY nyP9/eYUiO7W1s8aFIVhffWdxW7VdV8MJzjMD99RaPq41rdQRkh6hLW/I /flg9q+oOW2d90UL6CuzimD9OGz3R+YcmNRQGR1/ufNfkbl8fSAw5I3+Q WufBKBuZvMAcH4h1FjMmseEBG3crQvdv1v0LR3+uomUkYG5QovVWJ1FVx Q==; X-CSE-ConnectionGUID: aTv/SOk6QC23cSDg7na/fw== X-CSE-MsgGUID: PlQBq96ySna9TeOS4OodlA== X-IronPort-AV: E=McAfee;i="6700,10204,11400"; a="56094847" X-IronPort-AV: E=Sophos;i="6.15,203,1739865600"; d="scan'208";a="56094847" Received: from fmviesa003.fm.intel.com ([10.60.135.143]) by orvoesa103.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 11 Apr 2025 02:54:27 -0700 X-CSE-ConnectionGUID: UvPzAWSkRjKRPQcon/wMKQ== X-CSE-MsgGUID: YG/8wwTCRRefbCG60CtkbA== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.15,203,1739865600"; d="scan'208";a="133265579" Received: from vpanait-mobl.ger.corp.intel.com (HELO localhost) ([10.245.246.115]) by fmviesa003-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 11 Apr 2025 02:54:24 -0700 From: Jani Nikula To: intel-gfx@lists.freedesktop.org, intel-xe@lists.freedesktop.org Cc: jani.nikula@intel.com, rodrigo.vivi@intel.com, lucas.demarchi@intel.com, ville.syrjala@linux.intel.com Subject: [PATCH 1/4] drm/{i915,xe}: Move intel_pch under display Date: Fri, 11 Apr 2025 12:54:11 +0300 Message-Id: <041e3dee494aa15c22172360f2bdd9b15e4acb00.1744364975.git.jani.nikula@intel.com> X-Mailer: git-send-email 2.39.5 In-Reply-To: References: MIME-Version: 1.0 Organization: Intel Finland Oy - BIC 0357606-4 - Westendinkatu 7, 02160 Espoo X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" From: Rodrigo Vivi The only usage of the "PCH" infra is to detect which South Display Engine we should be using. Move it under display so we can convert all its callers towards intel_display struct later. No functional or code change. Signed-off-by: Rodrigo Vivi Reviewed-by: Jani Nikula Signed-off-by: Jani Nikula Reviewed-by: Lucas De Marchi --- drivers/gpu/drm/i915/Makefile | 2 +- drivers/gpu/drm/i915/{soc => display}/intel_pch.c | 2 +- drivers/gpu/drm/i915/{soc => display}/intel_pch.h | 2 +- drivers/gpu/drm/i915/i915_drv.h | 3 +-- drivers/gpu/drm/xe/Makefile | 2 +- drivers/gpu/drm/xe/compat-i915-headers/soc/intel_pch.h | 6 ------ drivers/gpu/drm/xe/xe_device_types.h | 2 +- 7 files changed, 6 insertions(+), 13 deletions(-) rename drivers/gpu/drm/i915/{soc => display}/intel_pch.c (99%) rename drivers/gpu/drm/i915/{soc => display}/intel_pch.h (98%) delete mode 100644 drivers/gpu/drm/xe/compat-i915-headers/soc/intel_pch.h diff --git a/drivers/gpu/drm/i915/Makefile b/drivers/gpu/drm/i915/Makefile index c8fc271b33b7..13d4a16f7d33 100644 --- a/drivers/gpu/drm/i915/Makefile +++ b/drivers/gpu/drm/i915/Makefile @@ -52,7 +52,6 @@ i915-y += \ i915-y += \ soc/intel_dram.o \ soc/intel_gmch.o \ - soc/intel_pch.o \ soc/intel_rom.o # core library code @@ -282,6 +281,7 @@ i915-y += \ display/intel_modeset_setup.o \ display/intel_modeset_verify.o \ display/intel_overlay.o \ + display/intel_pch.o \ display/intel_pch_display.o \ display/intel_pch_refclk.o \ display/intel_plane_initial.o \ diff --git a/drivers/gpu/drm/i915/soc/intel_pch.c b/drivers/gpu/drm/i915/display/intel_pch.c similarity index 99% rename from drivers/gpu/drm/i915/soc/intel_pch.c rename to drivers/gpu/drm/i915/display/intel_pch.c index 82dc7fbd1a3e..37766e40fd1c 100644 --- a/drivers/gpu/drm/i915/soc/intel_pch.c +++ b/drivers/gpu/drm/i915/display/intel_pch.c @@ -1,6 +1,6 @@ // SPDX-License-Identifier: MIT /* - * Copyright 2019 Intel Corporation. + * Copyright 2025 Intel Corporation. */ #include "i915_drv.h" diff --git a/drivers/gpu/drm/i915/soc/intel_pch.h b/drivers/gpu/drm/i915/display/intel_pch.h similarity index 98% rename from drivers/gpu/drm/i915/soc/intel_pch.h rename to drivers/gpu/drm/i915/display/intel_pch.h index 635aea7a5539..b9fa2b2f07bc 100644 --- a/drivers/gpu/drm/i915/soc/intel_pch.h +++ b/drivers/gpu/drm/i915/display/intel_pch.h @@ -1,6 +1,6 @@ /* SPDX-License-Identifier: MIT */ /* - * Copyright 2019 Intel Corporation. + * Copyright 2025 Intel Corporation. */ #ifndef __INTEL_PCH__ diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h index 236c48d282e4..65e795a4ecba 100644 --- a/drivers/gpu/drm/i915/i915_drv.h +++ b/drivers/gpu/drm/i915/i915_drv.h @@ -38,6 +38,7 @@ #include "display/intel_display_limits.h" #include "display/intel_display_core.h" +#include "display/intel_pch.h" #include "gem/i915_gem_context_types.h" #include "gem/i915_gem_shrinker.h" @@ -49,8 +50,6 @@ #include "gt/intel_workarounds.h" #include "gt/uc/intel_uc.h" -#include "soc/intel_pch.h" - #include "i915_drm_client.h" #include "i915_gem.h" #include "i915_gpu_error.h" diff --git a/drivers/gpu/drm/xe/Makefile b/drivers/gpu/drm/xe/Makefile index c5d6681645ed..3ecac0a38b82 100644 --- a/drivers/gpu/drm/xe/Makefile +++ b/drivers/gpu/drm/xe/Makefile @@ -198,7 +198,6 @@ xe-$(CONFIG_DRM_XE_DISPLAY) += \ # SOC code shared with i915 xe-$(CONFIG_DRM_XE_DISPLAY) += \ i915-soc/intel_dram.o \ - i915-soc/intel_pch.o \ i915-soc/intel_rom.o # Display code shared with i915 @@ -273,6 +272,7 @@ xe-$(CONFIG_DRM_XE_DISPLAY) += \ i915-display/intel_panel.o \ i915-display/intel_pfit.o \ i915-display/intel_pmdemand.o \ + i915-display/intel_pch.o \ i915-display/intel_pps.o \ i915-display/intel_psr.o \ i915-display/intel_qp_tables.o \ diff --git a/drivers/gpu/drm/xe/compat-i915-headers/soc/intel_pch.h b/drivers/gpu/drm/xe/compat-i915-headers/soc/intel_pch.h deleted file mode 100644 index 9c46556d33a4..000000000000 --- a/drivers/gpu/drm/xe/compat-i915-headers/soc/intel_pch.h +++ /dev/null @@ -1,6 +0,0 @@ -/* SPDX-License-Identifier: MIT */ -/* - * Copyright © 2023 Intel Corporation - */ - -#include "../../../i915/soc/intel_pch.h" diff --git a/drivers/gpu/drm/xe/xe_device_types.h b/drivers/gpu/drm/xe/xe_device_types.h index 0369fc09c9da..9662bbfb257c 100644 --- a/drivers/gpu/drm/xe/xe_device_types.h +++ b/drivers/gpu/drm/xe/xe_device_types.h @@ -31,7 +31,7 @@ #endif #if IS_ENABLED(CONFIG_DRM_XE_DISPLAY) -#include "soc/intel_pch.h" +#include "intel_pch.h" #include "intel_display_core.h" #include "intel_display_device.h" #endif From patchwork Fri Apr 11 09:54:12 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jani Nikula X-Patchwork-Id: 14048001 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id AE480C36010 for ; Fri, 11 Apr 2025 09:54:36 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 47C9910EB4C; Fri, 11 Apr 2025 09:54:36 +0000 (UTC) Authentication-Results: gabe.freedesktop.org; dkim=pass (2048-bit key; unprotected) header.d=intel.com header.i=@intel.com header.b="GtpRHLRJ"; dkim-atps=neutral Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.11]) by gabe.freedesktop.org (Postfix) with ESMTPS id 3015F10EB51; Fri, 11 Apr 2025 09:54:35 +0000 (UTC) DKIM-Signature: v=1; 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d="scan'208";a="133265624" Received: from vpanait-mobl.ger.corp.intel.com (HELO localhost) ([10.245.246.115]) by fmviesa003-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 11 Apr 2025 02:54:29 -0700 From: Jani Nikula To: intel-gfx@lists.freedesktop.org, intel-xe@lists.freedesktop.org Cc: jani.nikula@intel.com, rodrigo.vivi@intel.com, lucas.demarchi@intel.com, ville.syrjala@linux.intel.com Subject: [PATCH 2/4] drm/i915/display: Convert intel_pch towards intel_display Date: Fri, 11 Apr 2025 12:54:12 +0300 Message-Id: <8ffe86eb2a02153e3f866a81fb6dc8a3327a0f25.1744364975.git.jani.nikula@intel.com> X-Mailer: git-send-email 2.39.5 In-Reply-To: References: MIME-Version: 1.0 Organization: Intel Finland Oy - BIC 0357606-4 - Westendinkatu 7, 02160 Espoo X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" From: Rodrigo Vivi Now that intel_pch lives under display, let's begin its conversion towards struct intel_display. Move the pch_type to inside intel_display and convert the callers. While doing it, sort intel_display_core.h include list alphabetically. Signed-off-by: Rodrigo Vivi Reviewed-by: Jani Nikula Signed-off-by: Jani Nikula --- .../gpu/drm/i915/display/intel_display_core.h | 6 +- drivers/gpu/drm/i915/display/intel_pch.c | 242 +++++++++--------- drivers/gpu/drm/i915/display/intel_pch.h | 40 +-- drivers/gpu/drm/i915/i915_driver.c | 2 +- drivers/gpu/drm/i915/i915_drv.h | 3 - drivers/gpu/drm/xe/display/xe_display.c | 2 +- drivers/gpu/drm/xe/xe_device_types.h | 1 - 7 files changed, 155 insertions(+), 141 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_display_core.h b/drivers/gpu/drm/i915/display/intel_display_core.h index eb6d6f2d0f75..48e47f0fd8b7 100644 --- a/drivers/gpu/drm/i915/display/intel_display_core.h +++ b/drivers/gpu/drm/i915/display/intel_display_core.h @@ -21,12 +21,13 @@ #include "intel_display_limits.h" #include "intel_display_params.h" #include "intel_display_power.h" +#include "intel_dmc_wl.h" #include "intel_dpll_mgr.h" #include "intel_fbc.h" #include "intel_global_state.h" #include "intel_gmbus.h" #include "intel_opregion.h" -#include "intel_dmc_wl.h" +#include "intel_pch.h" #include "intel_wm_types.h" struct task_struct; @@ -289,6 +290,9 @@ struct intel_display { /* Platform (and subplatform, if any) identification */ struct intel_display_platforms platform; + /* Intel PCH: where the south display engine lives */ + enum intel_pch pch_type; + /* Display functions */ struct { /* Top level crtc-ish functions */ diff --git a/drivers/gpu/drm/i915/display/intel_pch.c b/drivers/gpu/drm/i915/display/intel_pch.c index 37766e40fd1c..e63480dd01fe 100644 --- a/drivers/gpu/drm/i915/display/intel_pch.c +++ b/drivers/gpu/drm/i915/display/intel_pch.c @@ -39,139 +39,150 @@ /* Map PCH device id to PCH type, or PCH_NONE if unknown. */ static enum intel_pch -intel_pch_type(const struct drm_i915_private *dev_priv, unsigned short id) +intel_pch_type(const struct intel_display *display, unsigned short id) { switch (id) { case INTEL_PCH_IBX_DEVICE_ID_TYPE: - drm_dbg_kms(&dev_priv->drm, "Found Ibex Peak PCH\n"); - drm_WARN_ON(&dev_priv->drm, GRAPHICS_VER(dev_priv) != 5); + drm_dbg_kms(display->drm, "Found Ibex Peak PCH\n"); + drm_WARN_ON(display->drm, DISPLAY_VER(display) != 5); return PCH_IBX; case INTEL_PCH_CPT_DEVICE_ID_TYPE: - drm_dbg_kms(&dev_priv->drm, "Found CougarPoint PCH\n"); - drm_WARN_ON(&dev_priv->drm, - GRAPHICS_VER(dev_priv) != 6 && !IS_IVYBRIDGE(dev_priv)); + drm_dbg_kms(display->drm, "Found CougarPoint PCH\n"); + drm_WARN_ON(display->drm, + DISPLAY_VER(display) != 6 && + !display->platform.ivybridge); return PCH_CPT; case INTEL_PCH_PPT_DEVICE_ID_TYPE: - drm_dbg_kms(&dev_priv->drm, "Found PantherPoint PCH\n"); - drm_WARN_ON(&dev_priv->drm, - GRAPHICS_VER(dev_priv) != 6 && !IS_IVYBRIDGE(dev_priv)); + drm_dbg_kms(display->drm, "Found PantherPoint PCH\n"); + drm_WARN_ON(display->drm, + DISPLAY_VER(display) != 6 && + !display->platform.ivybridge); /* PPT is CPT compatible */ return PCH_CPT; case INTEL_PCH_LPT_DEVICE_ID_TYPE: - drm_dbg_kms(&dev_priv->drm, "Found LynxPoint PCH\n"); - drm_WARN_ON(&dev_priv->drm, - !IS_HASWELL(dev_priv) && !IS_BROADWELL(dev_priv)); - drm_WARN_ON(&dev_priv->drm, - IS_HASWELL_ULT(dev_priv) || IS_BROADWELL_ULT(dev_priv)); + drm_dbg_kms(display->drm, "Found LynxPoint PCH\n"); + drm_WARN_ON(display->drm, + !display->platform.haswell && + !display->platform.broadwell); + drm_WARN_ON(display->drm, + display->platform.haswell_ult || + display->platform.broadwell_ult); return PCH_LPT_H; case INTEL_PCH_LPT_LP_DEVICE_ID_TYPE: - drm_dbg_kms(&dev_priv->drm, "Found LynxPoint LP PCH\n"); - drm_WARN_ON(&dev_priv->drm, - !IS_HASWELL(dev_priv) && !IS_BROADWELL(dev_priv)); - drm_WARN_ON(&dev_priv->drm, - !IS_HASWELL_ULT(dev_priv) && !IS_BROADWELL_ULT(dev_priv)); + drm_dbg_kms(display->drm, "Found LynxPoint LP PCH\n"); + drm_WARN_ON(display->drm, + !display->platform.haswell && + !display->platform.broadwell); + drm_WARN_ON(display->drm, + !display->platform.haswell_ult && + !display->platform.broadwell_ult); return PCH_LPT_LP; case INTEL_PCH_WPT_DEVICE_ID_TYPE: - drm_dbg_kms(&dev_priv->drm, "Found WildcatPoint PCH\n"); - drm_WARN_ON(&dev_priv->drm, - !IS_HASWELL(dev_priv) && !IS_BROADWELL(dev_priv)); - drm_WARN_ON(&dev_priv->drm, - IS_HASWELL_ULT(dev_priv) || IS_BROADWELL_ULT(dev_priv)); + drm_dbg_kms(display->drm, "Found WildcatPoint PCH\n"); + drm_WARN_ON(display->drm, + !display->platform.haswell && + !display->platform.broadwell); + drm_WARN_ON(display->drm, + display->platform.haswell_ult || + display->platform.broadwell_ult); /* WPT is LPT compatible */ return PCH_LPT_H; case INTEL_PCH_WPT_LP_DEVICE_ID_TYPE: - drm_dbg_kms(&dev_priv->drm, "Found WildcatPoint LP PCH\n"); - drm_WARN_ON(&dev_priv->drm, - !IS_HASWELL(dev_priv) && !IS_BROADWELL(dev_priv)); - drm_WARN_ON(&dev_priv->drm, - !IS_HASWELL_ULT(dev_priv) && !IS_BROADWELL_ULT(dev_priv)); + drm_dbg_kms(display->drm, "Found WildcatPoint LP PCH\n"); + drm_WARN_ON(display->drm, + !display->platform.haswell && + !display->platform.broadwell); + drm_WARN_ON(display->drm, + !display->platform.haswell_ult && + !display->platform.broadwell_ult); /* WPT is LPT compatible */ return PCH_LPT_LP; case INTEL_PCH_SPT_DEVICE_ID_TYPE: - drm_dbg_kms(&dev_priv->drm, "Found SunrisePoint PCH\n"); - drm_WARN_ON(&dev_priv->drm, - !IS_SKYLAKE(dev_priv) && !IS_KABYLAKE(dev_priv)); + drm_dbg_kms(display->drm, "Found SunrisePoint PCH\n"); + drm_WARN_ON(display->drm, + !display->platform.skylake && + !display->platform.kabylake); return PCH_SPT; case INTEL_PCH_SPT_LP_DEVICE_ID_TYPE: - drm_dbg_kms(&dev_priv->drm, "Found SunrisePoint LP PCH\n"); - drm_WARN_ON(&dev_priv->drm, - !IS_SKYLAKE(dev_priv) && - !IS_KABYLAKE(dev_priv) && - !IS_COFFEELAKE(dev_priv) && - !IS_COMETLAKE(dev_priv)); + drm_dbg_kms(display->drm, "Found SunrisePoint LP PCH\n"); + drm_WARN_ON(display->drm, + !display->platform.skylake && + !display->platform.kabylake && + !display->platform.coffeelake && + !display->platform.cometlake); return PCH_SPT; case INTEL_PCH_KBP_DEVICE_ID_TYPE: - drm_dbg_kms(&dev_priv->drm, "Found Kaby Lake PCH (KBP)\n"); - drm_WARN_ON(&dev_priv->drm, - !IS_SKYLAKE(dev_priv) && - !IS_KABYLAKE(dev_priv) && - !IS_COFFEELAKE(dev_priv) && - !IS_COMETLAKE(dev_priv)); + drm_dbg_kms(display->drm, "Found Kaby Lake PCH (KBP)\n"); + drm_WARN_ON(display->drm, + !display->platform.skylake && + !display->platform.kabylake && + !display->platform.coffeelake && + !display->platform.cometlake); /* KBP is SPT compatible */ return PCH_SPT; case INTEL_PCH_CNP_DEVICE_ID_TYPE: - drm_dbg_kms(&dev_priv->drm, "Found Cannon Lake PCH (CNP)\n"); - drm_WARN_ON(&dev_priv->drm, - !IS_COFFEELAKE(dev_priv) && - !IS_COMETLAKE(dev_priv)); + drm_dbg_kms(display->drm, "Found Cannon Lake PCH (CNP)\n"); + drm_WARN_ON(display->drm, + !display->platform.coffeelake && + !display->platform.cometlake); return PCH_CNP; case INTEL_PCH_CNP_LP_DEVICE_ID_TYPE: - drm_dbg_kms(&dev_priv->drm, + drm_dbg_kms(display->drm, "Found Cannon Lake LP PCH (CNP-LP)\n"); - drm_WARN_ON(&dev_priv->drm, - !IS_COFFEELAKE(dev_priv) && - !IS_COMETLAKE(dev_priv)); + drm_WARN_ON(display->drm, + !display->platform.coffeelake && + !display->platform.cometlake); return PCH_CNP; case INTEL_PCH_CMP_DEVICE_ID_TYPE: case INTEL_PCH_CMP2_DEVICE_ID_TYPE: - drm_dbg_kms(&dev_priv->drm, "Found Comet Lake PCH (CMP)\n"); - drm_WARN_ON(&dev_priv->drm, - !IS_COFFEELAKE(dev_priv) && - !IS_COMETLAKE(dev_priv) && - !IS_ROCKETLAKE(dev_priv)); + drm_dbg_kms(display->drm, "Found Comet Lake PCH (CMP)\n"); + drm_WARN_ON(display->drm, + !display->platform.coffeelake && + !display->platform.cometlake && + !display->platform.rocketlake); /* CMP is CNP compatible */ return PCH_CNP; case INTEL_PCH_CMP_V_DEVICE_ID_TYPE: - drm_dbg_kms(&dev_priv->drm, "Found Comet Lake V PCH (CMP-V)\n"); - drm_WARN_ON(&dev_priv->drm, - !IS_COFFEELAKE(dev_priv) && - !IS_COMETLAKE(dev_priv)); + drm_dbg_kms(display->drm, "Found Comet Lake V PCH (CMP-V)\n"); + drm_WARN_ON(display->drm, + !display->platform.coffeelake && + !display->platform.cometlake); /* CMP-V is based on KBP, which is SPT compatible */ return PCH_SPT; case INTEL_PCH_ICP_DEVICE_ID_TYPE: case INTEL_PCH_ICP2_DEVICE_ID_TYPE: - drm_dbg_kms(&dev_priv->drm, "Found Ice Lake PCH\n"); - drm_WARN_ON(&dev_priv->drm, !IS_ICELAKE(dev_priv)); + drm_dbg_kms(display->drm, "Found Ice Lake PCH\n"); + drm_WARN_ON(display->drm, !display->platform.icelake); return PCH_ICP; case INTEL_PCH_MCC_DEVICE_ID_TYPE: - drm_dbg_kms(&dev_priv->drm, "Found Mule Creek Canyon PCH\n"); - drm_WARN_ON(&dev_priv->drm, !(IS_JASPERLAKE(dev_priv) || - IS_ELKHARTLAKE(dev_priv))); + drm_dbg_kms(display->drm, "Found Mule Creek Canyon PCH\n"); + drm_WARN_ON(display->drm, !(display->platform.jasperlake || + display->platform.elkhartlake)); /* MCC is TGP compatible */ return PCH_TGP; case INTEL_PCH_TGP_DEVICE_ID_TYPE: case INTEL_PCH_TGP2_DEVICE_ID_TYPE: - drm_dbg_kms(&dev_priv->drm, "Found Tiger Lake LP PCH\n"); - drm_WARN_ON(&dev_priv->drm, !IS_TIGERLAKE(dev_priv) && - !IS_ROCKETLAKE(dev_priv) && - !IS_SKYLAKE(dev_priv) && - !IS_KABYLAKE(dev_priv) && - !IS_COFFEELAKE(dev_priv) && - !IS_COMETLAKE(dev_priv)); + drm_dbg_kms(display->drm, "Found Tiger Lake LP PCH\n"); + drm_WARN_ON(display->drm, !display->platform.tigerlake && + !display->platform.rocketlake && + !display->platform.skylake && + !display->platform.kabylake && + !display->platform.coffeelake && + !display->platform.cometlake); return PCH_TGP; case INTEL_PCH_JSP_DEVICE_ID_TYPE: - drm_dbg_kms(&dev_priv->drm, "Found Jasper Lake PCH\n"); - drm_WARN_ON(&dev_priv->drm, !(IS_JASPERLAKE(dev_priv) || - IS_ELKHARTLAKE(dev_priv))); + drm_dbg_kms(display->drm, "Found Jasper Lake PCH\n"); + drm_WARN_ON(display->drm, !(display->platform.jasperlake || + display->platform.elkhartlake)); /* JSP is ICP compatible */ return PCH_ICP; case INTEL_PCH_ADP_DEVICE_ID_TYPE: case INTEL_PCH_ADP2_DEVICE_ID_TYPE: case INTEL_PCH_ADP3_DEVICE_ID_TYPE: case INTEL_PCH_ADP4_DEVICE_ID_TYPE: - drm_dbg_kms(&dev_priv->drm, "Found Alder Lake PCH\n"); - drm_WARN_ON(&dev_priv->drm, !IS_ALDERLAKE_S(dev_priv) && - !IS_ALDERLAKE_P(dev_priv)); + drm_dbg_kms(display->drm, "Found Alder Lake PCH\n"); + drm_WARN_ON(display->drm, !display->platform.alderlake_s && + !display->platform.alderlake_p); return PCH_ADP; default: return PCH_NONE; @@ -189,7 +200,7 @@ static bool intel_is_virt_pch(unsigned short id, } static void -intel_virt_detect_pch(const struct drm_i915_private *dev_priv, +intel_virt_detect_pch(const struct intel_display *display, unsigned short *pch_id, enum intel_pch *pch_type) { unsigned short id = 0; @@ -201,44 +212,45 @@ intel_virt_detect_pch(const struct drm_i915_private *dev_priv, * make an educated guess as to which PCH is really there. */ - if (IS_ALDERLAKE_S(dev_priv) || IS_ALDERLAKE_P(dev_priv)) + if (display->platform.alderlake_s || display->platform.alderlake_p) id = INTEL_PCH_ADP_DEVICE_ID_TYPE; - else if (IS_TIGERLAKE(dev_priv) || IS_ROCKETLAKE(dev_priv)) + else if (display->platform.tigerlake || display->platform.rocketlake) id = INTEL_PCH_TGP_DEVICE_ID_TYPE; - else if (IS_JASPERLAKE(dev_priv) || IS_ELKHARTLAKE(dev_priv)) + else if (display->platform.jasperlake || display->platform.elkhartlake) id = INTEL_PCH_MCC_DEVICE_ID_TYPE; - else if (IS_ICELAKE(dev_priv)) + else if (display->platform.icelake) id = INTEL_PCH_ICP_DEVICE_ID_TYPE; - else if (IS_COFFEELAKE(dev_priv) || - IS_COMETLAKE(dev_priv)) + else if (display->platform.coffeelake || + display->platform.cometlake) id = INTEL_PCH_CNP_DEVICE_ID_TYPE; - else if (IS_KABYLAKE(dev_priv) || IS_SKYLAKE(dev_priv)) + else if (display->platform.kabylake || display->platform.skylake) id = INTEL_PCH_SPT_DEVICE_ID_TYPE; - else if (IS_HASWELL_ULT(dev_priv) || IS_BROADWELL_ULT(dev_priv)) + else if (display->platform.haswell_ult || + display->platform.broadwell_ult) id = INTEL_PCH_LPT_LP_DEVICE_ID_TYPE; - else if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) + else if (display->platform.haswell || display->platform.broadwell) id = INTEL_PCH_LPT_DEVICE_ID_TYPE; - else if (GRAPHICS_VER(dev_priv) == 6 || IS_IVYBRIDGE(dev_priv)) + else if (DISPLAY_VER(display) == 6 || display->platform.ivybridge) id = INTEL_PCH_CPT_DEVICE_ID_TYPE; - else if (GRAPHICS_VER(dev_priv) == 5) + else if (DISPLAY_VER(display) == 5) id = INTEL_PCH_IBX_DEVICE_ID_TYPE; if (id) - drm_dbg_kms(&dev_priv->drm, "Assuming PCH ID %04x\n", id); + drm_dbg_kms(display->drm, "Assuming PCH ID %04x\n", id); else - drm_dbg_kms(&dev_priv->drm, "Assuming no PCH\n"); + drm_dbg_kms(display->drm, "Assuming no PCH\n"); - *pch_type = intel_pch_type(dev_priv, id); + *pch_type = intel_pch_type(display, id); /* Sanity check virtual PCH id */ - if (drm_WARN_ON(&dev_priv->drm, + if (drm_WARN_ON(display->drm, id && *pch_type == PCH_NONE)) id = 0; *pch_id = id; } -void intel_detect_pch(struct drm_i915_private *dev_priv) +void intel_detect_pch(struct intel_display *display) { struct pci_dev *pch = NULL; unsigned short id; @@ -248,21 +260,21 @@ void intel_detect_pch(struct drm_i915_private *dev_priv) * South display engine on the same PCI device: just assign the fake * PCH. */ - if (DISPLAY_VER(dev_priv) >= 20) { - dev_priv->pch_type = PCH_LNL; + if (DISPLAY_VER(display) >= 20) { + display->pch_type = PCH_LNL; return; - } else if (IS_BATTLEMAGE(dev_priv) || IS_METEORLAKE(dev_priv)) { + } else if (display->platform.battlemage || display->platform.meteorlake) { /* * Both north display and south display are on the SoC die. * The real PCH (if it even exists) is uninvolved in display. */ - dev_priv->pch_type = PCH_MTL; + display->pch_type = PCH_MTL; return; - } else if (IS_DG2(dev_priv)) { - dev_priv->pch_type = PCH_DG2; + } else if (display->platform.dg2) { + display->pch_type = PCH_DG2; return; - } else if (IS_DG1(dev_priv)) { - dev_priv->pch_type = PCH_DG1; + } else if (display->platform.dg1) { + display->pch_type = PCH_DG1; return; } @@ -283,14 +295,14 @@ void intel_detect_pch(struct drm_i915_private *dev_priv) id = pch->device & INTEL_PCH_DEVICE_ID_MASK; - pch_type = intel_pch_type(dev_priv, id); + pch_type = intel_pch_type(display, id); if (pch_type != PCH_NONE) { - dev_priv->pch_type = pch_type; + display->pch_type = pch_type; break; } else if (intel_is_virt_pch(id, pch->subsystem_vendor, pch->subsystem_device)) { - intel_virt_detect_pch(dev_priv, &id, &pch_type); - dev_priv->pch_type = pch_type; + intel_virt_detect_pch(display, &id, &pch_type); + display->pch_type = pch_type; break; } } @@ -299,16 +311,16 @@ void intel_detect_pch(struct drm_i915_private *dev_priv) * Use PCH_NOP (PCH but no South Display) for PCH platforms without * display. */ - if (pch && !HAS_DISPLAY(dev_priv)) { - drm_dbg_kms(&dev_priv->drm, + if (pch && !HAS_DISPLAY(display)) { + drm_dbg_kms(display->drm, "Display disabled, reverting to NOP PCH\n"); - dev_priv->pch_type = PCH_NOP; + display->pch_type = PCH_NOP; } else if (!pch) { - if (i915_run_as_guest() && HAS_DISPLAY(dev_priv)) { - intel_virt_detect_pch(dev_priv, &id, &pch_type); - dev_priv->pch_type = pch_type; + if (i915_run_as_guest() && HAS_DISPLAY(display)) { + intel_virt_detect_pch(display, &id, &pch_type); + display->pch_type = pch_type; } else { - drm_dbg_kms(&dev_priv->drm, "No PCH found.\n"); + drm_dbg_kms(display->drm, "No PCH found.\n"); } } diff --git a/drivers/gpu/drm/i915/display/intel_pch.h b/drivers/gpu/drm/i915/display/intel_pch.h index b9fa2b2f07bc..b2b309a9fe6b 100644 --- a/drivers/gpu/drm/i915/display/intel_pch.h +++ b/drivers/gpu/drm/i915/display/intel_pch.h @@ -6,7 +6,9 @@ #ifndef __INTEL_PCH__ #define __INTEL_PCH__ -struct drm_i915_private; +#include "intel_display_conversion.h" + +struct intel_display; /* * Sorted by south display engine compatibility. @@ -34,23 +36,23 @@ enum intel_pch { PCH_LNL, }; -#define INTEL_PCH_TYPE(dev_priv) ((dev_priv)->pch_type) -#define HAS_PCH_DG2(dev_priv) (INTEL_PCH_TYPE(dev_priv) == PCH_DG2) -#define HAS_PCH_ADP(dev_priv) (INTEL_PCH_TYPE(dev_priv) == PCH_ADP) -#define HAS_PCH_DG1(dev_priv) (INTEL_PCH_TYPE(dev_priv) == PCH_DG1) -#define HAS_PCH_TGP(dev_priv) (INTEL_PCH_TYPE(dev_priv) == PCH_TGP) -#define HAS_PCH_ICP(dev_priv) (INTEL_PCH_TYPE(dev_priv) == PCH_ICP) -#define HAS_PCH_CNP(dev_priv) (INTEL_PCH_TYPE(dev_priv) == PCH_CNP) -#define HAS_PCH_SPT(dev_priv) (INTEL_PCH_TYPE(dev_priv) == PCH_SPT) -#define HAS_PCH_LPT_H(dev_priv) (INTEL_PCH_TYPE(dev_priv) == PCH_LPT_H) -#define HAS_PCH_LPT_LP(dev_priv) (INTEL_PCH_TYPE(dev_priv) == PCH_LPT_LP) -#define HAS_PCH_LPT(dev_priv) (INTEL_PCH_TYPE(dev_priv) == PCH_LPT_H || \ - INTEL_PCH_TYPE(dev_priv) == PCH_LPT_LP) -#define HAS_PCH_CPT(dev_priv) (INTEL_PCH_TYPE(dev_priv) == PCH_CPT) -#define HAS_PCH_IBX(dev_priv) (INTEL_PCH_TYPE(dev_priv) == PCH_IBX) -#define HAS_PCH_NOP(dev_priv) (INTEL_PCH_TYPE(dev_priv) == PCH_NOP) -#define HAS_PCH_SPLIT(dev_priv) (INTEL_PCH_TYPE(dev_priv) != PCH_NONE) - -void intel_detect_pch(struct drm_i915_private *dev_priv); +#define INTEL_PCH_TYPE(_display) (__to_intel_display(_display)->pch_type) +#define HAS_PCH_DG2(display) (INTEL_PCH_TYPE(display) == PCH_DG2) +#define HAS_PCH_ADP(display) (INTEL_PCH_TYPE(display) == PCH_ADP) +#define HAS_PCH_DG1(display) (INTEL_PCH_TYPE(display) == PCH_DG1) +#define HAS_PCH_TGP(display) (INTEL_PCH_TYPE(display) == PCH_TGP) +#define HAS_PCH_ICP(display) (INTEL_PCH_TYPE(display) == PCH_ICP) +#define HAS_PCH_CNP(display) (INTEL_PCH_TYPE(display) == PCH_CNP) +#define HAS_PCH_SPT(display) (INTEL_PCH_TYPE(display) == PCH_SPT) +#define HAS_PCH_LPT_H(display) (INTEL_PCH_TYPE(display) == PCH_LPT_H) +#define HAS_PCH_LPT_LP(display) (INTEL_PCH_TYPE(display) == PCH_LPT_LP) +#define HAS_PCH_LPT(display) (INTEL_PCH_TYPE(display) == PCH_LPT_H || \ + INTEL_PCH_TYPE(display) == PCH_LPT_LP) +#define HAS_PCH_CPT(display) (INTEL_PCH_TYPE(display) == PCH_CPT) +#define HAS_PCH_IBX(display) (INTEL_PCH_TYPE(display) == PCH_IBX) +#define HAS_PCH_NOP(display) (INTEL_PCH_TYPE(display) == PCH_NOP) +#define HAS_PCH_SPLIT(display) (INTEL_PCH_TYPE(display) != PCH_NONE) + +void intel_detect_pch(struct intel_display *display); #endif /* __INTEL_PCH__ */ diff --git a/drivers/gpu/drm/i915/i915_driver.c b/drivers/gpu/drm/i915/i915_driver.c index f5262b8ad237..787a9864c687 100644 --- a/drivers/gpu/drm/i915/i915_driver.c +++ b/drivers/gpu/drm/i915/i915_driver.c @@ -264,7 +264,7 @@ static int i915_driver_early_probe(struct drm_i915_private *dev_priv) i915_gem_init_early(dev_priv); /* This must be called before any calls to HAS_PCH_* */ - intel_detect_pch(dev_priv); + intel_detect_pch(display); intel_irq_init(dev_priv); intel_display_driver_early_probe(display); diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h index 65e795a4ecba..38cd1750bc99 100644 --- a/drivers/gpu/drm/i915/i915_drv.h +++ b/drivers/gpu/drm/i915/i915_drv.h @@ -271,9 +271,6 @@ struct drm_i915_private { /* pm private clock gating functions */ const struct drm_i915_clock_gating_funcs *clock_gating_funcs; - /* PCH chipset type */ - enum intel_pch pch_type; - unsigned long gem_quirks; struct i915_gem_mm mm; diff --git a/drivers/gpu/drm/xe/display/xe_display.c b/drivers/gpu/drm/xe/display/xe_display.c index 20c3bcd953b7..45836fca51d8 100644 --- a/drivers/gpu/drm/xe/display/xe_display.c +++ b/drivers/gpu/drm/xe/display/xe_display.c @@ -134,7 +134,7 @@ int xe_display_init_early(struct xe_device *xe) spin_lock_init(&xe->uncore.lock); /* This must be called before any calls to HAS_PCH_* */ - intel_detect_pch(xe); + intel_detect_pch(display); intel_display_driver_early_probe(display); diff --git a/drivers/gpu/drm/xe/xe_device_types.h b/drivers/gpu/drm/xe/xe_device_types.h index 9662bbfb257c..b69cd91c46d1 100644 --- a/drivers/gpu/drm/xe/xe_device_types.h +++ b/drivers/gpu/drm/xe/xe_device_types.h @@ -586,7 +586,6 @@ struct xe_device { * migrating to the right sub-structs */ struct intel_display display; - enum intel_pch pch_type; struct dram_info { bool wm_lv_0_adjust_needed; From patchwork Fri Apr 11 09:54:13 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jani Nikula X-Patchwork-Id: 14048002 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 4CCAAC369AA for ; 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X-CSE-ConnectionGUID: OQkQsxoATfC8YbdbvzLEDw== X-CSE-MsgGUID: HZPecSVzRnGUDFSBLqjFSg== X-IronPort-AV: E=McAfee;i="6700,10204,11400"; a="56094864" X-IronPort-AV: E=Sophos;i="6.15,203,1739865600"; d="scan'208";a="56094864" Received: from fmviesa003.fm.intel.com ([10.60.135.143]) by orvoesa103.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 11 Apr 2025 02:54:37 -0700 X-CSE-ConnectionGUID: OltnPvjWQFKpEQq2VWTBAw== X-CSE-MsgGUID: hp2SXuFOSwuLQBtuEagO4w== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.15,203,1739865600"; d="scan'208";a="133265655" Received: from vpanait-mobl.ger.corp.intel.com (HELO localhost) ([10.245.246.115]) by fmviesa003-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 11 Apr 2025 02:54:35 -0700 From: Jani Nikula To: intel-gfx@lists.freedesktop.org, intel-xe@lists.freedesktop.org Cc: jani.nikula@intel.com, rodrigo.vivi@intel.com, lucas.demarchi@intel.com, ville.syrjala@linux.intel.com Subject: [PATCH 3/4] drm/i915/pch: move PCH detection to intel_display_driver_early_probe() Date: Fri, 11 Apr 2025 12:54:13 +0300 Message-Id: X-Mailer: git-send-email 2.39.5 In-Reply-To: References: MIME-Version: 1.0 Organization: Intel Finland Oy - BIC 0357606-4 - Westendinkatu 7, 02160 Espoo X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" Make PCH detection part of display. For now, call it also for !HAS_DISPLAY() to avoid functional changes here. Signed-off-by: Jani Nikula Reviewed-by: Lucas De Marchi --- drivers/gpu/drm/i915/display/intel_display_driver.c | 3 +++ drivers/gpu/drm/i915/display/intel_pch.c | 2 +- drivers/gpu/drm/i915/display/intel_pch.h | 2 +- drivers/gpu/drm/i915/i915_driver.c | 3 --- drivers/gpu/drm/xe/display/xe_display.c | 3 --- 5 files changed, 5 insertions(+), 8 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_display_driver.c b/drivers/gpu/drm/i915/display/intel_display_driver.c index efee8925987e..e4192f6cb0c7 100644 --- a/drivers/gpu/drm/i915/display/intel_display_driver.c +++ b/drivers/gpu/drm/i915/display/intel_display_driver.c @@ -180,6 +180,9 @@ static void intel_plane_possible_crtcs_init(struct intel_display *display) void intel_display_driver_early_probe(struct intel_display *display) { + /* This must be called before any calls to HAS_PCH_* */ + intel_pch_detect(display); + if (!HAS_DISPLAY(display)) return; diff --git a/drivers/gpu/drm/i915/display/intel_pch.c b/drivers/gpu/drm/i915/display/intel_pch.c index e63480dd01fe..c5045d2527b4 100644 --- a/drivers/gpu/drm/i915/display/intel_pch.c +++ b/drivers/gpu/drm/i915/display/intel_pch.c @@ -250,7 +250,7 @@ intel_virt_detect_pch(const struct intel_display *display, *pch_id = id; } -void intel_detect_pch(struct intel_display *display) +void intel_pch_detect(struct intel_display *display) { struct pci_dev *pch = NULL; unsigned short id; diff --git a/drivers/gpu/drm/i915/display/intel_pch.h b/drivers/gpu/drm/i915/display/intel_pch.h index b2b309a9fe6b..cf4dab1b98bf 100644 --- a/drivers/gpu/drm/i915/display/intel_pch.h +++ b/drivers/gpu/drm/i915/display/intel_pch.h @@ -53,6 +53,6 @@ enum intel_pch { #define HAS_PCH_NOP(display) (INTEL_PCH_TYPE(display) == PCH_NOP) #define HAS_PCH_SPLIT(display) (INTEL_PCH_TYPE(display) != PCH_NONE) -void intel_detect_pch(struct intel_display *display); +void intel_pch_detect(struct intel_display *display); #endif /* __INTEL_PCH__ */ diff --git a/drivers/gpu/drm/i915/i915_driver.c b/drivers/gpu/drm/i915/i915_driver.c index 787a9864c687..97ff9855b5de 100644 --- a/drivers/gpu/drm/i915/i915_driver.c +++ b/drivers/gpu/drm/i915/i915_driver.c @@ -263,9 +263,6 @@ static int i915_driver_early_probe(struct drm_i915_private *dev_priv) i915_gem_init_early(dev_priv); - /* This must be called before any calls to HAS_PCH_* */ - intel_detect_pch(display); - intel_irq_init(dev_priv); intel_display_driver_early_probe(display); intel_clock_gating_hooks_init(dev_priv); diff --git a/drivers/gpu/drm/xe/display/xe_display.c b/drivers/gpu/drm/xe/display/xe_display.c index 45836fca51d8..68f064f33d4b 100644 --- a/drivers/gpu/drm/xe/display/xe_display.c +++ b/drivers/gpu/drm/xe/display/xe_display.c @@ -133,9 +133,6 @@ int xe_display_init_early(struct xe_device *xe) /* Fake uncore lock */ spin_lock_init(&xe->uncore.lock); - /* This must be called before any calls to HAS_PCH_* */ - intel_detect_pch(display); - intel_display_driver_early_probe(display); /* Early display init.. */ From patchwork Fri Apr 11 09:54:14 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jani Nikula X-Patchwork-Id: 14048003 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id DC427C369A9 for ; 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X-CSE-ConnectionGUID: CFjaFExrSdWzY45+pGsq4g== X-CSE-MsgGUID: sMmXVXfJRfmnrV4xAcomLQ== X-IronPort-AV: E=McAfee;i="6700,10204,11400"; a="56094880" X-IronPort-AV: E=Sophos;i="6.15,203,1739865600"; d="scan'208";a="56094880" Received: from fmviesa003.fm.intel.com ([10.60.135.143]) by orvoesa103.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 11 Apr 2025 02:54:43 -0700 X-CSE-ConnectionGUID: BWBoT/huRRu11Xdt3zcE7g== X-CSE-MsgGUID: pyd0YEA/QAiGsDttQEk8ew== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.15,203,1739865600"; d="scan'208";a="133265688" Received: from vpanait-mobl.ger.corp.intel.com (HELO localhost) ([10.245.246.115]) by fmviesa003-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 11 Apr 2025 02:54:41 -0700 From: Jani Nikula To: intel-gfx@lists.freedesktop.org, intel-xe@lists.freedesktop.org Cc: jani.nikula@intel.com, rodrigo.vivi@intel.com, lucas.demarchi@intel.com, ville.syrjala@linux.intel.com Subject: [PATCH 4/4] drm/i915/pch: clean up includes Date: Fri, 11 Apr 2025 12:54:14 +0300 Message-Id: <68ec70f6880b7af19bc93b9817959299634a555d.1744364975.git.jani.nikula@intel.com> X-Mailer: git-send-email 2.39.5 In-Reply-To: References: MIME-Version: 1.0 Organization: Intel Finland Oy - BIC 0357606-4 - Westendinkatu 7, 02160 Espoo X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" We no longer need i915_drv.h in intel_pch.c, and we no longer need intel_pch.h universally. With intel_pch.h being included from intel_display_core.h, it's still included pretty much everywhere, but there's no need to include it explicitly from i915_drv.h or xe_device_types.h. Signed-off-by: Jani Nikula Reviewed-by: Lucas De Marchi --- drivers/gpu/drm/i915/display/intel_pch.c | 4 +++- drivers/gpu/drm/i915/i915_drv.h | 1 - drivers/gpu/drm/xe/xe_device_types.h | 1 - 3 files changed, 3 insertions(+), 3 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_pch.c b/drivers/gpu/drm/i915/display/intel_pch.c index c5045d2527b4..fec1919e5386 100644 --- a/drivers/gpu/drm/i915/display/intel_pch.c +++ b/drivers/gpu/drm/i915/display/intel_pch.c @@ -3,8 +3,10 @@ * Copyright 2025 Intel Corporation. */ -#include "i915_drv.h" +#include + #include "i915_utils.h" +#include "intel_display_core.h" #include "intel_pch.h" #define INTEL_PCH_DEVICE_ID_MASK 0xff80 diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h index 38cd1750bc99..c0eec8fe5cad 100644 --- a/drivers/gpu/drm/i915/i915_drv.h +++ b/drivers/gpu/drm/i915/i915_drv.h @@ -38,7 +38,6 @@ #include "display/intel_display_limits.h" #include "display/intel_display_core.h" -#include "display/intel_pch.h" #include "gem/i915_gem_context_types.h" #include "gem/i915_gem_shrinker.h" diff --git a/drivers/gpu/drm/xe/xe_device_types.h b/drivers/gpu/drm/xe/xe_device_types.h index b69cd91c46d1..b9a892c44c67 100644 --- a/drivers/gpu/drm/xe/xe_device_types.h +++ b/drivers/gpu/drm/xe/xe_device_types.h @@ -31,7 +31,6 @@ #endif #if IS_ENABLED(CONFIG_DRM_XE_DISPLAY) -#include "intel_pch.h" #include "intel_display_core.h" #include "intel_display_device.h" #endif