From patchwork Sat Apr 12 19:40:03 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Hauke Mehrtens X-Patchwork-Id: 14049104 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 263BFC369AB for ; Sat, 12 Apr 2025 20:24:04 +0000 (UTC) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1u3hNz-0002Vg-Ka; Sat, 12 Apr 2025 16:23:31 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1u3gia-0005ld-JQ; Sat, 12 Apr 2025 15:40:44 -0400 Received: from mout-p-102.mailbox.org ([2001:67c:2050:0:465::102]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_CHACHA20_POLY1305:256) (Exim 4.90_1) (envelope-from ) id 1u3giZ-0004WV-2q; Sat, 12 Apr 2025 15:40:44 -0400 Received: from smtp202.mailbox.org (smtp202.mailbox.org [IPv6:2001:67c:2050:b231:465::202]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits) server-digest SHA256) (No client certificate requested) by mout-p-102.mailbox.org (Postfix) with ESMTPS id 4ZZkRh6xw5z9shn; Sat, 12 Apr 2025 21:40:32 +0200 (CEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=hauke-m.de; s=MBO0001; t=1744486833; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version: content-transfer-encoding:content-transfer-encoding; bh=3uYoCqQQCUB8iBV2tcSnaC2ZQgWOZfba1Gs7NYa+mYI=; b=ExjXzW7/n3f/xF6bFXhnN0ufrq0jip4BLOHEcR+g1u4hCcgmBFQEHQ11QyB+cpt7brJN0D IUjgl7IXyteTyku2So6KJc+PFxxyAjD2jLFNXLM8VBxPGI9/IzbjQxhD0iyqEWo/PyVlX9 vZGbxoTe6Jqlw3Q1zcoB2HHueWWjfdje0zaWe3o8ClrupW1GGKjIGDR1IKYlIqng0tPk1P YO6EkF7E3nb+qlfyfYxcFTyzKHhXsBheqy1fcz/W38mvl+7MNozRykUyWfnzIMtJ3qH++M qzoi1ZzIaHP1j3h5cupzsKeIlDrFpjKa9toLw5TTO99j/itGUs2lnS4S+9ourw== From: Hauke Mehrtens To: qemu-devel@nongnu.org Cc: arikalo@gmail.com, jiaxun.yang@flygoat.com, aurelien@aurel32.net, philmd@linaro.org, Hauke Mehrtens , qemu-stable@nongnu.org Subject: target/mips: Fix MIPS16e translation Date: Sat, 12 Apr 2025 21:40:03 +0200 Message-ID: <20250412194003.181411-1-hauke@hauke-m.de> MIME-Version: 1.0 X-Rspamd-Queue-Id: 4ZZkRh6xw5z9shn Received-SPF: pass client-ip=2001:67c:2050:0:465::102; envelope-from=hauke@hauke-m.de; helo=mout-p-102.mailbox.org X-Spam_score_int: -27 X-Spam_score: -2.8 X-Spam_bar: -- X-Spam_report: (-2.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_LOW=-0.7, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-Mailman-Approved-At: Sat, 12 Apr 2025 16:23:29 -0400 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Fix a wrong conversion to gen_op_addr_addi(). The framesize should be added like it was done before. This bug broke booting OpenWrt MIPS32 BE malta Linux system images generated by OpenWrt. Fixes: d0b24b7f50e1 ("target/mips: Use gen_op_addr_addi() when possible") Cc: qemu-stable@nongnu.org Signed-off-by: Hauke Mehrtens Reviewed-by: Philippe Mathieu-Daudé --- target/mips/tcg/mips16e_translate.c.inc | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/target/mips/tcg/mips16e_translate.c.inc b/target/mips/tcg/mips16e_translate.c.inc index a9af8f1e74..97da3456ea 100644 --- a/target/mips/tcg/mips16e_translate.c.inc +++ b/target/mips/tcg/mips16e_translate.c.inc @@ -306,7 +306,7 @@ static void gen_mips16_restore(DisasContext *ctx, int astatic; TCGv t0 = tcg_temp_new(); - gen_op_addr_addi(ctx, t0, cpu_gpr[29], -framesize); + gen_op_addr_addi(ctx, t0, cpu_gpr[29], framesize); if (do_ra) { decr_and_load(ctx, 31, t0); @@ -386,7 +386,7 @@ static void gen_mips16_restore(DisasContext *ctx, } } - gen_op_addr_addi(ctx, cpu_gpr[29], cpu_gpr[29], -framesize); + gen_op_addr_addi(ctx, cpu_gpr[29], cpu_gpr[29], framesize); } #if defined(TARGET_MIPS64)