From patchwork Mon Apr 14 16:45:12 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ayan Kumar Halder X-Patchwork-Id: 14050730 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.xenproject.org (lists.xenproject.org [192.237.175.120]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 93964C369A2 for ; Mon, 14 Apr 2025 16:45:59 +0000 (UTC) Received: from list by lists.xenproject.org with outflank-mailman.950877.1347067 (Exim 4.92) (envelope-from ) id 1u4MwJ-00041C-QO; Mon, 14 Apr 2025 16:45:43 +0000 X-Outflank-Mailman: Message body and most headers restored to incoming version Received: by outflank-mailman (output) from mailman id 950877.1347067; Mon, 14 Apr 2025 16:45:43 +0000 Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1u4MwJ-000415-Nf; Mon, 14 Apr 2025 16:45:43 +0000 Received: by outflank-mailman (input) for mailman id 950877; Mon, 14 Apr 2025 16:45:42 +0000 Received: from se1-gles-flk1-in.inumbo.com ([94.247.172.50] helo=se1-gles-flk1.inumbo.com) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1u4MwI-0003ls-9p for xen-devel@lists.xenproject.org; Mon, 14 Apr 2025 16:45:42 +0000 Received: from NAM02-SN1-obe.outbound.protection.outlook.com (mail-sn1nam02on20624.outbound.protection.outlook.com [2a01:111:f403:2406::624]) by se1-gles-flk1.inumbo.com (Halon) with ESMTPS id e5771f0f-194f-11f0-9ffb-bf95429c2676; Mon, 14 Apr 2025 18:45:40 +0200 (CEST) Received: from SJ0PR13CA0072.namprd13.prod.outlook.com (2603:10b6:a03:2c4::17) by SA1PR12MB9492.namprd12.prod.outlook.com (2603:10b6:806:459::7) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.8632.30; Mon, 14 Apr 2025 16:45:36 +0000 Received: from SJ1PEPF00001CEB.namprd03.prod.outlook.com (2603:10b6:a03:2c4:cafe::a5) by SJ0PR13CA0072.outlook.office365.com (2603:10b6:a03:2c4::17) with Microsoft SMTP Server (version=TLS1_3, cipher=TLS_AES_256_GCM_SHA384) id 15.20.8655.8 via Frontend Transport; Mon, 14 Apr 2025 16:45:35 +0000 Received: from SATLEXMB03.amd.com (165.204.84.17) by SJ1PEPF00001CEB.mail.protection.outlook.com (10.167.242.27) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.20.8655.12 via Frontend Transport; Mon, 14 Apr 2025 16:45:35 +0000 Received: from SATLEXMB06.amd.com (10.181.40.147) by SATLEXMB03.amd.com (10.181.40.144) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.39; Mon, 14 Apr 2025 11:45:34 -0500 Received: from SATLEXMB04.amd.com (10.181.40.145) by SATLEXMB06.amd.com (10.181.40.147) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.39; Mon, 14 Apr 2025 11:45:34 -0500 Received: from xcbayankuma40.xilinx.com (10.180.168.240) by SATLEXMB04.amd.com (10.181.40.145) with Microsoft SMTP Server id 15.1.2507.39 via Frontend Transport; Mon, 14 Apr 2025 11:45:33 -0500 X-BeenThere: xen-devel@lists.xenproject.org List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Errors-To: xen-devel-bounces@lists.xenproject.org Precedence: list Sender: "Xen-devel" X-Inumbo-ID: e5771f0f-194f-11f0-9ffb-bf95429c2676 ARC-Seal: i=1; a=rsa-sha256; s=arcselector10001; d=microsoft.com; cv=none; b=YkLGeK8NvI9E04+WsEcBjcNKijn9i3zcwOwyfxkmlGg4PW5Ii3+SOVr4TJFkro+657El1mGG2YyEpy/hn9fYZw+GpxMg3kP+uyxBSx6o01gGEABq5HZPwqafH2lcA3fKIWZD9xKjXI3u6YxbFHCHH7bQw3iq9f8bror6pGTDnXBvrPkMALdxr7ongtMvrdEJvBcklZt04EPXbD3St14Beq91Y8s2sYWrvSbxu+YM0qcQPYR3dbOcWaGrXG7IZ7R1FvcKl+ac/EQ79rcJBUqvbykZ70c1XdbEd0InFzduFDqTc2UaFdUSqKTEBi36cdXgEoZAyRtnWsbrw4PZmPCN8w== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector10001; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1; bh=ZuwCRj4OOUZ4a9010l9+6ShDpNXekNIhaBCOz4phGPQ=; b=yA5TjKbhe1ki5VlJhTlQU9E2cB0LV0mMM2dBvpOq+QsT9K7Eo95sI1YaXfmMbrC+I4x8I+TZ/jWdRMiF7wuCcY19OGUwKTV9xtP8CgEwH+fxxQSBZSzWl48FU2jAeNtcTcj8uXGjKzPUgjhcCIZi5168Y2H5FgTthMSPp9FEZD6mLOhEPe8bAg4e8WWzJbe/b7uT7iLOEwzB03i4sq2i6TP8LNLLBE+gLNkIuGd8DCHVUBkmZrSvM7k2RkvXS7s6q0UMZjXvkNfHutRG2f7BO0TwrNQL0EYgoglBwN3/tdFPvzlaiTrxoSr7vyv4kHjmQUeXBHBtaVowrUd8xMqdbA== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass (sender ip is 165.204.84.17) smtp.rcpttodomain=lists.xenproject.org smtp.mailfrom=amd.com; dmarc=pass (p=quarantine sp=quarantine pct=100) action=none header.from=amd.com; dkim=none (message not signed); arc=none (0) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=amd.com; s=selector1; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=ZuwCRj4OOUZ4a9010l9+6ShDpNXekNIhaBCOz4phGPQ=; b=lzVdwo0q/sHo4VQe0Pvja4vI8PJ3re6zOa9WFlZiFIpGsnKnX4DHUkk5yCYFD1y0f1mIaUUMenI+7iUT3Kys/5fShvnBkkCLDYA1rZ/PX8u5/ZLOFGub+Uk/aFRLsh6xp3LE7lS36Bx0W3sMBbeiHegbAg/3/fPmHyt7rfqbcYo= X-MS-Exchange-Authentication-Results: spf=pass (sender IP is 165.204.84.17) smtp.mailfrom=amd.com; dkim=none (message not signed) header.d=none;dmarc=pass action=none header.from=amd.com; Received-SPF: Pass (protection.outlook.com: domain of amd.com designates 165.204.84.17 as permitted sender) receiver=protection.outlook.com; client-ip=165.204.84.17; helo=SATLEXMB03.amd.com; pr=C From: Ayan Kumar Halder To: CC: Ayan Kumar Halder , Stefano Stabellini , Julien Grall , Bertrand Marquis , Michal Orzel , "Volodymyr Babchuk" , Luca Fancellu Subject: [PATCH v7 1/3] xen/arm: Move some of the functions to common file Date: Mon, 14 Apr 2025 17:45:12 +0100 Message-ID: <20250414164514.588373-2-ayan.kumar.halder@amd.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20250414164514.588373-1-ayan.kumar.halder@amd.com> References: <20250414164514.588373-1-ayan.kumar.halder@amd.com> MIME-Version: 1.0 X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: SJ1PEPF00001CEB:EE_|SA1PR12MB9492:EE_ X-MS-Office365-Filtering-Correlation-Id: 04d68a0e-0f7c-4593-952b-08dd7b73c771 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|82310400026|36860700013|376014|1800799024; X-Microsoft-Antispam-Message-Info: uf8G5axzb8Wg51YjAODCrwi2/Aw3FNdB95akj5W+qqRVFaMSUvz+F2wo/SFkE1uqcduvJeQD6YNhKpq4H3IIhGlw6GmgdQg1lohjNxQk+IyBiM/9XnUdJNQi2rt5eZtWn3hGD4wOP4yUS8uPo2kR1aUnDdKVeobYxOGkh4Fallr/Xg3YSnbR23YmYhGmWnK/TjZT83v2yfShX8hXWGPrkMo8pN3ccMY+3oFAI6IG7NePIAKrEwaH2X/VfPlFY2PcVShLbXmbAqtNNRA9KPORJXhZVCVOvbOsGOBh3ejbLmyip3PL9kYo8j4H5Yf4MXyOs2nC85Vh0VmU+U/OL+ioCgugs/McTXxYgTdxHkd2w5WtlGFRMRuGDKB/rfLhV99WWTZK6aXw4D50DI5auW1IVJzim/5pxHc2vvEIFpWufJFA7Tirgkrj9Op2/eHfzRUwCwG4ZiGHpjg4QeBcSIYK3sFsokNRUvix9cjs2C1M/Jm3Ak39m4LIQTX9jD7K3IgS6pOdi4cQmzgR8PCvD3I2OQ5YEbwgxqxVj/qDQCGwxsXE2VZ9he9kEjgLNeuc1BJQhcnJP+aB1eyvhoKhgyXaiCccFoyDtvc9D4F3u2JUoSfhBmwAHFu8sHzbUJ/3AGcJB51dUqQW1g4Zsn63VosmlIc7dXQVRCNcxnSfVW88KRNZtPg+nMRxtMpnP3jtFTV+DveNjIgn31nz2WB7Iahpp8IFUpoiRLGPy+8Jk6bLbVDcTY/34bWDdv+up6VhbEFRdHi9O6lWpXLV9SBuGQ6hF8M76pSs3/W0XA6/0iVQ3AdON28xdy67uOO0QsBYCOtmYBD0tLdf+FCEBXJtZP2zOcXSM5BIWppp8DnxbNeamqLktLteubllflUxDWCLQ1R0w+cwyZ07TyUq9X0mvwfXrtIXAMYLq3zTmPcchaQoMdyLeVS8UlrJUhiLCEiEvo2/4A9hIKRPOkDTFUkxQH2z7ug62yPmBRTXMLepeotu6y1O67+bSFilR76YCrxsKhek4hPdFHDYbSLnkG+Bynf90ScIKom/pWmf/ai5XYctoLrawtetYQYrTr+EenAKKE963Qs+JwgxMLuv2vyB63zQvamxgKx/KDK5t01pxMGs0wZYlhmFoiLfjYNDLpmIj9FMh+4+QmMasuQo/gmHO1DI81xh2qVpEScgMOXfh0L6r8U0xp2vHshhwByFyFcwm/folBatgQF3Ygb40ywib5jwRHpS0D8QtmvCcXZEh7/qwksQMLZSywtml+A+GGnpKuGcXBT5j1LVsLh8Gu/wHmb+nU3UHtUA2L4zPrYvNS6AE8tWMm/0Hfk74odulF5Ksy+sbos+4kN9f1sfPGQMnFpRVclpJ4alM5tsqwb3jO4WwTf7NzUuEN8c1K7iOR5B9cMh1Dsu6os0Ca7SRjRng9PTaRavD9vlcyqwFrnx+Hnp89U7AklrFSjvKPPHSJqrS2SsglK2F4SUMMfMSsDtgnrNsl8ZtzZO0Ov25zUYSXbCZ977WfFLAgjosjpvnCc7Qz0k X-Forefront-Antispam-Report: CIP:165.204.84.17;CTRY:US;LANG:en;SCL:1;SRV:;IPV:CAL;SFV:NSPM;H:SATLEXMB03.amd.com;PTR:InfoDomainNonexistent;CAT:NONE;SFS:(13230040)(82310400026)(36860700013)(376014)(1800799024);DIR:OUT;SFP:1101; X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 14 Apr 2025 16:45:35.2637 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 04d68a0e-0f7c-4593-952b-08dd7b73c771 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB03.amd.com] X-MS-Exchange-CrossTenant-AuthSource: SJ1PEPF00001CEB.namprd03.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: SA1PR12MB9492 regions.inc is added to hold the common earlyboot MPU regions configurations between arm64 and arm32. prepare_xen_region, fail_insufficient_regions() will be used by both arm32 and arm64. Thus, they have been moved to regions.inc. *_PRBAR are moved to arm64/sysregs.h. *_PRLAR are moved to regions.inc as they are common between arm32 and arm64. Introduce WRITE_SYSREG_ASM to write to the system registers from regions.inc. Signed-off-by: Ayan Kumar Halder Reviewed-by: Luca Fancellu Reviewed-by: Michal Orzel Tested-by: Luca Fancellu --- Changes from v1 - 1. enable_mpu() now sets HMAIR{0,1} registers. This is similar to what is being done in enable_mmu(). All the mm related configurations happen in this function. 2. Fixed some typos. v2 - 1. Extracted the arm64 head.S functions/macros in a common file. v3 - 1. Moved *_PRLAR are moved to prepare_xen_region.inc 2. enable_boot_cpu_mm() is preserved in mpu/head.S. 3. STORE_SYSREG is renamed as WRITE_SYSREG_ASM() 4. LOAD_SYSREG is removed. 5. No need to save/restore lr in enable_boot_cpu_mm(). IOW, keep it as it was in the original code. v4 - 1. Rename prepare_xen_region.inc to common.inc 2. enable_secondary_cpu_mm() is moved back to mpu/head.S. v5 - 1. Rename common.inc to regions.inc. 2. WRITE_SYSREG_ASM() in enclosed within #ifdef __ASSEMBLY__. v6 - 1. Add Michal's R-b and Luca's T-b. xen/arch/arm/arm64/mpu/head.S | 78 +---------------------- xen/arch/arm/include/asm/arm64/sysregs.h | 13 ++++ xen/arch/arm/include/asm/mpu/regions.inc | 79 ++++++++++++++++++++++++ 3 files changed, 93 insertions(+), 77 deletions(-) create mode 100644 xen/arch/arm/include/asm/mpu/regions.inc diff --git a/xen/arch/arm/arm64/mpu/head.S b/xen/arch/arm/arm64/mpu/head.S index ed01993d85..6d336cafbb 100644 --- a/xen/arch/arm/arm64/mpu/head.S +++ b/xen/arch/arm/arm64/mpu/head.S @@ -3,83 +3,7 @@ * Start-of-day code for an Armv8-R MPU system. */ -#include -#include - -/* Backgroud region enable/disable */ -#define SCTLR_ELx_BR BIT(17, UL) - -#define REGION_TEXT_PRBAR 0x38 /* SH=11 AP=10 XN=00 */ -#define REGION_RO_PRBAR 0x3A /* SH=11 AP=10 XN=10 */ -#define REGION_DATA_PRBAR 0x32 /* SH=11 AP=00 XN=10 */ -#define REGION_DEVICE_PRBAR 0x22 /* SH=10 AP=00 XN=10 */ - -#define REGION_NORMAL_PRLAR 0x0f /* NS=0 ATTR=111 EN=1 */ -#define REGION_DEVICE_PRLAR 0x09 /* NS=0 ATTR=100 EN=1 */ - -/* - * Macro to prepare and set a EL2 MPU memory region. - * We will also create an according MPU memory region entry, which - * is a structure of pr_t, in table \prmap. - * - * sel: region selector - * base: reg storing base address - * limit: reg storing limit address - * prbar: store computed PRBAR_EL2 value - * prlar: store computed PRLAR_EL2 value - * maxcount: maximum number of EL2 regions supported - * attr_prbar: PRBAR_EL2-related memory attributes. If not specified it will be - * REGION_DATA_PRBAR - * attr_prlar: PRLAR_EL2-related memory attributes. If not specified it will be - * REGION_NORMAL_PRLAR - * - * Preserves \maxcount - * Output: - * \sel: Next available region selector index. - * Clobbers \base, \limit, \prbar, \prlar - * - * Note that all parameters using registers should be distinct. - */ -.macro prepare_xen_region, sel, base, limit, prbar, prlar, maxcount, attr_prbar=REGION_DATA_PRBAR, attr_prlar=REGION_NORMAL_PRLAR - /* Check if the region is empty */ - cmp \base, \limit - beq 1f - - /* Check if the number of regions exceeded the count specified in MPUIR_EL2 */ - cmp \sel, \maxcount - bge fail_insufficient_regions - - /* Prepare value for PRBAR_EL2 reg and preserve it in \prbar.*/ - and \base, \base, #MPU_REGION_MASK - mov \prbar, #\attr_prbar - orr \prbar, \prbar, \base - - /* Limit address should be inclusive */ - sub \limit, \limit, #1 - and \limit, \limit, #MPU_REGION_MASK - mov \prlar, #\attr_prlar - orr \prlar, \prlar, \limit - - msr PRSELR_EL2, \sel - isb - msr PRBAR_EL2, \prbar - msr PRLAR_EL2, \prlar - dsb sy - isb - - add \sel, \sel, #1 - -1: -.endm - -/* - * Failure caused due to insufficient MPU regions. - */ -FUNC_LOCAL(fail_insufficient_regions) - PRINT("- Selected MPU region is above the implemented number in MPUIR_EL2 -\r\n") -1: wfe - b 1b -END(fail_insufficient_regions) +#include /* * Enable EL2 MPU and data cache diff --git a/xen/arch/arm/include/asm/arm64/sysregs.h b/xen/arch/arm/include/asm/arm64/sysregs.h index b593e4028b..7440d495e4 100644 --- a/xen/arch/arm/include/asm/arm64/sysregs.h +++ b/xen/arch/arm/include/asm/arm64/sysregs.h @@ -462,6 +462,17 @@ #define ZCR_ELx_LEN_SIZE 9 #define ZCR_ELx_LEN_MASK 0x1ff +#define REGION_TEXT_PRBAR 0x38 /* SH=11 AP=10 XN=00 */ +#define REGION_RO_PRBAR 0x3A /* SH=11 AP=10 XN=10 */ +#define REGION_DATA_PRBAR 0x32 /* SH=11 AP=00 XN=10 */ +#define REGION_DEVICE_PRBAR 0x22 /* SH=10 AP=00 XN=10 */ + +#ifdef __ASSEMBLY__ + +#define WRITE_SYSREG_ASM(v, name) "msr " __stringify(name,) #v + +#else /* __ASSEMBLY__ */ + /* Access to system registers */ #define WRITE_SYSREG64(v, name) do { \ @@ -481,6 +492,8 @@ #define WRITE_SYSREG_LR(v, index) WRITE_SYSREG(v, ICH_LR_REG(index)) #define READ_SYSREG_LR(index) READ_SYSREG(ICH_LR_REG(index)) +#endif /* !__ASSEMBLY__ */ + #endif /* _ASM_ARM_ARM64_SYSREGS_H */ /* diff --git a/xen/arch/arm/include/asm/mpu/regions.inc b/xen/arch/arm/include/asm/mpu/regions.inc new file mode 100644 index 0000000000..47868a1526 --- /dev/null +++ b/xen/arch/arm/include/asm/mpu/regions.inc @@ -0,0 +1,79 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include +#include + +/* Backgroud region enable/disable */ +#define SCTLR_ELx_BR BIT(17, UL) + +#define REGION_NORMAL_PRLAR 0x0f /* NS=0 ATTR=111 EN=1 */ +#define REGION_DEVICE_PRLAR 0x09 /* NS=0 ATTR=100 EN=1 */ + +/* + * Macro to prepare and set a EL2 MPU memory region. + * We will also create an according MPU memory region entry, which + * is a structure of pr_t, in table \prmap. + * + * sel: region selector + * base: reg storing base address + * limit: reg storing limit address + * prbar: store computed PRBAR_EL2 value + * prlar: store computed PRLAR_EL2 value + * maxcount: maximum number of EL2 regions supported + * attr_prbar: PRBAR_EL2-related memory attributes. If not specified it will be + * REGION_DATA_PRBAR + * attr_prlar: PRLAR_EL2-related memory attributes. If not specified it will be + * REGION_NORMAL_PRLAR + * + * Preserves maxcount + * Output: + * sel: Next available region selector index. + * Clobbers base, limit, prbar, prlar + * + * Note that all parameters using registers should be distinct. + */ +.macro prepare_xen_region, sel, base, limit, prbar, prlar, maxcount, attr_prbar=REGION_DATA_PRBAR, attr_prlar=REGION_NORMAL_PRLAR + /* Check if the region is empty */ + cmp \base, \limit + beq 1f + + /* Check if the number of regions exceeded the count specified in MPUIR_EL2 */ + cmp \sel, \maxcount + bge fail_insufficient_regions + + /* Prepare value for PRBAR_EL2 reg and preserve it in \prbar.*/ + and \base, \base, #MPU_REGION_MASK + mov \prbar, #\attr_prbar + orr \prbar, \prbar, \base + + /* Limit address should be inclusive */ + sub \limit, \limit, #1 + and \limit, \limit, #MPU_REGION_MASK + mov \prlar, #\attr_prlar + orr \prlar, \prlar, \limit + + WRITE_SYSREG_ASM(\sel, PRSELR_EL2) + isb + WRITE_SYSREG_ASM(\prbar, PRBAR_EL2) + WRITE_SYSREG_ASM(\prlar, PRLAR_EL2) + dsb sy + isb + + add \sel, \sel, #1 + +1: +.endm + +/* Failure caused due to insufficient MPU regions. */ +FUNC_LOCAL(fail_insufficient_regions) + PRINT("- Selected MPU region is above the implemented number in MPUIR_EL2 -\r\n") +1: wfe + b 1b +END(fail_insufficient_regions) + +/* + * Local variables: + * mode: ASM + * indent-tabs-mode: nil + * End: + */ From patchwork Mon Apr 14 16:45:13 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ayan Kumar Halder X-Patchwork-Id: 14050734 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.xenproject.org (lists.xenproject.org [192.237.175.120]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 672EDC369B2 for ; Mon, 14 Apr 2025 16:52:08 +0000 (UTC) Received: from list by lists.xenproject.org with outflank-mailman.950903.1347077 (Exim 4.92) (envelope-from ) id 1u4N2K-0007LB-Fi; Mon, 14 Apr 2025 16:51:56 +0000 X-Outflank-Mailman: Message body and most headers restored to incoming version Received: by outflank-mailman (output) from mailman id 950903.1347077; Mon, 14 Apr 2025 16:51:56 +0000 Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1u4N2K-0007L4-B0; Mon, 14 Apr 2025 16:51:56 +0000 Received: by outflank-mailman (input) for mailman id 950903; Mon, 14 Apr 2025 16:51:55 +0000 Received: from se1-gles-flk1-in.inumbo.com ([94.247.172.50] helo=se1-gles-flk1.inumbo.com) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1u4Mwy-0003ls-Ch for xen-devel@lists.xenproject.org; Mon, 14 Apr 2025 16:46:24 +0000 Received: from NAM12-DM6-obe.outbound.protection.outlook.com (mail-dm6nam12on2060a.outbound.protection.outlook.com [2a01:111:f403:2417::60a]) by se1-gles-flk1.inumbo.com (Halon) with ESMTPS id fec1014e-194f-11f0-9ffb-bf95429c2676; Mon, 14 Apr 2025 18:46:22 +0200 (CEST) Received: from DS7PR05CA0082.namprd05.prod.outlook.com (2603:10b6:8:57::23) by DS7PR12MB9525.namprd12.prod.outlook.com (2603:10b6:8:251::12) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.8632.27; Mon, 14 Apr 2025 16:46:16 +0000 Received: from DS1PEPF0001708E.namprd03.prod.outlook.com (2603:10b6:8:57:cafe::c) by DS7PR05CA0082.outlook.office365.com (2603:10b6:8:57::23) with Microsoft SMTP Server (version=TLS1_3, cipher=TLS_AES_256_GCM_SHA384) id 15.20.8655.14 via Frontend Transport; Mon, 14 Apr 2025 16:46:16 +0000 Received: from SATLEXMB04.amd.com (165.204.84.17) by DS1PEPF0001708E.mail.protection.outlook.com (10.167.17.134) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.20.8655.12 via Frontend Transport; Mon, 14 Apr 2025 16:46:16 +0000 Received: from SATLEXMB05.amd.com (10.181.40.146) by SATLEXMB04.amd.com (10.181.40.145) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.39; Mon, 14 Apr 2025 11:46:16 -0500 Received: from SATLEXMB04.amd.com (10.181.40.145) by SATLEXMB05.amd.com (10.181.40.146) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.39; Mon, 14 Apr 2025 11:46:15 -0500 Received: from xcbayankuma40.xilinx.com (10.180.168.240) by SATLEXMB04.amd.com (10.181.40.145) with Microsoft SMTP Server id 15.1.2507.39 via Frontend Transport; Mon, 14 Apr 2025 11:46:14 -0500 X-BeenThere: xen-devel@lists.xenproject.org List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Errors-To: xen-devel-bounces@lists.xenproject.org Precedence: list Sender: "Xen-devel" X-Inumbo-ID: fec1014e-194f-11f0-9ffb-bf95429c2676 ARC-Seal: i=1; a=rsa-sha256; s=arcselector10001; d=microsoft.com; cv=none; b=fyouC0F1VOJPrYxwNG9BIiDftSAGZl2JdkovJLtWUwBDEFos7mSFwlk+vw5ahoGmel/AEmkQldyL1fN4ft84H0vzp24EWIJMOce5Ox9xREvmSxDG9dJPB1beU09qAA5YQfut6KCv2xzNHFcZhtDUsLDsKmH2FLRDSgXSF/6lpnbt/A/3oD7CKtEk+7OXKMzSz7eGnA6eX7viwIxErO4Fals7vt2mxfH44SHtnVCiXPj1Us0Do/Jc2d/zK2u/mMi1GeKoEoXnIqdhW2k4kTe8ecW95x3ELqO8xtRZwg9heuTESVjzhIxxO3z0VxdN2Yf7oWgYyvnhhZSjtGW0Z/klvw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector10001; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1; bh=KNIWLC11mww1ctAKkkxjTtOLEi7G6fnYwxxAr4py6UM=; b=h+SWg9Vb1QZP/UaODgcPtfB1aAQvBI0+rm/50929WDAc9ZTArdJYjNda+tX6Dz2CWAzWIDZ2iAPjBpu86+97eNfue4sxk7mat1cA/Ty7cMycJX6rnPrzJrJ1pZe3d6y4XsIpmhjXdkIRRYa0Jgnycky8qNPfislx4RkFx9zJTB+soCIVNDvO6iiLLly16Eymw3tlZo6FD+CzAerIbPLbdFXAY4K4XGFhNtB286FtMlDaWmmZEaEbKonkWS5j02L1Alw9Aq0zgNiRhcEkezwU8RWFsi3+tywzdrjjqeKLU+fyhGvoD0oMXeOkbMZb/3ERkj7zBvhI9/DmTA6WmStv3A== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass (sender ip is 165.204.84.17) smtp.rcpttodomain=lists.xenproject.org smtp.mailfrom=amd.com; dmarc=pass (p=quarantine sp=quarantine pct=100) action=none header.from=amd.com; dkim=none (message not signed); arc=none (0) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=amd.com; s=selector1; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=KNIWLC11mww1ctAKkkxjTtOLEi7G6fnYwxxAr4py6UM=; b=IgK+ZK8LswMi2LK67SsZCpWiuRD/1L1W9cBsh53UDIOnJKABwIfgovRD+h0ANdsCpRU5IaSghBuLABmbvbngXl28U3eYO+awIlJL+Ibutj85IoyKrFPNkAYV9WFn5pIVs5/sDAihh4x8GzA/W4DFErtWQKuHoFKWKI3aB2svw+U= X-MS-Exchange-Authentication-Results: spf=pass (sender IP is 165.204.84.17) smtp.mailfrom=amd.com; dkim=none (message not signed) header.d=none;dmarc=pass action=none header.from=amd.com; Received-SPF: Pass (protection.outlook.com: domain of amd.com designates 165.204.84.17 as permitted sender) receiver=protection.outlook.com; client-ip=165.204.84.17; helo=SATLEXMB04.amd.com; pr=C From: Ayan Kumar Halder To: CC: Ayan Kumar Halder , Stefano Stabellini , Julien Grall , Bertrand Marquis , Michal Orzel , "Volodymyr Babchuk" , Luca Fancellu Subject: [PATCH v7 2/3] xen/arm32: Create the same boot-time MPU regions as arm64 Date: Mon, 14 Apr 2025 17:45:13 +0100 Message-ID: <20250414164514.588373-3-ayan.kumar.halder@amd.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20250414164514.588373-1-ayan.kumar.halder@amd.com> References: <20250414164514.588373-1-ayan.kumar.halder@amd.com> MIME-Version: 1.0 Received-SPF: None (SATLEXMB05.amd.com: ayan.kumar.halder@amd.com does not designate permitted sender hosts) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: DS1PEPF0001708E:EE_|DS7PR12MB9525:EE_ X-MS-Office365-Filtering-Correlation-Id: c6ab11f8-a117-4af2-0d7d-08dd7b73e011 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|82310400026|1800799024|36860700013|376014; X-Microsoft-Antispam-Message-Info: AfF9FriVU48jUW3H4JKW2A432M8zrp7NGpvY1r50FK1At5zWIjsqRQ7TvIdFgcYRu9lUur3bPBBpTsRRpU9rWHWuG3+k5ZVdmJFB3soiEMfZ2CTGVWPEqy3pb0ShxtkppE9its+PkMq2hkJBS2PLxVaj8cz1xFJYMx6ChIzecmMdsjdNFzyijmA1tU8aBPAZ6Xnk1N87EFkT6WGCHs7kTJkTBiIEDYr9XHhRyfxll0XrIBHru5OYyzepVC3XUcJQj1nxR7ZXkWpG/L4amPSdcNltpEEZAithrBQDDt9x+AbnNkj/NeWHwupM7LqwUaU04+8RNPf/LAuEfB5SXOCVLLf6lXFRUd7gKaEIXXcdWzxzGKH2CbRFqR3PgU4meRPIHeKhtC+qmYp8v8jJAoGzbxpNgx0IG1ljZ2K6mNq/O5sw4N1oZcL+FOxTt8hCzEADZ34RqiyHEo+GyoTLR7VSdpsq6dTl4WRu/Y27S4g9TTx/FFiYXOJpO5KvX9rV0pxljN7/TXFyMGliXMLbya66ZbL0tCn4GKL44YkgWhCwmU1P5Q3Nt0Pr4+Cs5jHEuUdOGjCdE+mQdGk1mjDcP7wEP36Lk5uYsVn/gZ7U3kSu2YcqPqXBtwKdF4NbbI20vFtmI7h5PfvfwLdikF479ILV06KYfRp3ctfU+kO02L29bHQ3tznCa0Fmh7JNE6RrU5ODQHN04hDcEVbd4qLQSIyqIJa1jsNihzeF4QHWgp/VKFwGj0x0tkBSW3TP7l7qTOLb7Ebn14HEIkxxJEoh5U9dwo6g04MliWwxj8fM761MdV0LI0dtT2YMGKSKf+OrHwkGcjmfxPx2s7zpE/n6MZeTZNbJcT1Wzem5sFxpxyzw5siq4JsGIn9xlLXXy15+Tiq/aRyEMpPqQ1CbTjiuuF0H30qJG2+myFEgrnoqtJwT+PXBRZISFkyb2Yg4bQlOuRJ7aJVeEYcGv7whQIIT89GoqrXG4gLn04ctkZqgUYHUBsXmouSL1VvOs9hE7JAocn8co7CaKRBU6MyJWS+uWCB0NsWwfaX9KZhyIYCoKby+a89iyJohrs1K8MFQEB7ogVjkqxKo/7MeRYphZkM2gHFg6Y02nYEv9dplgKu45IIrIUfl6732XwhthfAxZR3UXLZNRYmoy5p9X31C2SUEsjuKdO9YloUULoaldANpED6OOf7pzd7+xdNhoR/pCuNEEcoqdpHgXVp7Hr70Cv0rfTDOZ8VppSQidLUjOdrN8V/f7yKcXtcPddudJv/aPExb/hvcFCFRbqDUwmzgDQs5+zR/5L/pUAVI80PFe4+8VaSe7L4OzBzb7w0Je2Kp+bnYU1cpMhpw7CahEHyHtpy1wDEHMVqsbOAF5rDdOtMlSTypmptmUYZ+MCfSostJ15JttMlGPhunY5Lo23+Z0lCpA3UFALGjNsltR9BX7bfTDDRa9Rk8FX2kp+S6mzhsEnSSsfQGUlVzv/2F/ecmvdG2mULYaLfpnebJhsACMLJDH/tXTLeDMXzg5i/DvTcDAScwvgDl X-Forefront-Antispam-Report: CIP:165.204.84.17;CTRY:US;LANG:en;SCL:1;SRV:;IPV:CAL;SFV:NSPM;H:SATLEXMB04.amd.com;PTR:InfoDomainNonexistent;CAT:NONE;SFS:(13230040)(82310400026)(1800799024)(36860700013)(376014);DIR:OUT;SFP:1101; X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 14 Apr 2025 16:46:16.6366 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: c6ab11f8-a117-4af2-0d7d-08dd7b73e011 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: DS1PEPF0001708E.namprd03.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DS7PR12MB9525 Create Boot-time MPU protection regions (similar to Armv8-R AArch64) for Armv8-R AArch32. Also, defined *_PRBAR macros for arm32. The only difference from arm64 is that XN is 1-bit for arm32. Define the system registers and macros in mpu/cpregs.h. Introduce WRITE_SYSREG_ASM() to write to system registers in assembly. Signed-off-by: Ayan Kumar Halder Reviewed-by: Luca Fancellu Tested-by: Luca Fancellu Reviewed-by: Michal Orzel --- Changes from v1 - 1. enable_mpu() now sets HMAIR{0,1} registers. This is similar to what is being done in enable_mmu(). All the mm related configurations happen in this function. 2. Fixed some typos. v2 - 1. Include the common prepare_xen_region.inc in head.S. 2. Define LOAD_SYSREG()/STORE_SYSREG() for arm32. v3 - 1. Rename STORE_SYSREG() as WRITE_SYSREG_ASM() 2. enable_boot_cpu_mm() is defined in head.S v4 - 1. *_PRBAR is moved to arm32/sysregs.h. 2. MPU specific CP15 system registers are defined in mpu/cpregs.h. v5 - 1. WRITE_SYSREG_ASM is enclosed within #ifdef __ASSEMBLY__ 2. enable_mpu() clobbers r0 only. 3. Definitions in mpu/cpregs.h in enclosed within ARM_32. 4. Removed some #ifdefs and style changes. v6 - 1. Coding style issues. 2. Kept Luca's R-b and T-b as the changes should not impact the behavior. 3. Added alias and renamed the sysregs as it is named in the specs. xen/arch/arm/arm32/Makefile | 1 + xen/arch/arm/arm32/mpu/Makefile | 1 + xen/arch/arm/arm32/mpu/head.S | 104 +++++++++++++++++++++++ xen/arch/arm/include/asm/arm32/sysregs.h | 13 ++- xen/arch/arm/include/asm/cpregs.h | 2 + xen/arch/arm/include/asm/mpu/cpregs.h | 32 +++++++ 6 files changed, 151 insertions(+), 2 deletions(-) create mode 100644 xen/arch/arm/arm32/mpu/Makefile create mode 100644 xen/arch/arm/arm32/mpu/head.S create mode 100644 xen/arch/arm/include/asm/mpu/cpregs.h diff --git a/xen/arch/arm/arm32/Makefile b/xen/arch/arm/arm32/Makefile index 40a2b4803f..537969d753 100644 --- a/xen/arch/arm/arm32/Makefile +++ b/xen/arch/arm/arm32/Makefile @@ -1,5 +1,6 @@ obj-y += lib/ obj-$(CONFIG_MMU) += mmu/ +obj-$(CONFIG_MPU) += mpu/ obj-$(CONFIG_EARLY_PRINTK) += debug.o obj-y += domctl.o diff --git a/xen/arch/arm/arm32/mpu/Makefile b/xen/arch/arm/arm32/mpu/Makefile new file mode 100644 index 0000000000..3340058c08 --- /dev/null +++ b/xen/arch/arm/arm32/mpu/Makefile @@ -0,0 +1 @@ +obj-y += head.o diff --git a/xen/arch/arm/arm32/mpu/head.S b/xen/arch/arm/arm32/mpu/head.S new file mode 100644 index 0000000000..b2c5245e51 --- /dev/null +++ b/xen/arch/arm/arm32/mpu/head.S @@ -0,0 +1,104 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Start-of-day code for an Armv8-R-AArch32 MPU system. + */ + +#include +#include +#include +#include +#include +#include + +/* + * Set up the memory attribute type tables and enable EL2 MPU and data cache. + * If the Background region is enabled, then the MPU uses the default memory + * map as the Background region for generating the memory + * attributes when MPU is disabled. + * Since the default memory map of the Armv8-R AArch32 architecture is + * IMPLEMENTATION DEFINED, we intend to turn off the Background region here. + * + * Clobbers r0 + */ +FUNC_LOCAL(enable_mpu) + /* Set up memory attribute type tables */ + mov_w r0, MAIR0VAL + mcr CP32(r0, HMAIR0) + mov_w r0, MAIR1VAL + mcr CP32(r0, HMAIR1) + + mrc CP32(r0, HSCTLR) + bic r0, r0, #SCTLR_ELx_BR /* Disable Background region */ + orr r0, r0, #SCTLR_Axx_ELx_M /* Enable MPU */ + orr r0, r0, #SCTLR_Axx_ELx_C /* Enable D-cache */ + mcr CP32(r0, HSCTLR) + isb + + ret +END(enable_mpu) + +/* + * Maps the various sections of Xen (described in xen.lds.S) as different MPU + * regions. + * + * Clobbers r0 - r5 + * + */ +FUNC(enable_boot_cpu_mm) + /* Get the number of regions specified in MPUIR_EL2 */ + mrc CP32(r5, MPUIR_EL2) + and r5, r5, #NUM_MPU_REGIONS_MASK + + /* x0: region sel */ + mov r0, #0 + /* Xen text section. */ + mov_w r1, _stext + mov_w r2, _etext + prepare_xen_region r0, r1, r2, r3, r4, r5, attr_prbar=REGION_TEXT_PRBAR + + /* Xen read-only data section. */ + mov_w r1, _srodata + mov_w r2, _erodata + prepare_xen_region r0, r1, r2, r3, r4, r5, attr_prbar=REGION_RO_PRBAR + + /* Xen read-only after init and data section. (RW data) */ + mov_w r1, __ro_after_init_start + mov_w r2, __init_begin + prepare_xen_region r0, r1, r2, r3, r4, r5 + + /* Xen code section. */ + mov_w r1, __init_begin + mov_w r2, __init_data_begin + prepare_xen_region r0, r1, r2, r3, r4, r5, attr_prbar=REGION_TEXT_PRBAR + + /* Xen data and BSS section. */ + mov_w r1, __init_data_begin + mov_w r2, __bss_end + prepare_xen_region r0, r1, r2, r3, r4, r5 + +#ifdef CONFIG_EARLY_PRINTK + /* Xen early UART section. */ + mov_w r1, CONFIG_EARLY_UART_BASE_ADDRESS + mov_w r2, (CONFIG_EARLY_UART_BASE_ADDRESS + CONFIG_EARLY_UART_SIZE) + prepare_xen_region r0, r1, r2, r3, r4, r5, attr_prbar=REGION_DEVICE_PRBAR, attr_prlar=REGION_DEVICE_PRLAR +#endif + + b enable_mpu +END(enable_boot_cpu_mm) + +/* + * We don't yet support secondary CPUs bring-up. Implement a dummy helper to + * please the common code. + */ +FUNC(enable_secondary_cpu_mm) + PRINT("- SMP not enabled yet -\r\n") +1: wfe + b 1b +END(enable_secondary_cpu_mm) + +/* + * Local variables: + * mode: ASM + * indent-tabs-mode: nil + * End: + */ diff --git a/xen/arch/arm/include/asm/arm32/sysregs.h b/xen/arch/arm/include/asm/arm32/sysregs.h index 22871999af..ef1a870fd6 100644 --- a/xen/arch/arm/include/asm/arm32/sysregs.h +++ b/xen/arch/arm/include/asm/arm32/sysregs.h @@ -20,7 +20,16 @@ * uses r0 as a placeholder register. */ #define CMD_CP32(name...) "mcr " __stringify(CP32(r0, name)) ";" -#ifndef __ASSEMBLY__ +#define REGION_TEXT_PRBAR 0x18 /* SH=11 AP=10 XN=0 */ +#define REGION_RO_PRBAR 0x1D /* SH=11 AP=10 XN=1 */ +#define REGION_DATA_PRBAR 0x19 /* SH=11 AP=00 XN=1 */ +#define REGION_DEVICE_PRBAR 0x11 /* SH=10 AP=00 XN=1 */ + +#ifdef __ASSEMBLY__ + +#define WRITE_SYSREG_ASM(v, name) mcr CP32(v, name) + +#else /* __ASSEMBLY__ */ /* C wrappers */ #define READ_CP32(name...) ({ \ @@ -84,7 +93,7 @@ /* MVFR2 is not defined on ARMv7 */ #define MVFR2_MAYBE_UNDEFINED -#endif /* __ASSEMBLY__ */ +#endif /* !__ASSEMBLY__ */ #endif /* __ASM_ARM_ARM32_SYSREGS_H */ /* diff --git a/xen/arch/arm/include/asm/cpregs.h b/xen/arch/arm/include/asm/cpregs.h index aec9e8f329..a7503a190f 100644 --- a/xen/arch/arm/include/asm/cpregs.h +++ b/xen/arch/arm/include/asm/cpregs.h @@ -1,6 +1,8 @@ #ifndef __ASM_ARM_CPREGS_H #define __ASM_ARM_CPREGS_H +#include + /* * AArch32 Co-processor registers. * diff --git a/xen/arch/arm/include/asm/mpu/cpregs.h b/xen/arch/arm/include/asm/mpu/cpregs.h new file mode 100644 index 0000000000..d5cd0e04d5 --- /dev/null +++ b/xen/arch/arm/include/asm/mpu/cpregs.h @@ -0,0 +1,32 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef __ARM_MPU_CPREGS_H +#define __ARM_MPU_CPREGS_H + +/* CP15 CR0: MPU Type Register */ +#define HMPUIR p15,4,c0,c0,4 + +/* CP15 CR6: MPU Protection Region Base/Limit/Select Address Register */ +#define HPRSELR p15,4,c6,c2,1 +#define HPRBAR p15,4,c6,c3,0 +#define HPRLAR p15,4,c6,c8,1 + +/* Aliases of AArch64 names for use in common code */ +#ifdef CONFIG_ARM_32 +/* Alphabetically... */ +#define MPUIR_EL2 HMPUIR +#define PRBAR_EL2 HPRBAR +#define PRLAR_EL2 HPRLAR +#define PRSELR_EL2 HPRSELR +#endif /* CONFIG_ARM_32 */ + +#endif /* __ARM_MPU_CPREGS_H */ + +/* + * Local variables: + * mode: C + * c-file-style: "BSD" + * c-basic-offset: 4 + * indent-tabs-mode: nil + * End: + */ From patchwork Mon Apr 14 16:45:14 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ayan Kumar Halder X-Patchwork-Id: 14050735 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.xenproject.org (lists.xenproject.org [192.237.175.120]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id CA969C369A2 for ; Mon, 14 Apr 2025 16:52:09 +0000 (UTC) Received: from list by lists.xenproject.org with outflank-mailman.950904.1347082 (Exim 4.92) (envelope-from ) id 1u4N2K-0007NL-Ln; Mon, 14 Apr 2025 16:51:56 +0000 X-Outflank-Mailman: Message body and most headers restored to incoming version Received: by outflank-mailman (output) from mailman id 950904.1347082; Mon, 14 Apr 2025 16:51:56 +0000 Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1u4N2K-0007MI-HS; Mon, 14 Apr 2025 16:51:56 +0000 Received: by outflank-mailman (input) for mailman id 950904; Mon, 14 Apr 2025 16:51:55 +0000 Received: from se1-gles-flk1-in.inumbo.com ([94.247.172.50] helo=se1-gles-flk1.inumbo.com) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1u4Mx1-0003ls-Lw for xen-devel@lists.xenproject.org; Mon, 14 Apr 2025 16:46:27 +0000 Received: from NAM04-BN8-obe.outbound.protection.outlook.com (mail-bn8nam04on20625.outbound.protection.outlook.com [2a01:111:f403:2408::625]) by se1-gles-flk1.inumbo.com (Halon) with ESMTPS id 00cbdb30-1950-11f0-9ffb-bf95429c2676; Mon, 14 Apr 2025 18:46:26 +0200 (CEST) Received: from DM6PR07CA0055.namprd07.prod.outlook.com (2603:10b6:5:74::32) by IA1PR12MB7517.namprd12.prod.outlook.com (2603:10b6:208:41a::19) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.8632.32; Mon, 14 Apr 2025 16:46:20 +0000 Received: from DS1PEPF0001708F.namprd03.prod.outlook.com (2603:10b6:5:74:cafe::28) by DM6PR07CA0055.outlook.office365.com (2603:10b6:5:74::32) with Microsoft SMTP Server (version=TLS1_3, cipher=TLS_AES_256_GCM_SHA384) id 15.20.8632.33 via Frontend Transport; Mon, 14 Apr 2025 16:46:20 +0000 Received: from SATLEXMB04.amd.com (165.204.84.17) by DS1PEPF0001708F.mail.protection.outlook.com (10.167.17.139) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.20.8655.12 via Frontend Transport; Mon, 14 Apr 2025 16:46:19 +0000 Received: from SATLEXMB05.amd.com (10.181.40.146) by SATLEXMB04.amd.com (10.181.40.145) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.39; Mon, 14 Apr 2025 11:46:19 -0500 Received: from SATLEXMB04.amd.com (10.181.40.145) by SATLEXMB05.amd.com (10.181.40.146) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.39; Mon, 14 Apr 2025 11:46:18 -0500 Received: from xcbayankuma40.xilinx.com (10.180.168.240) by SATLEXMB04.amd.com (10.181.40.145) with Microsoft SMTP Server id 15.1.2507.39 via Frontend Transport; Mon, 14 Apr 2025 11:46:17 -0500 X-BeenThere: xen-devel@lists.xenproject.org List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Errors-To: xen-devel-bounces@lists.xenproject.org Precedence: list Sender: "Xen-devel" X-Inumbo-ID: 00cbdb30-1950-11f0-9ffb-bf95429c2676 ARC-Seal: i=1; a=rsa-sha256; s=arcselector10001; d=microsoft.com; cv=none; b=r2Ss3YpbaX2r/31bF47lv3jwZZlIGmbBpue2MxX/wuZ/R8OTdQU1O18n+s8oMvAc+Acs7njsIAjc4tOyNDVD0+W+JPODvgPH3bxYV8wSuVB0j+eXHH5c4U7t2iqYIzgqsOarIE7AMaysbKpyec787+jHD7zbL0d1Q3THBcbhmsnAd4KjFm6O6HVS1ZLwWbsiWBJsyOuRBgX6ZX2c30WaHr635SIbkq96cy0dRBKfozYqcfIbAjGamV/CuXN3627l6sQpFj05xlInleT5q+GulFqwPew8jJBhrOgz0jljHAhCtpWt/pbqQQ975SsbeYqd0RSn6NRRmdm93yw0/jXiqQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector10001; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1; bh=jPXfW0xKjKPyqHJAGBnbbDaBbiWamWXqAsxKqj91BhA=; b=QhU3u8IZuAbyOjM0LDz82UQpAE2ZvZVDpoPpnrh9N/QHHb81izkp3WXw0i0sMNVZAlgahvnTcq+x2lve6nKg/jJFErCBR0dbhULZXefO3Ur0zEb5Rs+fgiSmE1r6ImcdhD219nYKZAZ9XYPaibxFodh04r/8fMI9QBMX9Fqda9LA8eiK61woKDQOIZHYvspOFa16nCv57hVzTA0D+QYkg1yzdvxpf5YKpl1Dk0zlEzHbbc3vJMeAhVcvQDjnG6eQGz3s5C4xV296vDWRlMi6cnKLBa944OA3jqdrWBafTbNPqWkJJcqnCWSu0mFX7DfW9awvsoLJMjxGyhgmiTPi3g== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass (sender ip is 165.204.84.17) smtp.rcpttodomain=lists.xenproject.org smtp.mailfrom=amd.com; dmarc=pass (p=quarantine sp=quarantine pct=100) action=none header.from=amd.com; dkim=none (message not signed); arc=none (0) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=amd.com; s=selector1; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=jPXfW0xKjKPyqHJAGBnbbDaBbiWamWXqAsxKqj91BhA=; b=XRvD8q8p3XiPVG9AzJBPIdL+ASA88+zL7+3qAMmRVc5xNAQm86MTA3D3XMJQC7Bf4KBtD5dWicdkoZxsf7MlvHR2WGJ043H7LMvfLT0fTX6vTz/Fx71Gz9o7aAPgEfbpj8LrC26AW5QzPMEi6ktjhe3f8HoeIh1094/2dFUKxds= X-MS-Exchange-Authentication-Results: spf=pass (sender IP is 165.204.84.17) smtp.mailfrom=amd.com; dkim=none (message not signed) header.d=none;dmarc=pass action=none header.from=amd.com; Received-SPF: Pass (protection.outlook.com: domain of amd.com designates 165.204.84.17 as permitted sender) receiver=protection.outlook.com; client-ip=165.204.84.17; helo=SATLEXMB04.amd.com; pr=C From: Ayan Kumar Halder To: CC: Ayan Kumar Halder , Stefano Stabellini , Julien Grall , Bertrand Marquis , Michal Orzel , "Volodymyr Babchuk" , Luca Fancellu Subject: [PATCH v7 3/3] xen/arm32: mpu: Stubs to build MPU for arm32 Date: Mon, 14 Apr 2025 17:45:14 +0100 Message-ID: <20250414164514.588373-4-ayan.kumar.halder@amd.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20250414164514.588373-1-ayan.kumar.halder@amd.com> References: <20250414164514.588373-1-ayan.kumar.halder@amd.com> MIME-Version: 1.0 Received-SPF: None (SATLEXMB05.amd.com: ayan.kumar.halder@amd.com does not designate permitted sender hosts) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: DS1PEPF0001708F:EE_|IA1PR12MB7517:EE_ X-MS-Office365-Filtering-Correlation-Id: c95b6a67-e794-4456-b78e-08dd7b73e20a X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|376014|1800799024|36860700013|82310400026; X-Microsoft-Antispam-Message-Info: 0wkXQu5cACHti+AAXt0zUw900QM+d8nhjryWCSdTMXlHNIduPImX9wlknkCDX+T1JreHtTWfR6I1OLKoODYXSxaEKsCyeoc3rvXJnHr1vfP7CbteRbUrfAgqo4G4L4PXqsuM0uloLg8JC0QdPs6EFTUhJRwuBOqmpQYhvT+r+g9rtoy27XaVMmWPM7UY0zGmxvsfL2RUEu+64qgf1/YD86MEXzL6ZjXQ8gyOHkl9cQuHiqhT4wmOjOQi+dFMDNB+jjAZlhKy5WfgfesxkJBv8cR3boDcKvgOq7KrmOV6BRk94QeQ4drJblhk2uOgv6xxPepTc1WEoVG2mKEJiSyy/e/JkVn8uF1Cmee3rKowpI3QSBViSul6+O9GsBKLPEAo6OMU9ApCLry9t693q8fcKWUjLQphPxxu/gYZV08sR37DgEGS9oPnKXmZOnIyp0Z45Kv8nNHa+KYJNSkNrKVQHHfRtFLd2MpEFDX42WMHcqhnG/aChwA5V7UvI468tP0/BcbvjfuD9kmqhW0IqYziTjbZZVvq6oMbCb0PVAVqzuBriOcmLA1A+byNdIMd9EqPze3I/0/Sj7njgGeErCsFQ7g5GYuI6X+NkmEXWMPkBJv+jRvMoLloL4EbLEoLQpA7vbZDfpRgNZDHnmtrZRdcnj7Qs8Gjbvshnp2uQFMQ1qWEwX1X7t5XSIc4bCVwM1K5mPsRDRggLmeuCM1degDJPoAzLgA0BtwjvgAcEn1tOwwUvQW4yh9jqdXQtmWzw6JWTClkq/e9IvM+uz4HGER8Aw0mHdtFcAz3eLkkIEsdSKUcSJ+TN5ypqDjod4+aygVbiSdfn4XKvS8CosrT0d5j6mcMJNWed5v8BjK/eZU5bqKZqr9uFhJjfcLN3OA6Wo3au1ed/7gjzKb66fbOhIZHgmscnujOiFiW8LlFE+I/NvkLSSLMpL2HZ7C64G6XmV2XaKca9nvqHVQLATc58fEmXpMLy1MH9ItgVEIKPOZsogKGDMx9dTp3FpqABUTWFEY7HiqXdNZmUo5pJIxytBvLEqw1PgkyCBHUZFafSRXoXsMv0FGydbwriz8JTxSlpQppAZCI2gOIlG2gSbFuERnpkZ8ftM5JAkLuij0fN2O/1/ImQa63Z1DuzdTa8AjsxPByOiUiKKVu46wRVXrWAS0WNfVT70Mpe1DIuYK0nyZIhJ3FbVvtFeHOgjnffrp4zmaD9wqtZZvO1Ic3lS9hxg7CVgah7Se4KWYjRhv+3g9py21uCKaNRBtfF93FgFrdVR40dH1ya6uvjjmZ6usa4ay2rkuAo+/TQg6zAmsvNVAE3XxVvgu2ht7clUwrUeZLUhJ+XhZrNLwIFo2QGMXHhv0ViTk8l4/xmz19kkbrDsbf//FZ/W+6tUQAqhRRs/KA7Tchd6U1Wef/b5xq6Y/H3yXOuKfCbENOwlgTU7FXkGRCdf200NdCQhsdYvMvQIl+rz0jzz1kl0SjWjSWOtI/+lfE+a9EZTSb9jNbzX65YeDW4yymWHEmvLZBTrGgJtCqQCrwGnbcjfcbnLsyG2v/bue3nA== X-Forefront-Antispam-Report: CIP:165.204.84.17;CTRY:US;LANG:en;SCL:1;SRV:;IPV:CAL;SFV:NSPM;H:SATLEXMB04.amd.com;PTR:InfoDomainNonexistent;CAT:NONE;SFS:(13230040)(376014)(1800799024)(36860700013)(82310400026);DIR:OUT;SFP:1101; X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 14 Apr 2025 16:46:19.9349 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: c95b6a67-e794-4456-b78e-08dd7b73e20a X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: DS1PEPF0001708F.namprd03.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: IA1PR12MB7517 Add stubs to enable compilation. is_xen_heap_page() and is_xen_heap_mfn() are not implemented for arm32 MPU. Thus, introduce the stubs for these functions in asm/mpu/mm.h and move the original code to asm/mmu/mm.h (as it is used for arm32 MMU based system). Signed-off-by: Ayan Kumar Halder Reviewed-by: Luca Fancellu Reviewed-by: Michal Orzel Tested-by: Luca Fancellu --- Changes from :- v1, v2 - 1. New patch introduced in v3. 2. Should be applied on top of https://patchwork.kernel.org/project/xen-devel/cover/20250316192445.2376484-1-luca.fancellu@arm.com/ v3 - 1. Add stubs for map_domain_page() and similar functions. 2. 'BUG_ON("unimplemented")' is kept in all the stubs. v4 - 1. is_xen_heap_mfn() macros are defined across mpu/mm.h (ARM32 specific) , mmu/mm.h (ARM32 specific) and asm/mm.h (ARM64 specific) 2. s/(void*)0/NULL v5 - 1. Add the headers for smpboot.c, domain_page.c and p2m.c. 2. Inclusion of headers and makefile entries are sorted alphabetically. 3. Update the commit message and style changes. v6 - 1. Add R-b and T-b. xen/arch/arm/arm32/mpu/Makefile | 2 ++ xen/arch/arm/arm32/mpu/p2m.c | 19 +++++++++++++ xen/arch/arm/arm32/mpu/smpboot.c | 26 ++++++++++++++++++ xen/arch/arm/include/asm/mm.h | 9 +------ xen/arch/arm/include/asm/mmu/mm.h | 7 +++++ xen/arch/arm/include/asm/mpu/mm.h | 5 ++++ xen/arch/arm/mpu/Makefile | 1 + xen/arch/arm/mpu/domain_page.c | 45 +++++++++++++++++++++++++++++++ 8 files changed, 106 insertions(+), 8 deletions(-) create mode 100644 xen/arch/arm/arm32/mpu/p2m.c create mode 100644 xen/arch/arm/arm32/mpu/smpboot.c create mode 100644 xen/arch/arm/mpu/domain_page.c diff --git a/xen/arch/arm/arm32/mpu/Makefile b/xen/arch/arm/arm32/mpu/Makefile index 3340058c08..cf0540aecc 100644 --- a/xen/arch/arm/arm32/mpu/Makefile +++ b/xen/arch/arm/arm32/mpu/Makefile @@ -1 +1,3 @@ obj-y += head.o +obj-y += p2m.o +obj-y += smpboot.o diff --git a/xen/arch/arm/arm32/mpu/p2m.c b/xen/arch/arm/arm32/mpu/p2m.c new file mode 100644 index 0000000000..3d9abe4400 --- /dev/null +++ b/xen/arch/arm/arm32/mpu/p2m.c @@ -0,0 +1,19 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include +#include +#include + +void __init setup_virt_paging(void) +{ + BUG_ON("unimplemented"); +} + +/* + * Local variables: + * mode: C + * c-file-style: "BSD" + * c-basic-offset: 4 + * indent-tabs-mode: nil + * End: + */ diff --git a/xen/arch/arm/arm32/mpu/smpboot.c b/xen/arch/arm/arm32/mpu/smpboot.c new file mode 100644 index 0000000000..5090f443f5 --- /dev/null +++ b/xen/arch/arm/arm32/mpu/smpboot.c @@ -0,0 +1,26 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include +#include +#include +#include + +int prepare_secondary_mm(int cpu) +{ + BUG_ON("unimplemented"); + return -EINVAL; +} + +void update_boot_mapping(bool enable) +{ + BUG_ON("unimplemented"); +} + +/* + * Local variables: + * mode: C + * c-file-style: "BSD" + * c-basic-offset: 4 + * indent-tabs-mode: nil + * End: + */ diff --git a/xen/arch/arm/include/asm/mm.h b/xen/arch/arm/include/asm/mm.h index fbffaccef4..5b67c0f8bb 100644 --- a/xen/arch/arm/include/asm/mm.h +++ b/xen/arch/arm/include/asm/mm.h @@ -170,14 +170,7 @@ struct page_info #define _PGC_need_scrub _PGC_allocated #define PGC_need_scrub PGC_allocated -#ifdef CONFIG_ARM_32 -#define is_xen_heap_page(page) is_xen_heap_mfn(page_to_mfn(page)) -#define is_xen_heap_mfn(mfn) ({ \ - unsigned long mfn_ = mfn_x(mfn); \ - (mfn_ >= mfn_x(directmap_mfn_start) && \ - mfn_ < mfn_x(directmap_mfn_end)); \ -}) -#else +#ifdef CONFIG_ARM_64 #define is_xen_heap_page(page) ((page)->count_info & PGC_xen_heap) #define is_xen_heap_mfn(mfn) \ (mfn_valid(mfn) && is_xen_heap_page(mfn_to_page(mfn))) diff --git a/xen/arch/arm/include/asm/mmu/mm.h b/xen/arch/arm/include/asm/mmu/mm.h index caba987edc..7f4d59137d 100644 --- a/xen/arch/arm/include/asm/mmu/mm.h +++ b/xen/arch/arm/include/asm/mmu/mm.h @@ -27,6 +27,13 @@ extern unsigned long directmap_base_pdx; }) #ifdef CONFIG_ARM_32 +#define is_xen_heap_page(page) is_xen_heap_mfn(page_to_mfn(page)) +#define is_xen_heap_mfn(mfn) ({ \ + unsigned long mfn_ = mfn_x(mfn); \ + (mfn_ >= mfn_x(directmap_mfn_start) && \ + mfn_ < mfn_x(directmap_mfn_end)); \ +}) + /** * Find the virtual address corresponding to a machine address * diff --git a/xen/arch/arm/include/asm/mpu/mm.h b/xen/arch/arm/include/asm/mpu/mm.h index 86f33d9836..bfd840fa5d 100644 --- a/xen/arch/arm/include/asm/mpu/mm.h +++ b/xen/arch/arm/include/asm/mpu/mm.h @@ -13,6 +13,11 @@ extern struct page_info *frame_table; #define virt_to_maddr(va) ((paddr_t)((vaddr_t)(va) & PADDR_MASK)) +#ifdef CONFIG_ARM_32 +#define is_xen_heap_page(page) ({ BUG_ON("unimplemented"); false; }) +#define is_xen_heap_mfn(mfn) ({ BUG_ON("unimplemented"); false; }) +#endif + /* On MPU systems there is no translation, ma == va. */ static inline void *maddr_to_virt(paddr_t ma) { diff --git a/xen/arch/arm/mpu/Makefile b/xen/arch/arm/mpu/Makefile index 21bbc517b5..c7e3aa4d87 100644 --- a/xen/arch/arm/mpu/Makefile +++ b/xen/arch/arm/mpu/Makefile @@ -1,3 +1,4 @@ +obj-$(CONFIG_ARM_32) += domain_page.o obj-y += mm.o obj-y += p2m.o obj-y += setup.init.o diff --git a/xen/arch/arm/mpu/domain_page.c b/xen/arch/arm/mpu/domain_page.c new file mode 100644 index 0000000000..df5e06b6db --- /dev/null +++ b/xen/arch/arm/mpu/domain_page.c @@ -0,0 +1,45 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include +#include +#include +#include + +void *map_domain_page_global(mfn_t mfn) +{ + BUG_ON("unimplemented"); + return NULL; +} + +/* Map a page of domheap memory */ +void *map_domain_page(mfn_t mfn) +{ + BUG_ON("unimplemented"); + return NULL; +} + +/* Release a mapping taken with map_domain_page() */ +void unmap_domain_page(const void *ptr) +{ + BUG_ON("unimplemented"); +} + +mfn_t domain_page_map_to_mfn(const void *ptr) +{ + BUG_ON("unimplemented"); + return INVALID_MFN; +} + +void unmap_domain_page_global(const void *va) +{ + BUG_ON("unimplemented"); +} + +/* + * Local variables: + * mode: C + * c-file-style: "BSD" + * c-basic-offset: 4 + * indent-tabs-mode: nil + * End: + */