From patchwork Tue Apr 15 03:39:39 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Kever Yang X-Patchwork-Id: 14051417 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 5976AC369B8 for ; Tue, 15 Apr 2025 03:39:55 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:Message-Id:Date:Subject:Cc :To:From:Reply-To:Content-ID:Content-Description:Resent-Date:Resent-From: Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:In-Reply-To:References: List-Owner; bh=AGM0saffcPVZ8EuqserBv5uLZtcp/635Alm0vlbWQVk=; b=M/Tg4vShsTamHT mhyQGEtTPWeKEI4vwfWFZq8lh6gVtJ/3gj/WHsz60f0XtMRGifgBmnnpjuPDqfcFXuFZgK6tZN5yf AC3IWt/515SQWSRuT6REvoa/r4TAm3X4zbmSrYCgvZ3UdDOCQiz94HAyQIde6j1FfoqkAY10t38wn QWa6nu4z2rEk1I1BtJuaMSG089tlVdLl+XZOcBGBJLm6Ni4xL9AEmHuR0uEh//MGhUeUuS4niRtQM 4s9Qxz+udkW7LT+aZ5lpyCLkUwic0P4lWuwWxoDY4A9Sg6v18kh1X7hw62vRpWia5bb2Y3blaZFKy oJ5dnNuUp7XwUuQHemLQ==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.98.2 #2 (Red Hat Linux)) id 1u4X9K-00000004KSR-0Svj; Tue, 15 Apr 2025 03:39:50 +0000 Received: from mail-m32115.qiye.163.com ([220.197.32.115]) by bombadil.infradead.org with esmtps (Exim 4.98.2 #2 (Red Hat Linux)) id 1u4X9I-00000004KRV-0RIO; Tue, 15 Apr 2025 03:39:49 +0000 Received: from localhost.localdomain (unknown [103.29.142.67]) by smtp.qiye.163.com (Hmail) with ESMTP id 11e3d2162; Tue, 15 Apr 2025 11:39:42 +0800 (GMT+08:00) From: Kever Yang To: heiko@sntech.de Cc: linux-rockchip@lists.infradead.org, Kever Yang , devicetree@vger.kernel.org, Conor Dooley , Rob Herring , Lukasz Luba , linux-pm@vger.kernel.org, linux-kernel@vger.kernel.org, Krzysztof Kozlowski , Zhang Rui , "Rafael J. Wysocki" , linux-arm-kernel@lists.infradead.org, Daniel Lezcano Subject: [PATCH v2 1/2] dt-bindings: rockchip-thermal: Support the RK3562 SoC compatible Date: Tue, 15 Apr 2025 11:39:39 +0800 Message-Id: <20250415033940.47914-1-kever.yang@rock-chips.com> X-Mailer: git-send-email 2.25.1 MIME-Version: 1.0 X-HM-Spam-Status: e1kfGhgUHx5ZQUpXWQgPGg8OCBgUHx5ZQUlOS1dZFg8aDwILHllBWSg2Ly tZV1koWUFITzdXWS1ZQUlXWQ8JGhUIEh9ZQVkaHhhJVktNS0pCTUtDSx0ZSlYVFAkWGhdVEwETFh oSFyQUDg9ZV1kYEgtZQVlKS0hVSUJVSk9JVU1MWVdZFhoPEhUdFFlBWU9LSFVKS0lPT09IVUpLS1 VKQktLWQY+ X-HM-Tid: 0a963788044203afkunm11e3d2162 X-HM-MType: 1 X-HM-Sender-Digest: e1kMHhlZQR0aFwgeV1kSHx4VD1lBWUc6MTY6Sio6LDJRKBohPksjLDYZ DBAKCT9VSlVKTE9PTUNDSENPQkxDVTMWGhIXVRAeDR4JVQIaFRw7CRQYEFYYExILCFUYFBZFWVdZ EgtZQVlKS0hVSUJVSk9JVU1MWVdZCAFZQUpMSU03Bg++ DKIM-Signature: a=rsa-sha256; b=N33YyMZqBQWAADFsHHYVkwM5CpZdGJC7buuowxQEqP5pwbiUAT0k2BcbsHeand2+okwtZugZvAJf15gYcKVTeCJuRpIBfZ6ednIVXZfw0qKHCBdKPIsdOXirM1x1I8XwNKBruM5I5/ay9pIsJUw9jQQqzMBN+dpDz417sjgP+o0=; c=relaxed/relaxed; s=default; d=rock-chips.com; v=1; bh=nsAist8AxtC7M4LMr9CEpwZWddUC1Wkb4AeT8FbLZpM=; h=date:mime-version:subject:message-id:from; X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20250414_203948_295828_502EAA21 X-CRM114-Status: UNSURE ( 5.80 ) X-CRM114-Notice: Please train this message. X-BeenThere: linux-rockchip@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: Upstream kernel work for Rockchip platforms List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "Linux-rockchip" Errors-To: linux-rockchip-bounces+linux-rockchip=archiver.kernel.org@lists.infradead.org Add a new compatible for tsadc on RK3562 SoCs. Signed-off-by: Kever Yang --- Changes in v2: None Documentation/devicetree/bindings/thermal/rockchip-thermal.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/thermal/rockchip-thermal.yaml b/Documentation/devicetree/bindings/thermal/rockchip-thermal.yaml index b717ea8261ca..f55f2045fc84 100644 --- a/Documentation/devicetree/bindings/thermal/rockchip-thermal.yaml +++ b/Documentation/devicetree/bindings/thermal/rockchip-thermal.yaml @@ -20,6 +20,7 @@ properties: - rockchip,rk3328-tsadc - rockchip,rk3368-tsadc - rockchip,rk3399-tsadc + - rockchip,rk3562-tsadc - rockchip,rk3568-tsadc - rockchip,rk3588-tsadc - rockchip,rv1108-tsadc From patchwork Tue Apr 15 03:39:40 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Kever Yang X-Patchwork-Id: 14051418 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 3DBEFC369AB for ; Tue, 15 Apr 2025 03:41:44 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To: Message-Id:Date:Subject:Cc:To:From:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=Ve/RozSK5CTfUrSCuliMr1asplR3GGTrzQDO+ISWSXg=; b=y4sa7ibq437Vi0 pWt8TTkT0c/Wn8GjbKzxPw4d6ZefZpbJO4lpnd8ZWgH8RuoQZjfsVM81SMGxZ2K9jVU8WHedHDQ2U 9ISiKit+04LWk/jea+BQUAwd9GTIpN0TwQpZTMU6Xz0afpOvl6/SgQj0b0IUXpr39fC1UwnX8YGd3 rlIGrUy510bGuV8d7k70pw502+FkR2U1EFW2Nmgxivh5Vm+lOpN1tBujof+nMjyMcogWs6Zgaox9p K6ug3zKWicocv3s/zGKG2fXW1FQRwFvgMhdvIqOvo1IGKQrasOV4eV3pJ2dfmdQF5bQ5NVr69SZnk V7VP40MYkblZIp7SYHGQ==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.98.2 #2 (Red Hat Linux)) id 1u4XB7-00000004Kf2-0Ruu; Tue, 15 Apr 2025 03:41:41 +0000 Received: from mail-m19731117.qiye.163.com ([220.197.31.117]) by bombadil.infradead.org with esmtps (Exim 4.98.2 #2 (Red Hat Linux)) id 1u4X9J-00000004KRd-2SGW; Tue, 15 Apr 2025 03:39:51 +0000 Received: from localhost.localdomain (unknown [103.29.142.67]) by smtp.qiye.163.com (Hmail) with ESMTP id 11e3d216f; Tue, 15 Apr 2025 11:39:45 +0800 (GMT+08:00) From: Kever Yang To: heiko@sntech.de Cc: linux-rockchip@lists.infradead.org, Shaohan Yao , Kever Yang , linux-pm@vger.kernel.org, Lukasz Luba , linux-kernel@vger.kernel.org, Zhang Rui , "Rafael J. Wysocki" , linux-arm-kernel@lists.infradead.org, Daniel Lezcano Subject: [PATCH v2 2/2] thermal: rockchip: Add support for rk3562 SoC Date: Tue, 15 Apr 2025 11:39:40 +0800 Message-Id: <20250415033940.47914-2-kever.yang@rock-chips.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20250415033940.47914-1-kever.yang@rock-chips.com> References: <20250415033940.47914-1-kever.yang@rock-chips.com> MIME-Version: 1.0 X-HM-Spam-Status: e1kfGhgUHx5ZQUpXWQgPGg8OCBgUHx5ZQUlOS1dZFg8aDwILHllBWSg2Ly tZV1koWUFITzdXWS1ZQUlXWQ8JGhUIEh9ZQVlCSBhJVh9LSB8eQ04fT0NISVYVFAkWGhdVEwETFh oSFyQUDg9ZV1kYEgtZQVlKS0hVSUJVSk9JVU1MWVdZFhoPEhUdFFlBWU9LSFVKS0lPT09IVUpLS1 VKQktLWQY+ X-HM-Tid: 0a9637880cbf03afkunm11e3d216f X-HM-MType: 1 X-HM-Sender-Digest: e1kMHhlZQR0aFwgeV1kSHx4VD1lBWUc6NSI6Qyo*TDJPKBoBUUsQLB0I NzdPChFVSlVKTE9PTUNDSENNQkhOVTMWGhIXVRAeDR4JVQIaFRw7CRQYEFYYExILCFUYFBZFWVdZ EgtZQVlKS0hVSUJVSk9JVU1MWVdZCAFZQUxJQkg3Bg++ DKIM-Signature: a=rsa-sha256; b=E1z1LHnRVGLNNS4WWPVLhmjYfgda3WsrsneNuwVnou+gflyY7DJcEepEsxSu0G25Mbj/FiFFtEL9fCgZhfXAP4cgof0iaT+8lBiTsHBqTU9KJUfohk2rfg1DQvVbukDu+odLnXPoQQPwQvZgaw9gYDtm0TklzApbxfnXCwy4xfo=; c=relaxed/relaxed; s=default; d=rock-chips.com; v=1; bh=1Tre13DFbEzWLiu/T9e9wWJekgfPen9D+iwat8GNKM0=; h=date:mime-version:subject:message-id:from; X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20250414_203949_825942_84C9B9D7 X-CRM114-Status: GOOD ( 17.13 ) X-BeenThere: linux-rockchip@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: Upstream kernel work for Rockchip platforms List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "Linux-rockchip" Errors-To: linux-rockchip-bounces+linux-rockchip=archiver.kernel.org@lists.infradead.org From: Shaohan Yao There is one Temperature Sensor with channel 0 on rk3562 SoC. This driver adds the mapping table as-is from the TRM so that we can always sync to the TRM once there have any change in the future. Signed-off-by: Shaohan Yao Signed-off-by: Kever Yang --- Changes in v2: - Update the commit message drivers/thermal/rockchip_thermal.c | 112 ++++++++++++++++++++++++++++- 1 file changed, 111 insertions(+), 1 deletion(-) diff --git a/drivers/thermal/rockchip_thermal.c b/drivers/thermal/rockchip_thermal.c index a8ad85feb68f..3278472b06f9 100644 --- a/drivers/thermal/rockchip_thermal.c +++ b/drivers/thermal/rockchip_thermal.c @@ -1,6 +1,7 @@ // SPDX-License-Identifier: GPL-2.0-only /* - * Copyright (c) 2014-2016, Fuzhou Rockchip Electronics Co., Ltd + * Copyright (c) 2014-2021, Fuzhou Rockchip Electronics Co., Ltd. + * Copyright (c) 2021-2024, Rockchip Electronics Co., Ltd. * Caesar Wang */ @@ -185,6 +186,8 @@ struct rockchip_thermal_data { #define TSADCV2_AUTO_PERIOD_HT 0x6c #define TSADCV3_AUTO_PERIOD 0x154 #define TSADCV3_AUTO_PERIOD_HT 0x158 +#define TSADCV9_Q_MAX 0x210 +#define TSADCV9_FLOW_CON 0x218 #define TSADCV2_AUTO_EN BIT(0) #define TSADCV2_AUTO_EN_MASK BIT(16) @@ -195,6 +198,7 @@ struct rockchip_thermal_data { #define TSADCV2_AUTO_TSHUT_POLARITY_MASK BIT(24) #define TSADCV3_AUTO_Q_SEL_EN BIT(1) +#define TSADCV3_AUTO_Q_SEL_EN_MASK BIT(17) #define TSADCV2_INT_SRC_EN(chn) BIT(chn) #define TSADCV2_INT_SRC_EN_MASK(chn) BIT(16 + (chn)) @@ -220,6 +224,12 @@ struct rockchip_thermal_data { #define TSADCV5_AUTO_PERIOD_HT_TIME 1622 /* 2.5ms */ #define TSADCV6_AUTO_PERIOD_TIME 5000 /* 2.5ms */ #define TSADCV6_AUTO_PERIOD_HT_TIME 5000 /* 2.5ms */ +#define TSADCV7_AUTO_PERIOD_TIME 3000 /* 2.5ms */ +#define TSADCV7_AUTO_PERIOD_HT_TIME 3000 /* 2.5ms */ +#define TSADCV12_AUTO_PERIOD_TIME 3000 /* 2.5ms */ +#define TSADCV12_AUTO_PERIOD_HT_TIME 3000 /* 2.5ms */ +#define TSADCV3_Q_MAX_VAL 0x7ff /* 11bit 2047 */ +#define TSADCV12_Q_MAX_VAL 0xfff /* 12bit 4095 */ #define TSADCV2_USER_INTER_PD_SOC 0x340 /* 13 clocks */ #define TSADCV5_USER_INTER_PD_SOC 0xfc0 /* 97us, at least 90us */ @@ -230,6 +240,8 @@ struct rockchip_thermal_data { #define PX30_GRF_SOC_CON2 0x0408 +#define RK3562_GRF_TSADC_CON 0x0580 + #define RK3568_GRF_TSADC_CON 0x0600 #define RK3568_GRF_TSADC_ANA_REG0 (0x10001 << 0) #define RK3568_GRF_TSADC_ANA_REG1 (0x10001 << 1) @@ -498,6 +510,45 @@ static const struct tsadc_table rk3399_code_table[] = { {TSADCV3_DATA_MASK, 125000}, }; +static const struct tsadc_table rk3562_code_table[] = { + {0, -40000}, + {1419, -40000}, + {1428, -35000}, + {1436, -30000}, + {1445, -25000}, + {1453, -20000}, + {1462, -15000}, + {1470, -10000}, + {1479, -5000}, + {1487, 0}, + {1496, 5000}, + {1504, 10000}, + {1512, 15000}, + {1521, 20000}, + {1529, 25000}, + {1538, 30000}, + {1546, 35000}, + {1555, 40000}, + {1563, 45000}, + {1572, 50000}, + {1580, 55000}, + {1589, 60000}, + {1598, 65000}, + {1606, 70000}, + {1615, 75000}, + {1623, 80000}, + {1632, 85000}, + {1640, 90000}, + {1648, 95000}, + {1657, 100000}, + {1666, 105000}, + {1674, 110000}, + {1682, 115000}, + {1691, 120000}, + {1699, 125000}, + {TSADCV2_DATA_MASK, 125000}, +}; + static const struct tsadc_table rk3568_code_table[] = { {0, -40000}, {1584, -40000}, @@ -835,6 +886,37 @@ static void rk_tsadcv8_initialize(struct regmap *grf, void __iomem *regs, regs + TSADCV2_AUTO_CON); } +static void rk_tsadcv12_initialize(struct regmap *grf, void __iomem *regs, + enum tshut_polarity tshut_polarity) +{ + writel_relaxed(TSADCV12_AUTO_PERIOD_TIME, regs + TSADCV3_AUTO_PERIOD); + writel_relaxed(TSADCV12_AUTO_PERIOD_HT_TIME, + regs + TSADCV3_AUTO_PERIOD_HT); + writel_relaxed(TSADCV2_HIGHT_INT_DEBOUNCE_COUNT, + regs + TSADCV3_HIGHT_INT_DEBOUNCE); + writel_relaxed(TSADCV2_HIGHT_TSHUT_DEBOUNCE_COUNT, + regs + TSADCV3_HIGHT_TSHUT_DEBOUNCE); + writel_relaxed(TSADCV12_Q_MAX_VAL, regs + TSADCV9_Q_MAX); + writel_relaxed(TSADCV3_AUTO_Q_SEL_EN | TSADCV3_AUTO_Q_SEL_EN_MASK, + regs + TSADCV2_AUTO_CON); + if (tshut_polarity == TSHUT_HIGH_ACTIVE) + writel_relaxed(TSADCV2_AUTO_TSHUT_POLARITY_HIGH | + TSADCV2_AUTO_TSHUT_POLARITY_MASK, + regs + TSADCV2_AUTO_CON); + else + writel_relaxed(TSADCV2_AUTO_TSHUT_POLARITY_MASK, + regs + TSADCV2_AUTO_CON); + + if (!IS_ERR(grf)) { + regmap_write(grf, RK3562_GRF_TSADC_CON, RK3568_GRF_TSADC_TSEN); + udelay(15); + regmap_write(grf, RK3562_GRF_TSADC_CON, RK3568_GRF_TSADC_ANA_REG0); + regmap_write(grf, RK3562_GRF_TSADC_CON, RK3568_GRF_TSADC_ANA_REG1); + regmap_write(grf, RK3562_GRF_TSADC_CON, RK3568_GRF_TSADC_ANA_REG2); + usleep_range(100, 200); + } +} + static void rk_tsadcv2_irq_ack(void __iomem *regs) { u32 val; @@ -1259,6 +1341,30 @@ static const struct rockchip_tsadc_chip rk3399_tsadc_data = { }, }; +static const struct rockchip_tsadc_chip rk3562_tsadc_data = { + .chn_offset = 0, + .chn_num = 1, /* one channels for tsadc */ + + .tshut_mode = TSHUT_MODE_GPIO, /* default TSHUT via GPIO give PMIC */ + .tshut_polarity = TSHUT_LOW_ACTIVE, /* default TSHUT LOW ACTIVE */ + .tshut_temp = 95000, + + .initialize = rk_tsadcv12_initialize, + .irq_ack = rk_tsadcv4_irq_ack, + .control = rk_tsadcv4_control, + .get_temp = rk_tsadcv4_get_temp, + .set_alarm_temp = rk_tsadcv3_alarm_temp, + .set_tshut_temp = rk_tsadcv3_tshut_temp, + .set_tshut_mode = rk_tsadcv3_tshut_mode, + + .table = { + .id = rk3562_code_table, + .length = ARRAY_SIZE(rk3562_code_table), + .data_mask = TSADCV2_DATA_MASK, + .mode = ADC_INCREMENT, + }, +}; + static const struct rockchip_tsadc_chip rk3568_tsadc_data = { /* cpu, gpu */ .chn_offset = 0, @@ -1338,6 +1444,10 @@ static const struct of_device_id of_rockchip_thermal_match[] = { .compatible = "rockchip,rk3399-tsadc", .data = (void *)&rk3399_tsadc_data, }, + { + .compatible = "rockchip,rk3562-tsadc", + .data = (void *)&rk3562_tsadc_data, + }, { .compatible = "rockchip,rk3568-tsadc", .data = (void *)&rk3568_tsadc_data,