From patchwork Tue Apr 15 13:32:58 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Alexander Stein X-Patchwork-Id: 14052256 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id C4646C369AB for ; Tue, 15 Apr 2025 13:37:52 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender:List-Subscribe:List-Help :List-Post:List-Archive:List-Unsubscribe:List-Id:Content-Transfer-Encoding: MIME-Version:Message-ID:Date:Subject:Cc:To:From:Reply-To:Content-Type: Content-ID:Content-Description:Resent-Date:Resent-From:Resent-Sender: Resent-To:Resent-Cc:Resent-Message-ID:In-Reply-To:References:List-Owner; bh=R2SZvhgWOcXu74APsWOF5IGVz2bjc0yiT34pBzEhPzg=; b=M8RkPV/pCVoYyPeG3NALzn0sxk P12gN2OvUWGR58OfOJPuWVu+0jwBRZDkfxrpMRmI0+kPKX/4lgSupTJIVNMSqNeyZtnunGJnjg9t8 +EaFsNqEAFBmOOz2dY8HhwYLBmjECh3PDhXJDFercanEAkMw4GZcBLpVmiRE5mBz/J3S57Z1/KqE9 guUE5ZRnYM6mE32OKz1JP6LW5jZGrWaqrb2r/kBEKdBGhkxLukfl4anLD/UH4OoIhrfVE6dh2ejfm /8+z0mA6vkfbtMdqZEZGHcJukYAZRyKKsa4hYprASNGJ+e/MlloIYtwGLzG6dd9aAJLNbg/jSPbCc 0zO8hnlw==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.98.2 #2 (Red Hat Linux)) id 1u4gTp-00000005wZW-3K38; Tue, 15 Apr 2025 13:37:37 +0000 Received: from mx1.tq-group.com ([93.104.207.81]) by bombadil.infradead.org with esmtps (Exim 4.98.2 #2 (Red Hat Linux)) id 1u4gPa-00000005vQE-1u2d for linux-arm-kernel@lists.infradead.org; Tue, 15 Apr 2025 13:33:16 +0000 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=tq-group.com; i=@tq-group.com; q=dns/txt; s=key1; t=1744723994; x=1776259994; h=from:to:cc:subject:date:message-id:mime-version: content-transfer-encoding; bh=R2SZvhgWOcXu74APsWOF5IGVz2bjc0yiT34pBzEhPzg=; b=gzgn44aiSzNNvBQvYpSHdq4KDSbuWFtI0A/la6Jc74q2JExEcnyh9b2y FSRu0QXN056mEoM9y2vQTk7MHHAclXC1j2Ve1Xg5E8sCOJw7R7b3ws0Pw tzc6Cl8wsPyzzehOoZFfT9aDWdnV5R7Ki/gT02g4MG0tSdRPXRwLOSYHA bh6xWlLG8/jDxm7+bHbvKfpQCsaX/yLNNxPHNVY1u2UG5olboSRYeeFkl L6pddGHN2vK5QoD753/IVwin6VKzH5YhYmoo0pf01L2IwLwXwYqjGJZW5 ImOXEn/bCXFIbrobWNnQkwQOoWJ8Er3Cm2jEjmUM0s9vmyqMtu96EuMhF g==; X-CSE-ConnectionGUID: FzvENSeBT/eNc8+aXFsG1Q== X-CSE-MsgGUID: iKjBA6smT3i4jVEC3eJDkQ== X-IronPort-AV: E=Sophos;i="6.15,213,1739833200"; d="scan'208";a="43543921" Received: from vmailcow01.tq-net.de ([10.150.86.48]) by mx1.tq-group.com with ESMTP; 15 Apr 2025 15:33:12 +0200 X-CheckPoint: {67FE6017-19-903EAEAC-E04C76C8} X-MAIL-CPID: 41A4BAF9440150BB2E011C50814F7D8B_5 X-Control-Analysis: str=0001.0A006397.67FE6014.0029,ss=1,re=0.000,recu=0.000,reip=0.000,cl=1,cld=1,fgs=0 Received: from [127.0.0.1] (localhost [127.0.0.1]) by localhost (Mailerdaemon) with ESMTPSA id 072EA16352A; Tue, 15 Apr 2025 15:33:04 +0200 (CEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ew.tq-group.com; s=dkim; t=1744723987; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version: content-transfer-encoding:content-transfer-encoding; bh=R2SZvhgWOcXu74APsWOF5IGVz2bjc0yiT34pBzEhPzg=; b=Aye+2S9OSazLcxSrARooQIIqEveTec8F0AuUZg7N0qxWL4N3rFbkLV0m/aKsaWjujxk4KJ iVbqYFijDFu5vULgJ3uzsKQI6FeOpEV+cWnb2ocKKBc5EYWUGOftgpoXCUhRPcaDbvOTQ8 QLsngYPwAJDruKTEh2ffEyatPXO17Cl4Swmi/H9PpurvFivHiuUAWLQ1YwVThexqDYj+EP B+z3T+aXfrcaWgSvHxXSrsx/9yHiC8dit59WZCd04ziXxRkpJFSD0cyA5qDAfrAe5ATeFG o5cx6e2F+E7h8wbwrElMBJo0vtNblnMYym0EF3LEpGkZefwH9FNGInu1HGsfsA== From: Alexander Stein To: Rob Herring , Krzysztof Kozlowski , Conor Dooley , Shawn Guo , Sascha Hauer , Pengutronix Kernel Team , Fabio Estevam , Geert Uytterhoeven , Magnus Damm Cc: Markus Niebel , devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, imx@lists.linux.dev, linux-arm-kernel@lists.infradead.org, linux@ew.tq-group.com, linux-renesas-soc@vger.kernel.org, Alexander Stein Subject: [PATCH 1/2] dt-bindings: arm: add TQMa8XxS boards Date: Tue, 15 Apr 2025 15:32:58 +0200 Message-ID: <20250415133301.443511-1-alexander.stein@ew.tq-group.com> X-Mailer: git-send-email 2.43.0 MIME-Version: 1.0 X-Last-TLS-Session-Version: TLSv1.3 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20250415_063314_979436_54FB693A X-CRM114-Status: UNSURE ( 7.52 ) X-CRM114-Notice: Please train this message. X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org From: Markus Niebel TQMa8XxS is a SOM series featuring NXP i.MX8X SoC. They are called TQMa8XQPS and TQMa8XDPS respectively. MB-SMARC-2 is a carrier reference design. Signed-off-by: Markus Niebel Signed-off-by: Alexander Stein --- Documentation/devicetree/bindings/arm/fsl.yaml | 16 ++++++++++++++++ 1 file changed, 16 insertions(+) diff --git a/Documentation/devicetree/bindings/arm/fsl.yaml b/Documentation/devicetree/bindings/arm/fsl.yaml index a6fd347de03fe..1c5fcd69e93e6 100644 --- a/Documentation/devicetree/bindings/arm/fsl.yaml +++ b/Documentation/devicetree/bindings/arm/fsl.yaml @@ -1333,6 +1333,22 @@ properties: - const: tq,imx8qxp-tqma8xqp # TQ-Systems GmbH TQMa8XQP SOM (with i.MX8QXP) - const: fsl,imx8qxp + - description: + TQMa8XxS is a series of SOM featuring NXP i.MX8X system-on-chip + variants. It has the SMARC-2.0 form factor and is designed to be placed on + different carrier boards. MB-SMARC-2 is a carrier reference design. + oneOf: + - items: + - enum: + - tq,imx8qxp-tqma8xqps-mb-smarc-2 # TQ-Systems GmbH TQMa8QXPS SOM on MB-SMARC-2 + - const: tq,imx8qxp-tqma8xqps # TQ-Systems GmbH TQMa8QXPS SOM + - const: fsl,imx8qxp + - items: + - enum: + - tq,imx8dxp-tqma8xdps-mb-smarc-2 # TQ-Systems GmbH TQMa8XDPS SOM on MB-SMARC-2 + - const: tq,imx8dxp-tqma8xdps # TQ-Systems GmbH TQMa8XDPS SOM + - const: fsl,imx8dxp + - description: i.MX8ULP based Boards items: - enum: From patchwork Tue Apr 15 13:32:59 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Alexander Stein X-Patchwork-Id: 14052257 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id A7242C369AB for ; Tue, 15 Apr 2025 13:39:44 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender:List-Subscribe:List-Help :List-Post:List-Archive:List-Unsubscribe:List-Id:Content-Transfer-Encoding: MIME-Version:References:In-Reply-To:Message-ID:Date:Subject:Cc:To:From: Reply-To:Content-Type:Content-ID:Content-Description:Resent-Date:Resent-From: Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:List-Owner; bh=1Ux5/bV5QOPhTGD6jADoyM3HTqpzrzVxNGsBDxVST5Y=; b=zRlKWgw2YFrPH18ohp+2pCeNSo n7fWb2LLFHsTXGl7nniiYA+5ILz3wB7DIaC6sPW7t5BSLE4Rglg1T4WmtPwl+00MCAbj9xk/Nwsas yJNWL5QBOju9LwjP4UTrRxVzjNz813CduteonuJ/Z5uauk4O/WJFZpUBkT0cD8NXZV+0h2z1XhOLg 9MturkAgdGo0ne9zeFIBivSMRIOLxmHSYzb4yjXoXye3Dk+hZ2pyqQ+Q5v2H2Q9k6Dnxbc0R6DEIq B9asiwFg72xr3sS6wu0GFGYVKj0oTNSQhlIQ99MSiO87rkRZ3Eu54N3Nsf5VgmjBZUb9DtqDQwwOv eHCtq5MA==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.98.2 #2 (Red Hat Linux)) id 1u4gVc-00000005wxH-2PKa; Tue, 15 Apr 2025 13:39:28 +0000 Received: from mx1.tq-group.com ([93.104.207.81]) by bombadil.infradead.org with esmtps (Exim 4.98.2 #2 (Red Hat Linux)) id 1u4gPg-00000005vQE-1apw for linux-arm-kernel@lists.infradead.org; Tue, 15 Apr 2025 13:33:23 +0000 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=tq-group.com; i=@tq-group.com; q=dns/txt; s=key1; t=1744724000; x=1776260000; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=1Ux5/bV5QOPhTGD6jADoyM3HTqpzrzVxNGsBDxVST5Y=; b=me5qrJpAXOoC0Eewma2RPGHtUGqX9PSieR8axRJw5fzflz2v9KNBHpax 7SanANGGNHrSAaBrVYvU3xwO1H/ajzOnC/vydYnXSBvYYdc3sW1QhgHqR NgDhtL0JZE/7DjuZHR5vYj/bexWtkDhTFsn/dXkzN++3xcFfB+opZEvPj yrTBJJtLfyeYFKVRR4w4CBVr1+6CzUpKSP8dKWzv7b3xS9rrvYf0Uy2W8 B7VERuPWBT499Im9nWlDAhldTb+UvYDXDHIlMP6yO44i/yLM96ISs1wHX qH+SIqyTrjbRzZWwcfg15KnDNBsnip+xA95vMz8oUaQcQ8XmRV9PeDthS w==; X-CSE-ConnectionGUID: Cxw1Qbr/TW+joe1chzO9Gg== X-CSE-MsgGUID: YoRUlHt9SESaLPfNjK/6Sw== X-IronPort-AV: E=Sophos;i="6.15,213,1739833200"; d="scan'208";a="43543934" Received: from vmailcow01.tq-net.de ([10.150.86.48]) by mx1.tq-group.com with ESMTP; 15 Apr 2025 15:33:18 +0200 X-CheckPoint: {67FE601E-6-B1D34AC3-DEA5B19F} X-MAIL-CPID: 563622A89361B505C6585DC274AB6254_4 X-Control-Analysis: str=0001.0A006398.67FE6023.0034,ss=1,re=0.000,recu=0.000,reip=0.000,cl=1,cld=1,fgs=0 Received: from [127.0.0.1] (localhost [127.0.0.1]) by localhost (Mailerdaemon) with ESMTPSA id 693451669A8; Tue, 15 Apr 2025 15:33:13 +0200 (CEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ew.tq-group.com; s=dkim; t=1744723993; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=1Ux5/bV5QOPhTGD6jADoyM3HTqpzrzVxNGsBDxVST5Y=; b=aPHeUNbCckGcF1kplMPTNwLBvRHeEBnhXviccfhRn03FpZY7ICq0XUhXH61qY0B2AZ+1ng 7q/PFEPU3gynt3UGuOD727NZNhvTALM+rOEhpvAlC5OcyOHUy5IEGN7t5avMT5xdQk/bWI fI1h299f7cW/2RL3PfWmrZu5MIuVODSLNCFS7MqN6euocQX/LiuEVHEA0swBe73kS5wvhQ S7YfLDKMv7zC7JaPl6Ji6QpSxrYE1LjNUjK16MSLUhGTWAHCcFtDdbFKKnOqrBEJRgnYXv S+pVbC68sQDtXhWFxn0dW29ile/y3uvf9rvw7LpdvF14l47xqf/WMUA8vNt5rA== From: Alexander Stein To: Rob Herring , Krzysztof Kozlowski , Conor Dooley , Shawn Guo , Sascha Hauer , Pengutronix Kernel Team , Fabio Estevam , Geert Uytterhoeven , Magnus Damm Cc: Alexander Stein , devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, imx@lists.linux.dev, linux-arm-kernel@lists.infradead.org, linux@ew.tq-group.com, linux-renesas-soc@vger.kernel.org Subject: [PATCH 2/2] arm64: dts: freescale: add initial device tree for TQMa8XxS Date: Tue, 15 Apr 2025 15:32:59 +0200 Message-ID: <20250415133301.443511-2-alexander.stein@ew.tq-group.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250415133301.443511-1-alexander.stein@ew.tq-group.com> References: <20250415133301.443511-1-alexander.stein@ew.tq-group.com> MIME-Version: 1.0 X-Last-TLS-Session-Version: TLSv1.3 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20250415_063320_880418_45AB548D X-CRM114-Status: GOOD ( 17.61 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org This adds support for TQMa8XQPS and TQMa8XDPS modules on MB-SMARC-2 board. As the only difference is the mounted SoC, both module and baseboard files are shared. Signed-off-by: Alexander Stein --- MAINTAINERS | 1 + arch/arm64/boot/dts/freescale/Makefile | 2 + .../imx8dxp-tqma8xdps-mb-smarc-2.dts | 16 + .../boot/dts/freescale/imx8dxp-tqma8xdps.dtsi | 24 + .../imx8qxp-tqma8xqps-mb-smarc-2.dts | 16 + .../boot/dts/freescale/imx8qxp-tqma8xqps.dtsi | 14 + .../dts/freescale/tqma8xxs-mb-smarc-2.dtsi | 194 +++++ arch/arm64/boot/dts/freescale/tqma8xxs.dtsi | 768 ++++++++++++++++++ 8 files changed, 1035 insertions(+) create mode 100644 arch/arm64/boot/dts/freescale/imx8dxp-tqma8xdps-mb-smarc-2.dts create mode 100644 arch/arm64/boot/dts/freescale/imx8dxp-tqma8xdps.dtsi create mode 100644 arch/arm64/boot/dts/freescale/imx8qxp-tqma8xqps-mb-smarc-2.dts create mode 100644 arch/arm64/boot/dts/freescale/imx8qxp-tqma8xqps.dtsi create mode 100644 arch/arm64/boot/dts/freescale/tqma8xxs-mb-smarc-2.dtsi create mode 100644 arch/arm64/boot/dts/freescale/tqma8xxs.dtsi diff --git a/MAINTAINERS b/MAINTAINERS index b5acf50fc6af4..6cd3083084dc4 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -24576,6 +24576,7 @@ F: arch/arm64/boot/dts/freescale/fsl-*tqml*.dts* F: arch/arm64/boot/dts/freescale/imx*mba*.dts* F: arch/arm64/boot/dts/freescale/imx*tqma*.dts* F: arch/arm64/boot/dts/freescale/mba*.dtsi +F: arch/arm64/boot/dts/freescale/tqma8*.dtsi F: arch/arm64/boot/dts/freescale/tqml*.dts* F: drivers/gpio/gpio-tqmx86.c F: drivers/mfd/tqmx86.c diff --git a/arch/arm64/boot/dts/freescale/Makefile b/arch/arm64/boot/dts/freescale/Makefile index 1e3c13562bd71..37c5ffe8ba71b 100644 --- a/arch/arm64/boot/dts/freescale/Makefile +++ b/arch/arm64/boot/dts/freescale/Makefile @@ -105,6 +105,7 @@ dtb-$(CONFIG_ARCH_MXC) += imx8dx-colibri-iris-v2.dtb dtb-$(CONFIG_ARCH_MXC) += imx8dx-colibri-iris.dtb dtb-$(CONFIG_ARCH_MXC) += imx8dxl-evk.dtb dtb-$(CONFIG_ARCH_MXC) += imx8dxp-tqma8xdp-mba8xx.dtb +dtb-$(CONFIG_ARCH_MXC) += imx8dxp-tqma8xdps-mb-smarc-2.dtb dtb-$(CONFIG_ARCH_MXC) += imx8mm-beacon-kit.dtb dtb-$(CONFIG_ARCH_MXC) += imx8mm-data-modul-edm-sbc.dtb dtb-$(CONFIG_ARCH_MXC) += imx8mm-ddr4-evk.dtb @@ -294,6 +295,7 @@ imx8qxp-mek-pcie-ep-dtbs += imx8qxp-mek.dtb imx8qxp-mek-pcie-ep.dtbo dtb-$(CONFIG_ARCH_MXC) += imx8qxp-mek-pcie-ep.dtb dtb-$(CONFIG_ARCH_MXC) += imx8qxp-tqma8xqp-mba8xx.dtb +dtb-$(CONFIG_ARCH_MXC) += imx8qxp-tqma8xqps-mb-smarc-2.dtb dtb-$(CONFIG_ARCH_MXC) += imx8ulp-evk.dtb dtb-$(CONFIG_ARCH_MXC) += imx93-9x9-qsb.dtb diff --git a/arch/arm64/boot/dts/freescale/imx8dxp-tqma8xdps-mb-smarc-2.dts b/arch/arm64/boot/dts/freescale/imx8dxp-tqma8xdps-mb-smarc-2.dts new file mode 100644 index 0000000000000..331787df2fe47 --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx8dxp-tqma8xdps-mb-smarc-2.dts @@ -0,0 +1,16 @@ +// SPDX-License-Identifier: (GPL-2.0-or-later OR MIT) +/* + * Copyright (c) 2021-2025 TQ-Systems GmbH , + * D-82229 Seefeld, Germany. + * Author: Alexander Stein + */ + +/dts-v1/; + +#include "imx8dxp-tqma8xdps.dtsi" +#include "tqma8xxs-mb-smarc-2.dtsi" + +/ { + model = "TQ-Systems i.MX8DXP TQMa8XDPS on MB-SMARC-2"; + compatible = "tq,imx8dxp-tqma8xdps-mb-smarc-2", "tq,imx8dxp-tqma8xdps", "fsl,imx8dxp"; +}; diff --git a/arch/arm64/boot/dts/freescale/imx8dxp-tqma8xdps.dtsi b/arch/arm64/boot/dts/freescale/imx8dxp-tqma8xdps.dtsi new file mode 100644 index 0000000000000..a97286fe7e0d7 --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx8dxp-tqma8xdps.dtsi @@ -0,0 +1,24 @@ +// SPDX-License-Identifier: (GPL-2.0-or-later OR MIT) +/* + * Copyright (c) 2021-2025 TQ-Systems GmbH , + * D-82229 Seefeld, Germany. + * Author: Alexander Stein + */ + +#include "imx8dxp.dtsi" +#include "tqma8xxs.dtsi" + +/ { + model = "TQ-Systems i.MX8DXP TQMa8XDPS"; + compatible = "tq,imx8dxp-tqma8xdps", "fsl,imx8dxp"; +}; + +&pmic0_thermal { + cooling-maps { + map0 { + cooling-device = + <&A35_0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&A35_1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + }; + }; +}; diff --git a/arch/arm64/boot/dts/freescale/imx8qxp-tqma8xqps-mb-smarc-2.dts b/arch/arm64/boot/dts/freescale/imx8qxp-tqma8xqps-mb-smarc-2.dts new file mode 100644 index 0000000000000..3fa9b5aee2c38 --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx8qxp-tqma8xqps-mb-smarc-2.dts @@ -0,0 +1,16 @@ +// SPDX-License-Identifier: (GPL-2.0-or-later OR MIT) +/* + * Copyright (c) 2018-2025 TQ-Systems GmbH , + * D-82229 Seefeld, Germany. + * Author: Alexander Stein + */ + +/dts-v1/; + +#include "imx8qxp-tqma8xqps.dtsi" +#include "tqma8xxs-mb-smarc-2.dtsi" + +/ { + model = "TQ-Systems i.MX8QXP TQMa8XQPS on MB-SMARC-2"; + compatible = "tq,imx8qxp-tqma8xqps-mb-smarc-2", "tq,imx8qxp-tqma8xqps", "fsl,imx8qxp"; +}; diff --git a/arch/arm64/boot/dts/freescale/imx8qxp-tqma8xqps.dtsi b/arch/arm64/boot/dts/freescale/imx8qxp-tqma8xqps.dtsi new file mode 100644 index 0000000000000..f008b7a345058 --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx8qxp-tqma8xqps.dtsi @@ -0,0 +1,14 @@ +// SPDX-License-Identifier: (GPL-2.0-or-later OR MIT) +/* + * Copyright (c) 2018-2025 TQ-Systems GmbH , + * D-82229 Seefeld, Germany. + * Author: Alexander Stein + */ + +#include "imx8qxp.dtsi" +#include "tqma8xxs.dtsi" + +/ { + model = "TQ-Systems i.MX8QXP TQMa8XQPS"; + compatible = "tq,imx8qxp-tqma8xqps", "fsl,imx8qxp"; +}; diff --git a/arch/arm64/boot/dts/freescale/tqma8xxs-mb-smarc-2.dtsi b/arch/arm64/boot/dts/freescale/tqma8xxs-mb-smarc-2.dtsi new file mode 100644 index 0000000000000..478cc8ede05ef --- /dev/null +++ b/arch/arm64/boot/dts/freescale/tqma8xxs-mb-smarc-2.dtsi @@ -0,0 +1,194 @@ +// SPDX-License-Identifier: (GPL-2.0-or-later OR MIT) +/* + * Copyright (c) 2018-2025 TQ-Systems GmbH , + * D-82229 Seefeld, Germany. + * Author: Alexander Stein + */ + +/ { + aliases { + rtc0 = &rtc1; + rtc1 = &rtc; + }; + + backlight_lvds0: backlight-lvds0 { + compatible = "pwm-backlight"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_backlight_lvds0>; + /* PWM support still missing */ + brightness-levels = <0 4 8 16 32 64 128 255>; + default-brightness-level = <7>; + power-supply = <®_12v0>; + enable-gpios = <&lsio_gpio1 2 GPIO_ACTIVE_HIGH>; + status = "disabled"; + }; + + backlight_lvds1: backlight-lvds1 { + compatible = "pwm-backlight"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_backlight_lvds1>; + /* PWM support still missing */ + brightness-levels = <0 4 8 16 32 64 128 255>; + default-brightness-level = <7>; + power-supply = <®_12v0>; + enable-gpios = <&lsio_gpio1 0 GPIO_ACTIVE_HIGH>; + status = "disabled"; + }; + + chosen { + stdout-path = &lpuart0; + }; + + panel_lvds0: panel-lvds0 { + /* + * Display is not fixed, so compatible has to be added from + * DT + */ + backlight = <&backlight_lvds0>; + power-supply = <®_lvds0>; + status = "disabled"; + + port { + panel_in_lvds0: endpoint { + }; + }; + }; + + panel_lvds1: panel-lvds1 { + /* + * Display is not fixed, so compatible has to be added from + * DT + */ + backlight = <&backlight_lvds1>; + power-supply = <®_lvds1>; + status = "disabled"; + + port { + panel_in_lvds1: endpoint { + }; + }; + }; + + reg_1v8: regulator-1v8 { + compatible = "regulator-fixed"; + regulator-name = "1V8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + }; + + reg_3v3: regulator-3v3 { + compatible = "regulator-fixed"; + regulator-name = "3V3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + reg_12v0: regulator-12v0 { + compatible = "regulator-fixed"; + regulator-name = "12V0"; + regulator-min-microvolt = <12000000>; + regulator-max-microvolt = <12000000>; + regulator-always-on; + }; + + sound { + compatible = "fsl,imx-audio-tlv320aic32x4"; + model = "tqm-tlv320aic32"; + ssi-controller = <&sai1>; + audio-codec = <&tlv320aic3x04>; + }; +}; + +&fec1 { + status = "okay"; +}; + +&fec2 { + status = "okay"; +}; + +&flexcan2 { + xceiver-supply = <®_3v3>; + status = "okay"; +}; + +&flexcan3 { + xceiver-supply = <®_3v3>; + status = "okay"; +}; + +&i2c0 { + tlv320aic3x04: audio-codec@18 { + compatible = "ti,tlv320aic32x4"; + reg = <0x18>; + clocks = <&mclkout0_lpcg 0>; + clock-names = "mclk"; + iov-supply = <®_1v8>; + ldoin-supply = <®_3v3>; + }; + + eeprom2: eeprom@57 { + compatible = "atmel,24c32"; + reg = <0x57>; + pagesize = <32>; + vcc-supply = <®_3v3>; + }; +}; + +&lpspi1 { + status = "okay"; +}; + +&lpuart0 { + status = "okay"; +}; + +&lpuart3 { + status = "okay"; +}; + +®_sdvmmc { + off-on-delay-us = <200000>; + status = "okay"; +}; + +&usbotg1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usbotg1>; + srp-disable; + hnp-disable; + adp-disable; + power-active-high; + over-current-active-low; + dr_mode = "otg"; + status = "okay"; +}; + +&usbotg3 { + status = "okay"; +}; + +&usbotg3_cdns3 { + dr_mode = "host"; + status = "okay"; +}; + +&usb3_phy { + status = "okay"; +}; + +&usbphy1 { + status = "okay"; +}; + +&usdhc2 { + cd-gpios = <&lsio_gpio4 22 GPIO_ACTIVE_LOW>; + wp-gpios = <&lsio_gpio4 21 GPIO_ACTIVE_HIGH>; + vmmc-supply = <®_sdvmmc>; + no-1-8-v; + no-mmc; + no-sdio; + status = "okay"; +}; diff --git a/arch/arm64/boot/dts/freescale/tqma8xxs.dtsi b/arch/arm64/boot/dts/freescale/tqma8xxs.dtsi new file mode 100644 index 0000000000000..1fc509c7ac1e8 --- /dev/null +++ b/arch/arm64/boot/dts/freescale/tqma8xxs.dtsi @@ -0,0 +1,768 @@ +// SPDX-License-Identifier: (GPL-2.0-or-later OR MIT) +/* + * Copyright (c) 2018-2025 TQ-Systems GmbH , + * D-82229 Seefeld, Germany. + * Author: Alexander Stein + */ + +#include + +/delete-node/ &encoder_rpc; + +/ { + memory@80000000 { + device_type = "memory"; + /* + * DRAM base addr, minimal size : 1024 MiB DRAM + * should be corrected by bootloader + */ + reg = <0x00000000 0x80000000 0 0x40000000>; + }; + + clk_xtal25: clk-xtal25 { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <25000000>; + }; + + reg_tqma8xxs_3v3: regulator-3v3 { + compatible = "regulator-fixed"; + regulator-name = "3V3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + reg_lvds0: regulator-lvds0 { + compatible = "regulator-fixed"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_lvds0>; + regulator-name = "LCD0_VDD_EN"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpio = <&lsio_gpio1 3 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + + reg_lvds1: regulator-lvds1 { + compatible = "regulator-fixed"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_lvds1>; + regulator-name = "LCD1_VDD_EN"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpio = <&lsio_gpio1 1 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + + reg_sdvmmc: regulator-sdvmmc { + compatible = "regulator-fixed"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_sdvmmc>; + regulator-name = "SD1_VMMC"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpio = <&lsio_gpio4 19 GPIO_ACTIVE_HIGH>; + enable-active-high; + status = "disabled"; + }; + + reg_vmmc: regulator-vmmc { + compatible = "regulator-fixed"; + regulator-name = "MMC0_3V3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + reg_vqmmc: regulator-vqmmc { + compatible = "regulator-fixed"; + regulator-name = "MMC0_1V8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + }; + + reserved-memory { + #address-cells = <2>; + #size-cells = <2>; + ranges; + + /* + * global autoconfigured region for contiguous allocations + * must not exceed memory size and region + */ + linux,cma { + compatible = "shared-dma-pool"; + reusable; + size = <0 0x20000000>; + alloc-ranges = <0 0x96000000 0 0x30000000>; + linux,cma-default; + }; + + decoder_boot: decoder-boot@84000000 { + reg = <0 0x84000000 0 0x2000000>; + no-map; + }; + + encoder_boot: encoder-boot@86000000 { + reg = <0 0x86000000 0 0x200000>; + no-map; + }; + + m4_reserved: m4@88000000 { + no-map; + reg = <0 0x88000000 0 0x8000000>; + status = "disabled"; + }; + + vdev0vring0: vdev0vring0@90000000 { + compatible = "shared-dma-pool"; + reg = <0 0x90000000 0 0x8000>; + no-map; + status = "disabled"; + }; + + vdev0vring1: vdev0vring1@90008000 { + compatible = "shared-dma-pool"; + reg = <0 0x90008000 0 0x8000>; + no-map; + status = "disabled"; + }; + + vdev1vring0: vdev1vring0@90010000 { + compatible = "shared-dma-pool"; + reg = <0 0x90010000 0 0x8000>; + no-map; + status = "disabled"; + }; + + vdev1vring1: vdev1vring1@90018000 { + compatible = "shared-dma-pool"; + reg = <0 0x90018000 0 0x8000>; + no-map; + status = "disabled"; + }; + + rsc_table: rsc-table@900ff000 { + reg = <0 0x900ff000 0 0x1000>; + no-map; + status = "disabled"; + }; + + vdevbuffer: vdevbuffer@90400000 { + compatible = "shared-dma-pool"; + reg = <0 0x90400000 0 0x100000>; + no-map; + status = "disabled"; + }; + + decoder_rpc: decoder-rpc@92000000 { + reg = <0 0x92000000 0 0x100000>; + no-map; + }; + + encoder_rpc: encoder-rpc@92100000 { + reg = <0 0x92100000 0 0x700000>; + no-map; + }; + }; + +}; + +/* TQMa8XxS only uses industrial grade, reduce trip points accordingly */ +&cpu_alert0 { + temperature = <95000>; +}; + +&cpu_crit0 { + temperature = <100000>; +}; +/* end of temperature grade adjustments */ + +&fec1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_fec1>; + phy-mode = "rgmii-id"; + phy-handle = <ðphy0>; + fsl,magic-packet; + mac-address = [ 00 00 00 00 00 00 ]; + + mdio { + #address-cells = <1>; + #size-cells = <0>; + + ethphy0: ethernet-phy@0 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <0>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_ethphy0>; + ti,rx-internal-delay = ; + ti,tx-internal-delay = ; + ti,fifo-depth = ; + ti,dp83867-rxctrl-strap-quirk; + ti,clk-output-sel = ; + reset-gpios = <&lsio_gpio3 22 GPIO_ACTIVE_LOW>; + reset-assert-us = <500000>; + reset-deassert-us = <50000>; + enet-phy-lane-no-swap; + interrupt-parent = <&lsio_gpio1>; + interrupts = <30 IRQ_TYPE_EDGE_FALLING>; + }; + + ethphy3: ethernet-phy@3 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <3>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_ethphy1>; + ti,rx-internal-delay = ; + ti,tx-internal-delay = ; + ti,fifo-depth = ; + ti,dp83867-rxctrl-strap-quirk; + ti,clk-output-sel = ; + reset-gpios = <&lsio_gpio0 24 GPIO_ACTIVE_LOW>; + reset-assert-us = <500000>; + reset-deassert-us = <50000>; + enet-phy-lane-no-swap; + interrupt-parent = <&lsio_gpio1>; + interrupts = <14 IRQ_TYPE_EDGE_FALLING>; + }; + }; +}; + +&fec2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_fec2>; + phy-mode = "rgmii-id"; + phy-handle = <ðphy3>; + fsl,magic-packet; + mac-address = [ 00 00 00 00 00 00 ]; +}; + +&flexcan2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_can1>; +}; + +&flexcan3 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_can2>; +}; + +&flexspi0 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_flexspi0>; + status = "okay"; + + flash0: flash@0 { + compatible = "jedec,spi-nor"; + reg = <0>; + spi-max-frequency = <66000000>; + spi-tx-bus-width = <1>; + spi-rx-bus-width = <4>; + + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + }; + }; +}; + +&lsio_gpio0 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_smarc_fangpio>, <&pinctrl_smarc_mngtpio>; + + gpio-line-names = "", "", "", "", + "", "", "", "", + "", "", "", "", + "LID", "SLEEP", "CHARGING#", "CHGPRSNT#", + "BATLOW#", "", "", "", + "", "SMARC_GPIO6", "SMARC_GPIO5", "", + "PHY3 RST#", "", "", "SPI0_CS0", + "", "SPI0_CS1", "", ""; +}; + +&lsio_gpio1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_smarc_gpio>; + + gpio-line-names = "LCD1_BLKT_EN", "LCD1_VDD_EN", "LCD0_BLKT_EN", "LCD0_VDD_EN", + "SMARC_GPIO0", "SMARC_GPIO1", "SMARC_GPIO2", "", + "SMARC_GPIO3", "SMARC_GPIO8", "SMARC_GPIO7", "SMARC_GPIO10", + "SMARC_GPIO9", "SMARC_GPIO4", "", "", + "", "", "", "", + "", "", "", "", + "", "", "", "", + "", "", "", ""; +}; + +&lsio_gpio2 { + gpio-line-names = "RTC_INT#", "", "", "", + "", "", "", "", + "", "", "", "", + "", "", "", "", + "", "", "", "", + "", "", "", "", + "", "", "", "", + "", "", "", ""; +}; + +&lsio_gpio3 { + gpio-line-names = "", "", "", "", + "", "", "", "", + "", "", "", "", + "", "", "", "", + "", "", "", "", + "", "", "PHY0_RST#", "", + "", "", "", "", + "", "", "", ""; +}; + +&lsio_gpio4 { + gpio-line-names = "PCIE_PERST#", "", "PCIE_WAKE#", "USB_OTG1_PWR", + "", "", "", "", + "", "", "", "", + "", "", "", "", + "", "", "", "SDIO_PWR_EN", + "", "SDIO_WP", "SDIO_CD#", "", + "", "", "", "", + "", "", "", ""; +}; + +&i2c0 { + clock-frequency = <100000>; + pinctrl-names = "default", "gpio"; + pinctrl-0 = <&pinctrl_lpi2c0>; + pinctrl-1 = <&pinctrl_lpi2c0_gpio>; + scl-gpios = <&lsio_gpio3 8 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + sda-gpios = <&lsio_gpio3 7 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + status = "okay"; + + /* NXP SE97BTP with temperature sensor + eeprom */ + sensor0: temperature-sensor@1b { + compatible = "nxp,se97b", "jedec,jc-42.4-temp"; + reg = <0x1b>; + }; + + eeprom0: eeprom@50 { + compatible = "atmel,24c64"; + reg = <0x50>; + pagesize = <32>; + vcc-supply = <®_tqma8xxs_3v3>; + }; + + rtc1: rtc@51 { + compatible = "nxp,pcf85063a"; + reg = <0x51>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_rtc>; + quartz-load-femtofarads = <7000>; + interrupt-parent = <&lsio_gpio2>; + interrupts = <0 IRQ_TYPE_LEVEL_LOW>; + }; + + eeprom1: eeprom@53 { + compatible = "nxp,se97b", "atmel,24c02"; + reg = <0x53>; + pagesize = <16>; + read-only; + vcc-supply = <®_tqma8xxs_3v3>; + }; + + pcieclk: clock-generator@6a { + compatible = "renesas,9fgv0241"; + reg = <0x6a>; + clocks = <&clk_xtal25>; + #clock-cells = <1>; + }; +}; + +&lpspi1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_spi1>; + cs-gpios = <&lsio_gpio0 27 GPIO_ACTIVE_LOW>, <&lsio_gpio0 29 GPIO_ACTIVE_LOW>; +}; + +&lpuart0 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_lpuart0>; +}; + +&lpuart3 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_lpuart3>; +}; + +&mu_m0 { + status = "okay"; +}; + +&mu1_m0 { + status = "okay"; +}; + +&sai1 { + assigned-clocks = <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_PLL>, + <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_SLV_BUS>, + <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_MST_BUS>, + <&sai1_lpcg 0>; + assigned-clock-rates = <786432000>, <49152000>, <12288000>, <49152000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_sai1>; + status = "okay"; +}; + +&thermal_zones { + pmic0_thermal: pmic0-thermal { + polling-delay-passive = <250>; + polling-delay = <2000>; + thermal-sensors = <&tsens IMX_SC_R_PMIC_0>; + + trips { + pmic_alert0: trip0 { + temperature = <110000>; + hysteresis = <2000>; + type = "passive"; + }; + + pmic_crit0: trip1 { + temperature = <125000>; + hysteresis = <2000>; + type = "critical"; + }; + }; + + cooling-maps { + map0 { + trip = <&pmic_alert0>; + cooling-device = + <&A35_0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&A35_1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&A35_2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&A35_3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + }; + }; + }; +}; + +&usdhc1 { + pinctrl-names = "default", "state_100mhz", "state_200mhz"; + pinctrl-0 = <&pinctrl_usdhc1>; + pinctrl-1 = <&pinctrl_usdhc1_100mhz>; + pinctrl-2 = <&pinctrl_usdhc1_200mhz>; + vmmc-supply = <®_vmmc>; + vqmmc-supply = <®_vqmmc>; + bus-width = <8>; + non-removable; + no-sd; + no-sdio; + status = "okay"; +}; + +&usdhc2 { + pinctrl-names = "default", "state_100mhz", "state_200mhz"; + pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>; + pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>; + pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>; + bus-width = <4>; + /* NOTE: CD / WP and VMMC support depends on mainboard */ +}; + +&vpu { + compatible = "nxp,imx8qxp-vpu"; + status = "okay"; +}; + +&vpu_core0 { + memory-region = <&decoder_boot>, <&decoder_rpc>; + status = "okay"; +}; + +&vpu_core1 { + memory-region = <&encoder_boot>, <&encoder_rpc>; + status = "okay"; +}; + +&iomuxc { + pinctrl_backlight_lvds0: backlight-lvds0grp { + fsl,pins = ; + }; + + pinctrl_backlight_lvds1: backlight-lvds1grp { + fsl,pins = ; + }; + + pinctrl_can1: can1grp { + fsl,pins = , + ; + }; + + pinctrl_can2: can2grp { + fsl,pins = , + ; + }; + + pinctrl_ethphy0: ethphy0grp { + fsl,pins = , + ; + }; + + pinctrl_ethphy1: ethphy1grp { + fsl,pins = , + ; + }; + + pinctrl_fec1: fec1grp { + fsl,pins = , + , + , + , + , + , + , + , + , + , + , + , + , + ; + }; + + pinctrl_fec2: fec2grp { + fsl,pins = , + , + , + , + , + , + , + , + , + , + , + ; + }; + + pinctrl_flexspi0: flexspi0grp { + fsl,pins = , + , + , + , + , + , + , + , + , + , + , + , + , + ; + }; + + pinctrl_smarc_gpio: smarcgpiogrp { + fsl,pins = /* SMARC_GPIO0 / CAM0_PWR# */ + , + /* SMARC_GPIO1 / CAM1_PWR# */ + , + /* SMARC_GPIO2 / CAM0_RST# */ + , + /* SMARC_GPIO3 / CAM1_RST# */ + , + /* SMARC_GPIO4 / HDA_RST# */ + , + /* SMARC_GPIO7 */ + , + /* SMARC_GPIO8 */ + , + /* SMARC_GPIO9 */ + , + /* SMARC_GPIO10 */ + ; + }; + + pinctrl_smarc_fangpio: smarcfangpiogrp { + fsl,pins = /* SMARC_GPIO5 */ + , + /* SMARC_GPIO6 */ + ; + }; + + pinctrl_smarc_mngtpio: smarcmngtgpiogrp { + fsl,pins = /* SMARC BATLOW# */ + , + /* SMARC SLEEP */ + , + /* SMARC CHGPRSNT# */ + , + /* SMARC CHARGING# */ + , + /* SMARC LID */ + ; + }; + + pinctrl_lvds0: lbdpanel0grp { + fsl,pins = /* LCD PWR */ + ; + }; + + pinctrl_lvds1: lbdpanel1grp { + fsl,pins = /* LCD PWR */ + ; + }; + + pinctrl_lpi2c0: lpi2c0grp { + fsl,pins = , + ; + }; + + pinctrl_lpi2c0_gpio: lpi2c0gpiogrp { + fsl,pins = , + ; + }; + + pinctrl_lpuart0: lpuart0grp { + fsl,pins = , + , + , + ; + }; + + pinctrl_lpuart3: lpuart3grp { + fsl,pins = , + ; + }; + + pinctrl_i2c0_mipi_lvds0: mipi-lvds0-i2c0grp { + fsl,pins = , + ; + }; + + pinctrl_i2c0_gpio_mipi_lvds0: mipi-lvds0-i2c0-gpiogrp { + fsl,pins = , + ; + }; + + pinctrl_pcieb: pcieagrp { + fsl,pins = , + , + ; + }; + + pinctrl_pwm_mipi_lvds0: mipi-lvds0-pwmgrp { + fsl,pins = ; + }; + + pinctrl_pwm_mipi_lvds1: mipi-lvds1-pwmgrp { + fsl,pins = ; + }; + + pinctrl_rtc: rtcgrp { + fsl,pins = ; + }; + + pinctrl_usdhc1: usdhc1grp { + fsl,pins = , + , + , + , + , + , + , + , + , + , + ; + }; + + pinctrl_usdhc1_100mhz: usdhc1100mhzgrp { + fsl,pins = , + , + , + , + , + , + , + , + , + , + ; + }; + + pinctrl_usdhc1_200mhz: usdhc1200mhzgrp { + fsl,pins = , + , + , + , + , + , + , + , + , + , + ; + }; + + pinctrl_sdvmmc: sdvmmcgrp { + fsl,pins = ; + }; + + pinctrl_spi1: spi1grp { + fsl,pins = /* PD + PDRV Low + INOUT - MEK has 0x0600004c */ + , + , + , + , + ; + }; + + pinctrl_sai1: sai1grp { + fsl,pins = , + , + , + , + ; + }; + + pinctrl_usbotg1: usbotg1grp { + fsl,pins = , + ; + }; + + pinctrl_usdhc2_gpio: usdhc2gpiogrp { + fsl,pins = , + ; + }; + + pinctrl_usdhc2: usdhc2grp { + fsl,pins = , + , + , + , + , + , + ; + }; + + pinctrl_usdhc2_100mhz: usdhc2100mhzgrp { + fsl,pins = , + , + , + , + , + , + ; + }; + + pinctrl_usdhc2_200mhz: usdhc2200mhzgrp { + fsl,pins = , + , + , + , + , + , + ; + }; +};