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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 15 Apr 2025 14:55:12.3729 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: d8a3c66b-8448-41cc-7866-08dd7c2d8642 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: CH2PEPF0000014A.namprd02.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: BY5PR12MB4276 Currently, the MCE subsystem sysfs interface will be removed if the thresholding sysfs interface fails to be created. A common failure is due to new MCA bank types that are not recognized and don't have a short name set. The MCA thresholding feature is optional and should not break the common MCE sysfs interface. Also, new MCA bank types are occasionally introduced, and updates will be needed to recognize them. But likewise, this should not break the common sysfs interface. Keep the MCE sysfs interface regardless of the status of the thresholding sysfs interface. Cc: stable@vger.kernel.org Reviewed-by: Qiuxu Zhuo Tested-by: Tony Luck Reviewed-by: Tony Luck Signed-off-by: Yazen Ghannam --- Notes: Link: https://lore.kernel.org/r/20250213-wip-mca-updates-v2-1-3636547fe05f@amd.com v2->v3: * Added tags from Qiuxu and Tony. v1->v2: * New in v2. * Included stable tag but there's no specific commit for Fixes. arch/x86/kernel/cpu/mce/core.c | 8 +------- 1 file changed, 1 insertion(+), 7 deletions(-) diff --git a/arch/x86/kernel/cpu/mce/core.c b/arch/x86/kernel/cpu/mce/core.c index 255927f0284e..72c2aa0809c0 100644 --- a/arch/x86/kernel/cpu/mce/core.c +++ b/arch/x86/kernel/cpu/mce/core.c @@ -2801,15 +2801,9 @@ static int mce_cpu_dead(unsigned int cpu) static int mce_cpu_online(unsigned int cpu) { struct timer_list *t = this_cpu_ptr(&mce_timer); - int ret; mce_device_create(cpu); - - ret = mce_threshold_create_device(cpu); - if (ret) { - mce_device_remove(cpu); - return ret; - } + mce_threshold_create_device(cpu); mce_reenable_cpu(); mce_start_timer(t); return 0; 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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 15 Apr 2025 14:55:13.2791 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: a9ddf246-7905-4f5f-c186-08dd7c2d86cc X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: CH2PEPF0000014A.namprd02.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DM4PR12MB7765 The return values are not checked, so set return type to 'void'. Also, move function declarations to internal.h, since these functions are only used within the MCE subsystem. Signed-off-by: Yazen Ghannam --- Notes: Link: https://lore.kernel.org/r/20250213-wip-mca-updates-v2-2-3636547fe05f@amd.com v2->v3: * Include mce_threshold_remove_device(). v1->v2: * New in v2. arch/x86/include/asm/mce.h | 6 ------ arch/x86/kernel/cpu/mce/amd.c | 22 ++++++++++------------ arch/x86/kernel/cpu/mce/internal.h | 4 ++++ 3 files changed, 14 insertions(+), 18 deletions(-) diff --git a/arch/x86/include/asm/mce.h b/arch/x86/include/asm/mce.h index 6c77c03139f7..752802bf966b 100644 --- a/arch/x86/include/asm/mce.h +++ b/arch/x86/include/asm/mce.h @@ -371,15 +371,9 @@ enum smca_bank_types { extern bool amd_mce_is_memory_error(struct mce *m); -extern int mce_threshold_create_device(unsigned int cpu); -extern int mce_threshold_remove_device(unsigned int cpu); - void mce_amd_feature_init(struct cpuinfo_x86 *c); enum smca_bank_types smca_get_bank_type(unsigned int cpu, unsigned int bank); #else - -static inline int mce_threshold_create_device(unsigned int cpu) { return 0; }; -static inline int mce_threshold_remove_device(unsigned int cpu) { return 0; }; static inline bool amd_mce_is_memory_error(struct mce *m) { return false; }; static inline void mce_amd_feature_init(struct cpuinfo_x86 *c) { } #endif diff --git a/arch/x86/kernel/cpu/mce/amd.c b/arch/x86/kernel/cpu/mce/amd.c index 9d852c3b2cb5..7ff479c679fb 100644 --- a/arch/x86/kernel/cpu/mce/amd.c +++ b/arch/x86/kernel/cpu/mce/amd.c @@ -1290,12 +1290,12 @@ static void __threshold_remove_device(struct threshold_bank **bp) kfree(bp); } -int mce_threshold_remove_device(unsigned int cpu) +void mce_threshold_remove_device(unsigned int cpu) { struct threshold_bank **bp = this_cpu_read(threshold_banks); if (!bp) - return 0; + return; /* * Clear the pointer before cleaning up, so that the interrupt won't @@ -1304,7 +1304,7 @@ int mce_threshold_remove_device(unsigned int cpu) this_cpu_write(threshold_banks, NULL); __threshold_remove_device(bp); - return 0; + return; } /** @@ -1318,36 +1318,34 @@ int mce_threshold_remove_device(unsigned int cpu) * thread running on @cpu. The callback is invoked on all CPUs which are * online when the callback is installed or during a real hotplug event. */ -int mce_threshold_create_device(unsigned int cpu) +void mce_threshold_create_device(unsigned int cpu) { unsigned int numbanks, bank; struct threshold_bank **bp; - int err; if (!mce_flags.amd_threshold) - return 0; + return; bp = this_cpu_read(threshold_banks); if (bp) - return 0; + return; numbanks = this_cpu_read(mce_num_banks); bp = kcalloc(numbanks, sizeof(*bp), GFP_KERNEL); if (!bp) - return -ENOMEM; + return; for (bank = 0; bank < numbanks; ++bank) { if (!(this_cpu_read(bank_map) & BIT_ULL(bank))) continue; - err = threshold_create_bank(bp, cpu, bank); - if (err) { + if (threshold_create_bank(bp, cpu, bank)) { __threshold_remove_device(bp); - return err; + return; } } this_cpu_write(threshold_banks, bp); if (thresholding_irq_en) mce_threshold_vector = amd_threshold_interrupt; - return 0; + return; } diff --git a/arch/x86/kernel/cpu/mce/internal.h b/arch/x86/kernel/cpu/mce/internal.h index b5ba598e54cb..64ac25b95360 100644 --- a/arch/x86/kernel/cpu/mce/internal.h +++ b/arch/x86/kernel/cpu/mce/internal.h @@ -265,6 +265,8 @@ void mce_prep_record_common(struct mce *m); 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Tue, 15 Apr 2025 09:55:12 -0500 From: Yazen Ghannam Date: Tue, 15 Apr 2025 14:54:58 +0000 Subject: [PATCH v3 03/17] x86/mce/amd: Remove smca_banks_map Precedence: bulk X-Mailing-List: linux-edac@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-ID: <20250415-wip-mca-updates-v3-3-8ffd9eb4aa56@amd.com> References: <20250415-wip-mca-updates-v3-0-8ffd9eb4aa56@amd.com> In-Reply-To: <20250415-wip-mca-updates-v3-0-8ffd9eb4aa56@amd.com> To: , Tony Luck CC: , , , Qiuxu Zhuo X-Mailer: b4 0.15-dev-9b767 X-ClientProxiedBy: SATLEXMB03.amd.com (10.181.40.144) To SATLEXMB04.amd.com (10.181.40.145) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: CH2PEPF0000014A:EE_|DS7PR12MB5909:EE_ X-MS-Office365-Filtering-Correlation-Id: f77c4f6b-a147-47bd-5cc6-08dd7c2d8708 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|36860700013|82310400026|376014|1800799024|13003099007|7053199007; X-Microsoft-Antispam-Message-Info: =?utf-8?q?S05QCzSdFKShhlKNumxUQWR75KwFc8n?= =?utf-8?q?e1OfODXvn3K0q6iniBStOJSFcyzCXsrXQucCbC72CrHKqlMrerE0uR3qU8xz98mw8?= =?utf-8?q?zUFJlWUdIb8CcaKCUlzt9NRfRJgBSEgRd+F5ioF9folgbZJ6vV1LtgfCRiVLXu5/Z?= =?utf-8?q?F/URjsmenuoO0usnr7NuqbKNK4/J68Rwo7lBh4YlHw+hJr9ffPdRHBjq0clT6KbWo?= =?utf-8?q?wUcRnJ8K4bhH5lLmjui5V602seEFbcNKv4ylt2CfwYwX55AkBbu3rs1Y+Uvi01roc?= =?utf-8?q?jUViL72oynyO1QoE8G2IbZno2B0J/QH1zkHw/6huX3KiYyXmqRXNRRwXfJlQfsb4i?= =?utf-8?q?1UkQLV1iW8/A/Jnm9IcuMNOgIe2I8d8RQdQx2Rj9XN7d3zsNLtjOG5pmfbtgp9V0o?= =?utf-8?q?vikCs0Fxirr3zKrGBut+VlsVB+cM1wHL8kb3nKiOpTNee4LtIR6GZBpMoKN87JWA8?= =?utf-8?q?oVetaIGRCeYESp0ucJ0Xis45LdMDmRJdryASVHFduMFcRnqemLJloo6iF9Rhfc6y3?= =?utf-8?q?5FpzXtej2Vi3G6Gzc1A0iBFu27NnM2w8L6pxQDzhpnNYj8XsvrABHIyUipHPlGdwG?= =?utf-8?q?8L4kT7xwm/8dTE9QcrZECye+YnD3RcKRp+BKYOj5q7f/UxDvenwWBilA2wVuClPqP?= =?utf-8?q?wWplUoDpreHpGK7ubgpjkJvEn0rjCRbxwRjz8x+DZoZFzbmfN4BYmMstzPL/sS8D7?= =?utf-8?q?2D0lCHezFFz/shl0U3RuVmTE13pD7rZHtPu79gsI1UOcbGH8p79klNxcXcJNwb0Ka?= =?utf-8?q?sssKE2sMIppmdA1WKAYx3f0iHQycpDB7h1Iz8OTuRrmhAOhX6/XMl0Exz3qTtYK4O?= =?utf-8?q?OcD+ehwZ5PvfRGD7evOvzytQypPg2vxI1efPwd2X7Rh5tj2yG3b0RexoC7T22CA+e?= =?utf-8?q?7VczN30gEP3C1dgcC15SxxaqBvRQ6Q9HEdlaAsZldYk7VNidbOJoNHAwlUidZAPQC?= =?utf-8?q?OAF2u5n+IwdPf1YkW4qU7J6UDDPLhEAfIkVgognY6MLP4cQLA4vyP2wo8N6e/D+y6?= =?utf-8?q?CaK1U3SGhxZXBBl/8B9eTW95zNC8RxnVy3x0WUa1WEfty2miq2AdQrboIaHM1smGp?= =?utf-8?q?01cdycu22S6y8CoX+LmBpcWBxjg9ff53E35co1uDLWlZzLSpk+dA6qoRU+fRWQOrX?= =?utf-8?q?klt9jMZ0IKD0ek1HMcq846XIYgEG5TzCxt/eySi9AaDGFKzpgI0OyjpEMjFG4HxAj?= =?utf-8?q?oYnGr7UL9a7I4ASpafUHbHJZ1YbdSe+u+vlWSDNg/yVDVCRIZ7GrH2kX/VnBNdDF7?= =?utf-8?q?VPjlGhUw0kA0nxoqb5WE51HpJ1JECpPyb4mUJpU5MWw1zsQc75+dfYnjFPc/kZBD4?= =?utf-8?q?hNTvEm62pt1abw/QJC2a0gWacBFdMIM1ogMerb2l4md3YlzMocmcMABirxuMso7fY?= =?utf-8?q?1MivQzxuZ+T59HPU5e8aUstptzIWLSyGXel5e6wP3sAYL8PbYunqe6FUY3XQow5rB?= =?utf-8?q?lgSpeCXkMquXyZlbDEwDIPhIy0ZJDVLg=3D=3D?= X-Forefront-Antispam-Report: CIP:165.204.84.17;CTRY:US;LANG:en;SCL:1;SRV:;IPV:CAL;SFV:NSPM;H:SATLEXMB04.amd.com;PTR:InfoDomainNonexistent;CAT:NONE;SFS:(13230040)(36860700013)(82310400026)(376014)(1800799024)(13003099007)(7053199007);DIR:OUT;SFP:1101; X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 15 Apr 2025 14:55:13.6698 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: f77c4f6b-a147-47bd-5cc6-08dd7c2d8708 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: CH2PEPF0000014A.namprd02.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DS7PR12MB5909 The MCx_MISC0[BlkPtr] field was used on legacy systems to hold a register offset for the next MCx_MISC* register. In this way, an implementation-specific number of registers can be discovered at runtime. The MCAX/SMCA register space simplifies this by always including the MCx_MISC[1-4] registers. The MCx_MISC0[BlkPtr] field is used to indicate (true/false) whether any MCx_MISC[1-4] registers are present. But it indicates neither which ones nor how many. Therefore, all the registers are accessed and their bits are checked. AMD systems generally enforce a Read-as-Zero/Writes-Ignored policy for unused registers. Therefore, there is no harm to read an unused register. This is already done in practice for most of the MCx_MISC registers. Remove the smca_banks_map variable as it is effectively redundant. Reviewed-by: Qiuxu Zhuo Tested-by: Tony Luck Reviewed-by: Tony Luck Signed-off-by: Yazen Ghannam --- Notes: Link: https://lore.kernel.org/r/20250213-wip-mca-updates-v2-3-3636547fe05f@amd.com v2->v3: * Minor edit in commit message. * Added tags from Qiuxu and Tony. v1->v2: * New in v2. arch/x86/kernel/cpu/mce/amd.c | 30 ------------------------------ 1 file changed, 30 deletions(-) diff --git a/arch/x86/kernel/cpu/mce/amd.c b/arch/x86/kernel/cpu/mce/amd.c index 7ff479c679fb..46ff41c1b50d 100644 --- a/arch/x86/kernel/cpu/mce/amd.c +++ b/arch/x86/kernel/cpu/mce/amd.c @@ -252,9 +252,6 @@ static DEFINE_PER_CPU(struct threshold_bank **, threshold_banks); */ static DEFINE_PER_CPU(u64, bank_map); -/* Map of banks that have more than MCA_MISC0 available. */ -static DEFINE_PER_CPU(u64, smca_misc_banks_map); - static void amd_threshold_interrupt(void); static void amd_deferred_error_interrupt(void); @@ -264,28 +261,6 @@ static void default_deferred_error_interrupt(void) } void (*deferred_error_int_vector)(void) = default_deferred_error_interrupt; -static void smca_set_misc_banks_map(unsigned int bank, unsigned int cpu) -{ - u32 low, high; - - /* - * For SMCA enabled processors, BLKPTR field of the first MISC register - * (MCx_MISC0) indicates presence of additional MISC regs set (MISC1-4). - */ - if (rdmsr_safe(MSR_AMD64_SMCA_MCx_CONFIG(bank), &low, &high)) - return; - - if (!(low & MCI_CONFIG_MCAX)) - return; - - if (rdmsr_safe(MSR_AMD64_SMCA_MCx_MISC(bank), &low, &high)) - return; - - if (low & MASK_BLKPTR_LO) - per_cpu(smca_misc_banks_map, cpu) |= BIT_ULL(bank); - -} - static void smca_configure(unsigned int bank, unsigned int cpu) { u8 *bank_counts = this_cpu_ptr(smca_bank_counts); @@ -326,8 +301,6 @@ static void smca_configure(unsigned int bank, unsigned int cpu) wrmsr(smca_config, low, high); } - smca_set_misc_banks_map(bank, cpu); - if (rdmsr_safe(MSR_AMD64_SMCA_MCx_IPID(bank), &low, &high)) { pr_warn("Failed to read MCA_IPID for bank %d\n", bank); return; @@ -532,9 +505,6 @@ static u32 smca_get_block_address(unsigned int bank, unsigned int block, if (!block) return MSR_AMD64_SMCA_MCx_MISC(bank); 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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 15 Apr 2025 14:55:14.0604 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: f6176b4b-fd01-4612-f78c-08dd7c2d8743 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: CH2PEPF0000014A.namprd02.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: MN0PR12MB5953 The threshold_bank structure is a container for one or more threshold_block structures. Currently, the container has a single pointer to the 'first' threshold_block structure which then has a linked list of the remaining threshold_block structures. This results in an extra level of indirection where the 'first' block is checked before iterating over the remaining blocks. Remove the indirection by including the head of the block list in the threshold_bank structure which already acts as a container for all the bank's thresholding blocks. Reviewed-by: Qiuxu Zhuo Tested-by: Tony Luck Reviewed-by: Tony Luck Signed-off-by: Yazen Ghannam --- Notes: Link: https://lore.kernel.org/r/20250213-wip-mca-updates-v2-4-3636547fe05f@amd.com v2->v3: * Added tags from Qiuxu and Tony. v1->v2: * New in v2. arch/x86/kernel/cpu/mce/amd.c | 43 ++++++++++++------------------------------- 1 file changed, 12 insertions(+), 31 deletions(-) diff --git a/arch/x86/kernel/cpu/mce/amd.c b/arch/x86/kernel/cpu/mce/amd.c index 46ff41c1b50d..8e5a07f78346 100644 --- a/arch/x86/kernel/cpu/mce/amd.c +++ b/arch/x86/kernel/cpu/mce/amd.c @@ -241,7 +241,8 @@ struct threshold_block { struct threshold_bank { struct kobject *kobj; - struct threshold_block *blocks; + /* List of threshold blocks within this MCA bank. */ + struct list_head miscj; }; static DEFINE_PER_CPU(struct threshold_bank **, threshold_banks); @@ -901,9 +902,9 @@ static void log_and_reset_block(struct threshold_block *block) */ static void amd_threshold_interrupt(void) { - struct threshold_block *first_block = NULL, *block = NULL, *tmp = NULL; - struct threshold_bank **bp = this_cpu_read(threshold_banks); + struct threshold_bank **bp = this_cpu_read(threshold_banks), *thr_bank; unsigned int bank, cpu = smp_processor_id(); + struct threshold_block *block, *tmp; /* * Validate that the threshold bank has been initialized already. The @@ -917,16 +918,11 @@ static void amd_threshold_interrupt(void) if (!(per_cpu(bank_map, cpu) & BIT_ULL(bank))) continue; - first_block = bp[bank]->blocks; - if (!first_block) + thr_bank = bp[bank]; + if (!thr_bank) continue; - /* - * The first block is also the head of the list. Check it first - * before iterating over the rest. - */ - log_and_reset_block(first_block); - list_for_each_entry_safe(block, tmp, &first_block->miscj, miscj) + list_for_each_entry_safe(block, tmp, &thr_bank->miscj, miscj) log_and_reset_block(block); } } @@ -1145,13 +1141,7 @@ static int allocate_threshold_blocks(unsigned int cpu, struct threshold_bank *tb default_attrs[2] = NULL; } - INIT_LIST_HEAD(&b->miscj); - - /* This is safe as @tb is not visible yet */ - if (tb->blocks) - list_add(&b->miscj, &tb->blocks->miscj); - else - tb->blocks = b; + list_add(&b->miscj, &tb->miscj); err = kobject_init_and_add(&b->kobj, &threshold_ktype, tb->kobj, get_name(cpu, bank, b)); if (err) @@ -1202,6 +1192,8 @@ static int threshold_create_bank(struct threshold_bank **bp, unsigned int cpu, goto out_free; } + INIT_LIST_HEAD(&b->miscj); + err = allocate_threshold_blocks(cpu, b, bank, 0, mca_msr_reg(bank, MCA_MISC)); if (err) goto out_kobj; @@ -1222,26 +1214,15 @@ static void threshold_block_release(struct kobject *kobj) kfree(to_block(kobj)); } -static void deallocate_threshold_blocks(struct threshold_bank *bank) +static void threshold_remove_bank(struct threshold_bank *bank) { struct threshold_block *pos, *tmp; - list_for_each_entry_safe(pos, tmp, &bank->blocks->miscj, miscj) { + list_for_each_entry_safe(pos, tmp, &bank->miscj, miscj) { list_del(&pos->miscj); kobject_put(&pos->kobj); } - kobject_put(&bank->blocks->kobj); -} - -static void threshold_remove_bank(struct threshold_bank *bank) -{ - if (!bank->blocks) - goto out_free; - - deallocate_threshold_blocks(bank); - -out_free: kobject_put(bank->kobj); kfree(bank); } From patchwork Tue Apr 15 14:55:00 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Yazen Ghannam X-Patchwork-Id: 14052363 Received: from NAM11-CO1-obe.outbound.protection.outlook.com (mail-co1nam11on2078.outbound.protection.outlook.com [40.107.220.78]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id AC11229B77A; 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Tue, 15 Apr 2025 09:55:13 -0500 From: Yazen Ghannam Date: Tue, 15 Apr 2025 14:55:00 +0000 Subject: [PATCH v3 05/17] x86/mce: Cleanup bank processing on init Precedence: bulk X-Mailing-List: linux-edac@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-ID: <20250415-wip-mca-updates-v3-5-8ffd9eb4aa56@amd.com> References: <20250415-wip-mca-updates-v3-0-8ffd9eb4aa56@amd.com> In-Reply-To: <20250415-wip-mca-updates-v3-0-8ffd9eb4aa56@amd.com> To: , Tony Luck CC: , , , Qiuxu Zhuo X-Mailer: b4 0.15-dev-9b767 X-ClientProxiedBy: SATLEXMB03.amd.com (10.181.40.144) To SATLEXMB04.amd.com (10.181.40.145) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: CH2PEPF0000014A:EE_|LV3PR12MB9329:EE_ X-MS-Office365-Filtering-Correlation-Id: 346f6a5d-d486-4140-6a25-08dd7c2d8797 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|36860700013|82310400026|376014|1800799024|7053199007; X-Microsoft-Antispam-Message-Info: =?utf-8?q?cPQcf0laBOY+EKR4EPnberycIFiWNfn?= =?utf-8?q?zutJRqiXXDFeQDpmcKXnBDYkfkX3/X4UrGma7RicCttomfWuNSR4qq+AqEG0xjWXq?= =?utf-8?q?noWQzRNbNuB3ShFmosdlwdmrfUaL3KHFMY3VPgieIVf/plqGECSLi6QsnExSKk7/W?= =?utf-8?q?dzeJ/22boF13sSHTmuREidNG4nHqHwExfr7sGW5nuaLGvnkj2SbSIEkLqB9VVqKYx?= =?utf-8?q?G9D8XhoHnS0utAtS7U9gqpIIO8SxwZknggxUl5mlvGK7eiWdQVhP+VJpE4s0L76PB?= =?utf-8?q?OFc9iYWmCMqvSlaG2TrGLKubTHGpnMaUyKk4oqkAF3O1nfTou8ZS1y+mjBhe6DADt?= =?utf-8?q?NNZ3BNqvaTgPz08KyvO79wRVEXeQjvvgUepv+xOSOVxSfMq9f4MnyxBW6TjoKAwdm?= =?utf-8?q?v221AKidkXuhsFCLqACb++EGWh3PsudQsq2wJZZ5LyOUfcd3Z16s4U20sxE6habI7?= =?utf-8?q?EOhFWeTBBs9nSdZAZm0CpXmb0eTvpfm0HrQOCr9E8gx/gwqsFJd6H4BO/zNZZ8N3z?= =?utf-8?q?FUuZu0IJaO2L0d0Y4g3/MUq2ctGdql+4mrQbmjkkc/K3H9I9/Ih/e2Ohc5cxhUsZ3?= =?utf-8?q?XEicqjFkASBbTihfVFdSXN66azbz4SDrbgqmfoPHTi/V7+bjwj9gR+Re3pByZpPNl?= =?utf-8?q?liycLEsX6rk8VQ+KS8LoYuMPnL+uz3DynWbIaE2mTdu0FRBbtESeQe6ha39Y3lsol?= =?utf-8?q?4EUepsmU8Sho5JLygvc/ytz4UzzGc9evbhba9hCv5nSrR4FhWkFqed0abPYxpZIu5?= =?utf-8?q?EX1sHe/4wG9aktm4sXoQxc+6D+7UKFrWvjkaFpawu/bmAkZw0j4nwBl5C5dN5KlLO?= =?utf-8?q?J5/J96vVVYcAe3cH108NKa9bBO225cxhowu7DUFlOCjClqQwd30Gl0HyoUlEhr5DH?= =?utf-8?q?xheGS4IJaRF6WHOfjZF8fMV21myJozucO+ThWJG6r+FKhVlIoRvYFLrTDAoiVJHP2?= =?utf-8?q?bU0yofdbq/tVPawyayWS+g9YeVp5Dzu9zRreiwxSNMfascsK0RmyL0u0JQllx36K7?= =?utf-8?q?7vFAY4b2E13WNXXFh6Lyj38yrPlibWMl3aj6BK3z3QJhy6jMyV4aYe0vIZUNjcZxc?= =?utf-8?q?On7mILvF43AwkTFOgYZMdJLDV4Pg90k1ozcu7zLs+Tnu0ZC01LmkY077fBUn1MuL0?= =?utf-8?q?6c5fPiRefy1Jsy/LFYhcGvBexzmLSm9X6UXHCb/WmH6cgURjD09LvPGxc/gWpuv5X?= =?utf-8?q?FVjd1Up4gl69FZARCcxbZdjLWKsIdtbrdOs51+yCDCC32npFQwzRviv7qhzKBf1Hd?= =?utf-8?q?YRIeXa9vP222/iTeISR/+FezEEfFhc8/Utmyio3ASIdSMIPtsRfJoD/mCbU9kbxo4?= =?utf-8?q?NO1cWIf8bmWicD7VhNFWWUhYuCQaG++pRcp9jU0wVfNugPyz9c+7fX8TPdbRO+P+N?= =?utf-8?q?+GKVMUl7eQzM6h17ptZQU8UO+AM/mUpqNEYDCJntSSw2fyv+lXtTrpUrOQa6u5fb5?= =?utf-8?q?3ZzwVHc5t31Z+HJNdHnBXsQC0zT93x7Q=3D=3D?= X-Forefront-Antispam-Report: CIP:165.204.84.17;CTRY:US;LANG:en;SCL:1;SRV:;IPV:CAL;SFV:NSPM;H:SATLEXMB04.amd.com;PTR:InfoDomainNonexistent;CAT:NONE;SFS:(13230040)(36860700013)(82310400026)(376014)(1800799024)(7053199007);DIR:OUT;SFP:1101; X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 15 Apr 2025 14:55:14.6073 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 346f6a5d-d486-4140-6a25-08dd7c2d8797 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: CH2PEPF0000014A.namprd02.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: LV3PR12MB9329 From: Borislav Petkov Unify the bank preparation into __mcheck_cpu_init_clear_banks(), rename that function to what it does now - prepares banks. Do this so that generic and vendor banks init goes first so that settings done during that init can take effect before the first bank polling takes place. Move __mcheck_cpu_check_banks() into __mcheck_cpu_init_prepare_banks() as it already loops over the banks. The MCP_DONTLOG flag is no longer needed, since the MCA polling function is now called only if boot-time logging should be done. Signed-off-by: Borislav Petkov Reviewed-by: Yazen Ghannam Reviewed-by: Qiuxu Zhuo Tested-by: Tony Luck Reviewed-by: Tony Luck --- Notes: Link: https://lore.kernel.org/r/20250213-wip-mca-updates-v2-5-3636547fe05f@amd.com v2->v3: * Update commit message. * Add tags from Qiuxu and Tony. v1->v2: * New in v2, but based on old patch (see link). * Kept old tags for reference. arch/x86/include/asm/mce.h | 3 +- arch/x86/kernel/cpu/mce/core.c | 63 ++++++++++++------------------------------ 2 files changed, 19 insertions(+), 47 deletions(-) diff --git a/arch/x86/include/asm/mce.h b/arch/x86/include/asm/mce.h index 752802bf966b..3224f3862dc8 100644 --- a/arch/x86/include/asm/mce.h +++ b/arch/x86/include/asm/mce.h @@ -290,8 +290,7 @@ DECLARE_PER_CPU(mce_banks_t, mce_poll_banks); enum mcp_flags { MCP_TIMESTAMP = BIT(0), /* log time stamp */ MCP_UC = BIT(1), /* log uncorrected errors */ - MCP_DONTLOG = BIT(2), /* only clear, don't log */ - MCP_QUEUE_LOG = BIT(3), /* only queue to genpool */ + MCP_QUEUE_LOG = BIT(2), /* only queue to genpool */ }; void machine_check_poll(enum mcp_flags flags, mce_banks_t *b); diff --git a/arch/x86/kernel/cpu/mce/core.c b/arch/x86/kernel/cpu/mce/core.c index 72c2aa0809c0..ee801f8862d8 100644 --- a/arch/x86/kernel/cpu/mce/core.c +++ b/arch/x86/kernel/cpu/mce/core.c @@ -807,9 +807,6 @@ void machine_check_poll(enum mcp_flags flags, mce_banks_t *b) continue; log_it: - if (flags & MCP_DONTLOG) - goto clear_it; - mce_read_aux(&err, i); m->severity = mce_severity(m, NULL, NULL, false); /* @@ -1807,7 +1804,7 @@ static void __mcheck_cpu_mce_banks_init(void) /* * Init them all, __mcheck_cpu_apply_quirks() is going to apply * the required vendor quirks before - * __mcheck_cpu_init_clear_banks() does the final bank setup. + * __mcheck_cpu_init_prepare_banks() does the final bank setup. */ b->ctl = -1ULL; b->init = true; @@ -1846,21 +1843,8 @@ static void __mcheck_cpu_cap_init(void) static void __mcheck_cpu_init_generic(void) { - enum mcp_flags m_fl = 0; - mce_banks_t all_banks; u64 cap; - if (!mca_cfg.bootlog) - m_fl = MCP_DONTLOG; - - /* - * Log the machine checks left over from the previous reset. Log them - * only, do not start processing them. That will happen in mcheck_late_init() - * when all consumers have been registered on the notifier chain. - */ - bitmap_fill(all_banks, MAX_NR_BANKS); - machine_check_poll(MCP_UC | MCP_QUEUE_LOG | m_fl, &all_banks); - cr4_set_bits(X86_CR4_MCE); rdmsrq(MSR_IA32_MCG_CAP, cap); @@ -1868,36 +1852,23 @@ static void __mcheck_cpu_init_generic(void) wrmsr(MSR_IA32_MCG_CTL, 0xffffffff, 0xffffffff); } -static void __mcheck_cpu_init_clear_banks(void) +static void __mcheck_cpu_init_prepare_banks(void) { struct mce_bank *mce_banks = this_cpu_ptr(mce_banks_array); + u64 msrval; int i; - for (i = 0; i < this_cpu_read(mce_num_banks); i++) { - struct mce_bank *b = &mce_banks[i]; + /* + * Log the machine checks left over from the previous reset. Log them + * only, do not start processing them. That will happen in mcheck_late_init() + * when all consumers have been registered on the notifier chain. + */ + if (mca_cfg.bootlog) { + mce_banks_t all_banks; - if (!b->init) - continue; - wrmsrq(mca_msr_reg(i, MCA_CTL), b->ctl); - wrmsrq(mca_msr_reg(i, MCA_STATUS), 0); + bitmap_fill(all_banks, MAX_NR_BANKS); + machine_check_poll(MCP_UC | MCP_QUEUE_LOG, &all_banks); } -} - -/* - * Do a final check to see if there are any unused/RAZ banks. - * - * This must be done after the banks have been initialized and any quirks have - * been applied. - * - * Do not call this from any user-initiated flows, e.g. CPU hotplug or sysfs. - * Otherwise, a user who disables a bank will not be able to re-enable it - * without a system reboot. - */ -static void __mcheck_cpu_check_banks(void) -{ - struct mce_bank *mce_banks = this_cpu_ptr(mce_banks_array); - u64 msrval; - int i; for (i = 0; i < this_cpu_read(mce_num_banks); i++) { struct mce_bank *b = &mce_banks[i]; @@ -1905,6 +1876,9 @@ static void __mcheck_cpu_check_banks(void) if (!b->init) continue; + wrmsrq(mca_msr_reg(i, MCA_CTL), b->ctl); + wrmsrq(mca_msr_reg(i, MCA_STATUS), 0); + rdmsrq(mca_msr_reg(i, MCA_CTL), msrval); b->init = !!msrval; } @@ -2310,8 +2284,7 @@ void mcheck_cpu_init(struct cpuinfo_x86 *c) __mcheck_cpu_init_early(c); __mcheck_cpu_init_generic(); __mcheck_cpu_init_vendor(c); - __mcheck_cpu_init_clear_banks(); - __mcheck_cpu_check_banks(); + __mcheck_cpu_init_prepare_banks(); __mcheck_cpu_setup_timer(); } @@ -2479,7 +2452,7 @@ static void mce_syscore_resume(void) { __mcheck_cpu_init_generic(); __mcheck_cpu_init_vendor(raw_cpu_ptr(&cpu_info)); - __mcheck_cpu_init_clear_banks(); + __mcheck_cpu_init_prepare_banks(); } static struct syscore_ops mce_syscore_ops = { @@ -2497,7 +2470,7 @@ static void mce_cpu_restart(void *data) if (!mce_available(raw_cpu_ptr(&cpu_info))) return; __mcheck_cpu_init_generic(); - __mcheck_cpu_init_clear_banks(); + __mcheck_cpu_init_prepare_banks(); __mcheck_cpu_init_timer(); } From patchwork Tue Apr 15 14:55:01 2025 Content-Type: text/plain; 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client-ip=165.204.84.17; helo=SATLEXMB04.amd.com; pr=C Received: from SATLEXMB04.amd.com (165.204.84.17) by CH2PEPF0000014A.mail.protection.outlook.com (10.167.244.107) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.20.8655.12 via Frontend Transport; Tue, 15 Apr 2025 14:55:15 +0000 Received: from [127.0.1.1] (10.180.168.240) by SATLEXMB04.amd.com (10.181.40.145) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.39; Tue, 15 Apr 2025 09:55:13 -0500 From: Yazen Ghannam Date: Tue, 15 Apr 2025 14:55:01 +0000 Subject: [PATCH v3 06/17] x86/mce: Remove __mcheck_cpu_init_early() Precedence: bulk X-Mailing-List: linux-edac@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-ID: <20250415-wip-mca-updates-v3-6-8ffd9eb4aa56@amd.com> References: <20250415-wip-mca-updates-v3-0-8ffd9eb4aa56@amd.com> In-Reply-To: <20250415-wip-mca-updates-v3-0-8ffd9eb4aa56@amd.com> To: , Tony Luck CC: , , , Qiuxu Zhuo X-Mailer: b4 0.15-dev-9b767 X-ClientProxiedBy: SATLEXMB03.amd.com (10.181.40.144) To SATLEXMB04.amd.com (10.181.40.145) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: CH2PEPF0000014A:EE_|SJ2PR12MB8064:EE_ X-MS-Office365-Filtering-Correlation-Id: 500c4625-3f43-4a95-3dd7-08dd7c2d880c X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|376014|1800799024|82310400026|36860700013|13003099007|7053199007; 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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 15 Apr 2025 14:55:15.3104 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 500c4625-3f43-4a95-3dd7-08dd7c2d880c X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: CH2PEPF0000014A.namprd02.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: SJ2PR12MB8064 The __mcheck_cpu_init_early() function was introduced so that some vendor-specific features are detected before the first MCA polling event done in __mcheck_cpu_init_generic(). Currently, __mcheck_cpu_init_early() is only used on AMD-based systems and additional code will be needed to support various system configurations. However, the current and future vendor-specific code should be done during vendor init. This keeps all the vendor code in a common location and simplifies the generic init flow. Move all the __mcheck_cpu_init_early() code into mce_amd_feature_init(). Also, move __mcheck_cpu_init_generic() after __mcheck_cpu_init_prepare_banks() so that MCA is enabled after the first MCA polling event. Additionally, this brings the MCA init flow closer to what is described in the x86 docs. The AMD PPRs say "The operating system must initialize the MCA_CONFIG registers prior to initialization of the MCA_CTL registers. The MCA_CTL registers must be initialized prior to enabling the error reporting banks in MCG_CTL". However, the Intel SDM "Machine-Check Initialization Pseudocode" says MCG_CTL first then MCi_CTL. But both agree that CR4.MCE should be set last. Reviewed-by: Qiuxu Zhuo Tested-by: Tony Luck Reviewed-by: Tony Luck Signed-off-by: Yazen Ghannam --- Notes: Link: https://lore.kernel.org/r/20250213-wip-mca-updates-v2-6-3636547fe05f@amd.com v2->v3: * Update commit message. * Add tags from Qiuxu and Tony. v1->v2: * New in v2, but based on old patch (see link). * Changed cpu_has() to cpu_feature_enabled(). arch/x86/kernel/cpu/mce/amd.c | 4 ++++ arch/x86/kernel/cpu/mce/core.c | 20 +++----------------- 2 files changed, 7 insertions(+), 17 deletions(-) diff --git a/arch/x86/kernel/cpu/mce/amd.c b/arch/x86/kernel/cpu/mce/amd.c index 8e5a07f78346..aa23139a3092 100644 --- a/arch/x86/kernel/cpu/mce/amd.c +++ b/arch/x86/kernel/cpu/mce/amd.c @@ -656,6 +656,10 @@ void mce_amd_feature_init(struct cpuinfo_x86 *c) u32 low = 0, high = 0, address = 0; int offset = -1; + mce_flags.overflow_recov = cpu_feature_enabled(X86_FEATURE_OVERFLOW_RECOV); + mce_flags.succor = cpu_feature_enabled(X86_FEATURE_SUCCOR); + mce_flags.smca = cpu_feature_enabled(X86_FEATURE_SMCA); + mce_flags.amd_threshold = 1; for (bank = 0; bank < this_cpu_read(mce_num_banks); ++bank) { if (mce_flags.smca) diff --git a/arch/x86/kernel/cpu/mce/core.c b/arch/x86/kernel/cpu/mce/core.c index ee801f8862d8..331cd8984395 100644 --- a/arch/x86/kernel/cpu/mce/core.c +++ b/arch/x86/kernel/cpu/mce/core.c @@ -2029,19 +2029,6 @@ static bool __mcheck_cpu_ancient_init(struct cpuinfo_x86 *c) return false; } -/* - * Init basic CPU features needed for early decoding of MCEs. - */ -static void __mcheck_cpu_init_early(struct cpuinfo_x86 *c) -{ - if (c->x86_vendor == X86_VENDOR_AMD || c->x86_vendor == X86_VENDOR_HYGON) { - mce_flags.overflow_recov = !!cpu_has(c, X86_FEATURE_OVERFLOW_RECOV); - mce_flags.succor = !!cpu_has(c, X86_FEATURE_SUCCOR); - mce_flags.smca = !!cpu_has(c, X86_FEATURE_SMCA); - mce_flags.amd_threshold = 1; - } -} - static void mce_centaur_feature_init(struct cpuinfo_x86 *c) { struct mca_config *cfg = &mca_cfg; @@ -2281,10 +2268,9 @@ void mcheck_cpu_init(struct cpuinfo_x86 *c) mca_cfg.initialized = 1; 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Tue, 15 Apr 2025 09:55:14 -0500 From: Yazen Ghannam Date: Tue, 15 Apr 2025 14:55:02 +0000 Subject: [PATCH v3 07/17] x86/mce: Define BSP-only init Precedence: bulk X-Mailing-List: linux-edac@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-ID: <20250415-wip-mca-updates-v3-7-8ffd9eb4aa56@amd.com> References: <20250415-wip-mca-updates-v3-0-8ffd9eb4aa56@amd.com> In-Reply-To: <20250415-wip-mca-updates-v3-0-8ffd9eb4aa56@amd.com> To: , Tony Luck CC: , , , Qiuxu Zhuo X-Mailer: b4 0.15-dev-9b767 X-ClientProxiedBy: SATLEXMB03.amd.com (10.181.40.144) To SATLEXMB04.amd.com (10.181.40.145) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: CH2PEPF0000014A:EE_|DS0PR12MB8416:EE_ X-MS-Office365-Filtering-Correlation-Id: aa52ca7e-d5ef-46d6-fd49-08dd7c2d888c X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|376014|1800799024|82310400026|36860700013|7053199007; X-Microsoft-Antispam-Message-Info: =?utf-8?q?tbnBMaOkGZqgw1MeIppPdan+pe7zXEA?= =?utf-8?q?eum3XpTIh4koQqlrkF1aVqrakzIj8HtR0WU3gyK7bFYiOERmy+XZyg2Q0x95PvCQM?= =?utf-8?q?03hxKSflRSqDeL5GQ3ZheJKu0cxJKLqPOjE06XJ+aSE6NnZYnad40zn7d4lcE+9Uj?= =?utf-8?q?T/sYD4VJiFnXIOJHQ9BTFTEqDnn5KRjFlhBs2uFzNzhp7+GyCrFg3t8kfEOlWSS7l?= =?utf-8?q?V511Gapuu9FxzjoSGiVnL9BWcBIWr9QqPipDeLwp+/mTNtYBRKe0Xx8Ho09kMolkh?= =?utf-8?q?aJVLLGemhejB9IZqFaSbJBhzvPl2al7AgQf42rSaqgz3wmNHfAN3PDA00GuV1qLnx?= =?utf-8?q?9JaLauFin8eM+RNaBQyJcqyR3BYa95aGaBLVYKtKuigXnkX6YD4KbY129ScGr9D71?= =?utf-8?q?MiSVwoz2/nqyv4nQI+REAPmIyht3Mp3Emknp/zclAmex1XGQIMpchRAo1cgfJJAeD?= =?utf-8?q?T8JuwQjxRanu9i3VwI1pknxB7HH8tWsgKlnelQ4lmLSp6yPQ7VJ4HnqOZ4o0N/I3h?= =?utf-8?q?D/mp6s5Gr2yAjFARisNGtyZ7bfqQI2N3FHwmZuUcMErZkIewP+dvQzifBrxXhWiNV?= =?utf-8?q?WDdBUTBJOfu+NNmZRHscQ/sCiBWfr87hTE4ZIbLFRt0r65A3Av2Tr8WGKjSH6T2Vk?= =?utf-8?q?S9Sd5xvhEwq+8Fh8BlIJXmFANNLWu6QCpE+7Yk022imMDixhltKjAmL9YqV0JW/cy?= =?utf-8?q?fqVpQDQXX8MybHhyd/RaPIPoTQg5N0C8y3bjUqNQmO9VMnSFz1gHeXyf2ReoOnKVB?= =?utf-8?q?KceMtbxAfMSi5SNMkAtL5ykotg9QWbyvnmYyI5g1P/vyVvOHaHUKYRX/J5AQuGZhW?= =?utf-8?q?fT9ZBV888FzKLmKdJVIZlNIuz5J1ms1CnzZRTec6BpaGGe4+qkbKNnFGFoUSdkZ/S?= =?utf-8?q?GgQ/Xmneim73u7IhgCwpD+tnclu0DX7cZ2K02nuVp3mkEbJT+opn3cXEUdycZbDKk?= =?utf-8?q?yE5a2cm/dcpcwBh0rt/Ia430rt0yN/kbKMOxPaBIsnTigDOh0Sifb1nCxZzEoqvg0?= =?utf-8?q?Fa3IKv8UtEZC8vUeILv3sWgSOVC33tTGycrycfQbIuLAAL/VZ3qrXnn2U/56cp85d?= =?utf-8?q?lY1O2xKVX/e6v9AVHzaHn2nP19d6BtM4vTQPQYhFh5jUo11hpSr7ji+pfMROcesAV?= =?utf-8?q?NbKIocaBFvE6FiotkhnZYxToxemsF1Fdzp32TpI+p7b9PCD9LuhZZBXLglZaW2R0s?= =?utf-8?q?l9iLG0BRhiL9o7kxjxOu5iVmZY1JLrXnMM0aC8KgGeS8OmFb/pXBUDPmwdkfA3eBz?= =?utf-8?q?GyagRMy8IzQ6VitdeOTU6aX+SrCTCo8Qbl87g/sfgirJE+PpN07/1+FsZXqYgT5Bf?= =?utf-8?q?6C/RVi1mWpQUASGmWEd0RpuJkl69uvoyK6SK3/2KRK6ccPfvfEr3j39uuFVW0csW6?= =?utf-8?q?MEZRjD2PkMQdLAe7fdKxrKibjd8qYciXywLpLy/JW3eBdZwTCjZmYde8UpxkLfQdw?= =?utf-8?q?ixgxocNBG0?= X-Forefront-Antispam-Report: CIP:165.204.84.17;CTRY:US;LANG:en;SCL:1;SRV:;IPV:CAL;SFV:NSPM;H:SATLEXMB04.amd.com;PTR:InfoDomainNonexistent;CAT:NONE;SFS:(13230040)(376014)(1800799024)(82310400026)(36860700013)(7053199007);DIR:OUT;SFP:1101; X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 15 Apr 2025 14:55:16.2167 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: aa52ca7e-d5ef-46d6-fd49-08dd7c2d888c X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: CH2PEPF0000014A.namprd02.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DS0PR12MB8416 Currently, MCA initialization is executed identically on each CPU as they are brought online. However, a number of MCA initialization tasks only need to be done once. Define a function to collect all 'global' init tasks and call this from the BSP only. Start with CPU features. Reviewed-by: Qiuxu Zhuo Tested-by: Tony Luck Reviewed-by: Tony Luck Signed-off-by: Yazen Ghannam --- Notes: Link: https://lore.kernel.org/r/20250213-wip-mca-updates-v2-7-3636547fe05f@amd.com v2->v3: * Add tags from Qiuxu and Tony. v1->v2: * New in v2. arch/x86/include/asm/mce.h | 2 ++ arch/x86/kernel/cpu/common.c | 1 + arch/x86/kernel/cpu/mce/amd.c | 3 --- arch/x86/kernel/cpu/mce/core.c | 29 ++++++++++++++++++++++------- 4 files changed, 25 insertions(+), 10 deletions(-) diff --git a/arch/x86/include/asm/mce.h b/arch/x86/include/asm/mce.h index 3224f3862dc8..0108f69ec46a 100644 --- a/arch/x86/include/asm/mce.h +++ b/arch/x86/include/asm/mce.h @@ -241,12 +241,14 @@ struct cper_ia_proc_ctx; #ifdef CONFIG_X86_MCE int mcheck_init(void); +void cpu_mca_init(struct cpuinfo_x86 *c); void mcheck_cpu_init(struct cpuinfo_x86 *c); void mcheck_cpu_clear(struct cpuinfo_x86 *c); int apei_smca_report_x86_error(struct cper_ia_proc_ctx *ctx_info, u64 lapic_id); #else static inline int mcheck_init(void) { return 0; } +static inline void cpu_mca_init(struct cpuinfo_x86 *c) {} static inline void mcheck_cpu_init(struct cpuinfo_x86 *c) {} static inline void mcheck_cpu_clear(struct cpuinfo_x86 *c) {} static inline int apei_smca_report_x86_error(struct cper_ia_proc_ctx *ctx_info, diff --git a/arch/x86/kernel/cpu/common.c b/arch/x86/kernel/cpu/common.c index 079ded4eeb86..8e3e51281f12 100644 --- a/arch/x86/kernel/cpu/common.c +++ b/arch/x86/kernel/cpu/common.c @@ -1690,6 +1690,7 @@ static void __init early_identify_cpu(struct cpuinfo_x86 *c) setup_clear_cpu_cap(X86_FEATURE_LA57); detect_nopl(); + cpu_mca_init(c); } void __init init_cpu_devs(void) diff --git a/arch/x86/kernel/cpu/mce/amd.c b/arch/x86/kernel/cpu/mce/amd.c index aa23139a3092..206973d7dbcc 100644 --- a/arch/x86/kernel/cpu/mce/amd.c +++ b/arch/x86/kernel/cpu/mce/amd.c @@ -656,9 +656,6 @@ void mce_amd_feature_init(struct cpuinfo_x86 *c) u32 low = 0, high = 0, address = 0; int offset = -1; - mce_flags.overflow_recov = cpu_feature_enabled(X86_FEATURE_OVERFLOW_RECOV); - mce_flags.succor = cpu_feature_enabled(X86_FEATURE_SUCCOR); - mce_flags.smca = cpu_feature_enabled(X86_FEATURE_SMCA); mce_flags.amd_threshold = 1; for (bank = 0; bank < this_cpu_read(mce_num_banks); ++bank) { diff --git a/arch/x86/kernel/cpu/mce/core.c b/arch/x86/kernel/cpu/mce/core.c index 331cd8984395..d0a29e22cab0 100644 --- a/arch/x86/kernel/cpu/mce/core.c +++ b/arch/x86/kernel/cpu/mce/core.c @@ -1832,13 +1832,6 @@ static void __mcheck_cpu_cap_init(void) this_cpu_write(mce_num_banks, b); __mcheck_cpu_mce_banks_init(); - - /* Use accurate RIP reporting if available. */ - if ((cap & MCG_EXT_P) && MCG_EXT_CNT(cap) >= 9) - mca_cfg.rip_msr = MSR_IA32_MCG_EIP; - - if (cap & MCG_SER_P) - mca_cfg.ser = 1; } static void __mcheck_cpu_init_generic(void) @@ -2238,6 +2231,28 @@ DEFINE_IDTENTRY_RAW(exc_machine_check) } #endif +/* Called only on the boot CPU. */ +void cpu_mca_init(struct cpuinfo_x86 *c) +{ + u64 cap; + + if (!mce_available(c)) + return; + + mce_flags.overflow_recov = cpu_feature_enabled(X86_FEATURE_OVERFLOW_RECOV); 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Tue, 15 Apr 2025 09:55:14 -0500 From: Yazen Ghannam Date: Tue, 15 Apr 2025 14:55:03 +0000 Subject: [PATCH v3 08/17] x86/mce: Define BSP-only SMCA init Precedence: bulk X-Mailing-List: linux-edac@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-ID: <20250415-wip-mca-updates-v3-8-8ffd9eb4aa56@amd.com> References: <20250415-wip-mca-updates-v3-0-8ffd9eb4aa56@amd.com> In-Reply-To: <20250415-wip-mca-updates-v3-0-8ffd9eb4aa56@amd.com> To: , Tony Luck CC: , , , Qiuxu Zhuo X-Mailer: b4 0.15-dev-9b767 X-ClientProxiedBy: SATLEXMB03.amd.com (10.181.40.144) To SATLEXMB04.amd.com (10.181.40.145) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: CH2PEPF00000146:EE_|PH7PR12MB8778:EE_ X-MS-Office365-Filtering-Correlation-Id: 7b318ed9-6a74-4782-bced-08dd7c2d88af X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|82310400026|36860700013|1800799024|376014|13003099007; X-Microsoft-Antispam-Message-Info: =?utf-8?q?8Bx8MKZwav+dbnBySX2rwKOGWsTmAQX?= =?utf-8?q?aV8LtkqzvhLlP2jFsADrqWVpHza8Yzv14GrVMkaelz7tEFZEsRZz17o2ITAuS2qSc?= =?utf-8?q?/rqVsvnhiZ0FgH34bZPRzhWrI8QO5Q1roln3aaLLHYdl+lw7Frs2LaQlfRSWEDoY7?= =?utf-8?q?I5f1XyOXwlgOo1iYQn2odIKt2UHS5IeBd8hVDSxDB1ZyzU8otEHKY8GUpwdEGe2ut?= =?utf-8?q?D1eI2dYR/1B+UxXMLIjT72EL5MxlvWvlvxLRnwt9Msze2dbO1uhTAyaUpnrQXphIB?= =?utf-8?q?0ndsgLAZgh5ml4kx18nT+H50AJxyUtW6nvAALuLiJONtEFWi12+3LNDCVvszWmVOJ?= =?utf-8?q?o4ITz57tAFnnvis9E7iVHT5w242/o1JoJATe0o0X2+iL23Fce74BBwgC7DCps3e9G?= =?utf-8?q?HYPgPfMzoIchvMW4gSEXqIJ3ZbN5+wtPdvaqpssC9AIhAexnSZJhH5mL1L5wr9Mu5?= =?utf-8?q?4s7T+XEDrzOz7XlFTZtsOTn8RhMiZbXU5W+4Whi+vDNA+sY7D3k1QjfftD3sfTcRG?= =?utf-8?q?oC/ICkcWG13JXJ0bqRtM7A1F/fN31x9cHIGP0huMZsddfBzKhChqAcPJFZbiLxHkG?= =?utf-8?q?nwF2JGcfbssfTHs5RKeRrt6nZPbgbQfa+gtbziG/+IBkGvTILjmzgeSROuqLTTJfh?= =?utf-8?q?IUENwXxz4XiL1LFYKfpM+k/LmEQuSDBfBhkYRxcE0AoNALP+tsrOzN8nXJVSJgs/i?= =?utf-8?q?hRWQIW3lKgilzISNY6KbL52DG2txEerK+MXEPIZtUufqoBShSvg4ieSFl0k4XSnBq?= =?utf-8?q?lkHnSCMGwk9cW+wFUbNwZejj+v//eaI21ImctJhbvHGrDPjli1systrkNdbJto2iL?= =?utf-8?q?fL3a0r7RO+UUugo7myUN+fLbzfOcRCBIc+kubqFAlx1kes+a85biiPDJaazCR8tqs?= =?utf-8?q?zWQIkBvf2Zi55lvpBkVOrFvqErKdhLJqu5m5LWSx8/RGa/bIgawKlY/61oAKuPLGx?= =?utf-8?q?7tUvZ1m6uh5pZdxUqTe0wrTiGbR1jS1LHKXKb42ke4igYa+NPfu7TpEteTi73t/NS?= =?utf-8?q?nbYvFzycXwtRJ3OkF2XqPz7q+xtgqiTMmkez7/ricG+blowPvWD8+G7ew1ELWRyb1?= =?utf-8?q?nZz6gCmpsyLUybBou5ZfX5j0ujd3dQdXKFHqjiav/fLhYIkU+z3fUSYi44GUu31AF?= =?utf-8?q?OWXe6Y3WsnTE3vkb+Qlr/najRmawXZmymKk9LebzekpzJZWBc28pJYCmaWb+gQ8on?= =?utf-8?q?xkNrNiIPynWrlqa7FDUjHlPI1XjrBVvCkqhCtQa09qAhR3ax7l5t3nul5Azy4v2qT?= =?utf-8?q?KE6W3/ANIhCuC0SnRs2dkkOpxYP9Nnm9fWceVE7TRtt+HeIL8/eaKlFvLE/Mch2c6?= =?utf-8?q?k+nkaClAfG5Wooi3fIGCEzy1djXfTf77cgeuQXM/4Sd2hvZk788mMiljJA3mCOM0u?= =?utf-8?q?EWazOmqo/9an+cl4lVORZ2aDmZp2dPrZi4HGwhbEvrWXkKwFwdkOLc4C5IfixLWmO?= =?utf-8?q?xPeo/h4/fH?= X-Forefront-Antispam-Report: CIP:165.204.84.17;CTRY:US;LANG:en;SCL:1;SRV:;IPV:CAL;SFV:NSPM;H:SATLEXMB04.amd.com;PTR:InfoDomainNonexistent;CAT:NONE;SFS:(13230040)(82310400026)(36860700013)(1800799024)(376014)(13003099007);DIR:OUT;SFP:1101; X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 15 Apr 2025 14:55:16.4444 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 7b318ed9-6a74-4782-bced-08dd7c2d88af X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: CH2PEPF00000146.namprd02.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: PH7PR12MB8778 Currently on AMD systems, MCA interrupt handler functions are set during CPU init. However, the functions only need to be set once for the whole system. Assign the handlers only during BSP init. Do so only for SMCA systems to maintain the old behavior for legacy systems. Signed-off-by: Yazen Ghannam --- Notes: Link: https://lore.kernel.org/r/20250213-wip-mca-updates-v2-8-3636547fe05f@amd.com v2->v3: * No change. v1->v2: * New in v2. arch/x86/kernel/cpu/mce/amd.c | 6 ++++++ arch/x86/kernel/cpu/mce/core.c | 3 +++ arch/x86/kernel/cpu/mce/internal.h | 2 ++ 3 files changed, 11 insertions(+) diff --git a/arch/x86/kernel/cpu/mce/amd.c b/arch/x86/kernel/cpu/mce/amd.c index 206973d7dbcc..0d84b171b851 100644 --- a/arch/x86/kernel/cpu/mce/amd.c +++ b/arch/x86/kernel/cpu/mce/amd.c @@ -687,6 +687,12 @@ void mce_amd_feature_init(struct cpuinfo_x86 *c) deferred_error_interrupt_enable(c); } +void mce_smca_cpu_init(void) +{ + mce_threshold_vector = amd_threshold_interrupt; + deferred_error_int_vector = amd_deferred_error_interrupt; +} + /* * DRAM ECC errors are reported in the Northbridge (bank 4) with * Extended Error Code 8. diff --git a/arch/x86/kernel/cpu/mce/core.c b/arch/x86/kernel/cpu/mce/core.c index d0a29e22cab0..444d006366fd 100644 --- a/arch/x86/kernel/cpu/mce/core.c +++ b/arch/x86/kernel/cpu/mce/core.c @@ -2243,6 +2243,9 @@ void cpu_mca_init(struct cpuinfo_x86 *c) mce_flags.succor = cpu_feature_enabled(X86_FEATURE_SUCCOR); mce_flags.smca = cpu_feature_enabled(X86_FEATURE_SMCA); + if (mce_flags.smca) + mce_smca_cpu_init(); + rdmsrl(MSR_IA32_MCG_CAP, cap); /* Use accurate RIP reporting if available. */ diff --git a/arch/x86/kernel/cpu/mce/internal.h b/arch/x86/kernel/cpu/mce/internal.h index 64ac25b95360..87b69935d57d 100644 --- a/arch/x86/kernel/cpu/mce/internal.h +++ b/arch/x86/kernel/cpu/mce/internal.h @@ -294,12 +294,14 @@ static __always_inline void smca_extract_err_addr(struct mce *m) m->addr &= GENMASK_ULL(55, lsb); } +void mce_smca_cpu_init(void); #else static inline void mce_threshold_create_device(unsigned int cpu) { } static inline void mce_threshold_remove_device(unsigned int cpu) { } static inline bool amd_filter_mce(struct mce *m) { return false; } static inline bool amd_mce_usable_address(struct mce *m) { return false; } static inline void smca_extract_err_addr(struct mce *m) { } +static inline void mce_smca_cpu_init(void) {} #endif #ifdef CONFIG_X86_ANCIENT_MCE From patchwork Tue Apr 15 14:55:04 2025 Content-Type: text/plain; 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client-ip=165.204.84.17; helo=SATLEXMB04.amd.com; pr=C Received: from SATLEXMB04.amd.com (165.204.84.17) by CH2PEPF0000014A.mail.protection.outlook.com (10.167.244.107) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.20.8655.12 via Frontend Transport; Tue, 15 Apr 2025 14:55:16 +0000 Received: from [127.0.1.1] (10.180.168.240) by SATLEXMB04.amd.com (10.181.40.145) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.39; Tue, 15 Apr 2025 09:55:14 -0500 From: Yazen Ghannam Date: Tue, 15 Apr 2025 14:55:04 +0000 Subject: [PATCH v3 09/17] x86/mce: Do 'UNKNOWN' vendor check early Precedence: bulk X-Mailing-List: linux-edac@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-ID: <20250415-wip-mca-updates-v3-9-8ffd9eb4aa56@amd.com> References: <20250415-wip-mca-updates-v3-0-8ffd9eb4aa56@amd.com> In-Reply-To: <20250415-wip-mca-updates-v3-0-8ffd9eb4aa56@amd.com> To: , Tony Luck CC: , , , Qiuxu Zhuo X-Mailer: b4 0.15-dev-9b767 X-ClientProxiedBy: SATLEXMB03.amd.com (10.181.40.144) To SATLEXMB04.amd.com (10.181.40.145) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: CH2PEPF0000014A:EE_|CH2PR12MB4312:EE_ X-MS-Office365-Filtering-Correlation-Id: 42615be7-d1ea-4e7e-4a40-08dd7c2d88ba X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|1800799024|376014|36860700013|82310400026|7053199007; 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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 15 Apr 2025 14:55:16.5136 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 42615be7-d1ea-4e7e-4a40-08dd7c2d88ba X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: CH2PEPF0000014A.namprd02.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: CH2PR12MB4312 The 'UNKNOWN' vendor check is handled as a quirk that is run on each online CPU. However, all CPUs are expected to have the same vendor. Move the 'UNKNOWN' vendor check to the BSP-only init so it is done early and once. Remove the unnecessary return value from the quirks check. Reviewed-by: Qiuxu Zhuo Tested-by: Tony Luck Reviewed-by: Tony Luck Signed-off-by: Yazen Ghannam --- Notes: Link: https://lore.kernel.org/r/20250213-wip-mca-updates-v2-9-3636547fe05f@amd.com v2->v3: * Add tags from Qiuxu and Tony. v1->v2: * New in v2. arch/x86/kernel/cpu/mce/core.c | 18 ++++++++---------- 1 file changed, 8 insertions(+), 10 deletions(-) diff --git a/arch/x86/kernel/cpu/mce/core.c b/arch/x86/kernel/cpu/mce/core.c index 444d006366fd..9dc9d672a7d1 100644 --- a/arch/x86/kernel/cpu/mce/core.c +++ b/arch/x86/kernel/cpu/mce/core.c @@ -1974,14 +1974,11 @@ static void apply_quirks_zhaoxin(struct cpuinfo_x86 *c) } /* Add per CPU specific workarounds here */ -static bool __mcheck_cpu_apply_quirks(struct cpuinfo_x86 *c) +static void __mcheck_cpu_apply_quirks(struct cpuinfo_x86 *c) { struct mca_config *cfg = &mca_cfg; switch (c->x86_vendor) { - case X86_VENDOR_UNKNOWN: - pr_info("unknown CPU type - not enabling MCE support\n"); - return false; case X86_VENDOR_AMD: apply_quirks_amd(c); break; @@ -1997,8 +1994,6 @@ static bool __mcheck_cpu_apply_quirks(struct cpuinfo_x86 *c) cfg->monarch_timeout = 0; if (cfg->bootlog != 0) cfg->panic_timeout = 30; - - return true; } static bool __mcheck_cpu_ancient_init(struct cpuinfo_x86 *c) @@ -2239,6 +2234,12 @@ void cpu_mca_init(struct cpuinfo_x86 *c) if (!mce_available(c)) return; + if (c->x86_vendor == X86_VENDOR_UNKNOWN) { + mca_cfg.disabled = 1; + pr_info("unknown CPU type - not enabling MCE support\n"); + return; + } + mce_flags.overflow_recov = cpu_feature_enabled(X86_FEATURE_OVERFLOW_RECOV); mce_flags.succor = cpu_feature_enabled(X86_FEATURE_SUCCOR); mce_flags.smca = cpu_feature_enabled(X86_FEATURE_SMCA); @@ -2273,10 +2274,7 @@ void mcheck_cpu_init(struct cpuinfo_x86 *c) __mcheck_cpu_cap_init(); - if (!__mcheck_cpu_apply_quirks(c)) { - mca_cfg.disabled = 1; - return; - } + __mcheck_cpu_apply_quirks(c); if (!mce_gen_pool_init()) { mca_cfg.disabled = 1; From patchwork Tue Apr 15 14:55:05 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Yazen Ghannam X-Patchwork-Id: 14052369 Received: from NAM10-MW2-obe.outbound.protection.outlook.com (mail-mw2nam10on2063.outbound.protection.outlook.com [40.107.94.63]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id E22D5297A6F; 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Tue, 15 Apr 2025 09:55:15 -0500 From: Yazen Ghannam Date: Tue, 15 Apr 2025 14:55:05 +0000 Subject: [PATCH v3 10/17] x86/mce: Separate global and per-CPU quirks Precedence: bulk X-Mailing-List: linux-edac@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-ID: <20250415-wip-mca-updates-v3-10-8ffd9eb4aa56@amd.com> References: <20250415-wip-mca-updates-v3-0-8ffd9eb4aa56@amd.com> In-Reply-To: <20250415-wip-mca-updates-v3-0-8ffd9eb4aa56@amd.com> To: , Tony Luck CC: , , , Qiuxu Zhuo X-Mailer: b4 0.15-dev-9b767 X-ClientProxiedBy: SATLEXMB03.amd.com (10.181.40.144) To SATLEXMB04.amd.com (10.181.40.145) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: CH2PEPF00000146:EE_|IA1PR12MB6603:EE_ X-MS-Office365-Filtering-Correlation-Id: 179593d7-eef3-4333-cab6-08dd7c2d893e X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|82310400026|376014|1800799024|36860700013|7053199007; X-Microsoft-Antispam-Message-Info: =?utf-8?q?lnVuFNAIanP/YLO3q2rCiGFfbU3gme4?= =?utf-8?q?+3F7I4T1fMs7idll/GnZZmsKDBsUa+ARgyOc5oBXjqr/qH0jPTd11ufjW6Mla8FqY?= =?utf-8?q?CGShSmMMjKYY1eXlz32Jbb6cnt4g5WupnFJCcG/a/J2rJ3k7Q2l7VqWIc1HHdKv8l?= =?utf-8?q?lsvz616W5nNGOauxR47ZTCOfgfPyCvyEU3Ph2boLBU6m4bmV8bsE2iozJYdV/LdHr?= =?utf-8?q?VdtZsBr5K9/WUxX3rXIcOfCsyj+iVw8H+osl3kTximYe8gWnM6PgjIScglKi9r8uN?= =?utf-8?q?KjwPpphFBy50h/XrCThk3ClX8YOcxYupgkWejphmv7d0tq7qzNdYP+sneNj70p54b?= =?utf-8?q?cbrZWnWQFMnhnnD8TGDKAICIP0lWXzmQQiQZa6C1tX5EPIAqlMV6bHiKoiIBwkJCd?= =?utf-8?q?clJbj2YaU5MMm5vawQyyyTlSpDQLmdRG+6YwwvmGKolMEP6N7ZOFWz23JDrqmGOgP?= =?utf-8?q?6UjIsK8ueIqNKNzv8xT+0IgKMFm0N0RUYJn7sxyB4tLIqA9EfJ/7m90xtUHiALuOm?= =?utf-8?q?iu3tb4u8rn5Zmoxq336xD/YPreAUbMktrk7Y1LGge2Cl7fpLR/TyW2x6tcL+KlvN3?= =?utf-8?q?vsE/MFVNfXwdxAyFo9/r4ucYg2yy2OaaJrFJU9WBS3V78jdr6YoHtIyIPbElNXUqR?= =?utf-8?q?obtPWURgeyEhXFy7pqhLQHVcbxDBLpVvactXVeUUqmMT7/QDFPkWGt1p4OA9MuXoo?= =?utf-8?q?yVoCglqWyYux3AHK/cjRozYGh18f4pD+47qDyMQRXW0wsh0JRiKGUwT5iNsnmRCY1?= =?utf-8?q?dEy8uiXBFBptDN6SQ+S+bHQWV0Fa6uyI2aq6DNRbv28dOM1GtSve2vSk8HrU7aLiS?= =?utf-8?q?KrblgH8sLab+Wo3oJrEWAP9vUzuK9qby1YEfg4kTwxCo1GWxN9ajQGamH35IhG8Mc?= =?utf-8?q?y2Xmf82XMBD6LNlG2nGc0JebNx9on2sr9SaZ+v7Pkvq7F+UmYGiADn397zonwGON8?= =?utf-8?q?SIa+kZoAVN2r7mOW5TWMcuzeUdrAs5CiReFN7mKjBq8CuP5hHclAE/uJkjbdGCcKY?= =?utf-8?q?lJRueYINa6xpym/cgk1+FcJXZV6MMHQut1Gl7XArtD0RfHCaWDPd5alcPXFiWVlpz?= =?utf-8?q?2xBKOvBYG5YC0Z16OzNXnsxx6KJXYR8NHCmYuwDpVTPIiw53pUTeQo8l1gYDgmRJt?= =?utf-8?q?L1qQ3BWwsFj6Qh6cTTxjimQC2gwz6XN79EdeIkB/rdmkCjCCwpyB6eJOuHiu2XUX7?= =?utf-8?q?+UTE49/QDiRmQX8JfvzsrG+JjtfBV6e/5iBgsEFjM8Z1tPhi83zIFRNHKFrJRXnQt?= =?utf-8?q?0Oa9J+MDBUJZwhcupGYtYvmn6+FstIRqAiWjV2AVGsuOze9Ee62w9ZE/AWNk+ajhH?= =?utf-8?q?0K5nXsa5VaEodzQrSkNL2jKqy3kGW9K1ldwGVu5PAPpMgfgbD+i410yQV+AG2POah?= =?utf-8?q?UN2xagwgJHdYEir1oTuizwFxfXX5piYdr5W36ethqWq88LDoLOLNzpffsWRv2tJkW?= =?utf-8?q?eWJMy2gfn5jumLPH4r21GmFn+zC/45qw=3D=3D?= X-Forefront-Antispam-Report: CIP:165.204.84.17;CTRY:US;LANG:en;SCL:1;SRV:;IPV:CAL;SFV:NSPM;H:SATLEXMB04.amd.com;PTR:InfoDomainNonexistent;CAT:NONE;SFS:(13230040)(82310400026)(376014)(1800799024)(36860700013)(7053199007);DIR:OUT;SFP:1101; X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 15 Apr 2025 14:55:17.3819 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 179593d7-eef3-4333-cab6-08dd7c2d893e X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: CH2PEPF00000146.namprd02.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: IA1PR12MB6603 Many quirks are global configuration settings and a handful apply to each CPU. Move the per-CPU quirks to vendor init to execute them on each online CPU. Set the global quirks during BSP-only init so they're only executed once and early. Reviewed-by: Qiuxu Zhuo Tested-by: Tony Luck Reviewed-by: Tony Luck Signed-off-by: Yazen Ghannam --- Notes: Link: https://lore.kernel.org/r/20250213-wip-mca-updates-v2-10-3636547fe05f@amd.com v2->v3: * Update code comment. * Add tags from Qiuxu and Tony. v1->v2: * New in v2. arch/x86/kernel/cpu/mce/amd.c | 23 +++++++++++++++++++++++ arch/x86/kernel/cpu/mce/core.c | 36 ++---------------------------------- arch/x86/kernel/cpu/mce/intel.c | 18 ++++++++++++++++++ 3 files changed, 43 insertions(+), 34 deletions(-) diff --git a/arch/x86/kernel/cpu/mce/amd.c b/arch/x86/kernel/cpu/mce/amd.c index 0d84b171b851..6a69cac36c18 100644 --- a/arch/x86/kernel/cpu/mce/amd.c +++ b/arch/x86/kernel/cpu/mce/amd.c @@ -649,6 +649,28 @@ static void disable_err_thresholding(struct cpuinfo_x86 *c, unsigned int bank) wrmsrq(MSR_K7_HWCR, hwcr); } +static void amd_apply_quirks(struct cpuinfo_x86 *c) +{ + struct mce_bank *mce_banks = this_cpu_ptr(mce_banks_array); + + /* This should be disabled by the BIOS, but isn't always */ + if (c->x86 == 15 && this_cpu_read(mce_num_banks) > 4) { + /* + * disable GART TBL walk error reporting, which + * trips off incorrectly with the IOMMU & 3ware + * & Cerberus: + */ + clear_bit(10, (unsigned long *)&mce_banks[4].ctl); + } + + /* + * Various K7s with broken bank 0 around. Always disable + * by default. + */ + if (c->x86 == 6 && this_cpu_read(mce_num_banks)) + mce_banks[0].ctl = 0; +} + /* cpu init entry point, called from mce.c with preempt off */ void mce_amd_feature_init(struct cpuinfo_x86 *c) { @@ -656,6 +678,7 @@ void mce_amd_feature_init(struct cpuinfo_x86 *c) u32 low = 0, high = 0, address = 0; int offset = -1; + amd_apply_quirks(c); mce_flags.amd_threshold = 1; for (bank = 0; bank < this_cpu_read(mce_num_banks); ++bank) { diff --git a/arch/x86/kernel/cpu/mce/core.c b/arch/x86/kernel/cpu/mce/core.c index 9dc9d672a7d1..413c68f18084 100644 --- a/arch/x86/kernel/cpu/mce/core.c +++ b/arch/x86/kernel/cpu/mce/core.c @@ -1879,18 +1879,6 @@ static void __mcheck_cpu_init_prepare_banks(void) static void apply_quirks_amd(struct cpuinfo_x86 *c) { - struct mce_bank *mce_banks = this_cpu_ptr(mce_banks_array); - - /* This should be disabled by the BIOS, but isn't always */ - if (c->x86 == 15 && this_cpu_read(mce_num_banks) > 4) { - /* - * disable GART TBL walk error reporting, which - * trips off incorrectly with the IOMMU & 3ware - * & Cerberus: - */ - clear_bit(10, (unsigned long *)&mce_banks[4].ctl); - } - if (c->x86 < 0x11 && mca_cfg.bootlog < 0) { /* * Lots of broken BIOS around that don't clear them @@ -1899,13 +1887,6 @@ static void apply_quirks_amd(struct cpuinfo_x86 *c) mca_cfg.bootlog = 0; } - /* - * Various K7s with broken bank 0 around. Always disable - * by default. - */ - if (c->x86 == 6 && this_cpu_read(mce_num_banks)) - mce_banks[0].ctl = 0; - /* * overflow_recov is supported for F15h Models 00h-0fh * even though we don't have a CPUID bit for it. @@ -1919,23 +1900,10 @@ static void apply_quirks_amd(struct cpuinfo_x86 *c) static void apply_quirks_intel(struct cpuinfo_x86 *c) { - struct mce_bank *mce_banks = this_cpu_ptr(mce_banks_array); - /* Older CPUs (prior to family 6) don't need quirks. */ if (c->x86_vfm < INTEL_PENTIUM_PRO) return; - /* - * SDM documents that on family 6 bank 0 should not be written - * because it aliases to another special BIOS controlled - * register. - * But it's not aliased anymore on model 0x1a+ - * Don't ignore bank 0 completely because there could be a - * valid event later, merely don't write CTL0. - */ - if (c->x86_vfm < INTEL_NEHALEM_EP && this_cpu_read(mce_num_banks)) - mce_banks[0].init = false; - /* * All newer Intel systems support MCE broadcasting. Enable * synchronization with a one second timeout. @@ -2255,6 +2223,8 @@ void cpu_mca_init(struct cpuinfo_x86 *c) if (cap & MCG_SER_P) mca_cfg.ser = 1; + + __mcheck_cpu_apply_quirks(c); } /* @@ -2274,8 +2244,6 @@ void mcheck_cpu_init(struct cpuinfo_x86 *c) __mcheck_cpu_cap_init(); - __mcheck_cpu_apply_quirks(c); - if (!mce_gen_pool_init()) { mca_cfg.disabled = 1; pr_emerg("Couldn't allocate MCE records pool!\n"); diff --git a/arch/x86/kernel/cpu/mce/intel.c b/arch/x86/kernel/cpu/mce/intel.c index efcf21e9552e..ae9417d634ac 100644 --- a/arch/x86/kernel/cpu/mce/intel.c +++ b/arch/x86/kernel/cpu/mce/intel.c @@ -468,8 +468,26 @@ static void intel_imc_init(struct cpuinfo_x86 *c) } } +static void intel_apply_quirks(struct cpuinfo_x86 *c) +{ + /* + * SDM documents that on family 6 bank 0 should not be written + * because it aliases to another special BIOS controlled + * register. + * But it's not aliased anymore on model 0x1a+ + * Don't ignore bank 0 completely because there could be a + * valid event later, merely don't write CTL0. + * + * Older CPUs (prior to family 6) can't reach this point and already + * return early due to the check of __mcheck_cpu_ancient_init(). + */ + if (c->x86_vfm < INTEL_NEHALEM_EP && this_cpu_read(mce_num_banks)) + this_cpu_ptr(mce_banks_array)[0].init = false; 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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 15 Apr 2025 14:55:17.4511 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 445c9528-b5c9-411b-7eba-08dd7c2d8950 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: CH2PEPF0000014A.namprd02.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: MN0PR12MB6343 There are a number of generic and vendor-specific status checks in machine_check_poll(). These are used to determine if an error should be skipped. Move these into helper functions. Future vendor-specific checks will be added to the helpers. Reviewed-by: Qiuxu Zhuo Tested-by: Tony Luck Reviewed-by: Tony Luck Signed-off-by: Yazen Ghannam --- Notes: Link: https://lore.kernel.org/r/20250213-wip-mca-updates-v2-11-3636547fe05f@amd.com v2->v3: * Add tags from Qiuxu and Tony. v1->v2: * Change log_poll_error() to should_log_poll_error(). * Keep code comment. arch/x86/kernel/cpu/mce/core.c | 88 +++++++++++++++++++++++------------------- 1 file changed, 48 insertions(+), 40 deletions(-) diff --git a/arch/x86/kernel/cpu/mce/core.c b/arch/x86/kernel/cpu/mce/core.c index 413c68f18084..c82c9e435066 100644 --- a/arch/x86/kernel/cpu/mce/core.c +++ b/arch/x86/kernel/cpu/mce/core.c @@ -714,6 +714,52 @@ static noinstr void mce_read_aux(struct mce_hw_err *err, int i) DEFINE_PER_CPU(unsigned, mce_poll_count); +/* + * Newer Intel systems that support software error + * recovery need to make additional checks. Other + * CPUs should skip over uncorrected errors, but log + * everything else. + */ +static bool ser_should_log_poll_error(struct mce *m) +{ + /* Log "not enabled" (speculative) errors */ + if (!(m->status & MCI_STATUS_EN)) + return true; + + /* + * Log UCNA (SDM: 15.6.3 "UCR Error Classification") + * UC == 1 && PCC == 0 && S == 0 + */ + if (!(m->status & MCI_STATUS_PCC) && !(m->status & MCI_STATUS_S)) + return true; + + return false; +} + +static bool should_log_poll_error(enum mcp_flags flags, struct mce_hw_err *err) +{ + struct mce *m = &err->m; + + /* If this entry is not valid, ignore it. */ + if (!(m->status & MCI_STATUS_VAL)) + return false; + + /* + * If we are logging everything (at CPU online) or this + * is a corrected error, then we must log it. + */ + if ((flags & MCP_UC) || !(m->status & MCI_STATUS_UC)) + return true; + + if (mca_cfg.ser) + return ser_should_log_poll_error(m); + + if (m->status & MCI_STATUS_UC) + return false; + + return true; +} + /* * Poll for corrected events or events that happened before reset. * Those are just logged through /dev/mcelog. @@ -765,48 +811,10 @@ void machine_check_poll(enum mcp_flags flags, mce_banks_t *b) if (!mca_cfg.cmci_disabled) mce_track_storm(m); - /* If this entry is not valid, ignore it */ - if (!(m->status & MCI_STATUS_VAL)) + /* Verify that the error should be logged based on hardware conditions. */ + if (!should_log_poll_error(flags, &err)) continue; - /* - * If we are logging everything (at CPU online) or this - * is a corrected error, then we must log it. - */ - if ((flags & MCP_UC) || !(m->status & MCI_STATUS_UC)) - goto log_it; - - /* - * Newer Intel systems that support software error - * recovery need to make additional checks. Other - * CPUs should skip over uncorrected errors, but log - * everything else. - */ - if (!mca_cfg.ser) { - if (m->status & MCI_STATUS_UC) - continue; - goto log_it; - } - - /* Log "not enabled" (speculative) errors */ - if (!(m->status & MCI_STATUS_EN)) - goto log_it; - - /* - * Log UCNA (SDM: 15.6.3 "UCR Error Classification") - * UC == 1 && PCC == 0 && S == 0 - */ - if (!(m->status & MCI_STATUS_PCC) && !(m->status & MCI_STATUS_S)) - goto log_it; - - /* - * Skip anything else. Presumption is that our read of this - * bank is racing with a machine check. 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Tue, 15 Apr 2025 14:55:18 +0000 X-MS-Exchange-Authentication-Results: spf=pass (sender IP is 165.204.84.17) smtp.mailfrom=amd.com; dkim=none (message not signed) header.d=none;dmarc=pass action=none header.from=amd.com; Received-SPF: Pass (protection.outlook.com: domain of amd.com designates 165.204.84.17 as permitted sender) receiver=protection.outlook.com; client-ip=165.204.84.17; helo=SATLEXMB04.amd.com; pr=C Received: from SATLEXMB04.amd.com (165.204.84.17) by CH2PEPF0000014A.mail.protection.outlook.com (10.167.244.107) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.20.8655.12 via Frontend Transport; Tue, 15 Apr 2025 14:55:18 +0000 Received: from [127.0.1.1] (10.180.168.240) by SATLEXMB04.amd.com (10.181.40.145) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.39; Tue, 15 Apr 2025 09:55:16 -0500 From: Yazen Ghannam Date: Tue, 15 Apr 2025 14:55:07 +0000 Subject: [PATCH v3 12/17] x86/mce: Unify AMD THR handler with MCA Polling Precedence: bulk X-Mailing-List: linux-edac@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-ID: <20250415-wip-mca-updates-v3-12-8ffd9eb4aa56@amd.com> References: <20250415-wip-mca-updates-v3-0-8ffd9eb4aa56@amd.com> In-Reply-To: <20250415-wip-mca-updates-v3-0-8ffd9eb4aa56@amd.com> To: , Tony Luck CC: , , , Qiuxu Zhuo X-Mailer: b4 0.15-dev-9b767 X-ClientProxiedBy: SATLEXMB03.amd.com (10.181.40.144) To SATLEXMB04.amd.com (10.181.40.145) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: CH2PEPF0000014A:EE_|CH3PR12MB8709:EE_ X-MS-Office365-Filtering-Correlation-Id: e6d2c771-de30-48bc-b625-08dd7c2d89a8 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|376014|1800799024|36860700013|82310400026|13003099007; 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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 15 Apr 2025 14:55:18.0761 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: e6d2c771-de30-48bc-b625-08dd7c2d89a8 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: CH2PEPF0000014A.namprd02.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: CH3PR12MB8709 AMD systems optionally support an MCA thresholding interrupt. The interrupt should be used as another signal to trigger MCA polling. This is similar to how the Intel Corrected Machine Check interrupt (CMCI) is handled. AMD MCA thresholding is managed using the MCA_MISC registers within an MCA bank. The OS will need to modify the hardware error count field in order to reset the threshold limit and rearm the interrupt. Management of the MCA_MISC register should be done as a follow up to the basic MCA polling flow. It should not be the main focus of the interrupt handler. Furthermore, future systems will have the ability to send an MCA thresholding interrupt to the OS even when the OS does not manage the feature, i.e. MCA_MISC registers are Read-as-Zero/Locked. Call the common MCA polling function when handling the MCA thresholding interrupt. This will allow the OS to find any valid errors whether or not the MCA thresholding feature is OS-managed. Also, this allows the common MCA polling options and kernel parameters to apply to AMD systems. Add a callback to the MCA polling function to check and reset any threshold blocks that have reached their threshold limit. Signed-off-by: Yazen Ghannam --- Notes: Link: https://lore.kernel.org/r/20250213-wip-mca-updates-v2-12-3636547fe05f@amd.com v2->v3: * Add tags from Qiuxu and Tony. v1->v2: * Start collecting per-CPU items in a struct. * Keep and use mce_flags.amd_threshold. arch/x86/kernel/cpu/mce/amd.c | 49 ++++++++++++++++---------------------- arch/x86/kernel/cpu/mce/core.c | 3 +++ arch/x86/kernel/cpu/mce/internal.h | 2 ++ 3 files changed, 26 insertions(+), 28 deletions(-) diff --git a/arch/x86/kernel/cpu/mce/amd.c b/arch/x86/kernel/cpu/mce/amd.c index 6a69cac36c18..f8755a21fd48 100644 --- a/arch/x86/kernel/cpu/mce/amd.c +++ b/arch/x86/kernel/cpu/mce/amd.c @@ -54,6 +54,12 @@ static bool thresholding_irq_en; +struct mce_amd_cpu_data { + mce_banks_t thr_intr_banks; +}; + +static DEFINE_PER_CPU_READ_MOSTLY(struct mce_amd_cpu_data, mce_amd_data); + static const char * const th_names[] = { "load_store", "insn_fetch", @@ -559,6 +565,7 @@ prepare_threshold_block(unsigned int bank, unsigned int block, u32 addr, if (!b.interrupt_capable) goto done; + __set_bit(bank, this_cpu_ptr(&mce_amd_data)->thr_intr_banks); b.interrupt_enable = 1; if (!mce_flags.smca) { @@ -898,12 +905,7 @@ static void amd_deferred_error_interrupt(void) log_error_deferred(bank); } -static void log_error_thresholding(unsigned int bank, u64 misc) -{ - _log_error_deferred(bank, misc); -} - -static void log_and_reset_block(struct threshold_block *block) +static void reset_block(struct threshold_block *block) { struct thresh_restart tr; u32 low = 0, high = 0; @@ -917,23 +919,14 @@ static void log_and_reset_block(struct threshold_block *block) if (!(high & MASK_OVERFLOW_HI)) return; - /* Log the MCE which caused the threshold event. */ - log_error_thresholding(block->bank, ((u64)high << 32) | low); - - /* Reset threshold block after logging error. */ memset(&tr, 0, sizeof(tr)); tr.b = block; threshold_restart_bank(&tr); } -/* - * Threshold interrupt handler will service THRESHOLD_APIC_VECTOR. The interrupt - * goes off when error_count reaches threshold_limit. - */ -static void amd_threshold_interrupt(void) +void amd_reset_thr_limit(unsigned int bank) { - struct threshold_bank **bp = this_cpu_read(threshold_banks), *thr_bank; - unsigned int bank, cpu = smp_processor_id(); + struct threshold_bank **bp = this_cpu_read(threshold_banks); struct threshold_block *block, *tmp; /* @@ -941,20 +934,20 @@ static void amd_threshold_interrupt(void) * handler is installed at boot time, but on a hotplug event the * interrupt might fire before the data has been initialized. */ - if (!bp) + if (!bp || !bp[bank]) return; - for (bank = 0; bank < this_cpu_read(mce_num_banks); ++bank) { - if (!(per_cpu(bank_map, cpu) & BIT_ULL(bank))) - continue; - - thr_bank = bp[bank]; - if (!thr_bank) - continue; + list_for_each_entry_safe(block, tmp, &bp[bank]->miscj, miscj) + reset_block(block); +} - list_for_each_entry_safe(block, tmp, &thr_bank->miscj, miscj) - log_and_reset_block(block); - } +/* + * Threshold interrupt handler will service THRESHOLD_APIC_VECTOR. The interrupt + * goes off when error_count reaches threshold_limit. + */ +static void amd_threshold_interrupt(void) +{ + machine_check_poll(MCP_TIMESTAMP, &this_cpu_ptr(&mce_amd_data)->thr_intr_banks); } /* diff --git a/arch/x86/kernel/cpu/mce/core.c b/arch/x86/kernel/cpu/mce/core.c index c82c9e435066..de85b014653f 100644 --- a/arch/x86/kernel/cpu/mce/core.c +++ b/arch/x86/kernel/cpu/mce/core.c @@ -831,6 +831,9 @@ void machine_check_poll(enum mcp_flags flags, mce_banks_t *b) mce_log(&err); clear_it: + if (mce_flags.amd_threshold) + amd_reset_thr_limit(i); + /* * Clear state for this bank. */ diff --git a/arch/x86/kernel/cpu/mce/internal.h b/arch/x86/kernel/cpu/mce/internal.h index 87b69935d57d..aeb0a998f553 100644 --- a/arch/x86/kernel/cpu/mce/internal.h +++ b/arch/x86/kernel/cpu/mce/internal.h @@ -269,6 +269,7 @@ void mce_threshold_create_device(unsigned int cpu); void mce_threshold_remove_device(unsigned int cpu); extern bool amd_filter_mce(struct mce *m); bool amd_mce_usable_address(struct mce *m); +void amd_reset_thr_limit(unsigned int bank); /* * If MCA_CONFIG[McaLsbInStatusSupported] is set, extract ErrAddr in bits @@ -300,6 +301,7 @@ static inline void mce_threshold_create_device(unsigned int cpu) { } static inline void mce_threshold_remove_device(unsigned int cpu) { } static inline bool amd_filter_mce(struct mce *m) { return false; } static inline bool amd_mce_usable_address(struct mce *m) { return false; } +static inline void amd_reset_thr_limit(unsigned int bank) { } static inline void smca_extract_err_addr(struct mce *m) { } static inline void mce_smca_cpu_init(void) {} #endif From patchwork Tue Apr 15 14:55:08 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Yazen Ghannam X-Patchwork-Id: 14052365 Received: from NAM12-DM6-obe.outbound.protection.outlook.com (mail-dm6nam12on2041.outbound.protection.outlook.com [40.107.243.41]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 6EA3029C33B; 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Tue, 15 Apr 2025 09:55:16 -0500 From: Yazen Ghannam Date: Tue, 15 Apr 2025 14:55:08 +0000 Subject: [PATCH v3 13/17] x86/mce: Unify AMD DFR handler with MCA Polling Precedence: bulk X-Mailing-List: linux-edac@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-ID: <20250415-wip-mca-updates-v3-13-8ffd9eb4aa56@amd.com> References: <20250415-wip-mca-updates-v3-0-8ffd9eb4aa56@amd.com> In-Reply-To: <20250415-wip-mca-updates-v3-0-8ffd9eb4aa56@amd.com> To: , Tony Luck CC: , , , Qiuxu Zhuo X-Mailer: b4 0.15-dev-9b767 X-ClientProxiedBy: SATLEXMB03.amd.com (10.181.40.144) To SATLEXMB04.amd.com (10.181.40.145) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: CH2PEPF0000014A:EE_|CH1PPF6D0742E7B:EE_ X-MS-Office365-Filtering-Correlation-Id: cb703d9a-5955-441c-c7cf-08dd7c2d89da X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|36860700013|376014|1800799024|82310400026|7053199007; X-Microsoft-Antispam-Message-Info: =?utf-8?q?vLcqE53HLSSKOQSQZ/h+OqZmvnYyFnl?= =?utf-8?q?FDINmxEHxyYYPh+gcvMoi0FxDf3FaFdm0hNYmgaWy1p0kkjBXkkCrnnvA98rAUJp0?= =?utf-8?q?i9Eue3Vs6JEE36CjReUTKowSYm8v+B6D2lySdM5XXesHKBB9LjrvRkNyNxF1NffFg?= =?utf-8?q?hTD4OSztaKXD68krSQh9eqczGzl5tQXBpMLrRyrhc2MVUw+quFvdMlzsVsg16yTXX?= =?utf-8?q?rjs7S8qDzPnyPnCnhbb1QibdwaMvVKuDMVzXNoATqz+2+ZHuJGVljlIgDxuPCngq0?= =?utf-8?q?khl8nXvzeytzTkOLjn8e9kzbXjxvE+8SFj27OMZdA1KNpQFG9GhJhZPrREQShe505?= =?utf-8?q?ub2FRKO8qGKj9tuGOwHusp3nJBAtbxVVBYhBVfNx5sGpAX6X7+9KVVz2FtsN9ok+E?= =?utf-8?q?gi6yQv2FyXiUzbdglTr13NvB2T94zgDUYAL3QjbQLcFGgEH7hJNwnkbUmw7a5YdKT?= =?utf-8?q?3SZjsoXIX4Fv62Xmy5a4G0FEGcNS8fun7JN6fef2SIphwKKl9i2MJhoPigLREFfIg?= =?utf-8?q?os6/UfWZtOmvxsGBNaI0flCNf9uBPOS+jOoR7ToFMUpN1ioxDt9WuoO4T6ZBBeeb/?= =?utf-8?q?+ElZnsk1h5nBz+uK+w9KjMJ0q1Goym9f3po2+PLrARpjF6ePGXmtU8iVU9fhuwAxq?= =?utf-8?q?JHFoE3kFbhS9a72xuuzQCDbBx5pqlMyoUOoN5FBGg6Kj8/BZ0sOQ0veGP0uAnZmiY?= =?utf-8?q?QYWnm4WVf0zCgxo1HFxjNU/7RImtRa0YKu88QLPsXpS0/eaxrj96MUiBiPSywsKjc?= =?utf-8?q?P1kYonzh3K/jHGQ3aZ2ut+xeTjQrfL8PlTw+ONpJLVgifo96rl9/qQavU+keX2on3?= =?utf-8?q?p559KLBVNFT7v2xFvPDd6nfkUr59r0H6ezyUXn1OsUuscBJi/FjdxcDMIuUcLEZQY?= =?utf-8?q?SCQ7IzTMIGuw2DQNth/GpC5Hkha0xVVxtwA6U3VmxkiWVNqiok120VbG5Bu3X35a8?= =?utf-8?q?GyQohdpW6NZ0ZEB7llrWRBSKjcRqHwNP80eMA7fpnPYmo2BN7XTjk3Xb89dsOtW71?= =?utf-8?q?9FLhd/A7RMAIR2mTSB6QZFQJub9TvjN/jnZu78YSM5lNyh8Le7VDUm37exfG6JjXI?= =?utf-8?q?mp0PGTFvJz7P0q1/SlOhfSwAZGb9PF5o4bdG+0n8EH3U4W9WskBOY4HB7F77UAs5X?= =?utf-8?q?AY24O6Q1axmfmaXTmZESn4281s47kwREO/8R3CGj5SM8+rrrEIduqkubO9CnoK45p?= =?utf-8?q?F5f66g76skZ/3aGidzh3M9+Fs9h6y6wXUunsguLLnHuCEczbTCYK14XjhkGinQ/7n?= =?utf-8?q?uu07qqtYA7nVCP2HZ/wb8gAuV9L3pPuoY9UTkrwJaB0XUPdnCYwsANBBfDRxyu09M?= =?utf-8?q?j9Ub52I4ef0F6Yl2dVIaIuOAPwg2zl6kshDl+SBIgCEpsLZn7rj8GeiGMg83PVH5U?= =?utf-8?q?2UhXIUNqODV3iyWN/KzRqY8OoseW+Lj+I/tbST4kCeACGg08B5bG7ybC+NCS4iJAP?= =?utf-8?q?8VbmPSAfAr9TGP+9x2+HFqV3yRO3BWRw=3D=3D?= X-Forefront-Antispam-Report: CIP:165.204.84.17;CTRY:US;LANG:en;SCL:1;SRV:;IPV:CAL;SFV:NSPM;H:SATLEXMB04.amd.com;PTR:InfoDomainNonexistent;CAT:NONE;SFS:(13230040)(36860700013)(376014)(1800799024)(82310400026)(7053199007);DIR:OUT;SFP:1101; X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 15 Apr 2025 14:55:18.4042 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: cb703d9a-5955-441c-c7cf-08dd7c2d89da X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: CH2PEPF0000014A.namprd02.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: CH1PPF6D0742E7B AMD systems optionally support a deferred error interrupt. The interrupt should be used as another signal to trigger MCA polling. This is similar to how other MCA interrupts are handled. Deferred errors do not require any special handling related to the interrupt, e.g. resetting or rearming the interrupt, etc. However, Scalable MCA systems include a pair of registers, MCA_DESTAT and MCA_DEADDR, that should be checked for valid errors. This check should be done whenever MCA registers are polled. Currently, the deferred error interrupt does this check, but the MCA polling function does not. Call the MCA polling function when handling the deferred error interrupt. This keeps all "polling" cases in a common function. Call the polling function only for banks that have the deferred error interrupt enabled. Add an SMCA status check helper. This will do the same status check and register clearing that the interrupt handler has done. And it extends the common polling flow to find AMD deferred errors. Remove old code whose functionality is already covered in the common MCA code. Reviewed-by: Qiuxu Zhuo Tested-by: Tony Luck Reviewed-by: Tony Luck Signed-off-by: Yazen Ghannam --- Notes: Link: https://lore.kernel.org/r/20250213-wip-mca-updates-v2-13-3636547fe05f@amd.com v2->v3: * Add tags from Qiuxu and Tony. v1->v2: * Keep code comment. * Log directly from helper function rather than pass values. arch/x86/kernel/cpu/mce/amd.c | 103 ++--------------------------------------- arch/x86/kernel/cpu/mce/core.c | 60 +++++++++++++++++++++++- 2 files changed, 64 insertions(+), 99 deletions(-) diff --git a/arch/x86/kernel/cpu/mce/amd.c b/arch/x86/kernel/cpu/mce/amd.c index f8755a21fd48..62c4fe98d02a 100644 --- a/arch/x86/kernel/cpu/mce/amd.c +++ b/arch/x86/kernel/cpu/mce/amd.c @@ -56,6 +56,7 @@ static bool thresholding_irq_en; struct mce_amd_cpu_data { mce_banks_t thr_intr_banks; + mce_banks_t dfr_intr_banks; }; static DEFINE_PER_CPU_READ_MOSTLY(struct mce_amd_cpu_data, mce_amd_data); @@ -300,8 +301,10 @@ static void smca_configure(unsigned int bank, unsigned int cpu) * APIC based interrupt. First, check that no interrupt has been * set. */ - if ((low & BIT(5)) && !((high >> 5) & 0x3)) + if ((low & BIT(5)) && !((high >> 5) & 0x3)) { + __set_bit(bank, this_cpu_ptr(&mce_amd_data)->dfr_intr_banks); high |= BIT(5); + } this_cpu_ptr(mce_banks_array)[bank].lsb_in_status = !!(low & BIT(8)); @@ -794,37 +797,6 @@ bool amd_mce_usable_address(struct mce *m) return false; } -static void __log_error(unsigned int bank, u64 status, u64 addr, u64 misc) -{ - struct mce_hw_err err; - struct mce *m = &err.m; - - mce_prep_record(&err); - - m->status = status; - m->misc = misc; - m->bank = bank; - m->tsc = rdtsc(); - - if (m->status & MCI_STATUS_ADDRV) { - m->addr = addr; - - smca_extract_err_addr(m); - } - - if (mce_flags.smca) { - rdmsrq(MSR_AMD64_SMCA_MCx_IPID(bank), m->ipid); - - if (m->status & MCI_STATUS_SYNDV) { - rdmsrq(MSR_AMD64_SMCA_MCx_SYND(bank), m->synd); - rdmsrq(MSR_AMD64_SMCA_MCx_SYND1(bank), err.vendor.amd.synd1); - rdmsrq(MSR_AMD64_SMCA_MCx_SYND2(bank), err.vendor.amd.synd2); - } - } - - mce_log(&err); -} - DEFINE_IDTENTRY_SYSVEC(sysvec_deferred_error) { trace_deferred_error_apic_entry(DEFERRED_ERROR_VECTOR); @@ -834,75 +806,10 @@ DEFINE_IDTENTRY_SYSVEC(sysvec_deferred_error) apic_eoi(); } -/* - * Returns true if the logged error is deferred. False, otherwise. - */ -static inline bool -_log_error_bank(unsigned int bank, u32 msr_stat, u32 msr_addr, u64 misc) -{ - u64 status, addr = 0; - - rdmsrq(msr_stat, status); - if (!(status & MCI_STATUS_VAL)) - return false; - - if (status & MCI_STATUS_ADDRV) - rdmsrq(msr_addr, addr); - - __log_error(bank, status, addr, misc); - - wrmsrq(msr_stat, 0); - - return status & MCI_STATUS_DEFERRED; -} - -static bool _log_error_deferred(unsigned int bank, u32 misc) -{ - if (!_log_error_bank(bank, mca_msr_reg(bank, MCA_STATUS), - mca_msr_reg(bank, MCA_ADDR), misc)) - return false; - - /* - * Non-SMCA systems don't have MCA_DESTAT/MCA_DEADDR registers. - * Return true here to avoid accessing these registers. - */ - if (!mce_flags.smca) - return true; - - /* Clear MCA_DESTAT if the deferred error was logged from MCA_STATUS. */ - wrmsrq(MSR_AMD64_SMCA_MCx_DESTAT(bank), 0); - return true; -} - -/* - * We have three scenarios for checking for Deferred errors: - * - * 1) Non-SMCA systems check MCA_STATUS and log error if found. - * 2) SMCA systems check MCA_STATUS. If error is found then log it and also - * clear MCA_DESTAT. - * 3) SMCA systems check MCA_DESTAT, if error was not found in MCA_STATUS, and - * log it. - */ -static void log_error_deferred(unsigned int bank) -{ - if (_log_error_deferred(bank, 0)) - return; - - /* - * Only deferred errors are logged in MCA_DE{STAT,ADDR} so just check - * for a valid error. - */ - _log_error_bank(bank, MSR_AMD64_SMCA_MCx_DESTAT(bank), - MSR_AMD64_SMCA_MCx_DEADDR(bank), 0); -} - /* APIC interrupt handler for deferred errors */ static void amd_deferred_error_interrupt(void) { - unsigned int bank; - - for (bank = 0; bank < this_cpu_read(mce_num_banks); ++bank) - log_error_deferred(bank); + machine_check_poll(MCP_TIMESTAMP, &this_cpu_ptr(&mce_amd_data)->dfr_intr_banks); } static void reset_block(struct threshold_block *block) diff --git a/arch/x86/kernel/cpu/mce/core.c b/arch/x86/kernel/cpu/mce/core.c index de85b014653f..0a2a97681266 100644 --- a/arch/x86/kernel/cpu/mce/core.c +++ b/arch/x86/kernel/cpu/mce/core.c @@ -714,6 +714,61 @@ static noinstr void mce_read_aux(struct mce_hw_err *err, int i) DEFINE_PER_CPU(unsigned, mce_poll_count); +/* + * We have three scenarios for checking for Deferred errors: + * + * 1) Non-SMCA systems check MCA_STATUS and log error if found. + * 2) SMCA systems check MCA_STATUS. If error is found then log it and also + * clear MCA_DESTAT. + * 3) SMCA systems check MCA_DESTAT, if error was not found in MCA_STATUS, and + * log it. + */ +static bool smca_should_log_poll_error(enum mcp_flags flags, struct mce_hw_err *err) +{ + struct mce *m = &err->m; + + /* + * If this is a deferred error found in MCA_STATUS, then clear + * the redundant data from the MCA_DESTAT register. + */ + if (m->status & MCI_STATUS_VAL) { + if (m->status & MCI_STATUS_DEFERRED) + mce_wrmsrq(MSR_AMD64_SMCA_MCx_DESTAT(m->bank), 0); + + return true; + } + + /* + * If the MCA_DESTAT register has valid data, then use + * it as the status register. + */ + m->status = mce_rdmsrq(MSR_AMD64_SMCA_MCx_DESTAT(m->bank)); + + if (!(m->status & MCI_STATUS_VAL)) + return false; + + /* + * Gather all relevant data now and log the record before clearing + * the deferred status register. This avoids needing to go back to + * the polling function for these actions. + */ + mce_read_aux(err, m->bank); + + if (m->status & MCI_STATUS_ADDRV) + m->addr = mce_rdmsrq(MSR_AMD64_SMCA_MCx_DEADDR(m->bank)); + + smca_extract_err_addr(m); + m->severity = mce_severity(m, NULL, NULL, false); + + if (flags & MCP_QUEUE_LOG) + mce_gen_pool_add(err); + else + mce_log(err); + + mce_wrmsrq(MSR_AMD64_SMCA_MCx_DESTAT(m->bank), 0); + return false; +} + /* * Newer Intel systems that support software error * recovery need to make additional checks. Other @@ -740,6 +795,9 @@ static bool should_log_poll_error(enum mcp_flags flags, struct mce_hw_err *err) { struct mce *m = &err->m; + if (mce_flags.smca) + return smca_should_log_poll_error(flags, err); + /* If this entry is not valid, ignore it. */ if (!(m->status & MCI_STATUS_VAL)) return false; @@ -2226,7 +2284,7 @@ void cpu_mca_init(struct cpuinfo_x86 *c) if (mce_flags.smca) mce_smca_cpu_init(); - rdmsrl(MSR_IA32_MCG_CAP, cap); + rdmsrq(MSR_IA32_MCG_CAP, cap); /* Use accurate RIP reporting if available. */ if ((cap & MCG_EXT_P) && MCG_EXT_CNT(cap) >= 9) From patchwork Tue Apr 15 14:55:09 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Yazen Ghannam X-Patchwork-Id: 14052368 Received: from NAM10-MW2-obe.outbound.protection.outlook.com (mail-mw2nam10on2074.outbound.protection.outlook.com [40.107.94.74]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 74C172BCF40; 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Tue, 15 Apr 2025 09:55:16 -0500 From: Yazen Ghannam Date: Tue, 15 Apr 2025 14:55:09 +0000 Subject: [PATCH v3 14/17] x86/mce/amd: Enable interrupt vectors once per-CPU on SMCA systems Precedence: bulk X-Mailing-List: linux-edac@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-ID: <20250415-wip-mca-updates-v3-14-8ffd9eb4aa56@amd.com> References: <20250415-wip-mca-updates-v3-0-8ffd9eb4aa56@amd.com> In-Reply-To: <20250415-wip-mca-updates-v3-0-8ffd9eb4aa56@amd.com> To: , Tony Luck CC: , , , Qiuxu Zhuo X-Mailer: b4 0.15-dev-9b767 X-ClientProxiedBy: SATLEXMB03.amd.com (10.181.40.144) To SATLEXMB04.amd.com (10.181.40.145) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: CH2PEPF0000014A:EE_|BL1PR12MB5753:EE_ X-MS-Office365-Filtering-Correlation-Id: 379edea6-1900-4be1-eda5-08dd7c2d8a00 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|376014|1800799024|36860700013|82310400026|13003099007; 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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 15 Apr 2025 14:55:18.6542 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 379edea6-1900-4be1-eda5-08dd7c2d8a00 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: CH2PEPF0000014A.namprd02.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: BL1PR12MB5753 Scalable MCA systems have a per-CPU register that gives the APIC LVT offset for the thresholding and deferred error interrupts. Currently, this register is read once to set up the deferred error interrupt and then read again for each thresholding block. Furthermore, the APIC LVT registers are configured each time, but they only need to be configured once per-CPU. Move the APIC LVT setup to the early part of CPU init, so that the registers are set up once. Also, this ensures that the kernel is ready to service the interrupts before the individual error sources (each MCA bank) are enabled. Apply this change only to SMCA systems to avoid breaking any legacy behavior. The deferred error interrupt is technically advertised by the SUCCOR feature. However, this was first made available on SMCA systems. Therefore, only set up the deferred error interrupt on SMCA systems and simplify the code. Tested-by: Tony Luck Reviewed-by: Tony Luck Signed-off-by: Yazen Ghannam --- Notes: Link: https://lore.kernel.org/r/20250213-wip-mca-updates-v2-14-3636547fe05f@amd.com v2->v3: * Add tags from Tony. v1->v2: * Use new per-CPU struct. * Don't set up interrupt vectors. arch/x86/kernel/cpu/mce/amd.c | 113 ++++++++++++++++++------------------------ 1 file changed, 48 insertions(+), 65 deletions(-) diff --git a/arch/x86/kernel/cpu/mce/amd.c b/arch/x86/kernel/cpu/mce/amd.c index 62c4fe98d02a..9e226bdbdc40 100644 --- a/arch/x86/kernel/cpu/mce/amd.c +++ b/arch/x86/kernel/cpu/mce/amd.c @@ -43,9 +43,6 @@ /* Deferred error settings */ #define MSR_CU_DEF_ERR 0xC0000410 #define MASK_DEF_LVTOFF 0x000000F0 -#define MASK_DEF_INT_TYPE 0x00000006 -#define DEF_LVT_OFF 0x2 -#define DEF_INT_TYPE_APIC 0x2 /* Scalable MCA: */ @@ -57,6 +54,8 @@ static bool thresholding_irq_en; struct mce_amd_cpu_data { mce_banks_t thr_intr_banks; mce_banks_t dfr_intr_banks; + bool thr_intr_en; + bool dfr_intr_en; }; static DEFINE_PER_CPU_READ_MOSTLY(struct mce_amd_cpu_data, mce_amd_data); @@ -271,6 +270,7 @@ void (*deferred_error_int_vector)(void) = default_deferred_error_interrupt; static void smca_configure(unsigned int bank, unsigned int cpu) { + struct mce_amd_cpu_data *data = this_cpu_ptr(&mce_amd_data); u8 *bank_counts = this_cpu_ptr(smca_bank_counts); const struct smca_hwid *s_hwid; unsigned int i, hwid_mcatype; @@ -301,8 +301,8 @@ static void smca_configure(unsigned int bank, unsigned int cpu) * APIC based interrupt. First, check that no interrupt has been * set. */ - if ((low & BIT(5)) && !((high >> 5) & 0x3)) { - __set_bit(bank, this_cpu_ptr(&mce_amd_data)->dfr_intr_banks); + if ((low & BIT(5)) && !((high >> 5) & 0x3) && data->dfr_intr_en) { + __set_bit(bank, data->dfr_intr_banks); high |= BIT(5); } @@ -378,6 +378,14 @@ static bool lvt_off_valid(struct threshold_block *b, int apic, u32 lo, u32 hi) { int msr = (hi & MASK_LVTOFF_HI) >> 20; + /* + * On SMCA CPUs, LVT offset is programmed at a different MSR, and + * the BIOS provides the value. The original field where LVT offset + * was set is reserved. Return early here: + */ + if (mce_flags.smca) + return false; + if (apic < 0) { pr_err(FW_BUG "cpu %d, failed to setup threshold interrupt " "for bank %d, block %d (MSR%08X=0x%x%08x)\n", b->cpu, @@ -386,14 +394,6 @@ static bool lvt_off_valid(struct threshold_block *b, int apic, u32 lo, u32 hi) } if (apic != msr) { - /* - * On SMCA CPUs, LVT offset is programmed at a different MSR, and - * the BIOS provides the value. The original field where LVT offset - * was set is reserved. Return early here: - */ - if (mce_flags.smca) - return false; - pr_err(FW_BUG "cpu %d, invalid threshold interrupt offset %d " "for bank %d, block %d (MSR%08X=0x%x%08x)\n", b->cpu, apic, b->bank, b->block, b->address, hi, lo); @@ -474,41 +474,6 @@ static int setup_APIC_mce_threshold(int reserved, int new) return reserved; } -static int setup_APIC_deferred_error(int reserved, int new) -{ - if (reserved < 0 && !setup_APIC_eilvt(new, DEFERRED_ERROR_VECTOR, - APIC_EILVT_MSG_FIX, 0)) - return new; - - return reserved; -} - -static void deferred_error_interrupt_enable(struct cpuinfo_x86 *c) -{ - u32 low = 0, high = 0; - int def_offset = -1, def_new; - - if (rdmsr_safe(MSR_CU_DEF_ERR, &low, &high)) - return; - - def_new = (low & MASK_DEF_LVTOFF) >> 4; - if (!(low & MASK_DEF_LVTOFF)) { - pr_err(FW_BUG "Your BIOS is not setting up LVT offset 0x2 for deferred error IRQs correctly.\n"); - def_new = DEF_LVT_OFF; - low = (low & ~MASK_DEF_LVTOFF) | (DEF_LVT_OFF << 4); - } - - def_offset = setup_APIC_deferred_error(def_offset, def_new); - if ((def_offset == def_new) && - (deferred_error_int_vector != amd_deferred_error_interrupt)) - deferred_error_int_vector = amd_deferred_error_interrupt; - - if (!mce_flags.smca) - low = (low & ~MASK_DEF_INT_TYPE) | DEF_INT_TYPE_APIC; - - wrmsr(MSR_CU_DEF_ERR, low, high); -} - static u32 smca_get_block_address(unsigned int bank, unsigned int block, unsigned int cpu) { @@ -551,7 +516,6 @@ prepare_threshold_block(unsigned int bank, unsigned int block, u32 addr, int offset, u32 misc_high) { unsigned int cpu = smp_processor_id(); - u32 smca_low, smca_high; struct threshold_block b; int new; @@ -571,18 +535,10 @@ prepare_threshold_block(unsigned int bank, unsigned int block, u32 addr, __set_bit(bank, this_cpu_ptr(&mce_amd_data)->thr_intr_banks); b.interrupt_enable = 1; - if (!mce_flags.smca) { - new = (misc_high & MASK_LVTOFF_HI) >> 20; - goto set_offset; - } - - /* Gather LVT offset for thresholding: */ - if (rdmsr_safe(MSR_CU_DEF_ERR, &smca_low, &smca_high)) - goto out; - - new = (smca_low & SMCA_THR_LVT_OFF) >> 12; + if (mce_flags.smca) + goto done; -set_offset: + new = (misc_high & MASK_LVTOFF_HI) >> 20; offset = setup_APIC_mce_threshold(offset, new); if (offset == new) thresholding_irq_en = true; @@ -590,7 +546,6 @@ prepare_threshold_block(unsigned int bank, unsigned int block, u32 addr, done: mce_threshold_block_init(&b, offset); -out: return offset; } @@ -659,6 +614,32 @@ static void disable_err_thresholding(struct cpuinfo_x86 *c, unsigned int bank) wrmsrq(MSR_K7_HWCR, hwcr); } +/* + * Enable the APIC LVT interrupt vectors once per-CPU. This should be done before hardware is + * ready to send interrupts. + * + * Individual error sources are enabled later during per-bank init. + */ +static void smca_enable_interrupt_vectors(void) +{ + struct mce_amd_cpu_data *data = this_cpu_ptr(&mce_amd_data); + u64 mca_intr_cfg, offset; + + if (!mce_flags.smca || !mce_flags.succor) + return; + + if (rdmsrq_safe(MSR_CU_DEF_ERR, &mca_intr_cfg)) + return; + + offset = (mca_intr_cfg & SMCA_THR_LVT_OFF) >> 12; + if (!setup_APIC_eilvt(offset, THRESHOLD_APIC_VECTOR, APIC_EILVT_MSG_FIX, 0)) + data->thr_intr_en = true; + + offset = (mca_intr_cfg & MASK_DEF_LVTOFF) >> 4; + if (!setup_APIC_eilvt(offset, DEFERRED_ERROR_VECTOR, APIC_EILVT_MSG_FIX, 0)) + data->dfr_intr_en = true; +} + static void amd_apply_quirks(struct cpuinfo_x86 *c) { struct mce_bank *mce_banks = this_cpu_ptr(mce_banks_array); @@ -690,11 +671,16 @@ void mce_amd_feature_init(struct cpuinfo_x86 *c) amd_apply_quirks(c); mce_flags.amd_threshold = 1; + smca_enable_interrupt_vectors(); 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Tue, 15 Apr 2025 09:55:17 -0500 From: Yazen Ghannam Date: Tue, 15 Apr 2025 14:55:10 +0000 Subject: [PATCH v3 15/17] x86/mce/amd: Support SMCA Corrected Error Interrupt Precedence: bulk X-Mailing-List: linux-edac@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-ID: <20250415-wip-mca-updates-v3-15-8ffd9eb4aa56@amd.com> References: <20250415-wip-mca-updates-v3-0-8ffd9eb4aa56@amd.com> In-Reply-To: <20250415-wip-mca-updates-v3-0-8ffd9eb4aa56@amd.com> To: , Tony Luck CC: , , , Qiuxu Zhuo X-Mailer: b4 0.15-dev-9b767 X-ClientProxiedBy: SATLEXMB03.amd.com (10.181.40.144) To SATLEXMB04.amd.com (10.181.40.145) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: CH2PEPF00000146:EE_|BY5PR12MB4099:EE_ X-MS-Office365-Filtering-Correlation-Id: db9c5556-9b29-4b72-ae2d-08dd7c2d8a04 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|36860700013|1800799024|82310400026|376014|13003099007; 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This feature counts errors of all severities, but it is commonly used to report correctable errors with an interrupt rather than polling. Scalable MCA systems allow the Platform to take control of this feature. In this case, the OS will not see the feature configuration and control bits in the MCA_MISC* registers. The OS will not receive the MCA thresholding interrupt, and it will need to poll for correctable errors. A "corrected error interrupt" will be available on Scalable MCA systems. This will be used in the same configuration where the Platform controls MCA thresholding. However, the Platform will now be able to send the MCA thresholding interrupt to the OS. Check for the feature bit in the MCA_CONFIG register and confirm that the MCA thresholding interrupt handler is already enabled. If successful, set the feature enable bit in the MCA_CONFIG register to indicate to the Platform that the OS is ready for the interrupt. Tested-by: Tony Luck Reviewed-by: Tony Luck Signed-off-by: Yazen Ghannam --- Notes: Link: https://lore.kernel.org/r/20250213-wip-mca-updates-v2-15-3636547fe05f@amd.com v2->v3: * Add tags from Tony. v1->v2: * Use new per-CPU struct. arch/x86/kernel/cpu/mce/amd.c | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/arch/x86/kernel/cpu/mce/amd.c b/arch/x86/kernel/cpu/mce/amd.c index 9e226bdbdc40..d76a64c47a6d 100644 --- a/arch/x86/kernel/cpu/mce/amd.c +++ b/arch/x86/kernel/cpu/mce/amd.c @@ -306,6 +306,11 @@ static void smca_configure(unsigned int bank, unsigned int cpu) high |= BIT(5); } + if ((low & BIT(10)) && data->thr_intr_en) { + __set_bit(bank, data->thr_intr_banks); + high |= BIT(8); + } + this_cpu_ptr(mce_banks_array)[bank].lsb_in_status = !!(low & BIT(8)); wrmsr(smca_config, low, high); From patchwork Tue Apr 15 14:55:11 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Yazen Ghannam X-Patchwork-Id: 14052366 Received: from NAM10-BN7-obe.outbound.protection.outlook.com (mail-bn7nam10on2074.outbound.protection.outlook.com [40.107.92.74]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id CEE5D29E069; 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Tue, 15 Apr 2025 09:55:17 -0500 From: Yazen Ghannam Date: Tue, 15 Apr 2025 14:55:11 +0000 Subject: [PATCH v3 16/17] x86/mce: Handle AMD threshold interrupt storms Precedence: bulk X-Mailing-List: linux-edac@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-ID: <20250415-wip-mca-updates-v3-16-8ffd9eb4aa56@amd.com> References: <20250415-wip-mca-updates-v3-0-8ffd9eb4aa56@amd.com> In-Reply-To: <20250415-wip-mca-updates-v3-0-8ffd9eb4aa56@amd.com> To: , Tony Luck CC: , , , Qiuxu Zhuo X-Mailer: b4 0.15-dev-9b767 X-ClientProxiedBy: SATLEXMB03.amd.com (10.181.40.144) To SATLEXMB04.amd.com (10.181.40.145) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: CH2PEPF0000014A:EE_|CY5PR12MB6274:EE_ X-MS-Office365-Filtering-Correlation-Id: 4905a765-44fa-470c-600d-08dd7c2d8a54 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|376014|1800799024|82310400026|36860700013|7053199007; X-Microsoft-Antispam-Message-Info: =?utf-8?q?+S44jFc8kprlgKYiiGM1HiZnvGwqBy7?= =?utf-8?q?2yaXuhDB54MIPZCVSZatnG6XkwqEkMCZr9NScrBi1n6z5ka7hEYMkywO7x1LCbP65?= =?utf-8?q?Qh4Na5lZewFoiuTmVZh+pfhNIanzp3kAwa9EesY+u8mqOe1IxYQm/Vkzjc6aDFnfB?= =?utf-8?q?DN15IYoUp+9UbBhpY/dxVvxQVXkZSfx/okMGxjpqC/9U98SE2VGeQsU3yo41BX52W?= =?utf-8?q?KKJEOatqJRI8V/MSHkyhVSwm0lynEJ3cgodDzH0JOTDd1NO4DjczyerhjK/DU7JAa?= =?utf-8?q?rQ1B2df3XitGD3Yv+976wxUlFrOsSFDB3oKFUQimsmZFEkuLeRdZh+HYP1vB/lOZS?= =?utf-8?q?axliRPGO1tITVaaTWC9yn/PYGMqyYjsTGXAabGaWaQ+kgkUyGv3Xp2i+mup59ps1Z?= =?utf-8?q?FKrTcZXBdK6HVzDT28KoPY4DhSVt5cW6ZHGWSsJc4wNd1WxCaidgyA1aeAamJ5Ocr?= =?utf-8?q?mKnCseMSzX608oR7dyG8i85MfZ1dPX62+LwnFmmc4Z9FYktZSiytVvbJJDiexRDxl?= =?utf-8?q?ll+YTnUF7vhujihBd4M9R3Ty/6C5Y8gH41CE4I6RrMp4BCxI4KLYPjuMBcwHE7hIX?= =?utf-8?q?2j9kjnXDYobrK1OR1dT6DqmMcRIWrseEBEqWraGj/GB1gAR/dAfxjapU4b96OaMA6?= =?utf-8?q?Gu535TL0BCuvbcm64RUuXCkzrAZ6wbOdkVV4p66ZW2JR+016q7E9K5CHZaTUHvTHB?= =?utf-8?q?g3JikdSRnBh0rXY2AvuChzMsF8un4yPd5u4atb9nMg/MB3Mk1EpJON+Wh8+od4CPL?= =?utf-8?q?kEC3VLIB4CjQ/aDtYLu1WxH/TfVsNa5eEaS5W7kWqDg4URIvIo3eUDsDhG3mi8Gs8?= =?utf-8?q?+47ecb5fFAL0h43o69vJ29gXiWTXhiOzScux/TOTa5yZ+jQ34pHyzdTNZF5b71ku5?= =?utf-8?q?BVFk3buuz9Oj06zYgkgMi5g0N7UwDgfXSXUUYc9i2JW7C2U6GNm2uOzkH0r7D9Cnr?= =?utf-8?q?eO22Bq44fuoet/TASi+liK2Sg8Ql4Nuw8h60buh/Yhz9U199+T/ERQTu1HLlsRrPe?= =?utf-8?q?mQb/62Qq6nQoGZ2sox7OMWirrKTNKFQFymDSgyWWuPOw00XmmckBWzXuawwO/7fe4?= =?utf-8?q?Rpp4u8geqyLTBicIs8A6ZlGhf7RT9Tqko5Q9v/scEd+a4jGdttHGSP2wC+Z8cmBUy?= =?utf-8?q?e7D1X8xiQjPwethHtbhySfEUeD45l9BxDd+TL2GaeJV+oKtD/lVnf+wok6qUguM2s?= =?utf-8?q?UF1hzq3BsKO7oI9nDsblG0whIoopNKgKjCRddQm2Mwe+uFP77Rq/pFpvniZCmWToC?= =?utf-8?q?RZ6wzR6pQR7VPoMWTL/WJMj0il40Rs5z5QKVcVEpCNDobP88LBc7nFu+EiLAz81gE?= =?utf-8?q?xbUUM0JmCQO5lGNYfaLU9W0hXobpRROmVcNabXuP375U7urpsgFON8Dpx7RS0y/af?= =?utf-8?q?2L8qSsLpWKCi4vUuQgu3mJphW3jclqRWwANOfrykWxYdIWbUfJgklhm8ZUCDp/U4A?= =?utf-8?q?6XcO+KikOEkrNsTLGuCtZD1In2gN9MUw=3D=3D?= X-Forefront-Antispam-Report: CIP:165.204.84.17;CTRY:US;LANG:en;SCL:1;SRV:;IPV:CAL;SFV:NSPM;H:SATLEXMB04.amd.com;PTR:InfoDomainNonexistent;CAT:NONE;SFS:(13230040)(376014)(1800799024)(82310400026)(36860700013)(7053199007);DIR:OUT;SFP:1101; X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 15 Apr 2025 14:55:19.2011 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 4905a765-44fa-470c-600d-08dd7c2d8a54 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: CH2PEPF0000014A.namprd02.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: CY5PR12MB6274 From: Smita Koralahalli Extend the logic of handling CMCI storms to AMD threshold interrupts. Rely on the similar approach as of Intel's CMCI to mitigate storms per CPU and per bank. But, unlike CMCI, do not set thresholds and reduce interrupt rate on a storm. Rather, disable the interrupt on the corresponding CPU and bank. Re-enable back the interrupts if enough consecutive polls of the bank show no corrected errors (30, as programmed by Intel). Turning off the threshold interrupts would be a better solution on AMD systems as other error severities will still be handled even if the threshold interrupts are disabled. [Tony: Small tweak because mce_handle_storm() isn't a pointer now] [Yazen: Rebase and simplify] Reviewed-by: Qiuxu Zhuo Signed-off-by: Smita Koralahalli Signed-off-by: Tony Luck Signed-off-by: Yazen Ghannam --- Notes: Link: https://lore.kernel.org/r/20250213-wip-mca-updates-v2-16-3636547fe05f@amd.com v2->v3: * Add tag from Qiuxu. v1->v2: * New in v2, but based on older patch. * Rebased on current set and simplified. * Kept old tags. arch/x86/kernel/cpu/mce/amd.c | 18 ++++++++++++++++++ arch/x86/kernel/cpu/mce/internal.h | 2 ++ arch/x86/kernel/cpu/mce/threshold.c | 3 +++ 3 files changed, 23 insertions(+) diff --git a/arch/x86/kernel/cpu/mce/amd.c b/arch/x86/kernel/cpu/mce/amd.c index d76a64c47a6d..93f6cececad4 100644 --- a/arch/x86/kernel/cpu/mce/amd.c +++ b/arch/x86/kernel/cpu/mce/amd.c @@ -1218,3 +1218,21 @@ void mce_threshold_create_device(unsigned int cpu) mce_threshold_vector = amd_threshold_interrupt; return; } + +void mce_amd_handle_storm(unsigned int bank, bool on) +{ + struct threshold_bank **thr_banks = this_cpu_read(threshold_banks); + struct threshold_block *block, *tmp; + struct thresh_restart tr; + + if (!thr_banks || !thr_banks[bank]) + return; + + memset(&tr, 0, sizeof(tr)); + + list_for_each_entry_safe(block, tmp, &thr_banks[bank]->miscj, miscj) { + tr.b = block; + tr.b->interrupt_enable = on; + threshold_restart_bank(&tr); + } +} diff --git a/arch/x86/kernel/cpu/mce/internal.h b/arch/x86/kernel/cpu/mce/internal.h index aeb0a998f553..0dd77fa18d06 100644 --- a/arch/x86/kernel/cpu/mce/internal.h +++ b/arch/x86/kernel/cpu/mce/internal.h @@ -267,6 +267,7 @@ void mce_prep_record_per_cpu(unsigned int cpu, struct mce *m); #ifdef CONFIG_X86_MCE_AMD void mce_threshold_create_device(unsigned int cpu); void mce_threshold_remove_device(unsigned int cpu); +void mce_amd_handle_storm(unsigned int bank, bool on); extern bool amd_filter_mce(struct mce *m); bool amd_mce_usable_address(struct mce *m); void amd_reset_thr_limit(unsigned int bank); @@ -299,6 +300,7 @@ void mce_smca_cpu_init(void); #else static inline void mce_threshold_create_device(unsigned int cpu) { } static inline void mce_threshold_remove_device(unsigned int cpu) { } +static inline void mce_amd_handle_storm(unsigned int bank, bool on) { } static inline bool amd_filter_mce(struct mce *m) { return false; } static inline bool amd_mce_usable_address(struct mce *m) { return false; } static inline void amd_reset_thr_limit(unsigned int bank) { } diff --git a/arch/x86/kernel/cpu/mce/threshold.c b/arch/x86/kernel/cpu/mce/threshold.c index f4a007616468..45144598ec74 100644 --- a/arch/x86/kernel/cpu/mce/threshold.c +++ b/arch/x86/kernel/cpu/mce/threshold.c @@ -63,6 +63,9 @@ static void mce_handle_storm(unsigned int bank, bool on) case X86_VENDOR_INTEL: mce_intel_handle_storm(bank, on); break; + case X86_VENDOR_AMD: + mce_amd_handle_storm(bank, on); + break; } } From patchwork Tue Apr 15 14:55:12 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Yazen Ghannam X-Patchwork-Id: 14052371 Received: from NAM12-MW2-obe.outbound.protection.outlook.com (mail-mw2nam12on2076.outbound.protection.outlook.com [40.107.244.76]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id D872E2BCF76; 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Tue, 15 Apr 2025 09:55:18 -0500 From: Yazen Ghannam Date: Tue, 15 Apr 2025 14:55:12 +0000 Subject: [PATCH v3 17/17] x86/mce: Restore poll settings after storm subsides Precedence: bulk X-Mailing-List: linux-edac@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-ID: <20250415-wip-mca-updates-v3-17-8ffd9eb4aa56@amd.com> References: <20250415-wip-mca-updates-v3-0-8ffd9eb4aa56@amd.com> In-Reply-To: <20250415-wip-mca-updates-v3-0-8ffd9eb4aa56@amd.com> To: , Tony Luck CC: , , , Qiuxu Zhuo X-Mailer: b4 0.15-dev-9b767 X-ClientProxiedBy: SATLEXMB03.amd.com (10.181.40.144) To SATLEXMB04.amd.com (10.181.40.145) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: CH2PEPF00000146:EE_|LV3PR12MB9142:EE_ X-MS-Office365-Filtering-Correlation-Id: f42f6581-8ae0-4500-0c8d-08dd7c2d8a64 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|1800799024|376014|36860700013|82310400026; X-Microsoft-Antispam-Message-Info: =?utf-8?q?7z3nyqIFmKBqhxFZe50pXiZ5+iYMbZs?= =?utf-8?q?men30iT9FPuoaRECyOwL+ajVqfBYag5k1DUeaNkWMJOG9LBZDjKp/fmHmp3U0DiJK?= =?utf-8?q?P7zI3ljmYXgfmT44fJ/eRzlR9Apnr3dnEdcE7hOrrK8GnpUrsmmpomTgv9Ik73C/+?= =?utf-8?q?WeUwhQ4ODRTUAhmmJKxBsqEnrMmjb3nebW88MH1sEvFaS3lTdf+YuzcDy0MF/KZmI?= =?utf-8?q?EY8ddlt2rAuN1TZSg059zu771QtOoIDVz4irpi70Xf9CQsFZ0dtmgCSZ1GUSMbF1q?= =?utf-8?q?iy5OqKXAA/aDiRU/LJc3yaDdRH9y3fmUWMA/KnxiqmbPOHkAxAa2zAPChjhIba9ne?= =?utf-8?q?qijgi7MmqiXkOCqiOWi0wpTrMz/QORyMEXUuZVjQRbMWlBVonC2eP+Mx6qSC2gL7P?= =?utf-8?q?K+8ng79KJI1Js2F/0/orG7GCay8F4PD+Y8/ojDVv7Rmgupi6p/uLWJsgIc+5LB9l5?= =?utf-8?q?yUT92LPZAK1kg37yeHYMm22uRtmxGvJ8OT3PXoVVkQlUz0HvBx8taZngKTHDOW/J3?= =?utf-8?q?6jArA7d1GQ0zVW5zzREIf0dE2vdxEzzpC6zCX0oJQsb3k0fWKn5e3YS0ZCiJ456AZ?= =?utf-8?q?nwM2ynu+S7E/qKSNamWUBuBE8/1ML/s/Xi2qbagGHhhmzrlzo3/wSyLlegJaipO4H?= =?utf-8?q?/e1wbE43nqijIRds2Gfmbej97h/QjmT7jR/KiR1CL5FlxMyxZTKX6fU95ccpuRSoY?= =?utf-8?q?qIwDb/h/CrszuV8AXNU0h71iRsJl8yUMlrdN2hU+cA4ilVbpOxpGkloyjWSNvBECT?= =?utf-8?q?cA7PpJ+V44nPfrnd85BI9Qn66cs0K8u+nW06MIN18178CqNCsk/zesGEADyYGHcjO?= =?utf-8?q?P0YLtPe1/MaXMzFJjODQAOfYWanVUmnJ3yMVp+1UCplc10vCueBBsC+ngf6LMVCjg?= =?utf-8?q?FZGtEyCXNyQgTgzazMGYPefCP0GY3lYKtjJQM/Wtsld6muUtOu9SjB419PfUj1N5J?= =?utf-8?q?gpkMnQLmkmNYoLbV6yAd4UU9o+D7N2PtfOl8aGWP8hzSojAVDhorSNpWBE6COPvKf?= =?utf-8?q?savukIGtyUA0o2lMid2RGxmymNk8OroG/TVv4Br+XeKC6iyo/0dmbf/5r6fRkSFnm?= =?utf-8?q?6xFdeCOpjvdqUryjLisxFFqllGfHoQtEfOPLvU8uXDURu6SgAz4N8nPBnmF7XL9wt?= =?utf-8?q?nFBotvF8+uieffkQNzWjlzRZngOdIt8ym92gw63//G1ZBGivZEsUa94iL4UjXILlw?= =?utf-8?q?ScGL/f1texTOiVbaLxyXPAk2kEZBAL56qNf57y3V7pbA2bsz4bWVNiy9DaCYeC0GM?= =?utf-8?q?K9gMqzbNsYH0QD26CRuCn/l/LEpKpaahhFY1hCD+HlsnxO6dBuKZT0Hw2A+rPtW6b?= =?utf-8?q?OT9BoSpKs0JY+G5SA5wHDv88Wpq1btd11XO8NRFNNPuocRdcYfJrY3T//wlBJNFlg?= =?utf-8?q?7SBRTy6TmCWgm8BkEQW/YM4kroJrcNTcde/j5xcxvXDWKM7VkdIUH3ONZz1BLCBP1?= =?utf-8?q?U6qLH5ZGly?= X-Forefront-Antispam-Report: CIP:165.204.84.17;CTRY:US;LANG:en;SCL:1;SRV:;IPV:CAL;SFV:NSPM;H:SATLEXMB04.amd.com;PTR:InfoDomainNonexistent;CAT:NONE;SFS:(13230040)(1800799024)(376014)(36860700013)(82310400026);DIR:OUT;SFP:1101; X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 15 Apr 2025 14:55:19.3039 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: f42f6581-8ae0-4500-0c8d-08dd7c2d8a64 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: CH2PEPF00000146.namprd02.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: LV3PR12MB9142 Users can disable MCA polling by setting the "ignore_ce" parameter or by setting "check_interval=0". This tells the kernel to *not* start the MCE timer on a CPU. During a CMCI storm, the MCE timer will be started with a fixed interval. After the storm subsides, the timer's next interval is set to check_interval. This disregards the user's input through "ignore_ce" and "check_interval". Furthermore, if "check_interval=0", then the new timer will run faster than expected. Create a new helper to check these conditions and use it when a CMCI storm ends. Fixes: 7eae17c4add5 ("x86/mce: Add per-bank CMCI storm mitigation") Signed-off-by: Yazen Ghannam Cc: stable@vger.kernel.org --- Notes: v2->v3: * New in v3. arch/x86/kernel/cpu/mce/core.c | 9 +++++++-- 1 file changed, 7 insertions(+), 2 deletions(-) diff --git a/arch/x86/kernel/cpu/mce/core.c b/arch/x86/kernel/cpu/mce/core.c index 0a2a97681266..131015f5eadc 100644 --- a/arch/x86/kernel/cpu/mce/core.c +++ b/arch/x86/kernel/cpu/mce/core.c @@ -1806,6 +1806,11 @@ static void mc_poll_banks_default(void) void (*mc_poll_banks)(void) = mc_poll_banks_default; +static bool should_enable_timer(unsigned long iv) +{ + return !mca_cfg.ignore_ce && iv; +} + static void mce_timer_fn(struct timer_list *t) { struct timer_list *cpu_t = this_cpu_ptr(&mce_timer); @@ -1829,7 +1834,7 @@ static void mce_timer_fn(struct timer_list *t) if (mce_get_storm_mode()) { __start_timer(t, HZ); - } else { + } else if (should_enable_timer(iv)) { __this_cpu_write(mce_next_interval, iv); __start_timer(t, iv); } @@ -2142,7 +2147,7 @@ static void mce_start_timer(struct timer_list *t) { unsigned long iv = check_interval * HZ; - if (mca_cfg.ignore_ce || !iv) + if (!should_enable_timer(iv)) return; this_cpu_write(mce_next_interval, iv);