From patchwork Thu Apr 17 11:44:49 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Ville Syrjala X-Patchwork-Id: 14055384 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 944C4C369CB for ; Thu, 17 Apr 2025 11:45:02 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 254EE10EADA; Thu, 17 Apr 2025 11:45:02 +0000 (UTC) Authentication-Results: gabe.freedesktop.org; dkim=pass (2048-bit key; unprotected) header.d=intel.com header.i=@intel.com header.b="fs7NqfIB"; dkim-atps=neutral Received: from mgamail.intel.com (mgamail.intel.com [192.198.163.14]) by gabe.freedesktop.org (Postfix) with ESMTPS id 7C8E410EAD8 for ; Thu, 17 Apr 2025 11:45:00 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1744890301; x=1776426301; h=from:to:subject:date:message-id:in-reply-to:references: mime-version:content-transfer-encoding; bh=NObvFPHtUcjsfZmWyfSWP86janfUZ22MtQb6vC6rqHk=; b=fs7NqfIB4RQaX1mYv0MWmKvaaKKshBMFUXU0/oIwilhMSRoXoeMUXMW1 kRPFww/3CS9T7by96idyBUTjkAHzRlp9segPHFLenrgVliedPzRZewJWr A3AXIV4Y8ejcF1T7mx5NpArW/PyugogfzmluE2HkQ91g35O9fyyi+Qw60 oaAqoYKZLyuPDEn4MvUCKIR868Fnig7DLNCmaklZ6cCmO0OhDFYqLKwNC oqQgArgQk6iKQbaIYTofT+R6g0yDpDyXH3RCtvwACMIG1cnEAvH0lenYQ uxinPaXp1zeg7dTLrYQ8AASgQL+++Psrjc7V/M9Do+jgGir455Nv55ktr g==; X-CSE-ConnectionGUID: n9QzpHaYSsmppkJEf1fMsw== X-CSE-MsgGUID: cVjfw9fFQWyqbYtJ6hQQBQ== X-IronPort-AV: E=McAfee;i="6700,10204,11405"; a="46638239" X-IronPort-AV: E=Sophos;i="6.15,219,1739865600"; d="scan'208";a="46638239" Received: from orviesa005.jf.intel.com ([10.64.159.145]) by fmvoesa108.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 17 Apr 2025 04:45:00 -0700 X-CSE-ConnectionGUID: Pl59+z4kRhGiCSQlpX5FaA== X-CSE-MsgGUID: Hk63wjtqSiWY8gr19ZmyfA== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.15,219,1739865600"; d="scan'208";a="135943581" Received: from stinkpipe.fi.intel.com (HELO stinkbox) ([10.237.72.74]) by orviesa005.jf.intel.com with SMTP; 17 Apr 2025 04:44:59 -0700 Received: by stinkbox (sSMTP sendmail emulation); Thu, 17 Apr 2025 14:44:57 +0300 From: Ville Syrjala To: intel-gfx@lists.freedesktop.org Subject: [PATCH 1/6] drm/i915/vga: Clean up VGACNTRL bits Date: Thu, 17 Apr 2025 14:44:49 +0300 Message-ID: <20250417114454.12836-2-ville.syrjala@linux.intel.com> X-Mailer: git-send-email 2.49.0 In-Reply-To: <20250417114454.12836-1-ville.syrjala@linux.intel.com> References: <20250417114454.12836-1-ville.syrjala@linux.intel.com> MIME-Version: 1.0 X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" From: Ville Syrjälä Use REG_BIT() & co. for the VGACNTRL register bits. Signed-off-by: Ville Syrjälä Reviewed-by: Jani Nikula --- drivers/gpu/drm/i915/i915_reg.h | 7 ++++--- 1 file changed, 4 insertions(+), 3 deletions(-) diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index 49beab8e324d..81765f27b258 100644 --- a/drivers/gpu/drm/i915/i915_reg.h +++ b/drivers/gpu/drm/i915/i915_reg.h @@ -1814,9 +1814,10 @@ /* VBIOS regs */ #define VGACNTRL _MMIO(0x71400) -# define VGA_DISP_DISABLE (1 << 31) -# define VGA_2X_MODE (1 << 30) -# define VGA_PIPE_B_SELECT (1 << 29) +#define VGA_DISP_DISABLE REG_BIT(31) +#define VGA_2X_MODE REG_BIT(30) +#define VGA_PIPE_SEL_MASK REG_BIT(29) +#define VGA_PIPE_SEL(pipe) REG_FIELD_PREP(VGA_PIPE_SEL_MASK, (pipe)) #define VLV_VGACNTRL _MMIO(VLV_DISPLAY_BASE + 0x71400) From patchwork Thu Apr 17 11:44:50 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Ville Syrjala X-Patchwork-Id: 14055385 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 8D8A5C369C2 for ; Thu, 17 Apr 2025 11:45:05 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 25E5710EAD8; Thu, 17 Apr 2025 11:45:05 +0000 (UTC) Authentication-Results: gabe.freedesktop.org; dkim=pass (2048-bit key; unprotected) header.d=intel.com header.i=@intel.com header.b="UC7PfEyl"; dkim-atps=neutral Received: from mgamail.intel.com (mgamail.intel.com [192.198.163.14]) by gabe.freedesktop.org (Postfix) with ESMTPS id ADFE710EAD8 for ; Thu, 17 Apr 2025 11:45:03 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1744890304; x=1776426304; h=from:to:subject:date:message-id:in-reply-to:references: mime-version:content-transfer-encoding; bh=y1IeOO8iqF3GtF2oDGtOhboWVHyldF9LCOWBffadmvQ=; b=UC7PfEylcflvlQvOOvZCwuZ3j9Gu6VPEOI1Uqmt8Rhbf/XCoCF1gjXY/ rue8dNOYv3Ro35Sn9p35uTf8LT+91QQNmkY7o8oq37EjmKWci7n/HV+MM zbTMDg1MNOBj+OLTBb8FhGqt7dmnJDBhfYyRp+Fo8UzQb2X2U8y/kFg3j o8DvKQu31mAakH2x9ZxZgiHXz60RzmB2hOzlYIWQLSlSZvas0FWBEo0f8 K7JpMue6xBCmmILPJntOjKi8yruku4KohZQLdruflUIwXZxFOlVVxDnqm hfnv1itkhoWp09K33OaEiHhSso6WjPc0axCOO2ML5QEpx+EsAa5R3ONHf A==; X-CSE-ConnectionGUID: PNyzydrLRzGfyy1A7iEDbw== X-CSE-MsgGUID: TPMDCg2kQXK6uCe7N1QIKw== X-IronPort-AV: E=McAfee;i="6700,10204,11405"; a="46638246" X-IronPort-AV: E=Sophos;i="6.15,219,1739865600"; d="scan'208";a="46638246" Received: from orviesa005.jf.intel.com ([10.64.159.145]) by fmvoesa108.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 17 Apr 2025 04:45:04 -0700 X-CSE-ConnectionGUID: jBH8fIWATNusYdGytG8zPA== X-CSE-MsgGUID: iHJXtCmtTPC7s3kcZW//bg== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.15,219,1739865600"; d="scan'208";a="135943596" Received: from stinkpipe.fi.intel.com (HELO stinkbox) ([10.237.72.74]) by orviesa005.jf.intel.com with SMTP; 17 Apr 2025 04:45:02 -0700 Received: by stinkbox (sSMTP sendmail emulation); Thu, 17 Apr 2025 14:45:00 +0300 From: Ville Syrjala To: intel-gfx@lists.freedesktop.org Subject: [PATCH 2/6] drm/i915/vga: Add more VGACNTRL bits Date: Thu, 17 Apr 2025 14:44:50 +0300 Message-ID: <20250417114454.12836-3-ville.syrjala@linux.intel.com> X-Mailer: git-send-email 2.49.0 In-Reply-To: <20250417114454.12836-1-ville.syrjala@linux.intel.com> References: <20250417114454.12836-1-ville.syrjala@linux.intel.com> MIME-Version: 1.0 X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" From: Ville Syrjälä Define a pile of extra VGACNTRL bits. We don't really have any real use for most of these but nicer to have them all in one place rather than trawling the specs when one wants to know what's in there. I will have some real use for the CHV pipe select bits later. Signed-off-by: Ville Syrjälä Reviewed-by: Jani Nikula --- drivers/gpu/drm/i915/i915_reg.h | 21 +++++++++++++++++++-- 1 file changed, 19 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index 81765f27b258..a533889c2793 100644 --- a/drivers/gpu/drm/i915/i915_reg.h +++ b/drivers/gpu/drm/i915/i915_reg.h @@ -1815,9 +1815,26 @@ /* VBIOS regs */ #define VGACNTRL _MMIO(0x71400) #define VGA_DISP_DISABLE REG_BIT(31) -#define VGA_2X_MODE REG_BIT(30) -#define VGA_PIPE_SEL_MASK REG_BIT(29) +#define VGA_2X_MODE REG_BIT(30) /* pre-ilk */ +#define VGA_PIPE_SEL_MASK REG_BIT(29) /* pre-ivb */ #define VGA_PIPE_SEL(pipe) REG_FIELD_PREP(VGA_PIPE_SEL_MASK, (pipe)) +#define VGA_PIPE_SEL_MASK_CHV REG_GENMASK(29, 28) /* chv */ +#define VGA_PIPE_SEL_CHV(pipe) REG_FIELD_PREP(VGA_PIPE_SEL_MASK_CHV, (pipe)) +#define VGA_BORDER_ENABLE REG_BIT(26) +#define VGA_PIPE_CSC_ENABLE REG_BIT(24) /* ilk+ */ +#define VGA_CENTERING_ENABLE_MASK REG_GENMASK(25, 24) /* pre-ilk */ +#define VGA_PALETTE_READ_SEL REG_BIT(23) /* pre-ivb */ +#define VGA_PALETTE_A_WRITE_DISABLE REG_BIT(22) /* pre-ivb */ +#define VGA_PALETTE_B_WRITE_DISABLE REG_BIT(21) /* pre-ivb */ +#define VGA_LEGACY_8BIT_PALETTE_ENABLE REG_BIT(20) +#define VGA_PALETTE_BYPASS REG_BIT(19) +#define VGA_NINE_DOT_DISABLE REG_BIT(18) +#define VGA_PALETTE_READ_SEL_HI_CHV REG_BIT(15) /* chv */ +#define VGA_PALETTE_C_WRITE_DISABLE_CHV REG_BIT(14) /* chv */ +#define VGA_ACTIVE_THROTTLING_MASK REG_GENMASK(15, 12) /* ilk+ */ +#define VGA_BLANK_THROTTLING_MASK REG_GENMASK(11, 8) /* ilk+ */ +#define VGA_BLINK_DUTY_CYCLE_MASK REG_GENMASK(7, 6) +#define VGA_VSYNC_BLINK_RATE_MASK REG_GENMASK(5, 0) #define VLV_VGACNTRL _MMIO(VLV_DISPLAY_BASE + 0x71400) From patchwork Thu Apr 17 11:44:51 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Ville Syrjala X-Patchwork-Id: 14055386 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 8CFADC369B2 for ; Thu, 17 Apr 2025 11:45:08 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 278B810EADC; Thu, 17 Apr 2025 11:45:08 +0000 (UTC) Authentication-Results: gabe.freedesktop.org; dkim=pass (2048-bit key; unprotected) header.d=intel.com header.i=@intel.com header.b="AGZgyJ55"; dkim-atps=neutral Received: from mgamail.intel.com (mgamail.intel.com [192.198.163.14]) by gabe.freedesktop.org (Postfix) with ESMTPS id 6CE7910EADD for ; Thu, 17 Apr 2025 11:45:06 +0000 (UTC) DKIM-Signature: v=1; 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d="scan'208";a="135943626" Received: from stinkpipe.fi.intel.com (HELO stinkbox) ([10.237.72.74]) by orviesa005.jf.intel.com with SMTP; 17 Apr 2025 04:45:05 -0700 Received: by stinkbox (sSMTP sendmail emulation); Thu, 17 Apr 2025 14:45:03 +0300 From: Ville Syrjala To: intel-gfx@lists.freedesktop.org Subject: [PATCH 3/6] drm/i915/vga: Extract intel_vga_regs.h Date: Thu, 17 Apr 2025 14:44:51 +0300 Message-ID: <20250417114454.12836-4-ville.syrjala@linux.intel.com> X-Mailer: git-send-email 2.49.0 In-Reply-To: <20250417114454.12836-1-ville.syrjala@linux.intel.com> References: <20250417114454.12836-1-ville.syrjala@linux.intel.com> MIME-Version: 1.0 X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" From: Ville Syrjälä Extract the VGACNTR register definitions into their own header file, to declutter i915_reg.h a bit. Signed-off-by: Ville Syrjälä Reviewed-by: Jani Nikula --- drivers/gpu/drm/i915/display/intel_vga.c | 1 + drivers/gpu/drm/i915/display/intel_vga_regs.h | 38 +++++++++++++++++++ drivers/gpu/drm/i915/gvt/handlers.c | 1 + drivers/gpu/drm/i915/i915_reg.h | 30 --------------- drivers/gpu/drm/i915/intel_gvt_mmio_table.c | 1 + 5 files changed, 41 insertions(+), 30 deletions(-) create mode 100644 drivers/gpu/drm/i915/display/intel_vga_regs.h diff --git a/drivers/gpu/drm/i915/display/intel_vga.c b/drivers/gpu/drm/i915/display/intel_vga.c index 684b5d1bc87c..56047f701798 100644 --- a/drivers/gpu/drm/i915/display/intel_vga.c +++ b/drivers/gpu/drm/i915/display/intel_vga.c @@ -13,6 +13,7 @@ #include "i915_reg.h" #include "intel_de.h" #include "intel_vga.h" +#include "intel_vga_regs.h" static i915_reg_t intel_vga_cntrl_reg(struct intel_display *display) { diff --git a/drivers/gpu/drm/i915/display/intel_vga_regs.h b/drivers/gpu/drm/i915/display/intel_vga_regs.h new file mode 100644 index 000000000000..031da94cab79 --- /dev/null +++ b/drivers/gpu/drm/i915/display/intel_vga_regs.h @@ -0,0 +1,38 @@ +/* SPDX-License-Identifier: MIT */ +/* + * Copyright © 2025 Intel Corporation + */ + +#ifndef __INTEL_VGA_REGS_H__ +#define __INTEL_VGA_REGS_H__ + +#include "intel_display_reg_defs.h" + +#define VGACNTRL _MMIO(0x71400) +#define VGA_DISP_DISABLE REG_BIT(31) +#define VGA_2X_MODE REG_BIT(30) /* pre-ilk */ +#define VGA_PIPE_SEL_MASK REG_BIT(29) /* pre-ivb */ +#define VGA_PIPE_SEL(pipe) REG_FIELD_PREP(VGA_PIPE_SEL_MASK, (pipe)) +#define VGA_PIPE_SEL_MASK_CHV REG_GENMASK(29, 28) /* chv */ +#define VGA_PIPE_SEL_CHV(pipe) REG_FIELD_PREP(VGA_PIPE_SEL_MASK_CHV, (pipe)) +#define VGA_BORDER_ENABLE REG_BIT(26) +#define VGA_PIPE_CSC_ENABLE REG_BIT(24) /* ilk+ */ +#define VGA_CENTERING_ENABLE_MASK REG_GENMASK(25, 24) /* pre-ilk */ +#define VGA_PALETTE_READ_SEL REG_BIT(23) /* pre-ivb */ +#define VGA_PALETTE_A_WRITE_DISABLE REG_BIT(22) /* pre-ivb */ +#define VGA_PALETTE_B_WRITE_DISABLE REG_BIT(21) /* pre-ivb */ +#define VGA_LEGACY_8BIT_PALETTE_ENABLE REG_BIT(20) +#define VGA_PALETTE_BYPASS REG_BIT(19) +#define VGA_NINE_DOT_DISABLE REG_BIT(18) +#define VGA_PALETTE_READ_SEL_HI_CHV REG_BIT(15) /* chv */ +#define VGA_PALETTE_C_WRITE_DISABLE_CHV REG_BIT(14) /* chv */ +#define VGA_ACTIVE_THROTTLING_MASK REG_GENMASK(15, 12) /* ilk+ */ +#define VGA_BLANK_THROTTLING_MASK REG_GENMASK(11, 8) /* ilk+ */ +#define VGA_BLINK_DUTY_CYCLE_MASK REG_GENMASK(7, 6) +#define VGA_VSYNC_BLINK_RATE_MASK REG_GENMASK(5, 0) + +#define VLV_VGACNTRL _MMIO(VLV_DISPLAY_BASE + 0x71400) + +#define CPU_VGACNTRL _MMIO(0x41000) + +#endif /* __INTEL_VGA_REGS_H__ */ diff --git a/drivers/gpu/drm/i915/gvt/handlers.c b/drivers/gpu/drm/i915/gvt/handlers.c index e6e9010462e3..1344e6d20a34 100644 --- a/drivers/gpu/drm/i915/gvt/handlers.c +++ b/drivers/gpu/drm/i915/gvt/handlers.c @@ -56,6 +56,7 @@ #include "display/intel_pps_regs.h" #include "display/intel_psr_regs.h" #include "display/intel_sprite_regs.h" +#include "display/intel_vga_regs.h" #include "display/skl_universal_plane_regs.h" #include "display/skl_watermark_regs.h" #include "display/vlv_dsi_pll_regs.h" diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index a533889c2793..38fd44cff5e8 100644 --- a/drivers/gpu/drm/i915/i915_reg.h +++ b/drivers/gpu/drm/i915/i915_reg.h @@ -1812,36 +1812,6 @@ #define SWF3(dev_priv, i) _MMIO(DISPLAY_MMIO_BASE(dev_priv) + 0x72414 + (i) * 4) #define SWF_ILK(i) _MMIO(0x4F000 + (i) * 4) -/* VBIOS regs */ -#define VGACNTRL _MMIO(0x71400) -#define VGA_DISP_DISABLE REG_BIT(31) -#define VGA_2X_MODE REG_BIT(30) /* pre-ilk */ -#define VGA_PIPE_SEL_MASK REG_BIT(29) /* pre-ivb */ -#define VGA_PIPE_SEL(pipe) REG_FIELD_PREP(VGA_PIPE_SEL_MASK, (pipe)) -#define VGA_PIPE_SEL_MASK_CHV REG_GENMASK(29, 28) /* chv */ -#define VGA_PIPE_SEL_CHV(pipe) REG_FIELD_PREP(VGA_PIPE_SEL_MASK_CHV, (pipe)) -#define VGA_BORDER_ENABLE REG_BIT(26) -#define VGA_PIPE_CSC_ENABLE REG_BIT(24) /* ilk+ */ -#define VGA_CENTERING_ENABLE_MASK REG_GENMASK(25, 24) /* pre-ilk */ -#define VGA_PALETTE_READ_SEL REG_BIT(23) /* pre-ivb */ -#define VGA_PALETTE_A_WRITE_DISABLE REG_BIT(22) /* pre-ivb */ -#define VGA_PALETTE_B_WRITE_DISABLE REG_BIT(21) /* pre-ivb */ -#define VGA_LEGACY_8BIT_PALETTE_ENABLE REG_BIT(20) -#define VGA_PALETTE_BYPASS REG_BIT(19) -#define VGA_NINE_DOT_DISABLE REG_BIT(18) -#define VGA_PALETTE_READ_SEL_HI_CHV REG_BIT(15) /* chv */ -#define VGA_PALETTE_C_WRITE_DISABLE_CHV REG_BIT(14) /* chv */ -#define VGA_ACTIVE_THROTTLING_MASK REG_GENMASK(15, 12) /* ilk+ */ -#define VGA_BLANK_THROTTLING_MASK REG_GENMASK(11, 8) /* ilk+ */ -#define VGA_BLINK_DUTY_CYCLE_MASK REG_GENMASK(7, 6) -#define VGA_VSYNC_BLINK_RATE_MASK REG_GENMASK(5, 0) - -#define VLV_VGACNTRL _MMIO(VLV_DISPLAY_BASE + 0x71400) - -/* Ironlake */ - -#define CPU_VGACNTRL _MMIO(0x41000) - #define DIGITAL_PORT_HOTPLUG_CNTRL _MMIO(0x44030) #define DIGITAL_PORTA_HOTPLUG_ENABLE (1 << 4) #define DIGITAL_PORTA_PULSE_DURATION_2ms (0 << 2) /* pre-HSW */ diff --git a/drivers/gpu/drm/i915/intel_gvt_mmio_table.c b/drivers/gpu/drm/i915/intel_gvt_mmio_table.c index 76d84cbb8361..d581a9d2c063 100644 --- a/drivers/gpu/drm/i915/intel_gvt_mmio_table.c +++ b/drivers/gpu/drm/i915/intel_gvt_mmio_table.c @@ -21,6 +21,7 @@ #include "display/intel_pfit_regs.h" #include "display/intel_psr_regs.h" #include "display/intel_sprite_regs.h" +#include "display/intel_vga_regs.h" #include "display/skl_universal_plane_regs.h" #include "display/skl_watermark_regs.h" #include "display/vlv_dsi_pll_regs.h" From patchwork Thu Apr 17 11:44:52 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Ville Syrjala X-Patchwork-Id: 14055387 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 98334C369C2 for ; Thu, 17 Apr 2025 11:45:11 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 2B08B10EADE; Thu, 17 Apr 2025 11:45:11 +0000 (UTC) Authentication-Results: gabe.freedesktop.org; dkim=pass (2048-bit key; unprotected) header.d=intel.com header.i=@intel.com header.b="Oibd3QlJ"; dkim-atps=neutral Received: from mgamail.intel.com (mgamail.intel.com [192.198.163.14]) by gabe.freedesktop.org (Postfix) with ESMTPS id 97D1510EADD for ; Thu, 17 Apr 2025 11:45:09 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1744890310; x=1776426310; h=from:to:subject:date:message-id:in-reply-to:references: mime-version:content-transfer-encoding; bh=RTj6I8JtrGI0o43rrhjFYFE+9ItUtJWn3dNz4SLgeFs=; b=Oibd3QlJtY9SulFDhOptj2HI67cMRfAIPOoiw0Eo6dQxqlmjk7OiIP6l HqdQYCFzR51DzNRvdjr5VQJEsbJaMfgM8LhAS/fLnOdEsglc4u6L/LMzW 2TjX12n/9OVE4Oat+U8sQomJOXb9+I6ibOZskZmDnUCRMKGoFS6XSli5P +BgEATCB3MF/xQ8U+9Go3DrILIeLn9jCNsoJ5ElhLwcmNS6S1PnjYRlIn 28NhWoWQDBayYt6NIzwzYrZ9yv3Tn3DB6n8gdfHYmJY7UJrybdLu5dLDx Dq82ryk78syULzPwYPJ1Xt7BTNPYDjTNQjqvckmLTHB761zGDGKs9Cpc0 A==; X-CSE-ConnectionGUID: BbMHnWJzRsCDLv26SvQX+w== X-CSE-MsgGUID: J9NjeDaFRnyHDRd6YpUXTA== X-IronPort-AV: E=McAfee;i="6700,10204,11405"; a="46638259" X-IronPort-AV: E=Sophos;i="6.15,219,1739865600"; d="scan'208";a="46638259" Received: from orviesa005.jf.intel.com ([10.64.159.145]) by fmvoesa108.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 17 Apr 2025 04:45:09 -0700 X-CSE-ConnectionGUID: BZkYhM4KQrerjp7rBKHfbA== X-CSE-MsgGUID: HyAvpwhaSbm+Mpmh7D+YnA== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.15,219,1739865600"; d="scan'208";a="135943652" Received: from stinkpipe.fi.intel.com (HELO stinkbox) ([10.237.72.74]) by orviesa005.jf.intel.com with SMTP; 17 Apr 2025 04:45:08 -0700 Received: by stinkbox (sSMTP sendmail emulation); Thu, 17 Apr 2025 14:45:06 +0300 From: Ville Syrjala To: intel-gfx@lists.freedesktop.org Subject: [PATCH 4/6] drm/i915/vga: Include the current pipe in the VGA disable debug message Date: Thu, 17 Apr 2025 14:44:52 +0300 Message-ID: <20250417114454.12836-5-ville.syrjala@linux.intel.com> X-Mailer: git-send-email 2.49.0 In-Reply-To: <20250417114454.12836-1-ville.syrjala@linux.intel.com> References: <20250417114454.12836-1-ville.syrjala@linux.intel.com> MIME-Version: 1.0 X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" From: Ville Syrjälä Add some debugs to the VGA plane disable so that we can at least see from the logs when it happens (and on which pipe). I was curious about this at some point when I was seeing some random underruns near the time when we disable the VGA plane, but I think in the end that turned out to be a red herring. Signed-off-by: Ville Syrjälä Reviewed-by: Jani Nikula --- drivers/gpu/drm/i915/display/intel_vga.c | 29 +++++++++++++++++++++++- 1 file changed, 28 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/i915/display/intel_vga.c b/drivers/gpu/drm/i915/display/intel_vga.c index 56047f701798..7ee689a9da92 100644 --- a/drivers/gpu/drm/i915/display/intel_vga.c +++ b/drivers/gpu/drm/i915/display/intel_vga.c @@ -12,6 +12,7 @@ #include "i915_drv.h" #include "i915_reg.h" #include "intel_de.h" +#include "intel_display.h" #include "intel_vga.h" #include "intel_vga_regs.h" @@ -25,16 +26,42 @@ static i915_reg_t intel_vga_cntrl_reg(struct intel_display *display) return VGACNTRL; } +static bool has_vga_pipe_sel(struct intel_display *display) +{ + if (display->platform.i845g || + display->platform.i865g) + return false; + + if (display->platform.valleyview || + display->platform.cherryview) + return true; + + return DISPLAY_VER(display) < 7; +} + /* Disable the VGA plane that we never use */ void intel_vga_disable(struct intel_display *display) { struct pci_dev *pdev = to_pci_dev(display->drm->dev); i915_reg_t vga_reg = intel_vga_cntrl_reg(display); + enum pipe pipe; + u32 tmp; u8 sr1; - if (intel_de_read(display, vga_reg) & VGA_DISP_DISABLE) + tmp = intel_de_read(display, vga_reg); + if (tmp & VGA_DISP_DISABLE) return; + if (display->platform.cherryview) + pipe = REG_FIELD_GET(VGA_PIPE_SEL_MASK_CHV, tmp); + else if (has_vga_pipe_sel(display)) + pipe = REG_FIELD_GET(VGA_PIPE_SEL_MASK, tmp); + else + pipe = PIPE_A; + + drm_dbg_kms(display->drm, "Disabling VGA plane on pipe %c\n", + pipe_name(pipe)); + /* WaEnableVGAAccessThroughIOPort:ctg,elk,ilk,snb,ivb,vlv,hsw */ vga_get_uninterruptible(pdev, VGA_RSRC_LEGACY_IO); outb(0x01, VGA_SEQ_I); From patchwork Thu Apr 17 11:44:53 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Ville Syrjala X-Patchwork-Id: 14055388 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 92C16C369B2 for ; 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X-CSE-ConnectionGUID: HWkDaO6pRy29R1omP3IYqw== X-CSE-MsgGUID: SbK4wFZ8QsO/fdQ4AFOIRg== X-IronPort-AV: E=McAfee;i="6700,10204,11405"; a="46638263" X-IronPort-AV: E=Sophos;i="6.15,219,1739865600"; d="scan'208";a="46638263" Received: from orviesa005.jf.intel.com ([10.64.159.145]) by fmvoesa108.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 17 Apr 2025 04:45:12 -0700 X-CSE-ConnectionGUID: G8XykgwWQ9y2BVBIqqlaDQ== X-CSE-MsgGUID: ZIeLtS5WQHqgdsTN5DaPXg== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.15,219,1739865600"; d="scan'208";a="135943664" Received: from stinkpipe.fi.intel.com (HELO stinkbox) ([10.237.72.74]) by orviesa005.jf.intel.com with SMTP; 17 Apr 2025 04:45:11 -0700 Received: by stinkbox (sSMTP sendmail emulation); Thu, 17 Apr 2025 14:45:09 +0300 From: Ville Syrjala To: intel-gfx@lists.freedesktop.org Subject: [PATCH 5/6] drm/i915/vga: Nuke vga_redisable_power_on() Date: Thu, 17 Apr 2025 14:44:53 +0300 Message-ID: <20250417114454.12836-6-ville.syrjala@linux.intel.com> X-Mailer: git-send-email 2.49.0 In-Reply-To: <20250417114454.12836-1-ville.syrjala@linux.intel.com> References: <20250417114454.12836-1-ville.syrjala@linux.intel.com> MIME-Version: 1.0 X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" From: Ville Syrjälä Now that intel_vga_disable() itself will print a debug message, intel_vga_redisable_power_on() is completely redudant. Get rid of it. Signed-off-by: Ville Syrjälä Reviewed-by: Jani Nikula --- .../gpu/drm/i915/display/intel_display_power_well.c | 2 +- drivers/gpu/drm/i915/display/intel_vga.c | 13 +------------ drivers/gpu/drm/i915/display/intel_vga.h | 1 - 3 files changed, 2 insertions(+), 14 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_display_power_well.c b/drivers/gpu/drm/i915/display/intel_display_power_well.c index b9b4359751cc..9641fb5b846b 100644 --- a/drivers/gpu/drm/i915/display/intel_display_power_well.c +++ b/drivers/gpu/drm/i915/display/intel_display_power_well.c @@ -1252,7 +1252,7 @@ static void vlv_display_power_well_init(struct intel_display *display) intel_crt_reset(&encoder->base); } - intel_vga_redisable_power_on(display); + intel_vga_disable(display); intel_pps_unlock_regs_wa(display); } diff --git a/drivers/gpu/drm/i915/display/intel_vga.c b/drivers/gpu/drm/i915/display/intel_vga.c index 7ee689a9da92..d01de61105c1 100644 --- a/drivers/gpu/drm/i915/display/intel_vga.c +++ b/drivers/gpu/drm/i915/display/intel_vga.c @@ -74,17 +74,6 @@ void intel_vga_disable(struct intel_display *display) intel_de_posting_read(display, vga_reg); } -void intel_vga_redisable_power_on(struct intel_display *display) -{ - i915_reg_t vga_reg = intel_vga_cntrl_reg(display); - - if (!(intel_de_read(display, vga_reg) & VGA_DISP_DISABLE)) { - drm_dbg_kms(display->drm, - "Something enabled VGA plane, disabling it\n"); - intel_vga_disable(display); - } -} - void intel_vga_redisable(struct intel_display *display) { intel_wakeref_t wakeref; @@ -102,7 +91,7 @@ void intel_vga_redisable(struct intel_display *display) if (!wakeref) return; - intel_vga_redisable_power_on(display); + intel_vga_disable(display); intel_display_power_put(display, POWER_DOMAIN_VGA, wakeref); } diff --git a/drivers/gpu/drm/i915/display/intel_vga.h b/drivers/gpu/drm/i915/display/intel_vga.h index 824dfc32a199..d0716782c1f9 100644 --- a/drivers/gpu/drm/i915/display/intel_vga.h +++ b/drivers/gpu/drm/i915/display/intel_vga.h @@ -11,7 +11,6 @@ struct intel_display; void intel_vga_reset_io_mem(struct intel_display *display); void intel_vga_disable(struct intel_display *display); void intel_vga_redisable(struct intel_display *display); -void intel_vga_redisable_power_on(struct intel_display *display); int intel_vga_register(struct intel_display *display); void intel_vga_unregister(struct intel_display *display); From patchwork Thu Apr 17 11:44:54 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Ville Syrjala X-Patchwork-Id: 14055389 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 8558FC369CB for ; Thu, 17 Apr 2025 11:45:16 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 1EE4E10EAE0; Thu, 17 Apr 2025 11:45:16 +0000 (UTC) Authentication-Results: gabe.freedesktop.org; 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a="46638266" X-IronPort-AV: E=Sophos;i="6.15,219,1739865600"; d="scan'208";a="46638266" Received: from orviesa005.jf.intel.com ([10.64.159.145]) by fmvoesa108.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 17 Apr 2025 04:45:15 -0700 X-CSE-ConnectionGUID: pxJvYqUmQXePG6Z2/sBaQg== X-CSE-MsgGUID: zg0xsacVSsamtWhjHVG3ew== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.15,219,1739865600"; d="scan'208";a="135943673" Received: from stinkpipe.fi.intel.com (HELO stinkbox) ([10.237.72.74]) by orviesa005.jf.intel.com with SMTP; 17 Apr 2025 04:45:14 -0700 Received: by stinkbox (sSMTP sendmail emulation); Thu, 17 Apr 2025 14:45:12 +0300 From: Ville Syrjala To: intel-gfx@lists.freedesktop.org Subject: [PATCH 6/6] drm/i915/vga: Consolidate intel_vga_disable() calls Date: Thu, 17 Apr 2025 14:44:54 +0300 Message-ID: <20250417114454.12836-7-ville.syrjala@linux.intel.com> X-Mailer: git-send-email 2.49.0 In-Reply-To: <20250417114454.12836-1-ville.syrjala@linux.intel.com> References: <20250417114454.12836-1-ville.syrjala@linux.intel.com> MIME-Version: 1.0 X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" From: Ville Syrjälä Currently we disable the VGA plane from various places, sometimes multiple times in the same init/resume sequence. Get rid of all this mess and do it just once. The most correct place seems to be just after intel_early_display_was() as that one applies various workarounds that need to be in place before we touch any planes (including the VGA plane). Actually, we do still have a second caller in vlv_display_power_well_init(). I think we still need that as the reset value of VGACNTR is 0x0 and thus technically the VGA plane will be (at least partially) enabled after the power well has been toggled. In both cases we have the necessary power reference already held (INIT power domain for load/resume case, and the display power well itself being what we need for vlv_display_power_well_init()). Signed-off-by: Ville Syrjälä Reviewed-by: Jani Nikula --- .../drm/i915/display/intel_display_driver.c | 3 --- .../drm/i915/display/intel_modeset_setup.c | 3 +++ drivers/gpu/drm/i915/display/intel_vga.c | 22 ------------------- drivers/gpu/drm/i915/display/intel_vga.h | 1 - drivers/gpu/drm/i915/i915_driver.c | 3 --- 5 files changed, 3 insertions(+), 29 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_display_driver.c b/drivers/gpu/drm/i915/display/intel_display_driver.c index eb3ae05d1569..ac0f79476675 100644 --- a/drivers/gpu/drm/i915/display/intel_display_driver.c +++ b/drivers/gpu/drm/i915/display/intel_display_driver.c @@ -455,8 +455,6 @@ int intel_display_driver_probe_nogem(struct intel_display *display) intel_hti_init(display); - /* Just disable it once at startup */ - intel_vga_disable(display); intel_setup_outputs(display); ret = intel_dp_tunnel_mgr_init(display); @@ -693,7 +691,6 @@ __intel_display_driver_resume(struct intel_display *display, int ret, i; intel_modeset_setup_hw_state(display, ctx); - intel_vga_redisable(display); if (!state) return 0; diff --git a/drivers/gpu/drm/i915/display/intel_modeset_setup.c b/drivers/gpu/drm/i915/display/intel_modeset_setup.c index 5d5ade7fdd77..0325b0c9506d 100644 --- a/drivers/gpu/drm/i915/display/intel_modeset_setup.c +++ b/drivers/gpu/drm/i915/display/intel_modeset_setup.c @@ -31,6 +31,7 @@ #include "intel_pmdemand.h" #include "intel_tc.h" #include "intel_vblank.h" +#include "intel_vga.h" #include "intel_wm.h" #include "skl_watermark.h" @@ -935,6 +936,8 @@ void intel_modeset_setup_hw_state(struct intel_display *display, wakeref = intel_display_power_get(display, POWER_DOMAIN_INIT); intel_early_display_was(display); + intel_vga_disable(display); + intel_modeset_readout_hw_state(display); /* HW state is read out, now we need to sanitize this mess. */ diff --git a/drivers/gpu/drm/i915/display/intel_vga.c b/drivers/gpu/drm/i915/display/intel_vga.c index d01de61105c1..a0940a050994 100644 --- a/drivers/gpu/drm/i915/display/intel_vga.c +++ b/drivers/gpu/drm/i915/display/intel_vga.c @@ -74,28 +74,6 @@ void intel_vga_disable(struct intel_display *display) intel_de_posting_read(display, vga_reg); } -void intel_vga_redisable(struct intel_display *display) -{ - intel_wakeref_t wakeref; - - /* - * This function can be called both from intel_modeset_setup_hw_state or - * at a very early point in our resume sequence, where the power well - * structures are not yet restored. Since this function is at a very - * paranoid "someone might have enabled VGA while we were not looking" - * level, just check if the power well is enabled instead of trying to - * follow the "don't touch the power well if we don't need it" policy - * the rest of the driver uses. - */ - wakeref = intel_display_power_get_if_enabled(display, POWER_DOMAIN_VGA); - if (!wakeref) - return; - - intel_vga_disable(display); - - intel_display_power_put(display, POWER_DOMAIN_VGA, wakeref); -} - void intel_vga_reset_io_mem(struct intel_display *display) { struct pci_dev *pdev = to_pci_dev(display->drm->dev); diff --git a/drivers/gpu/drm/i915/display/intel_vga.h b/drivers/gpu/drm/i915/display/intel_vga.h index d0716782c1f9..16d699f3b641 100644 --- a/drivers/gpu/drm/i915/display/intel_vga.h +++ b/drivers/gpu/drm/i915/display/intel_vga.h @@ -10,7 +10,6 @@ struct intel_display; void intel_vga_reset_io_mem(struct intel_display *display); void intel_vga_disable(struct intel_display *display); -void intel_vga_redisable(struct intel_display *display); int intel_vga_register(struct intel_display *display); void intel_vga_unregister(struct intel_display *display); diff --git a/drivers/gpu/drm/i915/i915_driver.c b/drivers/gpu/drm/i915/i915_driver.c index 97ff9855b5de..96a52f963475 100644 --- a/drivers/gpu/drm/i915/i915_driver.c +++ b/drivers/gpu/drm/i915/i915_driver.c @@ -62,7 +62,6 @@ #include "display/intel_pch_refclk.h" #include "display/intel_pps.h" #include "display/intel_sprite_uapi.h" -#include "display/intel_vga.h" #include "display/skl_watermark.h" #include "gem/i915_gem_context.h" @@ -1202,8 +1201,6 @@ static int i915_drm_resume(struct drm_device *dev) i9xx_display_sr_restore(display); - intel_vga_redisable(display); - intel_gmbus_reset(display); intel_pps_unlock_regs_wa(display);